Pixel circuit and driving method therefor, display substrate, and display device

Abstract

A pixel circuit, comprising a driving sub-circuit (11), a first voltage write sub-circuit (12), a second voltage write sub-circuit (13), a write control sub-circuit (15), a coupling sub-circuit (16), a first reset sub-circuit (14) and a storage sub-circuit (17), wherein the first voltage write sub-circuit (12) is configured to write a data signal provided by a data line (DL) into a third node (N3) under the control of a first scanning line (GL1) during a data write stage (S4); the second voltage write sub-circuit (13) is configured to write a threshold voltage of the driving sub-circuit (11) into the third node (N3) under the control of a compensation control line (GP) during a threshold compensation stage (S3); the write control sub-circuit (15) is configured to connect the third node (N3) and a fourth node (N4); and the coupling sub-circuit (16) is configured to couple a signal written into the fourth node (N4) to a first node (N1).

Description

Pixel circuit and driving method thereof, display substrate and display device Technical Field

[0001] The present invention relates to, but is not limited to, display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) offer advantages such as ultra-thinness, wide viewing angles, active illumination, high brightness, continuously adjustable color, low cost, fast response time, low power consumption, a wide operating temperature range, and flexible displays. They have gradually become a highly promising next-generation display technology and are attracting increasing attention. Depending on the driving method, OLEDs can be categorized as either passive matrix (PM) or active matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0003] In recent years, with the rapid development of the display industry, AMOLED displays have been used in various industries, such as mobile phones, bracelets, watches, car displays, laptops, TVs, and more. However, with the continuous development of industries such as gaming that require high refresh rates, consumers' requirements for display screens are also becoming increasingly higher. High-refresh and even ultra-high-refresh displays are gradually being required by various industries.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate, and a display device.

[0007] In one aspect, this embodiment provides a pixel circuit, comprising: a driver subcircuit, a first voltage write subcircuit, a second voltage write subcircuit, a write control subcircuit, a coupling subcircuit, a first reset subcircuit, and a storage subcircuit. The driver subcircuit is coupled to a first node, a second node, and a third node, and is configured to provide a drive signal to the third node under the control of the first node. The first reset subcircuit is coupled to the first node, a first reset control line, and a first initial signal line, and is configured to write a first initial signal provided by the first initial signal line to the first node under the control of the first reset control line. The first voltage write subcircuit is coupled to the third node, a first scan line, and a data line, and is configured to write a data signal provided by the data line to the third node under the control of the first scan line during a data write phase. The second voltage write subcircuit is coupled to the second node, a compensation control line, and a second initial signal line, and is configured to write the threshold voltage of the driver subcircuit to the third node under the control of the compensation control line during a threshold compensation phase. The write control subcircuit is coupled to the third node, the fourth node, and the second scan line, and is configured to conduct the third node and the fourth node under control of the second scan line during the data write phase and the threshold compensation phase. The coupling subcircuit is coupled to the first node and the fourth node, and is configured to couple the signal written to the fourth node to the first node. The storage subcircuit is coupled to the first node and the first power line. Within a display cycle, the threshold compensation phase is independent of the data write phase.

[0008] In some exemplary embodiments, within a display cycle, the threshold compensation phase is located before the data writing phase, and a duration of the threshold compensation phase is greater than a duration of the data writing phase.

[0009] In some exemplary embodiments, the pixel circuit further includes: a first control subcircuit and a second control subcircuit. The first control subcircuit is coupled to the second node, the first control line, and the first power line, and is configured to conduct electricity between the first power line and the second node under the control of the first control line. The second control subcircuit is coupled to the third node, the second control line, and a fifth node, and is configured to transmit the drive signal to the fifth node under the control of the second control line. The fifth node is coupled to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is coupled to the second power line.

[0010] In some example embodiments, the first control signal provided by the first control line is different from the second control signal provided by the second control line.

[0011] In some exemplary embodiments, the pixel circuit further includes: a third voltage writing sub-circuit, coupled to the third node, the third scan line and the fourth initial signal line, and configured to write the fourth initial signal provided by the fourth initial signal line into the third node under the control of the third scan line before the threshold compensation stage.

[0012] In some exemplary embodiments, the first initial signal provided by the first initial signal line is the same as the second initial signal provided by the second initial signal line, and the fourth initial signal provided by the fourth initial signal line is greater than the first initial signal provided by the first initial signal line.

[0013] In some example embodiments, the first control signal provided by the first control line is the same as the second control signal provided by the second control line.

[0014] In some exemplary embodiments, the pixel circuit further includes: a second reset subcircuit, which is coupled to the fifth node, the second reset control line and the third initial signal line, and is configured to write the third initial signal provided by the third initial signal line into the fifth node under the control of the second reset control line.

[0015] In some exemplary embodiments, the first reset sub-circuit includes a first transistor, having a gate coupled to the first reset control line, a first electrode coupled to the first initial signal line, and a second electrode coupled to the first node. The write control sub-circuit includes a second transistor, having a gate coupled to the second scan line, a first electrode coupled to the third node, and a second electrode coupled to the fourth node. The drive sub-circuit includes a third transistor, having a gate coupled to the first node, a first electrode coupled to the second node, and a second electrode coupled to the third node. The first voltage write sub-circuit includes a fourth transistor, having a gate coupled to the first scan line, a first electrode coupled to the data line, and a second electrode coupled to the third node. The second voltage write sub-circuit includes a seventh transistor, having a gate coupled to the compensation control line, a first electrode coupled to the second initial signal line, and a second electrode coupled to the second node. The first control subcircuit includes a fifth transistor, a gate of the fifth transistor coupled to the first control line, a first electrode of the fifth transistor coupled to the first power line, and a second electrode of the fifth transistor coupled to the second node. The second control subcircuit includes a sixth transistor, a gate of the sixth transistor coupled to the second control line, a first electrode of the sixth transistor coupled to the third node, and a second electrode of the sixth transistor coupled to the fifth node. The second reset subcircuit includes an eighth transistor, a gate of the eighth transistor coupled to the second reset control line, a first electrode of the eighth transistor coupled to the third initial signal line, and a second electrode of the eighth transistor coupled to the fifth node. The third, fourth, fifth, sixth, seventh, and eighth transistors are first-type transistors; the first and second transistors are second-type transistors; and the first and second-type transistors are of different transistor types.

[0016] In some exemplary embodiments, the first type transistor is a low temperature polysilicon thin film transistor, and the second type transistor is an oxide thin film transistor.

[0017] In some exemplary embodiments, the storage subcircuit includes: a first capacitor; the coupling subcircuit includes: a second capacitor; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the first power line; a first electrode of the second capacitor is coupled to the fourth node, and a second electrode of the second capacitor is coupled to the first node.

[0018] On the other hand, this embodiment provides a driving method for a pixel circuit, which is applied to the pixel circuit as described above, and the driving method includes: the first reset sub-circuit writes the first initial signal provided by the first initial signal line into the first node under the control of the first reset control line; in the threshold compensation stage, the second voltage writing sub-circuit writes the threshold voltage of the driving sub-circuit into the third node under the control of the compensation control line, and the write control circuit turns on the third node and the fourth node under the control of the second scan line, and writes the threshold voltage into the fourth node; in the data writing stage, the first voltage writing sub-circuit writes the data signal provided by the data line into the third node under the control of the first scan line, the write control circuit writes the data signal into the fourth node, and the coupling sub-circuit couples the signal written into the fourth node to the first node; the driving sub-circuit provides a driving signal to the third node under the control of the first node.

[0019] In some exemplary embodiments, within a display cycle, the threshold compensation phase is located before the data writing phase, and a duration of the threshold compensation phase is greater than a duration of the data writing phase.

[0020] In some exemplary embodiments, the driving method of this example further includes: before the threshold compensation stage, the first control subcircuit charges the fourth node using a first voltage signal provided by a first power line under the control of a first control line.

[0021] In some exemplary embodiments, the pixel circuit further includes: a third voltage writing sub-circuit coupled to the third node, the third scan line and the fourth initial signal line; the driving method further includes: before the threshold compensation stage, the third voltage writing sub-circuit, under the control of the third scan line, uses the fourth initial signal provided by the fourth initial signal line to charge the fourth node; the fourth initial signal is greater than the first initial signal.

[0022] In some exemplary embodiments, within one display cycle, the duration of the effective level signal of the second scan signal provided by the second scan line is greater than the sum of the durations of the effective level signal of the first scan signal provided by the first scan line, the effective level signal of the third scan signal provided by the third scan line, and the effective level signal of the compensation control signal provided by the compensation control line.

[0023] On the other hand, this embodiment provides a display substrate, comprising: a substrate, a circuit structure layer disposed on the substrate, the circuit structure layer comprising a plurality of pixel circuits, at least one pixel circuit comprising: a first capacitor and a second capacitor; the second capacitor being located on a side of the first capacitor away from the substrate, and the orthographic projection of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate. The first capacitor comprises: a first plate and a second plate; the second capacitor comprises: a third plate and a fourth plate. The second plate of the first capacitor is located on a side of the first plate away from the substrate, the third plate of the second capacitor is located on a side of the fourth plate away from the substrate, and the fourth plate of the second capacitor is located on a side of the second plate of the first capacitor away from the substrate; the first plate of the first capacitor is connected to the fourth plate of the second capacitor.

[0024] In some exemplary embodiments, the second electrode plate of the first capacitor has a hollow region, and the connection position of the first electrode plate and the fourth electrode plate is located within the orthographic projection of the substrate of the hollow region.

[0025] In some exemplary embodiments, the orthographic projection of the third plate of the second capacitor on the substrate covers the orthographic projections of the first plate and the fourth plate on the substrate.

[0026] In some exemplary embodiments, the second plates of the first capacitors of the plurality of pixel circuits arranged along the first direction are interconnected integral structures, the integral structure is connected to a first power line extending along the second direction to form a mesh structure for transmitting a first voltage signal, and the first power line is located on a side of the integral structure away from the substrate; the first direction intersects the second direction.

[0027] In some exemplary embodiments, an integrated structure formed by connecting the second plates of the first capacitors of a plurality of pixel circuits arranged along the first direction is connected to the first power line through a ninth connecting electrode, and the ninth connecting electrode is located on a side of the integrated structure away from the substrate and on a side of the first power line close to the substrate.

[0028] In some exemplary embodiments, the pixel circuit is connected to a first initial signal line, a second initial signal line, and a third initial signal line; and the first initial signal line, the second initial signal line, and the third initial signal line are located in different conductive layers.

[0029] In some exemplary embodiments, the pixel circuit includes at least one first-type transistor and at least one second-type transistor. In a direction perpendicular to the display substrate, the circuit structure layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate; the first semiconductor layer includes an active layer of the at least one first-type transistor, and the second semiconductor layer includes an active layer of the at least one second-type transistor.

[0030] In some exemplary embodiments, the first plate of the first capacitor is located in the first conductive layer, and the second plate of the first capacitor is located in the second conductive layer; the third plate of the second capacitor is located in the fifth conductive layer, and the fourth plate of the second capacitor is located in the fourth conductive layer.

[0031] In some exemplary embodiments, the pixel circuit is electrically connected to a first initial signal line, the first initial signal line is located in the fourth conductive layer, and the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the lines located in the second conductive layer and the third conductive layer on the substrate.

[0032] In some exemplary embodiments, the pixel circuit is electrically connected to a second initial signal line and a third initial signal line, the third initial signal line is located in the second conductive layer, the second initial signal line is located in the third conductive layer, and the second initial signal line and the third initial signal line at least partially overlap in their orthographic projections on the substrate.

[0033] In some exemplary embodiments, the pixel circuit includes two second-type transistors, and the two second-type transistors are adjacent to each other in a first direction and are staggered along the first direction.

[0034] In some exemplary embodiments, the plurality of pixel circuits are divided into a plurality of pixel circuit groups, each pixel circuit group includes two pixel circuits adjacently arranged along a first direction, and the two pixel circuits in the pixel circuit group are symmetrically arranged about a first center line of the pixel circuit group in the first direction.

[0035] In some exemplary embodiments, two pixel circuits in the pixel circuit group are connected to the same first power line, the first power line is located at the first center line, and the data lines connected to the two pixel circuits are located on both sides of the first power line in the first direction.

[0036] On the other hand, an embodiment of the present disclosure provides a display device including the display substrate as described above.

[0037] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0038] Summary of the Figures

[0039] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0040] FIG1 is a schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0041] FIG2 is another schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0042] FIG3 is another schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0043] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0044] 5A and 5B are operation timing diagrams of the pixel circuit shown in FIG4 ;

[0045] FIG6 is another schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0046] FIG7 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0047] 8A and 8B are operation timing diagrams of the pixel circuit shown in FIG7 ;

[0048] FIG9 is a flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] FIG10 is a partial plan view of a circuit structure layer of a display substrate according to at least one embodiment of the present disclosure;

[0050] FIG11 is a schematic partial cross-sectional view along the QQ' direction in FIG10;

[0051] FIG12 is a schematic diagram of the display substrate after the first semiconductor layer is formed in FIG10;

[0052] FIG13A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG10;

[0053] FIG13B is a schematic diagram of the first conductive layer in FIG13A ;

[0054] FIG14A is a schematic diagram of the display substrate after forming the second conductive layer in FIG10;

[0055] FIG14B is a schematic diagram of the second conductive layer in FIG14A;

[0056] FIG15A is a schematic diagram of the display substrate after the second semiconductor layer is formed in FIG10;

[0057] FIG15B is a schematic diagram of the second semiconductor layer in FIG15A;

[0058] FIG16A is a schematic diagram of the display substrate after forming the third conductive layer in FIG10;

[0059] FIG16B is a schematic diagram of the third conductive layer in FIG16A;

[0060] FIG17 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG10;

[0061] FIG18A is a schematic diagram of the display substrate after the fourth conductive layer is formed in FIG10;

[0062] FIG18B is a schematic diagram of the fourth conductive layer in FIG17A ;

[0063] FIG19 is a schematic diagram of the display substrate after the sixth insulating layer is formed in FIG10;

[0064] FIG20 is a schematic diagram of the fifth conductive layer in FIG10 ;

[0065] FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0066] Details

[0067] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0068] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0069] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0070] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0071] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meanings of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0072] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0073] In this specification, to distinguish the two electrodes of a transistor other than the gate, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. The first electrode can be either the source or the drain, and the second electrode can be either the drain or the source. Furthermore, the gate of the transistor is referred to as the control electrode. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchanged.

[0074] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0076] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries and allow for process and measurement errors. In this disclosure, "same" includes both identical and substantially the same, where "substantially the same" means a difference of less than 10%.

[0077] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0078] In the present disclosure, the effective level signal includes a level signal that turns on a transistor. For example, the effective level signal that turns on a P-type transistor is a low level signal, and the effective level signal that turns on an N-type transistor is a high level signal.

[0079] In some implementations, for high-frequency driving applications (for example, display scenarios greater than 120 Hz, such as high-frequency display scenarios such as 240 Hz or 360 Hz), the data writing time and threshold voltage compensation time of the display substrate are severely compressed, resulting in insufficient threshold voltage compensation time, thereby causing poor threshold voltage sensitivity and compensation effect, affecting the display effect.

[0080] This embodiment provides a pixel circuit and a driving method thereof, a display substrate, and a display device, which can improve the problem of insufficient threshold voltage compensation time under high-frequency driving, thereby improving high-frequency display performance.

[0081] FIG1 is a schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG1 , the pixel circuit of this embodiment may include: a driver subcircuit 11, a first voltage write subcircuit 12, a second voltage write subcircuit 13, a first reset subcircuit 14, a write control subcircuit 15, a coupling subcircuit 16, and a storage subcircuit 17. The driver subcircuit 11 is coupled to a first node N1, a second node N2, and a third node N3, and is configured to provide a drive signal to the third node N3 under the control of the first node N1. The first reset subcircuit 14 is coupled to the first node N1, a first reset control line RST1, and a first initial signal line INIT1, and is configured to write a first initial signal provided by the first initial signal line INIT1 to the first node N1 under the control of the first reset control line RST1. The first voltage write subcircuit 12 is coupled to a third node N3, a first scan line GL1, and a data line DL, and is configured to write a data signal provided by the data line DL to the third node N3 under the control of the first scan line GL1 during a data write phase. The second voltage writing sub-circuit 13 is coupled to the second node N2, the compensation control line GP, and the second initial signal line INIT2. It is configured to write the threshold voltage of the driver sub-circuit 11 to the third node N3 under the control of the compensation control line GP during the threshold compensation phase. The write control sub-circuit 15 is coupled to the third node N3, the fourth node N4, and the second scan line GL2. It is configured to conduct the third node N3 and the fourth node N4 under the control of the second scan line GL2 during the data writing phase and the threshold compensation phase. The coupling sub-circuit 16 is coupled to the first node N1 and the fourth node N4 and is configured to couple the signal written to the fourth node N4 to the first node N1. The storage sub-circuit 17 is coupled to the first node N1 and the first power line VDD and is configured to store the voltage of the first node N1. Within a display cycle, the threshold compensation phase is independent of the data writing phase.

[0082] In the pixel circuit provided by this embodiment, the data signal and the threshold voltage of the driver subcircuit can be written to the fourth node through the third node and the write control subcircuit at different stages, and then written to the first node through the coupling subcircuit. By separately controlling the writing process of the data signal and the threshold voltage, it is advantageous to flexibly adjust the writing compensation time of the threshold voltage as needed, thereby increasing the compensation time of the threshold voltage, making the threshold voltage compensation time sufficient, thereby reducing the severity of poor display caused by insufficient threshold voltage compensation, and helping to improve the yield of the display substrate. Moreover, by separately controlling the writing process of the data signal and the threshold voltage, the writing time of the data signal can be reduced while ensuring the compensation time of the threshold voltage. The compensation of the threshold voltage is not affected by the writing process of the data signal, and can support full compensation of the threshold voltage at high refresh rates, thereby facilitating support of display products with high refresh rates, improving display brightness, and improving display uniformity.

[0083] In some examples, within a display cycle, the threshold compensation phase is located before the data writing phase, and the duration of the threshold compensation phase can be greater than the duration of the data writing phase. In some examples, the first scan line GL1 provides a first scan signal, and the compensation control line GP provides a compensation control signal. Within a display cycle, the duration of the effective level signal (e.g., a low level signal) of the first scan signal can be greater than the duration of the effective level signal of the compensation control signal, and the end time of the effective level signal of the compensation control signal can be earlier than the start time of the effective level signal of the first scan signal. The first scan signal and the compensation control signal can be provided by different gate drive circuits. In some examples, the duration of the compensation control signal can be adjusted within different display cycles. This example utilizes the compensation control signal to control the compensation duration of the threshold voltage, which can be beneficial to achieve sufficient compensation of the threshold voltage, thereby reducing poor display caused by insufficient threshold voltage compensation.

[0084] In some examples, the second scan line GL2 can provide a second scan signal, and the first reset control line RST1 can provide a first reset control signal. Within a display period, the duration of the effective level signal (e.g., a high level signal) of the first reset control signal can be the same as the duration of the effective level signal of the second scan signal. The starting time of the effective level signal of the first reset control signal can be earlier than the starting time of the effective level signal of the second scan signal, and the ending time of the effective level signal of the first reset control signal can be later than the starting time of the effective level signal of the second scan signal. The first reset control signal and the second scan signal can be provided by different levels of shift register units of the same gate drive circuit. For example, the nth level shift register unit of a gate drive circuit can provide the first reset control signal, and the n+7th level shift register unit of the gate drive circuit can provide the second scan signal, where n can be an integer greater than 0.

[0085] In some examples, the first initial signal provided by the first initial signal line INIT1 and the second initial signal provided by the second initial signal line INIT2 can be the same. In this example, the voltage written to the first node can be independent of the second initial signal, and only the data signal and the threshold voltage can be written to the first node. In other examples, the second initial signal can be smaller than the first initial signal.

[0086] FIG2 is another schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG2 , the pixel circuit of this embodiment may include: a driver subcircuit 11, a first voltage write subcircuit 12, a second voltage write subcircuit 13, a first reset subcircuit 14, a write control subcircuit 15, a coupling subcircuit 16, a storage subcircuit 17, a first control subcircuit 18, and a second control subcircuit 19. The first control subcircuit 18 is coupled to the second node N2, the first control line EML1, and the first power line VDD. Under the control of the first control line EML1, it is configured to conduct electricity between the first power line VDD and the second node N2. The second control subcircuit 19 is coupled to the third node N3, the fifth node N5, and the second control line EML2. Under the control of the second control line EML2, it is configured to transmit a drive signal to the fifth node N5. The fifth node N5 is coupled to the first electrode of the light-emitting element, and the second electrode of the light-emitting element may be coupled to the second power line VSS. The remaining structure of the pixel circuit of this embodiment can be referred to the description of the previous embodiment, and will not be repeated here.

[0087] In some examples, the light emitting element may be an organic light emitting diode (OLED). The first electrode of the light emitting element may be an anode, and the second electrode may be a cathode. However, this embodiment is not limited to this.

[0088] In some examples, the first power line VDD can continuously provide a constant high-level signal, for example, the first power line can provide a first voltage signal. The second power line VSS can continuously provide a constant low-level signal, for example, the second power line VSS can provide a second voltage signal. The first voltage signal can be greater than the second voltage signal.

[0089] In some examples, the first control signal provided by the first control line EML1 can be different from the second control signal provided by the second control line EML2. For example, within a display period, the duration of the active level signal (e.g., a low level signal) of the first control signal can be greater than the duration of the active level signal of the second control signal, and the effective level signal of the first control signal can end later than the effective level signal of the second control signal. The start time of the active level signal of the first control signal and the start time of the effective level signal of the second control signal can be the same. The first control signal and the second control signal can be generated by different gate drive circuits. For example, before the threshold compensation phase, the first control signal provided by the first control line EML1 can control the conduction of the first power line VDD and the second node N2 to charge the fourth node N4 using the first voltage signal provided by the first power line VDD, while the second control signal provided by the second control line EML2 can control the disconnection of the third node N3 and the fifth node N5.

[0090] FIG3 is another schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG3 , the pixel circuit of this embodiment may include: a driving subcircuit 11, a first voltage writing subcircuit 12, a second voltage writing subcircuit 13, a first reset subcircuit 14, a write control subcircuit 15, a coupling subcircuit 16, a storage subcircuit 17, a first control subcircuit 18, a second control subcircuit 19, and a second reset subcircuit 20. The second reset subcircuit 20 is coupled to the fifth node N5, the second reset control line RST2, and the third initial signal line INIT3, and is configured to write the third initial signal provided by the third initial signal line INIT3 to the fifth node N5 under the control of the second reset control line RST2. The remaining structure of the pixel circuit of this example can be referred to the description of the previous embodiment, and therefore will not be repeated here.

[0091] In some examples, the third initial signal provided by the third initial signal line INIT3 may be different from the first initial signal provided by the first initial signal line INIT1. However, this embodiment is not limited thereto. In this example, the fifth node N5 is initialized by setting the second reset sub-circuit 20.

[0092] In some examples, the compensation control signal provided by the compensation control line GP and the second reset control signal provided by the second reset control line RST2 can be the same. In some examples, the compensation control signal and the second reset control signal can be generated by the same gate driver circuit, for example, by the same stage of shift register units in the same gate driver circuit; or, the compensation control signal can be generated by the kth stage shift register unit of a gate driver circuit, and the second reset control signal can be generated by the k+1th stage shift register unit of the same gate driver circuit, where k is an integer greater than 0.

[0093] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG4 , the driving subcircuit 11 of the pixel circuit of this example may include: a third transistor (also referred to as a driving transistor) T3; the first voltage writing subcircuit 12 may include: a fourth transistor (also referred to as a data writing transistor) T4; the second voltage writing subcircuit 13 may include: a seventh transistor (also referred to as a compensation control transistor) T7; the first reset subcircuit 14 may include: a first transistor (also referred to as a first reset transistor) T1; the writing control subcircuit 15 may include: a second transistor (also referred to as a compensation writing transistor) T2; the coupling subcircuit 16 may include: a second capacitor C2; the storage subcircuit 17 may include: a first capacitor C1; the first control subcircuit 18 may include: a fifth transistor (also referred to as a first control transistor) T5; the second control subcircuit 19 may include: a sixth transistor (also referred to as a second control transistor) T6; and the second reset subcircuit 20 may include: an eighth transistor (also referred to as a second reset transistor) T8.

[0094] In some examples, as shown in FIG4 , the gate of the third transistor T3 is coupled to the first node N1, the first electrode is coupled to the second node N2, and the second electrode is coupled to the third node N3. The third transistor T3 can be configured to provide a drive signal to the third node N3 under the control of the first node N1. The gate of the first transistor T1 is coupled to the first reset control line RST1, the first electrode is coupled to the first initial signal line INIT1, and the second electrode is coupled to the first node N1. The first transistor T1 can be configured to write the first initial signal transmitted by the first initial signal line INIT1 to the first node N1 under the control of the first reset control line RST1. The gate of the second transistor T2 is coupled to the second scan line GL2, the first electrode is coupled to the third node N3, and the second electrode is coupled to the fourth node N4. The second transistor T2 can be configured to conduct electricity between the third node N3 and the fourth node N4 under the control of the second scan line GL2, so that the signal of the third node N3 is written to the fourth node N4. The fourth transistor T4 has a gate coupled to the first scan line GL1, a first electrode coupled to the data line DL, and a second electrode coupled to the third node N3. The fourth transistor T4 can be configured to write a data signal transmitted by the data line DL into the third node N3 under the control of the first scan line GL1. The fifth transistor T5 has a gate coupled to the first control line EML1, a first electrode coupled to the first power line VDD, and a second electrode coupled to the second node N2. The fifth transistor T5 can be configured to write a first voltage signal provided by the first power line VDD into the second node N2 under the control of the first control line EML1. The sixth transistor T6 has a gate coupled to the second control line EML2, a first electrode coupled to the third node N3, and a second electrode coupled to the fifth node N5. The sixth transistor T6 can be configured to conduct electricity between the third node N3 and the fifth node N5 under the control of the second control line EML2. The seventh transistor T7 has a gate coupled to the compensation control line GP, a first electrode coupled to the second initial signal line INIT2, and a second electrode coupled to the second node N2. The seventh transistor T7 can be configured to write the second initial signal transmitted by the second initial signal line INIT2 to the second node N2 under the control of the compensation control line GP. The gate of the eighth transistor T8 is coupled to the second reset control line RST2, the first electrode is coupled to the third initial signal line INIT3, and the second electrode is coupled to the fifth node N5. The eighth transistor T8 can be configured to write the third initial signal transmitted by the third initial signal line INIT3 to the fifth node N5 under the control of the second reset control line RST2. The first electrode of the first capacitor C1 is coupled to the first node N1, and the second electrode is coupled to the first power supply line VDD. The first capacitor C1 can be configured to store the voltage of the first node N1. The first electrode of the second capacitor C2 is coupled to the fourth node N4, and the second electrode is coupled to the first node N1. The second capacitor C2 can be configured to couple the signal written to the fourth node N4 to the first node N1.A first electrode of the light emitting element EL is coupled to the fifth node N5 , and a second electrode of the light emitting element EL is coupled to the second power supply line VSS.

[0095] In some examples, as shown in Figure 4, the first node N1 is the connection point of the first transistor T1, the third transistor T3, the first capacitor C1 and the second capacitor C2; the second node N2 is the connection point of the third transistor T3, the seventh transistor T7 and the fifth transistor T5; the third node N3 is the connection point of the second transistor T2, the third transistor T3, the fourth transistor T4 and the sixth transistor T6; the fourth node N4 is the connection point of the second capacitor C2 and the second transistor T2; and the fifth node N5 is the connection point of the sixth transistor T6, the eighth transistor T8 and the light-emitting element EL.

[0096] In some examples, as shown in FIG4 , the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the pixel circuit may be first-type transistors, and the first transistor T1 and the second transistor T2 may be second-type transistors. The transistor types of the first-type transistors and the second-type transistors may be different. In some examples, the first-type transistors may be P-type transistors, such as low-temperature polysilicon thin-film transistors, and the second-type transistors may be N-type transistors, such as oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistors may be low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistors may be oxide semiconductors (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, reduce power consumption, and improve display quality. In this example, the first transistor T1 and the second transistor T2 are oxide thin film transistors, which can help reduce leakage at the first node and the fourth node.

[0097] Figure 4 shows an exemplary structure of the driving sub-circuit 11, the first voltage writing sub-circuit 12, the second voltage writing sub-circuit 13, the write control sub-circuit 15, the coupling sub-circuit 16, the storage sub-circuit 17, the first reset sub-circuit 14, the second reset sub-circuit 20, the first control sub-circuit 18 and the second control sub-circuit 19. It is easy for those skilled in the art to understand that the implementation method of the above-mentioned sub-circuits is not limited to this, as long as the corresponding functions can be realized.

[0098] Figures 5A and 5B are operating timing diagrams of the pixel circuit shown in Figure 4. Figure 5B illustrates simulation results from the first node N1 to the fifth node N5. In Figure 5B, within one display cycle, the duration of the effective level signal of the compensation control signal is five times (i.e., 5 hours) the duration of the data writing duration (1 hour). The data writing duration can be the same as the duration of the effective level signal of the first scanning signal.

[0099] In some examples, as shown in Figure 4, the pixel circuit of this example may include: 8 transistors (i.e., the first transistor T1 to the eighth transistor T8), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 9 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the first reset control line RST1, the second reset control line RST2, the compensation control line GP, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3), and 2 power supply terminals (i.e., the first power line VDD and the second power line VSS).

[0100] In some examples, as shown in Figures 5A and 5B , within a display cycle, the operation process of the pixel circuit may include the following stages: In this example, the second reset control signal may be the same as the compensation control signal.

[0101] In the first phase S1, the first control signal provided by the first control line EML1 is at a low level, turning on the fifth transistor T5. The second control signal provided by the second control line EML2 is at a high level, turning off the sixth transistor T6. The first scan signal provided by the first scan line GL1 is at a high level, turning off the fourth transistor T4. The second scan signal provided by the second scan line GL2 is at a low level, turning off the second transistor T2. The compensation control signal provided by the compensation control line GP is at a high level, turning off the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 is at a high level, turning on the first transistor T1. The first initial signal transmitted by the first initial signal line INIT1 is written to the first node N1. The voltage of the first node N1 is reset using the first initial signal, so that the voltage Vn1 of the first node N1 equals Vinit1. Vinit1 is the first initial signal. The voltage value of the first initial signal can be less than 0.

[0102] In the second phase S2, the first control signal provided by the first control line EML1 remains at a low level, and the fifth transistor T5 remains in the on state. The second control signal provided by the second control line EML2 remains at a high level, and the sixth transistor T6 remains in the off state. The first scan signal provided by the first scan line GL1 is at a high level, and the fourth transistor T4 remains in the off state. The second scan signal provided by the second scan line GL2 switches to a high level, turning on the second transistor T2, thereby conducting current between the third node N3 and the fourth node N4. The compensation control signal provided by the compensation control line GP remains at a high level, and the seventh transistor T7 and the eighth transistor T8 remain in the off state. The first reset control signal provided by the first reset control line RST1 remains at a high level, and the first transistor T1 remains in the on state.

[0103] In the second phase S2, the first transistor T1 is turned on and writes the first initial signal to the first node N1. The first voltage signal Vdd provided by the first power line VDD can be written to the fourth node N4 in sequence through the conductive fifth transistor T5, the second node N2, the conductive third transistor T3, the third node N3, and the conductive second transistor T2, thereby charging the potential of the fourth node N4 so that the voltage Vn4 of the fourth node N4 equals Vdd.

[0104] The third stage S3 can also be called the threshold compensation stage. The first control signal provided by the first control line EML switches to a high level, turning off the fifth transistor T5. The second control signal provided by the second control line EML2 remains high, and the sixth transistor T6 remains off. The first scan signal provided by the first scan line GL1 remains high, and the fourth transistor T4 remains off. The second scan signal provided by the second scan line GL2 remains high, and the second transistor T2 remains on. The compensation control signal provided by the compensation control line GP switches to a low level, turning on the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 remains high, and the first transistor T1 remains on.

[0105] In the third stage S3, the first transistor T1 is in the on state, writing the first initial signal to the first node N1. The second initial signal provided by the second initial signal line INIT2 is sequentially written to the fourth node N4 through the conductive seventh transistor T7, the second node N2, the conductive third transistor T3, the third node N3, and the conductive second transistor T2, thereby compensating the threshold voltage of the third transistor T3. In this stage, the fourth node N4 can be used to reversely charge the third transistor T3 until the potential Vn4 of the fourth node N4 equals Vinit1 - Vth, so that the voltage difference Vgs between the gate and the first electrode of the third transistor T3 equals Vth, where Vth is the threshold voltage of the third transistor T3. In this stage, the threshold voltage of the third transistor can be fully written to the fourth node N4.

[0106] In the third stage S3 , the eighth transistor T8 is turned on, and the third initial signal provided by the third initial signal line INIT3 is written into the fifth node N5 , thereby initializing the fifth node N5 .

[0107] The fourth stage S4 can also be called the data writing stage. The first control signal provided by the first control line EML1 remains at a high level, and the fifth transistor T5 remains in the off state. The second control signal provided by the second control line EML2 remains at a high level, and the sixth transistor T6 remains in the off state. The first scan signal provided by the first scan line GL1 switches to a low level, turning on the fourth transistor T4. The second scan signal provided by the second scan line GL2 remains at a high level, and the second transistor T2 is in the on state. The compensation control signal provided by the compensation control line GP switches to a high level, turning off the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 is at a low level, turning off the first transistor T1.

[0108] In the fourth stage S4, the first transistor T1 is turned off and the fourth transistor T4 is turned on. The data signal transmitted by the data line DL can be written to the fourth node N4 through the conductive fourth transistor T4, the third node N3, and the conductive second transistor T2 in sequence. At this time, the transition voltage ΔVn4 of the fourth node N4 is equal to Vdata-(Vinit1-Vth), where Vdata is the voltage value of the data signal. Through the coupling effect of the second capacitor C2, the transition voltage of the fourth node N4 can be written to the first node, so that the voltage of the first node Vn1 is equal to Vinit1+(Vdata-(Vinit1-Vth))=Vdata+Vth.

[0109] After the fourth stage S4 and before the fifth stage S5, the first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 can remain at a high level, turning off the fifth transistor T5 and the sixth transistor T6. The first scan signal provided by the first scan line GL1 can remain at a high level, turning off the fourth transistor T4. The second scan signal provided by the second scan line GL2 can switch from a high level to a low level, turning off the second transistor T2. The compensation control signal provided by the compensation control line GP can remain at a high level, turning off the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 can remain at a low level, turning off the first transistor T1.

[0110] The fifth stage S5 can also be called the light-emitting stage. The first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 are switched to a low level, turning on the fifth transistor T5 and the sixth transistor T6. The first scan signal provided by the first scan line GL1 is at a high level, turning off the fourth transistor T4. The second scan signal provided by the second scan line GL2 is at a low level, turning off the second transistor T2. The compensation control signal provided by the compensation control line GP is at a high level, turning off the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 is at a low level, turning off the first transistor T1.

[0111] In the fifth stage S5 , the first voltage signal outputted by the first power line VDD can provide a driving signal to the first electrode of the light emitting element EL through the conductive fifth transistor T5 , the conductive third transistor T3 and the conductive sixth transistor T6 , thereby driving the light emitting element EL to emit light.

[0112] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage Vn1 of the first node N1 = Vdata + Vth, the driving current of the third transistor T3 is: I = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vdata+Vth-Vdd-Vth) 2 =0.5×K×(Vdata-Vdd) 2 .

[0113] Wherein, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the voltage value of the data signal transmitted by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0114] It can be seen from this that the driving current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3, and only depends on the data signal provided by the data line and the first voltage signal provided by the first power line. The pixel circuit of this example can compensate for the threshold voltage of the third transistor T3, eliminate the influence of the threshold voltage of the third transistor T3 on the driving current, and thus ensure uniform display brightness of the display substrate and improve the display effect.

[0115] In some examples, the compensation writing of the threshold voltage of the driving transistor can be completed within the duration of the effective level signal of the compensation control signal, and the writing of the data signal can be completed within the duration of the effective level signal of the first scanning signal. For example, within a display cycle, the duration of the effective level signal of the compensation control signal can be five times, ten times, or twenty times the duration of the effective level signal of the first scanning signal. By controlling the compensation writing of the threshold voltage and the writing of the data signal separately, it is beneficial to reduce the writing time of the data writing and increase the compensation time of the threshold voltage, so that the compensation of the threshold voltage is not affected by the data signal writing process, and can support the full compensation of the threshold voltage at a high refresh rate, thereby facilitating the support of display products with a high refresh rate, improving display brightness, and improving display uniformity.

[0116] In some examples, when the pixel circuit is applied to a low-frequency display scenario, a first reset control signal and a second scan signal driven at a low frequency may be used, and a compensation control signal, a first scan signal, a first control signal, and a second control signal driven at a high frequency may be used.

[0117] In some examples, the display substrate may include five different gate drive circuits (e.g., a first gate drive circuit, a second gate drive circuit, a third gate drive circuit, a fourth gate drive circuit, and a fifth gate drive circuit). For example, the first control signal may be generated by the first gate drive circuit, the second control signal may be generated by the second gate drive circuit, the compensation control signal and the second reset control signal may be generated by the third gate drive circuit, the first scan signal may be generated by the fourth gate drive circuit, and the second scan signal and the first reset control signal may be generated by the fifth gate drive circuit. For example, the first reset control signal received by a pixel circuit may be generated by the nth stage shift register unit of the fifth gate drive circuit, and the second scan signal received by the pixel circuit may be generated by the n+7th stage shift register unit of the fifth gate drive circuit, where n may be a natural number. The duration of the effective level signal (e.g., a low level signal) of the compensation control signal may be adjustable. For example, the duration of the effective level signal of the compensation control signal may be flexibly adjusted according to charging requirements.

[0118] FIG6 is another schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG6 , the pixel circuit of this embodiment may include: a driving subcircuit 11, a first voltage writing subcircuit 12, a second voltage writing subcircuit 13, a first reset subcircuit 14, a writing control subcircuit 15, a coupling subcircuit 16, a storage subcircuit 17, a first control subcircuit 18, a second control subcircuit 19, a second reset subcircuit 20, and a third voltage writing subcircuit 21. The third voltage writing subcircuit 21 is coupled to the third node N3, the third scan line GL3, and the fourth initial signal line INIT4, and is configured to write the fourth initial signal provided by the fourth initial signal line INIT4 to the third node N3 under the control of the third scan line GL3 before the threshold compensation phase. The remaining structure of the pixel circuit of this embodiment can be referred to the description of the previous embodiment, and therefore will not be repeated here.

[0119] In some examples, the first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 may be the same. In this example, the operation timings of the first control sub-circuit 18 and the second control sub-circuit 19 may be the same.

[0120] In some examples, the first initial signal provided by the first initial signal line INIT1 and the second initial signal provided by the second initial signal line INIT2 can be the same, and the fourth initial signal provided by the fourth initial signal line INIT4 can be greater than the first initial signal provided by the first initial signal line INIT1. For example, the voltage value of the fourth initial signal can be positive, and the voltage value of the first initial signal can be negative. In this example, the fourth initial signal can be used to charge the fourth node before the threshold compensation phase, and the voltage of the fourth node can be used to reversely charge the driver sub-circuit during the threshold compensation phase to achieve threshold voltage compensation writing.

[0121] In some examples, within a display cycle, the duration of the effective level signal of the first scan signal provided by the first scan line GL1 and the duration of the effective level signal of the third scan signal provided by the third scan line GL3 can be the same. The end time of the effective level signal of the third scan signal can be earlier than the start time of the effective level signal of the first scan signal. In some examples, the first scan signal and the third scan signal can be provided by the same gate drive circuit. For example, the mth stage shift register unit of a gate drive circuit provides the third scan signal, and the m+7th stage shift register unit can provide the first scan signal, where m can be a natural number. This embodiment is not limited to this.

[0122] FIG7 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG7 , the driver subcircuit 11 of the pixel circuit of this example may include a third transistor T3; the first voltage writing subcircuit 12 may include a fourth transistor T4; the second voltage writing subcircuit 13 may include a seventh transistor T7; the first reset subcircuit 14 may include a first transistor T1; the write control subcircuit 15 may include a second transistor T2; the coupling subcircuit 16 may include a second capacitor C2; the storage subcircuit 17 may include a first capacitor C1; the first control subcircuit 18 may include a fifth transistor T5; the second control subcircuit 19 may include a sixth transistor T6; the second reset subcircuit 20 may include an eighth transistor T8; and the third voltage writing subcircuit 21 may include a ninth transistor T9.

[0123] In some examples, as shown in FIG7 , the gate of the ninth transistor T9 is coupled to the third scan line GL3, the first electrode is coupled to the fourth initial signal line INIT4, and the second electrode is coupled to the third node N3. The ninth transistor T9 can be configured to write the fourth initial signal transmitted by the fourth initial signal line INIT4 to the third node N3 under the control of the third scan line GL3. The connection relationship between the remaining transistors and capacitors of the pixel circuit of this example can be as described above, and thus will not be repeated here.

[0124] In some examples, as shown in Figure 7, the first node N1 is the connection point of the first transistor T1, the third transistor T3, the first capacitor C1 and the second capacitor C2; the second node N2 is the connection point of the third transistor T3, the seventh transistor T7 and the fifth transistor T5; the third node N3 is the connection point of the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9; the fourth node N4 is the connection point of the second capacitor C2 and the second transistor T2; and the fifth node N5 is the connection point of the sixth transistor T6, the eighth transistor T8 and the light-emitting element EL.

[0125] In some examples, as shown in Figure 7, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 in the pixel circuit can be first type transistors, such as P-type transistors; the first transistor T1 and the second transistor T2 can be second type transistors, such as N-type transistors.

[0126] 8A and 8B are operation timing diagrams of the pixel circuit shown in FIG7 . FIG8B illustrates simulation results of the first node N1 to the fifth node N5. In some examples, as shown in FIG7 , the pixel circuit of this example may include: 9 transistors (i.e., the first transistor T1 to the ninth transistor T9), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 10 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the third scan line GL3, the first reset control line RST1, the compensation control line GP, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, and the fourth initial signal line INIT4), and 2 power supply terminals (i.e., the first power line VDD and the second power line VSS).

[0127] In some examples, as shown in Figures 8A and 8B , within a display cycle, the operation process of the pixel circuit may include the following stages: In this example, the second reset control signal and the compensation control signal are the same.

[0128] In the first phase S1, the first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 are both high, turning off the fifth transistor T5 and the sixth transistor T6. The second scan signal provided by the second scan line GL2 is low, turning off the second transistor T2. The first scan signal provided by the first scan line GL1 is high, turning off the fourth transistor T4. The third scan signal provided by the third scan line GL3 is high, turning off the ninth transistor T7. The compensation control signal provided by the compensation control line GP is high, turning off the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 is high, turning on the first transistor T1. The first initial signal transmitted by the first initial signal line INIT1 is written to the first node N1. The voltage of the first node N1 is reset using the first initial signal, so that the voltage Vn1 of the first node N1 equals Vinit1. Vinit1 is the voltage value of the first initial signal. The voltage value of the first initial signal can be less than 0.

[0129] In the second phase S2, the first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 are both at a high level, and the fifth transistor T5 and the sixth transistor T6 are in the off state. The first scan signal provided by the first scan line GL1 is at a high level, and the fourth transistor T4 remains in the off state. The second scan signal provided by the second scan line GL2 switches to a high level, turning on the second transistor T2, thereby conducting current between the third node N3 and the fourth node N4. The compensation control signal provided by the compensation control line GP remains at a high level, and the seventh transistor T7 and the eighth transistor T8 remain in the off state. The first reset control signal provided by the first reset control line RST1 remains at a high level, and the first transistor T1 remains in the on state. The third scan signal provided by the third scan line GL3 is switched to a low level, the ninth transistor T9 is turned on, and the fourth initial signal provided by the fourth initial signal line INIT4 can be written into the fourth node N4 in sequence through the turned-on ninth transistor T9, the third node N3, and the turned-on second transistor T2, and the potential of the fourth node N4 is charged, so that the voltage Vn4 of the fourth node N4 is equal to Vinit4, Vinit4 is the fourth initial signal, and the voltage value of the fourth initial signal can be greater than 0.

[0130] The third stage S3 can also be called the threshold compensation stage. The first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 are both high, turning off the fifth transistor T5 and the sixth transistor T6. The first scan signal provided by the first scan line GL1 is high, and the fourth transistor T4 remains off. The second scan signal provided by the second scan line GL2 is high, turning on the second transistor T2 and conducting current between the third node N3 and the fourth node N4. The third scan signal provided by the third scan line GL3 is high, turning off the ninth transistor T7. The compensation control signal provided by the compensation control line GP switches to a low level, turning on the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 remains high, and the first transistor T1 remains on.

[0131] In the third stage S3, the second initial signal provided by the second initial signal line INIT2 can be written into the fourth node N4 in sequence through the conductive seventh transistor T7, the second node N2, the conductive third transistor T3, the third node N3, and the conductive second transistor T2, thereby compensating the threshold voltage of the third transistor T3. In this stage, the fourth node N4 can be used to reversely charge the third transistor T3 until the potential Vn4 of the fourth node N4 reaches Vinit1 - Vth, so that the voltage difference Vgs between the gate and the first electrode of the third transistor T3 equals Vth, where Vth is the threshold voltage of the third transistor T3. In this stage, the threshold voltage of the third transistor can be fully written into the fourth node N4.

[0132] The fourth stage S4 can also be called the data writing stage. The first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 are both high, turning off the fifth transistor T5 and the sixth transistor T6. The first reset control signal provided by the first reset control line RST1 switches to a low level, turning off the first transistor T1. The second scan signal provided by the second scan line GL2 is high, turning on the second transistor T2 and conducting between the third node N3 and the fourth node N4. The third scan signal provided by the third scan line GL3 is high, turning off the ninth transistor T7. The compensation control signal provided by the compensation control line GP switches to a high level, turning off the seventh transistor T7 and the eighth transistor T8. The first scan signal provided by the first scan line GL1 switches to a low level, turning on the fourth transistor T4. The data signal transmitted by the data line DL can be written to the fourth node N4 in sequence through the conducting fourth transistor T4, the third node N3, and the conducting second transistor T2. At this time, the trip voltage ΔVn4 of the fourth node N4 is Vdata - (Vinit1 - Vth), where Vdata is the voltage value of the data signal. Through the coupling effect of the second capacitor C2, the jump voltage of the fourth node N4 can be written into the first node, so that the voltage of the first node Vn1 = Vinit1 + (Vdata - (Vinit1 - Vth)) = Vdata + Vth.

[0133] The fifth stage S5 can also be called the light-emitting stage. The first control signal provided by the first control line EML1 and the second control signal provided by the second control line EML2 are switched to a low level, turning on the fifth transistor T5 and the sixth transistor T6. The first scan signal provided by the first scan line GL1 is high, turning off the fourth transistor T4. The second scan signal provided by the second scan line GL2 is low, turning off the second transistor T2. The compensation control signal provided by the compensation control line GP is high, turning off the seventh transistor T7 and the eighth transistor T8. The first reset control signal provided by the first reset control line RST1 is low, turning off the first transistor T1. The third scan signal provided by the third scan line GL3 is high, turning off the ninth transistor T9.

[0134] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage Vn1 of the first node N1 = Vdata + Vth, the driving current of the third transistor T3 is: I = 0.5 × K × (Vgs - Vth) 2 =0.5×K×(Vdata+Vth-Vdd-Vth) 2 =0.5×K×(Vdata-Vdd) 2 .

[0135] In some examples, during a display period, the duration of the active level signal (e.g., a high level signal) of the second scan signal provided by the second scan line GL2 can be greater than the sum of the durations of the active level signal (e.g., a low level signal) of the first scan signal, the active level signal (e.g., a low level signal) of the third scan signal, and the active level signal (e.g., a low level signal) of the compensation control signal. In this example, charging the fourth node N4, writing the threshold voltage to the fourth node N4, and writing the data signal are all written through the path where the second transistor T2 is located.

[0136] In some examples, the display substrate may include four different gate drive circuits. For example, the first control signal and the second control signal may be generated by the same gate drive circuit, the first scan signal and the third scan signal may be generated by the same gate drive circuit, the second scan signal and the first reset control signal may be generated by the same gate drive circuit, and the compensation control signal may be generated by a gate drive circuit. For example, the first control signal and the second control signal received by a pixel circuit may be generated by the same level shift register unit of the same gate drive circuit. For example, the third scan signal received by a pixel circuit may be generated by the mth level shift register unit of a gate drive circuit, and the first scan signal received by the pixel circuit may be generated by the m+7th level shift register unit of the gate drive circuit, where m may be a natural number. The remaining description of the working timing of the pixel circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0137] FIG9 is a flowchart of a method for driving a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG9 , the method for driving a pixel circuit according to this example may include the following steps:

[0138] Step 701: Under the control of a first reset control line, a first reset sub-circuit writes a first initial signal provided by a first initial signal line into a first node.

[0139] Step 702: In the threshold compensation stage, the second voltage writing sub-circuit writes the threshold voltage of the driving sub-circuit into the third node under the control of the compensation control line. The writing control circuit, under the control of the second scan line, connects the third node and the fourth node and writes the threshold voltage into the fourth node.

[0140] Step 703: In the data writing phase, the first voltage writing sub-circuit writes the data signal provided by the data line into the third node under the control of the first scan line, the writing control circuit writes the data signal into the fourth node, and the coupling sub-circuit couples the signal written into the fourth node to the first node.

[0141] Step 704: The driving sub-circuit provides a driving signal to the third node under the control of the first node.

[0142] In some examples, within a display period, the threshold compensation phase may be located before the data writing phase, and the duration of the threshold compensation phase may be greater than the duration of the data writing phase.

[0143] In some examples, the driving method of this example may further include: before the threshold compensation stage, the first control subcircuit, under the control of the first control line, uses the first voltage signal provided by the first power line to charge the fourth node.

[0144] In some examples, the pixel circuit further includes: a third voltage writing subcircuit coupled to the third node, the third scan line, and the fourth initial signal line. The driving method of this example may further include: before the threshold compensation stage, the third voltage writing subcircuit, under control of the third scan line, charging the fourth node using a fourth initial signal provided by the fourth initial signal line; wherein the fourth initial signal is greater than the second initial signal.

[0145] In some examples, within a display cycle, the duration of the effective level signal of the second scan signal provided by the second scan line is greater than the sum of the durations of the effective level signal of the first scan signal provided by the first scan line, the effective level signal of the third scan signal provided by the third scan line, and the effective level signal of the compensation control signal provided by the compensation control line.

[0146] Regarding the driving method of the pixel circuit of this embodiment, reference can be made to the description of the aforementioned embodiment, and thus no further details will be given here.

[0147] This embodiment also provides a display substrate, comprising: a substrate, a circuit structure layer arranged on the substrate, the circuit structure layer comprising a plurality of pixel circuits, at least one pixel circuit comprising: a first capacitor and a second capacitor. The second capacitor is located on a side of the first capacitor away from the substrate, and the orthographic projection of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate. The first capacitor comprises: a first plate and a second plate, and the second capacitor comprises: a third plate and a fourth plate. The second plate of the first capacitor is located on a side of the first plate away from the substrate, the third plate of the second capacitor is located on a side of the fourth plate away from the substrate, and the fourth plate of the second capacitor is located on a side of the second plate of the first capacitor away from the substrate; the first plate of the first capacitor is connected to the fourth plate of the second capacitor.

[0148] The display substrate provided in this embodiment has two capacitors in a stacked arrangement that are connected to each other and included in the pixel circuit, which can save space occupied by the pixel circuit, thereby realizing a high-resolution display substrate.

[0149] In some exemplary embodiments, the second plate of the first capacitor may have a hollowed-out area, and the connection position of the first plate and the fourth plate may be located within the orthographic projection of the hollowed-out area on the substrate. In this example, the electrical connection between the first plate and the fourth plate is achieved by providing a hollowed-out area on the second plate. However, this embodiment is not limited to this. In other examples, the second plate may have a recessed portion, and the fourth plate may be electrically connected to the first plate at a position corresponding to the recessed portion.

[0150] In some exemplary embodiments, the orthographic projection of the third plate of the second capacitor on the substrate may overlap the orthographic projections of the first plate and the fourth plate on the substrate. In this example, by providing the third plate to overlap the first plate and the fourth plate, the potential stability of the node connected to the first plate and the fourth plate can be ensured.

[0151] In some exemplary embodiments, the second plates of the first capacitors of a plurality of pixel circuits arranged along a first direction may be interconnected integrally, and the integrally connected structure and the first power line extending along a second direction may be connected to form a mesh structure for transmitting the first voltage signal. The first power line may be located on a side of the integral structure away from the substrate. The first direction and the second direction may intersect; for example, the first direction may be perpendicular to the second direction. This example facilitates uniform transmission of the first voltage signal by forming a mesh structure for transmitting the first voltage signal.

[0152] In some exemplary embodiments, the integrated structure formed by connecting the second plates of the first capacitors of a plurality of pixel circuits arranged along the first direction may be connected to the first power line via a ninth connection electrode. The ninth connection electrode may be located on a side of the integrated structure away from the substrate and on a side of the first power line closer to the substrate. For example, the second plate may be located on the second conductive layer, the ninth connection electrode may be located on the fourth conductive layer, and the first power line may be located on the fifth conductive layer.

[0153] In some exemplary embodiments, the pixel circuit is connected to a first initial signal line, a second initial signal line, and a third initial signal line. The first initial signal line, the second initial signal line, and the third initial signal line may be located on different conductive layers. In this example, disposing the first initial signal line, the second initial signal line, and the third initial signal line on different conductive layers can help save wiring layout space.

[0154] In some exemplary embodiments, a pixel circuit may include at least one first-type transistor and at least one second-type transistor. In a direction perpendicular to the display substrate, the circuit structure layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The first semiconductor layer may include an active layer for the at least one first-type transistor, and the second semiconductor layer may include an active layer for the at least one second-type transistor.

[0155] In some exemplary embodiments, the first plate of the first capacitor may be located on the first conductive layer, and the second plate of the first capacitor may be located on the second conductive layer; the third plate of the second capacitor may be located on the fifth conductive layer, and the fourth plate of the second capacitor may be located on the fourth conductive layer. In this example, by stacking the first and second capacitors perpendicular to the display substrate, the space occupied by the two capacitors can be reduced.

[0156] In some exemplary embodiments, the pixel circuit is electrically connected to a first initial signal line. The first initial signal line may be located in the fourth conductive layer. The orthographic projection of the first initial signal line on the substrate may at least partially overlap with the orthographic projections of lines located in the second and third conductive layers on the substrate. In this example, by arranging the first initial signal line to overlap with the lines in the remaining conductive layers, wiring layout space can be saved.

[0157] In some exemplary embodiments, the pixel circuit is electrically connected to the second initial signal line and the third initial signal line. The third initial signal line may be located in the second conductive layer, the second initial signal line may be located in the third conductive layer, and the orthographic projections of the second initial signal line and the third initial signal line on the substrate may at least partially overlap. In this example, by stacking the second initial signal line and the third initial signal line located in different conductive layers, wiring layout space can be saved.

[0158] In some exemplary embodiments, a plurality of pixel circuits may be divided into a plurality of pixel circuit groups, each pixel circuit group including two pixel circuits adjacently arranged along a first direction, wherein the two pixel circuits in the pixel circuit group are symmetrically arranged about a first midline of the pixel circuit group in the first direction. In the present disclosure, "symmetry" may refer to loosely defined boundaries, allowing for generally symmetric conditions within the range of process and measurement errors. This example utilizes symmetrical pixel circuit arrangement to conserve pixel circuit space.

[0159] Figure 10 is a partial planar schematic diagram of the circuit structure layer of the display substrate of at least one embodiment of the present disclosure. In some examples, the circuit structure layer may include a plurality of pixel circuits arranged in an array. A plurality of pixel circuits arranged in sequence along a first direction X may be referred to as a row of pixel circuits, and a plurality of pixel circuits arranged in sequence along a second direction Y may be referred to as a column of pixel circuits. The first direction X may be perpendicular to the second direction Y. Figure 10 illustrates two rows and four columns of pixel circuits, for example, including the i-th row and the i+1-th row, the j-th column, the j+1-th column, the j+2-th column, and the j+3-th column, where i and j may be integers greater than 0. Figure 11 is a partial cross-sectional schematic diagram along the Q-Q' direction in Figure 10.

[0160] In some examples, as shown in FIG10 , in a direction parallel to the display substrate, the plurality of pixel circuits of the circuit structure layer can be divided into a plurality of pixel circuit groups, each pixel circuit group can include two pixel circuits arranged adjacent to each other along a first direction X. The two pixel circuits within each pixel circuit group can be symmetrically arranged about the first center line of the pixel circuit group along the first direction X. Taking a pixel circuit group including a pixel circuit 30a located in the i-th row and j-th column and a pixel circuit 30b located in the i-th row and j+1-th column as an example, the pixel circuits 30a and 30b within the pixel circuit group can be symmetrically arranged about the first center line O1. Two adjacent pixel circuit groups can be symmetrically arranged about the second center line of the two pixel circuit groups along the first direction X. For example, a pixel circuit group including pixel circuits 30a and 30b can be symmetrically arranged about the second center line O2 with respect to the pixel circuit group adjacent to the right. This example adopts a symmetrical arrangement of the two pixel circuits within the pixel circuit group, which can help reduce the space occupied by the pixel circuits, thereby realizing a high-resolution display substrate.

[0161] In some examples, as shown in FIG11 , in a direction perpendicular to the display substrate, the circuit structure layer may include: a first semiconductor layer 210, a first conductive layer 211, a second conductive layer 212, a second semiconductor layer 220, a third conductive layer 213, a fourth conductive layer 214, and a fifth conductive layer 215, sequentially disposed on the substrate 200. In some examples, the first conductive layer 211 may also be referred to as a first gate metal layer, the second conductive layer 212 may also be referred to as a second gate metal layer, the third conductive layer 213 may also be referred to as a third gate metal layer, the fourth conductive layer 214 may also be referred to as a first source-drain metal layer, and the fifth conductive layer 215 may also be referred to as a second source-drain metal layer. In some examples, a light-emitting structure layer and an encapsulation structure layer may be disposed on the side of the circuit structure layer away from the substrate 200. The light-emitting structure layer may include multiple light-emitting elements.

[0162] In some examples, as shown in FIG11 , the circuit structure layer may further include at least: first to sixth insulating layers 201 to 206. The first insulating layer 201 may be located between the first semiconductor layer 210 and the first conductive layer 211, the second insulating layer 202 may be located between the first conductive layer 211 and the second conductive layer 212, the third insulating layer 203 may be located between the second conductive layer 212 and the second semiconductor layer 220, the fourth insulating layer 204 may be located between the second semiconductor layer 220 and the third conductive layer 213, the fifth insulating layer 205 may be located between the third conductive layer 213 and the fourth conductive layer 214, and the sixth insulating layer 206 may be located between the fourth conductive layer 214 and the fifth conductive layer 215. In some examples, the first to fifth insulating layers 201 to 205 may be inorganic insulating layers, and the sixth insulating layer 206 may be an organic insulating layer. However, this embodiment is not limited thereto.

[0163] The structure and preparation process of the display substrate are exemplarily described below with reference to Figures 10 to 20. The "patterning process" mentioned in the embodiments of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0164] The terms "A and B are arranged in the same layer" and "A and B are in the same layer structure" mentioned in the present disclosure mean that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0165] The equivalent circuit of the pixel circuit of the circuit structure layer of this example can be shown in Figure 4. The pixel circuit may include six first-type transistors and two second-type transistors. The transistor types of the first-type transistors and the second-type transistors may be different. For example, the first-type transistor may be a low-temperature polysilicon thin-film transistor, and the second-type transistor may be an oxide thin-film transistor. In this example, the first transistor and the second transistor of the pixel circuit may be oxide thin-film transistors, and the third to eighth transistors may be low-temperature polysilicon thin-film transistors.

[0166] The following describes the structure of the pixel circuit 30a located in the i-th row and j-th column and the pixel circuit 30b located in the i-th row and j+1-th column as an example. The pixel circuit 30a may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, a first capacitor 41a, and a second capacitor 42a. The pixel circuit 30b may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, a first capacitor 41b, and a second capacitor 42b.

[0167] In some examples, the preparation process of the display substrate may include the following operations.

[0168] (1) Provide a substrate. In some examples, the substrate 200 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si). This embodiment does not limit this.

[0169] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the first semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0170] FIG. 12 is a schematic diagram of the display substrate after the first semiconductor layer is formed in FIG. 10 . In some examples, as shown in FIG12 , the first semiconductor layer of the display substrate may include at least: active layers of multiple first-type transistors of multiple pixel circuits (for example, may include: active layer 330a of the third transistor, active layer 340a of the fourth transistor, active layer 350a of the fifth transistor, active layer 360a of the sixth transistor, active layer 370a of the seventh transistor, and active layer 380a of the eighth transistor of the pixel circuit of the i-th row and j-th column; active layer 330b of the third transistor, active layer 340b of the fourth transistor, active layer 350b of the fifth transistor, active layer 360b of the sixth transistor, active layer 370b of the seventh transistor, and active layer 380b of the eighth transistor of the pixel circuit of the i-th row and j+1 column; active layer 380a' of the eighth transistor of the pixel circuit of the i-1-th row and j+1 column; active layer 380b' of the eighth transistor of the pixel circuit of the i-1-th row and j+1 column). In some examples, the active layer of each first-type transistor of the pixel circuit may include: at least one channel region, and a first region and a second region located on opposite sides of the channel region.

[0171] In some examples, as shown in FIG12 , the active layer 370a of the seventh transistor in the pixel circuit in the i-th row and j-th column is located on one side of the active layer 330a of the third transistor in the second direction Y, and the active layer 360a of the sixth transistor and the active layer 380a of the eighth transistor are located on a side opposite to the second direction Y of the active layer 330a of the third transistor. The active layer 340a of the fourth transistor is located on a side opposite to the first direction X of the active layer 330a of the third transistor, and the active layer 350a of the fifth transistor is located on a side of the active layer 330a of the third transistor in the first direction X. The active layer 380a′ of the eighth transistor in the pixel circuit in the i-1-th row and j-th column may be located on one side of the active layer 370a of the seventh transistor in the pixel circuit in the i-th row and j-th column and aligned in the first direction X. The active layer 380a of the eighth transistor in the pixel circuit in the i-th row and j-th column may be aligned in the first direction with the active layer of the seventh transistor in the pixel circuit in the i+th row and j-th column. The configuration of this example is helpful in saving the space occupied by the pixel circuit.

[0172] In some examples, as shown in FIG12 , the first semiconductor layer pattern of the pixel circuit in the i-th row and j-th column can be substantially symmetrical with the first semiconductor layer pattern of the pixel circuit in the i-th row and j+1-th column about the first center line O1. This configuration can facilitate subsequent sharing of vias and traces, thereby saving space occupied by the pixel circuits.

[0173] In some examples, as shown in FIG12 , the active layer 330 a of the third transistor, the active layer 340 a of the fourth transistor, and the active layer 350 a of the fifth transistor in the pixel circuit in the i-th row and j-th column can be interconnected as an integrated structure; the active layer 360 a of the sixth transistor and the active layer 380 a of the eighth transistor can be interconnected as an integrated structure. The first region of the active layer 330 a of the third transistor is directly connected to the second region of the active layer 350 a of the fifth transistor, and the second region of the active layer 330 a of the third transistor is directly connected to the second region of the active layer 340 a of the fourth transistor. The second region of the active layer 360 a of the sixth transistor is directly connected to the second region of the active layer 380 a of the eighth transistor.

[0174] In some examples, the first region of the active layer 340a of the fourth transistor, the first region of the active layer 350a of the fifth transistor, the first region of the active layer 360a of the sixth transistor, the first and second regions of the active layer 370a of the seventh transistor, and the first region of the active layer 380a of the eighth transistor can be set independently.

[0175] In some examples, as shown in FIG12 , the active layer 330 a of the third transistor may be substantially U-shaped; the active layer 340 a of the fourth transistor, the active layer 350 a of the fifth transistor, the active layer 360 a of the sixth transistor, the active layer 370 a of the seventh transistor, and the active layer 380 a of the eighth transistor may be substantially I-shaped. This embodiment is not limited thereto.

[0176] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure. The first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first insulating layer may also be referred to as a first gate insulating layer.

[0177] In some examples, after the first conductive layer is formed, the first semiconductor layer can be conductorized using the first conductive layer as a shield, and the first semiconductor layer in the area shielded by the first conductive layer forms a channel region of multiple first-type transistors, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the active layer of the first-type transistor are both conductorized.

[0178] FIG13A is a schematic diagram of the display substrate after forming the first conductive layer in FIG10 . FIG13B is a schematic diagram of the first conductive layer in FIG13A . In some examples, as shown in FIG13A and FIG13B , the first conductive layer of the display substrate may include at least: first scan lines (e.g., first scan lines GL1(i) and GL1(i+1)), compensation control lines (e.g., compensation control lines GP(i) and GP(i+1)), first control lines (e.g., first control lines EML1(i) and EML1(i+1)), second control lines (e.g., second control lines EML2(i) and EML2(i+1)), and first plates of first capacitors of a plurality of pixel circuits (e.g., first plates 411a and 411b).

[0179] In some examples, the shape of the first plate 411a of the first capacitor of the pixel circuit in the i-th row and j-th column can be approximately rectangular, for example, a rounded rectangle. The overlapping portion of the first plate 411a of the first capacitor and the active layer 330a of the third transistor 33a can serve as the gate of the third transistor 33a. The shape of the first plate 411b of the first capacitor of the pixel circuit in the i-th row and j+1-th column can be approximately rectangular, for example, a rounded rectangle. The overlapping portion of the first plate 411b of the first capacitor and the active layer 330b of the third transistor 33b can serve as the gate of the third transistor 33b. The first plates 411a and 411b can be approximately symmetrical about the first centerline O1.

[0180] In some examples, the first scan line GL1(i) can be substantially linear and extend along the first direction X. The first scan line GL1(i) can be located on one side of the first plates 411a and 411b in the second direction Y. The overlapping portion of the first scan line GL1(i) with the active layer 340a of the fourth transistor 34a in the pixel circuit of the i-th row and j-th column can serve as the gate of the fourth transistor 34a, and the overlapping portion with the active layer 340b of the fourth transistor 34b in the pixel circuit of the i-th row and j+1-th column can serve as the gate of the fourth transistor 34b. Along the first direction X, the first scan line GL1(i) can include: a first overlapping portion with the active layer 340a of the fourth transistor 34a; a second overlapping portion with the active layer 340b of the fourth transistor 34b; and an extension portion connecting the first overlapping portion and the second overlapping portion. The lengths of the first overlapping portion and the second overlapping portion along the second direction Y can be substantially the same, and the length of the first overlapping portion along the second direction Y can be greater than the length of the extension portion along the second direction Y. The configuration of this example can help ensure the performance of the fourth transistor and avoid the first scan line from overlapping with the remaining first semiconductor layer patterns.

[0181] In some examples, the compensation control lines GP(i) and GP(i+1) may be substantially straight lines extending along the first direction X. The compensation control line GP(i) may be located on one side of the first scan line GL1(i) in the second direction Y, and the compensation control line GP(i+1) may be located between the first scan line GL1(i+1) and the second control line EML2(i), and on one side of the second control line EML2(i) in the opposite direction to the second direction Y. The overlapping portion of the compensation control line GP(i) and the active layer 370a of the seventh transistor 37a of the pixel circuit in the i-th row and j-th column can serve as the gate of the seventh transistor 37a, the overlapping portion with the active layer 380a' of the eighth transistor 38a' of the pixel circuit in the i-1-th row and j-th column can serve as the gate of the eighth transistor 38a', the overlapping portion with the active layer 370b of the seventh transistor 37b of the pixel circuit in the i-th row and j+1-th column can serve as the gate of the seventh transistor 37b, and the overlapping portion with the active layer 380b' of the eighth transistor 38b' of the pixel circuit in the i-1-th row and j+1-th column can serve as the gate of the eighth transistor 38b'. The overlapping portion of the compensation control line GP(i+1) with the active layer 380a of the eighth transistor 38a in the pixel circuit of the i-th row and j-th column can serve as the gate of the eighth transistor 38a. The overlapping portion with the active layer of the seventh transistor in the pixel circuit of the i+1-th row and j-th column can serve as the gate of the seventh transistor. The overlapping portion with the active layer 380b of the eighth transistor 38b in the pixel circuit of the i-th row and j+1-th column can serve as the gate of the eighth transistor 38b. The overlapping portion with the active layer of the seventh transistor in the pixel circuit of the i+1-th row and j+1-th column can serve as the gate of the seventh transistor. In this example, the second reset control line connected to the gate of the eighth transistor in the pixel circuit of the current row can be connected to the compensation control line connected to the gate of the seventh transistor in the pixel circuit of the next row as an integrated structure.

[0182] In some examples, the first control line EML1(i) can be substantially in the shape of a zigzag line extending along the first direction X. The first control line EML1(i) can be located on a side of the first plates 411a and 411b opposite to the second direction Y. The first control line EML1(i) can be bent along the second direction Y. The overlapping portion of the first control line EML1(i) with the active layer 350a of the fifth transistor 35a in the pixel circuit of the i-th row and j-th column can serve as the gate of the fifth transistor 35a, and the overlapping portion of the first control line EML1(i) with the active layer 350b of the fifth transistor 35b in the pixel circuit of the i-th row and j+1-th column can serve as the gate of the fifth transistor 35b.

[0183] In some examples, the second control line EML2(i) can be substantially straight and extend along the first direction X. The second control line EML2(i) can be located on a side of the first control line EML1(i) opposite to the second direction Y. The overlapping portion of the second control line EML2(i) with the active layer 360a of the sixth transistor 36a in the pixel circuit in the i-th row and j-th column can serve as the gate of the sixth transistor 36a, and the overlapping portion of the second control line EML2(i) with the active layer 360b of the sixth transistor 36b in the pixel circuit in the i-th row and j+1-th column can serve as the gate of the sixth transistor 36b.

[0184] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned through a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second insulating layer may also be referred to as a second gate insulating layer.

[0185] FIG14A is a schematic diagram of the display substrate after the second conductive layer is formed in FIG10 . FIG14B is a schematic diagram of the second conductive layer in FIG14A . In some examples, as shown in FIG14A and FIG14B , the second conductive layer of the display substrate may include at least: a third initial signal line (e.g., third initial signal lines INIT3(i-1) and INIT3(i)), a first auxiliary line (e.g., RST1b(i) and RST1b(i+1)), a second auxiliary line (e.g., GL2b(i) and GL2b(i+1)), and second plates of first capacitors of a plurality of pixel circuits (e.g., second plates 412a and 412b).

[0186] In some examples, the orthographic projection of the second plate 412a of the first capacitor of the pixel circuit in the i-th row and j-th column on the substrate may partially overlap with the orthographic projection of the first plate 411a on the substrate. The orthographic projection of the second plate 412a on the substrate may, for example, cover the orthographic projection of the edge of the first plate 411a on the substrate. The second plate 412a may have a hollow area OPa, and the orthographic projection of the hollow area OPa on the substrate may be approximately rectangular, such as a rounded rectangle. The orthographic projection of the second plate 412a on the substrate may be approximately a rectangular ring. The orthographic projection of the hollow area OPa on the substrate may be located within the orthographic projection of the first plate 411a on the substrate. The second plate 412b of the first capacitor of the pixel circuit in the i-th row and j+1-th column may have a hollow area OPb, and the orthographic projection of the hollow area OPb on the substrate may be located within the orthographic projection range of the first plate 411b on the substrate. The orthographic projection of the second plate 412b on the substrate partially overlaps with the orthographic projection of the first plate 411b on the substrate. For example, the orthographic projection of the second plate 412b on the substrate may cover the orthographic projection of the edge of the first plate 411a on the substrate.

[0187] In some examples, adjacent second plates 412a and 412b within the same pixel circuit group can be connected via a first plate connecting block 413, while adjacent second plates 412a and 412b within different pixel circuit groups can be connected via a second plate connecting block 414. The first plate connecting block 413 and the second plate connecting block 414 can be substantially strip-shaped and extend along a first direction X. The length of the first plate connecting block 413 along the first direction X can be less than the length of the second plate connecting block 414 along the first direction X. The length of the first plate connecting block 413 along the second direction Y can be greater than the length of the second plate connecting block 414 along the second direction Y. The second plate 412b has an upper edge and a lower edge in the second direction Y. The distance between the first plate connecting block 413 and the lower edge of the second plate 412b can be less than the distance between the first plate connecting block 413 and the upper edge of the second plate 412b; and the distance between the second plate connecting block 414 and the lower edge of the second plate 412b can be greater than the distance between the second plate connecting block 414 and the upper edge of the second plate 412b. In this example, the second electrode plates 412 a and 412 b , the first electrode plate connecting block 413 , and the second electrode plate connecting block 414 adjacent to each other in the first direction X may be an integrated structure connected to each other.

[0188] In some examples, the third initial signal line INIT3(i-1) may be substantially linear and extend along the first direction X. The third initial signal line INIT3(i) may be located on one side of the second plates 412a and 412b in the second direction Y. An orthographic projection of the third initial signal line INIT3(i-1) on the substrate may at least partially overlap an orthographic projection of the compensation control line GP(i) located on the first conductive layer on the substrate.

[0189] In some examples, a first protrusion 451 may be provided on one side of the third initial signal line INIT3(i-1) close to the first electrode connection block 413, and the first protrusion 451 may be provided in each pixel circuit group. For example, the orthographic projection of the first protrusion 451 on the substrate may be located between the active layer 380a' of the eighth transistor 38a' and the active layer 380b' of the eighth transistor 38b'. The first protrusion 451 may be configured to be connected to the first region of the active layer 380a' of the eighth transistor 38a' and the first region of the active layer 380b' of the eighth transistor 38b' through the subsequently formed eighth connection electrode 508. In some examples, the third initial signal line INIT3(i-1) and the plurality of first protrusions 451 may be an integrated structure connected to each other.

[0190] In some examples, the first auxiliary line RST1b(i) may be located on one side of the second plates 412a and 412b in the opposite direction of the second direction Y. The first auxiliary line RST1b(i) may be substantially a straight line extending along the first direction X with uneven width.

[0191] In some examples, the second auxiliary line GL2b(i) may be located on a side of the first auxiliary line RST1b(i) in the opposite direction of the second direction Y and on a side of the first control line EML1(i) in the second direction Y. The second auxiliary line GL2b(i) may be substantially in the shape of a zigzag line extending along the first direction X.

[0192] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate forming the aforementioned structure, and the second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0193] FIG15A is a schematic diagram of the display substrate after the second semiconductor layer is formed in FIG10 . FIG15B is a schematic diagram of the second semiconductor layer in FIG15A . In some examples, as shown in FIG15A and FIG15B , the second semiconductor layer of the display substrate may include at least: active layers of second-type transistors of a plurality of pixel circuits (e.g., active layer 310 a of first transistor 31 a and active layer 320 a of second transistor 32 a in the pixel circuit of row i and column j; active layer 310 b of first transistor 31 b and active layer 320 b of second transistor 32 b in the pixel circuit of row i and column j+1).

[0194] In some examples, an orthographic projection of the active layer 310a of the first transistor 31a on the substrate may be located on a side of the active layer 340a of the fourth transistor 34a close to the active layer 330a of the third transistor 33a, and the active layer 320a of the second transistor 32a may be located on a side of the active layer 310a of the first transistor 31a in the first direction X. The active layer 310a of the first transistor 31a and the active layer 320a of the second transistor 32a are staggered in the first direction X. For example, the active layer 310a of the first transistor 31a may include a first end (i.e., a first region) and a second end (i.e., a second region) located on a side of the first end in the second direction Y. The active layer 320a of the second transistor 32a may include a first end (i.e., a first region) and a second end (i.e., a second region) located on a side of the first end in the second direction Y. The first end of the active layer 310a of the first transistor 31a may be aligned with the second end of the active layer 320a of the second transistor 32a in the first direction X.

[0195] In some examples, the orthographic projections of the active layer 310 a of the first transistor 31 a and the active layer 320 a of the second transistor 32 a on the substrate may be substantially I-shaped.

[0196] In some examples, the second semiconductor layer pattern of the pixel circuit in the i-th row and j-th column and the second semiconductor layer pattern of the pixel circuit in the i-th row and j+1-th column can be symmetrically arranged about the first center line O1, so the second semiconductor layer pattern of the pixel circuit in the i-th row and j+1-th column is not described here.

[0197] In some examples, the overlapping portion of the first auxiliary line RST1b(i) with the active layer 310a of the first transistor 31a can serve as the bottom gate of the first transistor 31a, and the overlapping portion with the active layer 310b of the first transistor 31b can serve as the bottom gate of the first transistor 31b. The width (i.e., the length along the second direction Y) of the overlapping portion of the first auxiliary line RST1b(i) with the active layer 310a of the first transistor 31a and the overlapping portion with the active layer 310b of the first transistor 31b can be greater than the width of the remaining portion of the first auxiliary line RST1b(i). The configuration of this example helps ensure that the first auxiliary line shields the channel region of the active layer of the first transistor from light, thereby avoiding affecting the performance of the first transistor.

[0198] In some examples, the overlapping portion of the second auxiliary line GL2b(i) with the active layer 320a of the second transistor 32a can serve as the bottom gate of the second transistor 32a, and the overlapping portion with the active layer 320b of the second transistor 32b can serve as the bottom gate of the second transistor 32b. The width (i.e., the length along the second direction Y) of the overlapping portion of the second auxiliary line GL2b(i) with the active layer 320a of the second transistor 32a and the overlapping portion with the active layer 320b of the second transistor 32b can be greater than the width of the remaining portion of the second auxiliary line GL2b(i). The configuration of this example helps ensure that the second auxiliary line shields the channel region of the active layer of the second transistor from light, thereby avoiding affecting the performance of the second transistor.

[0199] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0200] FIG16A is a schematic diagram of the display substrate after the third conductive layer is formed in FIG10 . FIG16B is a schematic diagram of the third conductive layer in FIG16A . In some examples, as shown in FIG16A and FIG16B , the third conductive layer of the display substrate may include at least: a second initial signal line (e.g., second initial signal lines INIT2(i) and INIT2(i+1)), a first reset control line (e.g., RST1(i) and RST1(i+1)), and a second scan line (e.g., GL2(i) and GL2(i+1)).

[0201] In some examples, the second initial signal line INIT2(i) can be located on one side of the first capacitor of the pixel circuit in the second direction Y. The second initial signal line INIT2(i) can be substantially in the shape of a straight line extending along the first direction X. The orthographic projection of the second initial signal line INIT2(i) on the substrate can at least partially overlap with the orthographic projection of the third initial signal line INIT3(i-1) located on the second conductive layer on the substrate. In this example, by stacking the compensation control line, the third initial signal line, and the second initial signal line, the space occupied by the wiring arrangement can be saved.

[0202] In some examples, a second protrusion 452 may be provided on a side of the second initial signal line INIT2(i) away from the second electrode connection block 414. The second protrusion 452 may be provided at the junction of two adjacent pixel circuit groups. For example, the orthographic projection of the second protrusion 452 on the substrate may be located between the active layers of the seventh transistors of the two adjacent pixel circuit groups. The second protrusion 452 may be configured to be connected to the first region of the active layer of the seventh transistor of the two adjacent pixel circuit groups through the subsequently formed first connection electrode 501 and the eleventh connection electrode 511. In some examples, the second initial signal line INIT2(i) and the plurality of second protrusions 452 may be an integrated structure connected to each other.

[0203] In some examples, the first reset control line RST1(i) can be located on a side of the second plates 412a and 412b opposite to the second direction Y. The first reset control line RST1(i) can be substantially straight and extend along the first direction X. The overlapping portion of the first reset control line RST1(i) with the active layer 310a of the first transistor 31a can serve as the gate of the first transistor 31a, and the overlapping portion with the active layer 310b of the first transistor 31b can serve as the gate of the first transistor 31b. The orthographic projection of the first reset control line RST1(i) on the substrate can at least partially overlap with the orthographic projection of the first auxiliary line RST1b(i) on the substrate. For example, the orthographic projection of the first auxiliary line RST1b(i) on the substrate can cover the orthographic projection of the first reset control line RST1(i) on the substrate.

[0204] In some examples, the second scan line GL2(i) can be located on a side of the first reset control line RST1(i) in a direction opposite to the second direction Y. The second scan line GL2(i) can be roughly in the shape of a zigzag line extending along the first direction X. The overlapping portion of the second scan line GL2(i) with the active layer 320a of the second transistor 32a can serve as the gate of the second transistor 32a, and the overlapping portion with the active layer 320b of the second transistor 32b can serve as the gate of the second transistor 32b. The orthographic projection of the second scan line GL2(i) on the substrate can at least partially overlap with the orthographic projection of the second auxiliary line GL2b(i) on the substrate. For example, the orthographic projection of the second auxiliary line GL2b(i) on the substrate can cover the orthographic projection of the second scan line GL2(i) on the substrate.

[0205] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. The fifth insulating layer may be provided with a first group of vias and a second group of vias. For example, the first group of vias is formed by a first patterning process, and the second group of vias is formed by a second patterning process. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0206] FIG17 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG10 . In some examples, as shown in FIG17 , the first group of vias defined in the fifth insulating layer of the display substrate may include: a plurality of first-type vias (e.g., first to ninth vias V1 to V9, and eleventh to nineteenth vias V11 to V19), a plurality of second-type vias (e.g., tenth to twentieth vias V10 and twenty-first vias V20), and a plurality of third-type vias (e.g., twenty-fifth to twenty-seventh vias V25 to V27); the second group of vias may include at least: a plurality of fourth-type vias (e.g., twenty-eighth to twenty-ninth vias V28 and V29), and a plurality of fifth-type vias (e.g., thirty-first to thirty-eighth vias V31 to V38).

[0207] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first type via can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second type via can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer within the third type via can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer within the fourth type via can be removed to expose a portion of the surface of the third conductive layer. The fifth insulating layer and the fourth insulating layer within the fifth type via can be removed to expose a portion of the surface of the second semiconductor layer.

[0208] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer.

[0209] FIG18A is a schematic diagram of the display substrate after the fourth conductive layer is formed in FIG10 . FIG18B is a schematic diagram of the fourth conductive layer in FIG17A . In some examples, as shown in FIG18A and FIG18B , the fourth conductive layer of the display substrate may include at least: a first initial signal line (e.g., INIT1(i) and INIT1(i+1)), fourth plates of second capacitors of multiple pixel circuits (e.g., fourth plates 422a and 422b), and multiple connection electrodes (e.g., including first to twentieth connection electrodes 501 to 520).

[0210] In some examples, the first initial signal line INIT1(i) can be substantially in the shape of a zigzag line extending along the first direction X. The orthographic projection of the first initial signal line INIT1(i) on the substrate is located on one side of the orthographic projection of the first control line EML1(i) on the substrate along the second direction Y. The orthographic projection of the first initial signal line INIT1(i) on the substrate at least partially overlaps with the orthographic projection of the second scan line GL2(i) located on the third conductive layer on the substrate. In this example, by stacking the second auxiliary line, the second scan line, and the first initial signal line, space occupied by the wiring arrangement can be reduced.

[0211] In some examples, a third protrusion 453 may be provided on one side of the first initial signal line INIT1(i) close to the second electrode connection block 414. The third protrusion 453 may be provided in each pixel circuit. For example, the orthographic projection of the third protrusion 453 on the substrate may be adjacent to the orthographic projection of the active layer of the fourth transistor on the substrate. One third protrusion 453 may be connected to the first area of ​​the active layer 310a of the first transistor 31a through the thirty-fourth via V34, and another third protrusion 453 may be connected to the first area of ​​the active layer 310b of the first transistor 31b through the thirty-eighth via V38. In some examples, the first initial signal line INIT1(i) and the plurality of third protrusions 453 may be an integrated structure connected to each other.

[0212] In some examples, the orthographic projection of the fourth plate 422a of the second capacitor 42a in the pixel circuit in the i-th row and j-th column on the substrate can be approximately rectangular. The orthographic projection of the fourth plate 422a on the substrate can overlap with the orthographic projections of the first plate 411a and the second plate 412a of the first capacitor 41a on the substrate. The orthographic projection of the fourth plate 422a on the substrate can cover the orthographic projection of the hollow area OPa on the substrate, and the orthographic projection of the second plate 412a on the substrate can cover the orthographic projection of the edge of the fourth plate 422a on the substrate. The fourth plate 422a can be connected to the first plate 411a through the tenth via V10. The orthographic projection of the tenth via V10 on the substrate can be located within the orthographic projection of the hollow area OPa on the substrate.

[0213] In some examples, the orthographic projection of the fourth plate 422b of the second capacitor 42b of the pixel circuit in the i-th row and j+1-th column onto the substrate can be substantially rectangular. The orthographic projection of the fourth plate 422b onto the substrate can overlap the orthographic projection of the hollowed-out area OPb onto the substrate, and the orthographic projection of the second plate 412b onto the substrate can overlap the orthographic projection of the edge of the fourth plate 422b onto the substrate. The fourth plate 422b can be connected to the first plate 411b via a twentieth via V20. The orthographic projection of the twentieth via V20 onto the substrate can be located within the orthographic projection of the hollowed-out area OPb onto the substrate.

[0214] In some examples, the first connection electrode 501 may be roughly dumbbell-shaped and extend along the first direction X. The first connection electrode 501 may be connected to the first region of the active layer 370a of the seventh transistor 37a through the first via V1, and may also be connected to the second protrusion 452 through the twenty-sixth via V26, thereby electrically connecting the seventh transistor 37a to the second initial signal line INIT2(i). The eleventh connection electrode 511 may be roughly dumbbell-shaped and extend along the first direction X. The eleventh connection electrode 511 may be connected to the first region of the active layer 370b of the seventh transistor 37b through the eleventh via V11, and may also be connected to another second protrusion 452 through the twenty-seventh via V27, thereby electrically connecting the seventh transistor 37b to the second initial signal line INIT2(i). The first connection electrode 501 and the eleventh connection electrode 511 of adjacent pixel circuit groups may be an integrated structure connected to each other.

[0215] In some examples, the second connection electrode 502 may be substantially rectangular. The second connection electrode 502 may be connected to the first region of the active layer 340a of the fourth transistor 34a through the third via hole V3. The second connection electrode 502 may be configured to be connected to a subsequently formed data line DL(j).

[0216] In some examples, the third connection electrode 503 can be substantially rectangular. The third connection electrode 503 can be connected to the second region of the active layer 310a of the first transistor 31a through a thirty-first via hole V31. The third connection electrode 503 can be located on a side of the fourth electrode plate 422a opposite to the first direction X, and the third connection electrode 503 and the fourth electrode plate 422a can be an integral structure connected to each other. The fourth electrode plate 422a can be electrically connected to the first transistor 31a through the third connection electrode 503.

[0217] In some examples, the fourth connection electrode 504 may be substantially rectangular. The fourth connection electrode 504 may be located on one side of the first initial signal line INIT1(i) in the second direction Y and may be adjacent to the third protrusion 453 in the first direction X. The fourth connection electrode 504 may be connected to the second region of the active layer 320a of the second transistor 32a through a thirty-third via hole V33.

[0218] In some examples, the fifth connection electrode 505 can be substantially in the shape of a zigzag extending along the first direction X. The fifth connection electrode 505 can be located on a side of the first initial signal line INIT1(i) opposite to the second direction Y. The fifth connection electrode 505 can be connected to the second region of the active layer 340a of the fourth transistor 34a through a fourth via V4, can be connected to the first region of the active layer 320a of the second transistor 32a through a thirty-fourth via V34, and can be connected to the first region of the active layer 360a of the sixth transistor 36a through a seventh via V7. The fifth connection electrode 505 can electrically connect the third transistor 33a, the second transistor 32a, the fourth transistor 34a, and the sixth transistor 36a, and can serve as the third node N3 of the pixel circuit 30a.

[0219] In some examples, the sixth connection electrode 506 can be substantially rectangular. The sixth connection electrode 506 can be located on a side of the fifth connection electrode 505 opposite to the second direction Y. The sixth connection electrode 506 can be connected to the second region of the active layer 360a of the sixth transistor 36a through an eighth via V8. The sixth connection electrode 506 can be configured to be electrically connected to a first anode connection electrode 523 formed subsequently.

[0220] In some examples, the seventh connection electrode 507 can be substantially zigzag-shaped. The seventh connection electrode 507 can be located on one side of the second connection electrode 502 in the first direction X. The seventh connection electrode 507 can be connected to the second region of the active layer 370a of the seventh transistor 37a through a second via V2, and can also be connected to the first region of the active layer 330a of the third transistor 33a through a fifth via V5. The seventh connection electrode 507 can electrically connect the seventh transistor 37a, the third transistor 33a, and the fifth transistor 35a, and can serve as the second node N2 of the pixel circuit 30a.

[0221] In some examples, the eighth connection electrode 508 can be substantially symmetrical about the first center line O1. The eighth connection electrode 508 can be substantially strip-shaped and extend along the first direction X. The eighth connection electrode 508 can be located between the seventh connection electrode 507 and the seventeenth connection electrode 517. The eighth connection electrode 508 can be connected to the first region of the active layer 380a' of the eighth transistor 38a' through the twenty-second via hole V22, can be connected to the first region of the active layer 380b' of the eighth transistor 38b' through the twenty-fourth via hole V24, and can be connected to the first protrusion 451 through the twenty-sixth via hole V26, thereby electrically connecting the eighth transistor 38a', the eighth transistor 38b', and the third initial signal line INIT3(i-1).

[0222] In some examples, the ninth connection electrode 509 can be substantially symmetrical about the first center line O1. The ninth connection electrode 509 can be substantially rectangular. The ninth connection electrode 509 can be located between the fourth electrode plates 422a and 422b. The ninth connection electrode 509 can be connected to the first electrode plate connection block 413 through the twenty-fifth via V25, thereby achieving electrical connection with the second electrode plates 412a and 412b. The ninth connection electrode 509 can be configured to be connected to the first power line 61a formed later.

[0223] In some examples, the tenth connection electrode 510 can be substantially symmetrical about the first centerline O1. The tenth connection electrode 510 can be located between the fifth connection electrode 505 and the fifteenth connection electrode 515. The tenth connection electrode 510 can be substantially in the shape of a Mickey Mouse head. The tenth connection electrode 510 can be connected to the first region of the active layer 350a of the fifth transistor 35a through a sixth via V6, and can also be connected to the first region of the active layer 350b of the fifth transistor 35b through a sixteenth via V16. The tenth connection electrode 510 can be configured to be connected to a first power line 61a formed later.

[0224] In some examples, the twelfth connection electrode 512 and the second connection electrode 502 can be substantially symmetrical about the first center line O1. The twelfth connection electrode 512 can be substantially rectangular. The twelfth connection electrode 512 can be connected to the first region of the active layer 340b of the fourth transistor 34b through the thirteenth via hole V13. The twelfth connection electrode 512 can be configured to be connected to a subsequently formed data line DL(j+1).

[0225] In some examples, the thirteenth connecting electrode 513 and the third connecting electrode 503 can be substantially symmetrical about the first centerline O1. The thirteenth connecting electrode 513 can be substantially rectangular. The thirteenth connecting electrode 513 can be connected to the second region of the active layer 310b of the first transistor 31b via a thirty-fifth via hole V35. The thirteenth connecting electrode 513 can be located on one side of the fourth electrode plate 422b in the first direction X, and the thirteenth connecting electrode 513 and the fourth electrode plate 422b can be an integral structure connected to each other. The fourth electrode plate 422b can be electrically connected to the first transistor 31b via the thirteenth connecting electrode 513.

[0226] In some examples, the fourteenth connection electrode 514 and the fourth connection electrode 504 can be substantially symmetrical about the first center line O1. The fourteenth connection electrode 514 can be substantially rectangular. The fourteenth connection electrode 514 can be located on one side of the first initial signal line INIT1(i) in the second direction Y and can be adjacent to the third protrusion 453 in the first direction X. The fourteenth connection electrode 514 can be connected to the second region of the active layer 320b of the second transistor 32b through the thirty-seventh via hole V37.

[0227] In some examples, the fifteenth connecting electrode 515 and the fifth connecting electrode 505 can be roughly symmetrical about the first center line O1. The fifteenth connecting electrode 515 can be roughly in the shape of a broken line extending along the first direction X. The fifteenth connecting electrode 515 can be located on the side of the first initial signal line INIT1(i) in the opposite direction of the second direction Y. The fifteenth connecting electrode 515 can be connected to the second area of ​​the active layer 340b of the fourth transistor 34b through the fourteenth via V14, and can also be connected to the first area of ​​the active layer 320b of the second transistor 32b through the thirty-eighth via V38, and can also be connected to the first area of ​​the active layer 360b of the sixth transistor 36b through the seventeenth via V17. The fifteenth connecting electrode 515 can realize the electrical connection of the third transistor 33b, the second transistor 32b, the fourth transistor 34b and the sixth transistor 36b, and can serve as the third node N3 of the pixel circuit 30b.

[0228] In some examples, the sixteenth connection electrode 516 and the sixth connection electrode 506 can be substantially symmetrical about the first center line O1. The sixteenth connection electrode 516 can be substantially rectangular. The sixteenth connection electrode 516 can be located on a side of the fifteenth connection electrode 515 opposite to the second direction Y. The sixteenth connection electrode 516 can be connected to the second region of the active layer 360b of the sixth transistor 36b through the eighteenth via V18. The sixteenth connection electrode 516 can be configured to be electrically connected to a second anode connection electrode 524 formed subsequently.

[0229] In some examples, the seventeenth connecting electrode 517 and the seventh connecting electrode 507 can be substantially symmetrical about the first center line O1. The seventeenth connecting electrode 517 can be substantially zigzag-shaped. The seventeenth connecting electrode 517 can be located on a side of the twelfth connecting electrode 512 opposite to the first direction X. The seventeenth connecting electrode 517 can be connected to the second region of the active layer 370b of the seventh transistor 37b through the twelfth via V12, and can also be connected to the first region of the active layer 330b of the third transistor 33b through the fifteenth via V15. The seventeenth connecting electrode 517 can electrically connect the seventh transistor 37b, the third transistor 33b, and the fifth transistor 35b, and can serve as the second node N2 of the pixel circuit 30b.

[0230] In some examples, the eighteenth connection electrode 518 can be substantially symmetrical about the first center line O1. The eighteenth connection electrode 518 can be substantially strip-shaped and extend along the first direction X. The eighteenth connection electrode 518 can be located on a side opposite to the sixth connection electrode 506 and the sixteenth connection electrode 516 in the second direction Y. The eighteenth connection electrode 518 can be connected to the first region of the active layer 380a of the eighth transistor 38a through the ninth via hole V9, can be connected to the first region of the active layer 380b of the eighth transistor 38b through the ninth via hole V19, and can be connected to a first protrusion 451 through the twenty-seventh via hole V27, thereby electrically connecting the eighth transistor 38a, the eighth transistor 38b, and the third initial signal line INIT3(i).

[0231] In some examples, the nineteenth connecting electrode 519 and the twentieth connecting electrode 520 can be located on one side of the eighth connecting electrode 508 in the second direction Y. The nineteenth connecting electrode 519 can be substantially rectangular. The nineteenth connecting electrode 519 can be connected to the second region of the active layer 380a' of the eighth transistor 38a' through a twenty-first via hole V21. The twentieth connecting electrode 520 can be substantially rectangular. The twentieth connecting electrode 520 can be connected to the second region of the active layer 380b' of the eighth transistor 38b' through a twenty-third via hole V23.

[0232] (9) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate having the aforementioned pattern, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as a first planar layer.

[0233] Figure 19 is a schematic diagram of the display substrate after the sixth insulating layer is formed in Figure 10. In some examples, as shown in Figure 19, the sixth insulating layer of the display substrate may have multiple vias, such as vias 41 to 45, and vias 51 to 53. The sixth insulating layer within vias 41 to 45, and vias 51 to 53, may be removed to expose a portion of the surface of the fourth conductive layer.

[0234] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the sixth insulating layer.

[0235] FIG20 is a schematic diagram of the fifth conductive layer in FIG10 . In some examples, as shown in FIG10 and FIG20 , the fifth conductive layer of the display substrate may include at least: a plurality of data lines (e.g., data lines DL(j), DL(j+1), DL(j+2), and DL(j+3)), a plurality of first power lines (e.g., first power lines 61 a and 61 b), third plates of second capacitors of a plurality of pixel circuits (e.g., third plate 421 a of second capacitor 42 a and third plate 421 b of second capacitor 42 b), and a plurality of connection electrodes (e.g., a twenty-first connection electrode 521, a twenty-second connection electrode 522, a first anode connection electrode 523, and a second anode connection electrode 524).

[0236] In some examples, the plurality of data lines and the plurality of first power lines may all extend along the second direction Y. The first power line connected to a pixel circuit group may be located between two data lines. For example, the first power line 61a may be located between the data lines DL(j) and DL(j+1), and the first power line 61b may be located between the data lines DL(j+2) and DL(j+3). The first power line 61a may be located on the first center line O1, and may be, for example, substantially symmetrical about the first center line O1.

[0237] In some examples, the data lines DL(j) and DL(j+1) can be substantially linear and extend along the second direction Y. The data line DL(j) can be connected to the second connection electrode 502 through the forty-first via hole V41, thereby being electrically connected to the fourth transistor 34 a. The data line DL(j+1) can be connected to the twelfth connection electrode 512 through the fifty-first via hole V51, thereby being electrically connected to the fourth transistor 34 b.

[0238] In some examples, the first power line 61a can be substantially linear and extend along the second direction Y. The first power line 61a can be connected to the ninth connection electrode 509 through the forty-fourth via V44 to achieve electrical connection with the second plates 412a and 412b of the first capacitor 41a. Furthermore, the first power line 61a can be connected to the tenth connection electrode 510 through the forty-fifth via V45. Because the tenth connection electrode 510 is electrically connected to the first region of the active layer of the fifth transistor 35a and the first region of the active layer of the fifth transistor 35b through the via, the first power line 61a writes the first voltage signal to the first electrode of the fifth transistor 35a and the first electrode of the fifth transistor 35b.

[0239] In some examples, a first power bump 61-1 may be provided on the side of the first power line 61a near the data line DL(j), and a second power bump 61-2 may be provided on the side of the first power line 61a near the data line DL(j+1). The first power bump 61-1 and the second power bump 61-2 may be approximately symmetrical about the first center line O1. The first end of the first power bump 61-1 is connected to the first power line 61a, and the second end extends toward the data line DL(j). The first end of the second power bump 61-2 is connected to the first power line 61a, and the second end extends toward the data line DL(j+1). The orthographic projections of the first power bump 61-1 and the second power bump 61-2 on the substrate may be approximately trapezoidal. The orthographic projection of the first power bump 61-1 on the substrate may at least partially overlap with the orthographic projection of the fifth transistor 35a on the substrate; the orthographic projection of the second power bump 61-2 on the substrate may at least partially overlap with the orthographic projection of the fifth transistor 35b on the substrate.

[0240] In some examples, the first power line 61a, the plurality of first power bumps 61-1, and the plurality of second power bumps 61-2 can be interconnected as an integral structure. In this example, the provision of the first and second power bumps can help improve the flatness of the entire fifth conductive layer. Furthermore, the use of the first and second power bumps not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between the first power line and the data line.

[0241] In some examples, the orthographic projection of the third plate 421a of the second capacitor 42a on the substrate can be substantially rectangular. The third plate 421a can be located between the data line DL(j) and the first power line 61a. The orthographic projection of the third plate 421a on the substrate can at least partially overlap with the orthographic projection of the fourth plate 422a on the substrate. For example, the orthographic projection of the third plate 421a on the substrate can cover the orthographic projection of the fourth plate 422a on the substrate.

[0242] In some examples, the third plate 421b of the second capacitor 42b and the third plate 421a of the second capacitor 42a can be substantially symmetrical about the first centerline O1. The orthographic projection of the third plate 421b of the second capacitor 42b on the substrate can be substantially rectangular. The third plate 421b can be located between the data line DL(j+1) and the first power line 61a. The orthographic projection of the third plate 421b on the substrate can at least partially overlap with the orthographic projection of the fourth plate 422b on the substrate. For example, the orthographic projection of the third plate 421b on the substrate can cover the orthographic projection of the fourth plate 422b on the substrate.

[0243] In some examples, the twenty-first connecting electrode 521 can be located on a side of the third electrode plate 421a in the opposite direction of the second direction Y, and can be located between the data line DL(j) and the first power supply protrusion 61-1 in the first direction X. The twenty-first connecting electrode 521 can be connected to the fourth connecting electrode 504 through the forty-second via V42. The twenty-first connecting electrode 521 and the third electrode plate 421a can be an integrated structure connected to each other. Since the fourth connecting electrode 504 is connected to the second region of the active layer of the second transistor 32a through the via, and the twenty-second connecting electrode 521 and the third electrode plate 421a are an integrated structure connected to each other, the third electrode plate 421a of the second capacitor 42a is electrically connected to the second electrode of the second transistor 32a.

[0244] In some examples, the twenty-second connecting electrode 522 can be located on a side of the third electrode plate 421b in the opposite direction of the second direction Y, and can be located between the data line DL(j+1) and the second power supply protrusion block 61-2 in the first direction X. The twenty-second connecting electrode 522 can be connected to the fourteenth connecting electrode 514 through the fifty-second via V52. The twenty-second connecting electrode 522 and the third electrode plate 421b can be an integrated structure connected to each other. Since the fourteenth connecting electrode 514 is connected to the second region of the active layer of the second transistor 32b through the via, and the twenty-second connecting electrode 522 and the third electrode plate 421b are an integrated structure connected to each other, the third electrode plate 421b of the second capacitor 42b is electrically connected to the second electrode of the second transistor 32b.

[0245] In some examples, the first anode connection electrode 523 can be substantially rectangular. The first anode connection electrode 523 can be connected to the sixth connection electrode 506 through the forty-third via hole V43 to achieve connection with the second region of the active layer of the sixth transistor 36a. The first anode connection electrode 523 can be electrically connected to the anode of a subsequently formed light-emitting element located in the anode layer.

[0246] In some examples, the second anode connection electrode 524 can be substantially rectangular. The second anode connection electrode 524 can be connected to the sixteenth connection electrode 516 through the fifty-third via hole V53 to achieve connection with the second region of the active layer of the sixth transistor 36b. The second anode connection electrode 524 can be electrically connected to the anode of a subsequently formed light-emitting element located in the anode layer.

[0247] At this point, the circuit structure layer of this example is completed on the substrate. In some examples, after the circuit structure layer is completed, a light-emitting structure layer and an encapsulation structure layer can be sequentially formed on the circuit structure layer. For example, the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer.

[0248] In some examples, a seventh insulating film is coated on the substrate forming the aforementioned pattern, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer (also referred to as a second flat layer). Subsequently, an anode film is deposited on the substrate forming the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer. Subsequently, a pixel definition film is coated, and a pixel definition layer is formed by masking, exposure, and development processes. The pixel definition layer may be formed with a plurality of pixel openings exposing the anode layer. An organic light-emitting layer is formed in the pixel openings formed above, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode layer, and the cathode layer is connected to the organic light-emitting layer. Subsequently, an encapsulation structure layer is formed on the cathode layer, for example, the encapsulation structure layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0249] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The sixth insulating layer and the seventh insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0250] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some examples, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs. For example, a passivation layer made of an inorganic insulating material can be formed between the sixth insulating layer and the fourth conductive layer. For another example, a bottom metal shielding layer can be provided on the side of the first semiconductor layer close to the substrate. The orthographic projection of the bottom metal shielding layer on the substrate can cover the orthographic projection of the channel region of the active layer of the first type transistor on the substrate to ensure the performance of the first type transistor.

[0251] The preparation process of this example can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0252] In the display substrate provided in this embodiment, the first capacitor 41a of the pixel circuit can be formed by overlapping a first plate 411a and a second plate 412a. The first plate 411a can serve as the first electrode of the first capacitor 41a, connected to the third transistor 33a, the first transistor 31a, and the second electrode of the second capacitor 41a. The second plate 412a of the first capacitor 41a can serve as the second electrode of the first capacitor 41a, electrically connected to the first power line. The first plate 411a is located on the first conductive layer and serves as the lower plate; the second plate 412a is located on the second conductive layer and serves as the upper plate.

[0253] In the display substrate provided in this embodiment, the second capacitor 42a of the pixel circuit can be formed by overlapping a third plate 421a and a fourth plate 422a. The third plate 421a can serve as the first electrode of the second capacitor 42a and be connected to the second transistor 32a; the fourth plate 422a can serve as the second electrode of the second capacitor 42a and be connected to the first electrode of the first capacitor 41a, the third transistor 33a, and the first transistor 31a. The fourth plate 422a can be located in the fourth conductive layer and serve as the lower plate; the third plate 421a can be located in the third conductive layer and serve as the upper plate.

[0254] In the display substrate provided in this embodiment, the first plate 411a of the first capacitor 41a of the pixel circuit also serves as the gate of the third transistor 33a, is connected to the fourth plate 422a of the second capacitor 42a through a via, and is connected to the second electrode of the first transistor 31a through the fourth plate 422a and the third connection electrode 503. The first plate 411a can serve as the first node N1 of the pixel circuit. The orthographic projection of the third plate 421a of the second capacitor 42a on the substrate can cover the orthographic projection of the first plate 411a on the substrate. Since the first plate 411a can serve as the first node N1 in the pixel circuit, the third plate 421a is used to cover and shield the first plate 411a, which can effectively shield the influence of other signals in the pixel circuit on the first node N1, and can ensure the potential stability of the first node N1, thereby improving the display effect.

[0255] In the display substrate provided in this embodiment, the second plates of the plurality of first capacitors located in the second conductive layer can be interconnected as an integral structure, forming a transverse routing line for transmitting the first voltage signal along the first direction X. The first power lines located in the fifth conductive layer can transmit the first voltage signal along the second direction Y. Because the first power lines can be electrically connected to the integral structure of the second plates via vias and the ninth connection electrode located in the fourth conductive layer, a mesh structure can be formed for transmitting the first voltage signal. This not only effectively reduces the resistance of the first power lines and the voltage drop of the first voltage signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity, thereby improving display quality and display quality.

[0256] In the display substrate provided in this embodiment, a first power protrusion and a second power protrusion connected to the first power line as an integral structure are provided on the fifth conductive layer, which can form a metal block with a larger area; moreover, the first electrode plate of the second capacitor included in the fifth conductive layer can also form a metal block with a larger area, which can improve the flatness of the entire surface of the fifth conductive layer, which is beneficial to improving the flatness of the anode, thereby improving display uniformity.

[0257] In the display substrate provided by this embodiment, the first initial signal line can be located in the fourth conductive layer, and the orthographic projection of the first initial signal line on the substrate can at least partially overlap with the orthographic projection of the second auxiliary line located in the second conductive layer and the second scanning line located in the third conductive layer on the substrate, thereby forming a wiring stacking structure of three conductive layers (including the second conductive layer, the third conductive layer and the fourth conductive layer), thereby saving more wiring space, reducing the space occupied by the pixel circuit, and realizing a high-resolution display substrate.

[0258] In the display substrate provided by this embodiment, the second initial signal line can be located in the third conductive layer, and the orthographic projection of the second initial signal line on the substrate can at least partially overlap with the orthographic projection of the third initial signal line located in the second conductive layer and the compensation control line located in the first conductive layer on the substrate, thereby forming a wiring stacking structure of three conductive layers (including the first conductive layer, the second conductive layer and the third conductive layer), thereby saving more wiring space, which is beneficial to reducing the space occupied by the pixel circuit and facilitating the realization of a high-resolution display substrate.

[0259] In the display substrate provided in this embodiment, the pixel circuit may include two oxide thin film transistors (i.e., a first transistor and a second transistor). The first transistor and the second transistor may be adjacent to each other in a first direction and staggered in the first direction X, thereby saving more wiring space and helping to reduce the space occupied by the pixel circuit.

[0260] FIG21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG21 , this embodiment provides a display device 91 comprising a display substrate 910 according to the aforementioned embodiment. In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be any of the following products: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device for e-government, banks, hospitals, power departments, etc.), a monitor, etc. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, etc.

[0261] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A pixel circuit, comprising: A driving subcircuit, a first voltage writing subcircuit, a second voltage writing subcircuit, a writing control subcircuit, a coupling subcircuit, a first reset subcircuit and a storage subcircuit; The driving subcircuit is coupled to the first node, the second node and the third node, and is configured to provide a driving signal to the third node under the control of the first node; The first reset subcircuit is coupled to the first node, the first reset control line and the first initial signal line, and is configured to write the first initial signal provided by the first initial signal line into the first node under the control of the first reset control line; The first voltage writing subcircuit is coupled to the third node, the first scan line and the data line, and is configured to write the data signal provided by the data line into the third node under the control of the first scan line during the data writing phase; The second voltage writing subcircuit is coupled to the second node, the compensation control line and the second initial signal line, and is configured to write the threshold voltage of the driving subcircuit into the third node under the control of the compensation control line during the threshold compensation phase; The write control subcircuit is coupled to the third node, the fourth node and the second scan line, and is configured to conduct the third node and the fourth node under the control of the second scan line during the data writing phase and the threshold compensation phase; The coupling subcircuit is coupled to the first node and the fourth node and is configured to couple the signal written to the fourth node to the first node; The storage sub-circuit is coupled to the first node and the first power line; In a display cycle, the threshold compensation phase is independent of the data writing phase.

2. The pixel circuit according to claim 1, wherein: In a display cycle, the threshold compensation phase is located before the data writing phase, and the duration of the threshold compensation phase is greater than the duration of the data writing phase.

3. The pixel circuit according to claim 1 or 2, further comprising: a first control subcircuit and a second control subcircuit; The first control subcircuit is coupled to the second node, the first control line and the first power line, and is configured to conduct the first power line and the second node under the control of the first control line; The second control subcircuit is coupled to the third node, the second control line and the fifth node, and is configured to transmit the drive signal to the fifth node under the control of the second control line, the fifth node is coupled to the first pole of the light-emitting element, and the second pole of the light-emitting element is coupled to the second power line.

4. The pixel circuit according to claim 3, wherein: The first control signal provided by the first control line is different from the second control signal provided by the second control line.

5. The pixel circuit according to claim 3, further comprising: The third voltage writing subcircuit is coupled to the third node, the third scan line and the fourth initial signal line, and is configured to write the fourth initial signal provided by the fourth initial signal line into the third node under the control of the third scan line before the threshold compensation stage.

6. The pixel circuit according to claim 5, wherein: The first initial signal provided by the first initial signal line is the same as the second initial signal provided by the second initial signal line, and the fourth initial signal provided by the fourth initial signal line is greater than the first initial signal provided by the first initial signal line.

7. The pixel circuit according to claim 5, wherein: The first control signal provided by the first control line is the same as the second control signal provided by the second control line.

8. The pixel circuit according to any one of claims 3 to 7, further comprising: The second reset subcircuit is coupled to the fifth node, the second reset control line and the third initial signal line, and is configured to write the third initial signal provided by the third initial signal line into the fifth node under the control of the second reset control line.

9. The pixel circuit according to claim 8, wherein: The first reset subcircuit comprises: a first transistor, a gate of the first transistor is coupled to the first reset control line, a first electrode of the first transistor is coupled to the first initial signal line, and a second electrode of the first transistor is coupled to the first node; The write control subcircuit comprises: a second transistor, a gate of the second transistor is coupled to the second scan line, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the fourth node; The driving subcircuit comprises: a third transistor, a gate of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the second node, and a second electrode of the third transistor is coupled to the third node; The first voltage writing sub-circuit comprises: a fourth transistor, a gate of the fourth transistor is coupled to the first scan line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to the third node; The second voltage writing sub-circuit comprises: a seventh transistor, a gate of the seventh transistor is coupled to the compensation control line, a first electrode of the seventh transistor is coupled to the second initial signal line, and a second electrode of the seventh transistor is coupled to the second node; The first control subcircuit comprises: a fifth transistor, a gate of the fifth transistor is coupled to the first control line, a first electrode of the fifth transistor is coupled to the first power line, and a second electrode of the fifth transistor is coupled to the second node; The second control subcircuit comprises: a sixth transistor, a gate of the sixth transistor is coupled to the second control line, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the fifth node; The second reset subcircuit comprises: an eighth transistor, a gate of the eighth transistor is coupled to the second reset control line, a first electrode of the eighth transistor is coupled to the third initial signal line, and a second electrode of the eighth transistor is coupled to the fifth node; Among them, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are first type transistors; the first transistor and the second transistor are second type transistors; the first type transistor and the second type transistor are different in transistor type.

10. The pixel circuit according to claim 9, wherein: The first type transistor is a low temperature polysilicon thin film transistor, and the second type transistor is an oxide thin film transistor.

11. The pixel circuit according to claim 1, wherein: The storage subcircuit includes: a first capacitor; the coupling subcircuit includes: a second capacitor; the first electrode of the first capacitor is coupled to the first node, and the second electrode of the first capacitor is coupled to the first power line; the first electrode of the second capacitor is coupled to the fourth node, and the second electrode of the second capacitor is coupled to the first node.

12. A driving method for a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 11, the driving method comprising: The first reset subcircuit writes the first initial signal provided by the first initial signal line into the first node under the control of the first reset control line; In the threshold compensation stage, the second voltage writing sub-circuit, under the control of the compensation control line, changes the threshold of the driving sub-circuit to A voltage is written into a third node, and the write control circuit, under the control of the second scan line, conducts the third node and the fourth node, and writes the threshold voltage into the fourth node; In the data writing stage, the first voltage writing subcircuit writes the data signal provided by the data line into the third node under the control of the first scanning line, the writing control circuit writes the data signal into the fourth node, and the coupling subcircuit couples the signal written into the fourth node to the first node; The driving sub-circuit provides a driving signal to the third node under the control of the first node.

13. The driving method according to claim 12, wherein: In a display cycle, the threshold compensation phase is located before the data writing phase, and the duration of the threshold compensation phase is greater than the duration of the data writing phase.

14. The driving method according to claim 13, further comprising: Before the threshold compensation stage, the first control subcircuit charges the fourth node using a first voltage signal provided by the first power line under the control of the first control line.

15. The driving method according to claim 13, wherein: The pixel circuit also includes: a third voltage writing sub-circuit, coupled to the third node, the third scan line and the fourth initial signal line; the driving method also includes: before the threshold compensation stage, the third voltage writing sub-circuit, under the control of the third scan line, uses the fourth initial signal provided by the fourth initial signal line to charge the fourth node; the fourth initial signal is greater than the first initial signal.

16. The driving method according to claim 15, wherein: Within a display cycle, the duration of the effective level signal of the second scanning signal provided by the second scanning line is greater than the sum of the durations of the effective level signal of the first scanning signal provided by the first scanning line, the effective level signal of the third scanning signal provided by the third scanning line, and the effective level signal of the compensation control signal provided by the compensation control line.

17. A display substrate, comprising: A substrate, a circuit structure layer disposed on the substrate, the circuit structure layer comprising a plurality of pixel circuits, at least one of the plurality of pixel circuits comprising: a first capacitor and a second capacitor; the second capacitor is located on a side of the first capacitor away from the substrate, and an orthographic projection of the second capacitor on the substrate at least partially overlaps with an orthographic projection of the first capacitor on the substrate; The first capacitor includes: a first plate and a second plate; the second capacitor includes: a third plate and a fourth plate; the second plate of the first capacitor is located on a side of the first plate away from the substrate, the third plate of the second capacitor is located on a side of the fourth plate away from the substrate, and the fourth plate of the second capacitor is located on a side of the second plate of the first capacitor away from the substrate; the first plate of the first capacitor is connected to the fourth plate of the second capacitor.

18. The display substrate according to claim 17, wherein: The second electrode plate of the first capacitor has a hollow area, and the connection position of the first electrode plate and the fourth electrode plate is located within the orthographic projection range of the hollow area on the substrate.

19. The display substrate according to claim 17, wherein: The orthographic projection of the third electrode plate of the second capacitor on the substrate covers the orthographic projections of the first electrode plate and the fourth electrode plate on the substrate.

20. The display substrate according to claim 17, wherein: The second plates of the first capacitors of the multiple pixel circuits arranged along the first direction are an integrated structure that is interconnected. The integrated structure is connected to a first power line extending along the second direction to form a mesh structure for transmitting a first voltage signal. The first power line is located on a side of the integrated structure away from the substrate. The first direction intersects the second direction.

21. The display substrate according to claim 20, wherein: An integrated structure formed by connecting the second plates of the first capacitors of multiple pixel circuits arranged along the first direction is connected to the first power line through a ninth connecting electrode, and the ninth connecting electrode is located on a side of the integrated structure away from the substrate and on a side of the first power line close to the substrate.

22. The display substrate according to claim 17, wherein: The pixel circuit is connected to a first initial signal line, a second initial signal line and a third initial signal line; the first initial signal line, the second initial signal line and the third initial signal line are located in different conductive layers.

23. The display substrate according to claim 17, wherein: The pixel circuit comprises: at least one first type transistor and at least one second type transistor; In a direction perpendicular to the display substrate, the circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged on the substrate; the first semiconductor layer includes an active layer of the at least one first type transistor, and the second semiconductor layer includes an active layer of the at least one second type transistor.

24. The display substrate according to claim 23, wherein: The first plate of the first capacitor is located in the first conductive layer, and the second plate of the first capacitor is located in the second conductive layer; the third plate of the second capacitor is located in the fifth conductive layer, and the fourth plate of the second capacitor is located in the fourth conductive layer.

25. The display substrate according to claim 23, wherein: The pixel circuit is electrically connected to a first initial signal line, the first initial signal line is located in the fourth conductive layer, and an orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of a line located in the second conductive layer and the third conductive layer on the substrate.

26. The display substrate according to claim 23, wherein: The pixel circuit is electrically connected to a second initial signal line and a third initial signal line, the third initial signal line is located in the second conductive layer, the second initial signal line is located in the third conductive layer, and the orthographic projections of the second initial signal line and the third initial signal line on the substrate at least partially overlap.

27. The display substrate according to claim 23, wherein: The pixel circuit includes two second-type transistors, which are adjacent to each other in a first direction and are staggeredly arranged along the first direction.

28. The display substrate according to claim 17, wherein: The plurality of pixel circuits are divided into a plurality of pixel circuit groups, each pixel circuit group includes two pixel circuits adjacently arranged along a first direction, and the two pixel circuits in the pixel circuit group are symmetrically arranged about a first center line of the pixel circuit group in the first direction.

29. The display substrate according to claim 28, wherein: The two pixel circuits in the pixel circuit group are connected to the same first power line, the first power line is located at the first center line, and the data lines connected to the two pixel circuits are located at both sides of the first power line in the first direction.

30. A display device comprising the display substrate according to any one of claims 17 to 29.

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