Sense amplifier, control method therefor, storage array structure, and memory

Abstract

Embodiments of the present disclosure relate to the technical field of storage, and provide a sense amplifier, a control method therefor, a storage array structure, and a memory. The sense amplifier comprises: a first signal amplification unit, wherein a first end and a second end of the first signal amplification unit are respectively adapted to be electrically connected to a first voltage end and a second voltage end, and a third end and a fourth end of the first signal amplification unit are respectively used as a first node and a second node; and a second signal amplification unit, wherein a first end, a second end, and a third end of the second signal amplification unit are respectively adapted to be electrically connected to a third voltage end, a fourth voltage end, and a bit line, and a fourth end of the second signal amplification unit is electrically connected to the first node. The sense amplifier is configured to amplify the voltage of the first node to a first voltage or a second voltage in a first signal amplification stage, and to write the second voltage or the first voltage back to a storage unit in a second signal amplification stage. The structure of the sense amplifier in the embodiments of the present disclosure can replace an edge reference array, and no additional reference array needs to be provided, thereby reducing the size of chips and reducing the chip cost.

Description

Sense amplifier and control method thereof, storage array structure and memory Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a sense amplifier and a control method thereof, a storage array structure, and a memory. Background Art

[0002] Currently, most DRAMs (Dynamic Random Access Memory) use an open bit line structure (open BL) to reduce chip size and thus reduce chip cost.

[0003] However, in an open bitline architecture, the reference voltage for each bitline is derived from the adjacent memory cell on the other side. Therefore, each bitline signal amplification requires a reference voltage. This existing architecture has the disadvantage of requiring an additional reference array at the edge of each memory cell in the memory array structure and employing control logic corresponding to the reference array, which increases the chip area and size.

[0004] Summary of the Invention

[0005] In view of the shortcomings of the existing methods, the present disclosure proposes a sense amplifier and a control method thereof, a storage array structure and a memory, so as to solve the technical problem in the prior art that the additional reference array increases the chip size.

[0006] In a first aspect, an embodiment of the present disclosure provides a sense amplifier, comprising:

[0007] a first signal amplifying unit, wherein the first end and the second end are respectively used to be electrically connected to the first voltage end and the second voltage end, and the third end and the fourth end serve as the first node and the second node respectively; the first voltage end is used to output a first voltage, and the second voltage end is used to output a second voltage, and the first voltage is greater than the second voltage;

[0008] a second signal amplifying unit, wherein the first end, the second end, and the third end are respectively electrically connected to the third voltage end, the fourth voltage end, and the bit line, and the fourth end is electrically connected to the first node; the voltage of the third voltage end is the same as the voltage of the first voltage end, and the voltage of the fourth voltage end is the same as the voltage of the second voltage end; and the bit line is electrically connected to the memory cell of the memory array structure;

[0009] The sense amplifier is configured such that in a first signal amplification stage, the first end, the first node, and the second end of the first signal amplification unit are conductive, so that the voltage of the first node is amplified to the first voltage or the second voltage; and in a second signal amplification stage, the first end and the third end of the second signal amplification unit are conductive, or the second end and the third end are conductive, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the memory cell.

[0010] In a second aspect, an embodiment of the present disclosure provides a memory array structure, comprising: a plurality of bit lines, a plurality of word lines, a plurality of memory cells distributed in a matrix, and a plurality of sense amplifiers as in the first aspect;

[0011] One bit line is electrically connected to one column of memory cells;

[0012] One word line is electrically connected to one row of memory cells;

[0013] Each bit line is electrically connected to the third terminal of the second signal amplifying unit of a corresponding sense amplifier.

[0014] In a third aspect, an embodiment of the present disclosure provides a dynamic random access memory, comprising: the storage array structure of the second aspect.

[0015] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a storage array structure as in the second aspect or a dynamic random access memory as in the third aspect.

[0016] In a fifth aspect, an embodiment of the present disclosure provides a control method, applied to the sense amplifier according to the first aspect, comprising:

[0017] In the first signal amplification stage, the first terminal, the first node, and the second terminal of the first signal amplification unit are controlled to be conductive, so that the voltage of the first node is amplified to the first voltage or the second voltage;

[0018] In the second signal amplification stage, the first and third terminals of the second signal amplification unit are turned on or the second and third terminals are turned on, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the memory cell of the memory array structure.

[0019] The beneficial technical effects brought about by the technical solutions provided by the embodiments of the present disclosure include:

[0020] The sensing amplifier of the disclosed embodiment can, in the first signal amplification stage, amplify the voltage of the first node to the first voltage or the second voltage through the first signal amplification unit, and in the second signal amplification stage, amplify the voltage of the bit line to the second voltage or the first voltage accordingly through the second signal amplification unit, so that the second voltage or the first voltage can be written back to the storage unit, thereby improving the data write-back effect. The disclosed embodiment designs a new sensing amplifier, which can realize signal sensing amplification based on the first signal amplification unit and the second signal amplification unit of the sensing amplifier. When the sensing amplifier is applied to the memory, there is no need to set a reference array at the edge of the storage array structure of the memory, so that the reference array area overhead required for the edge of the open bit line structure is greatly reduced, thereby reducing the size of the chip. Moreover, the disclosed embodiment can be to add a second signal amplification unit to the existing sensing amplifier, and replace the edge reference array by optimizing the structure of the sensing amplifier, thereby reducing the size of the chip and reducing the chip cost.

[0021] Additional aspects and advantages of the present disclosure will be set forth in part in the following description, will become apparent from the following description, or may be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0023] FIG1 is a schematic structural diagram of a first sensing amplifier provided by an embodiment of the present disclosure;

[0024] FIG2 is a schematic structural diagram of a second sensing amplifier provided by an embodiment of the present disclosure;

[0025] FIG3 is a schematic structural diagram of a third sensing amplifier provided in an embodiment of the present disclosure;

[0026] FIG4 is a schematic structural diagram of a fourth sensing amplifier provided in an embodiment of the present disclosure;

[0027] FIG5 is a schematic structural diagram of a fifth sensing amplifier provided by an embodiment of the present disclosure;

[0028] FIG6 is a schematic structural diagram of a sixth sensing amplifier provided in an embodiment of the present disclosure;

[0029] FIG7 is a schematic structural diagram of a seventh sense amplifier connected to a storage unit according to an embodiment of the present disclosure;

[0030] FIG8 is a schematic structural diagram of a seventh sense amplifier connected to a storage unit and a port according to an embodiment of the present disclosure;

[0031] FIG9 is a schematic structural diagram of a storage array structure provided by an embodiment of the present disclosure;

[0032] FIG10 is a flow chart of a control method provided by an embodiment of the present disclosure;

[0033] FIG11 is a flow chart of another control method provided by an embodiment of the present disclosure;

[0034] FIG12 is a flow chart of another control method provided by an embodiment of the present disclosure

[0035] FIG13 is a timing control diagram of a sense amplifier provided by an embodiment of the present disclosure;

[0036] FIG14 is a schematic diagram showing the five stages of the timing control diagram of FIG13;

[0037] FIG15 is a timing control diagram of another sense amplifier provided by an embodiment of the present disclosure;

[0038] FIG16 is a schematic diagram showing seven stages divided according to the timing control diagram of FIG15 .

[0039] Figure numerals: 10-sense amplifier; 110-first signal amplifying unit, 111-fifth switch module, 112-sixth switch module, 113-seventh switch module, 114-eighth switch module; 120-second signal amplifying unit, 121-first switch module, 122-second switch module; 130-third signal amplifying unit, 131-third switch module, 132-fourth switch module; 140-first isolation unit; 150-second isolation unit; 160-third isolation unit; 170-first pre-charging unit; 180-second pre-charging unit; 190-fourth isolation unit, 191-ninth switch module, 192-tenth switch module; 1100-offset elimination unit, 1101-eleventh switch module, 1102-twelfth switch module; A-first node, B-second node, C-third node, D-fourth node; 20-storage unit. DETAILED DESCRIPTION

[0040] The present disclosure is described in detail below. Examples of embodiments of the present disclosure are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. In addition, if the detailed description of the known technology is not necessary for the features of the present disclosure shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and should not be interpreted as limiting the present disclosure.

[0041] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which this disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0042] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present disclosure refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0043] The following describes in detail the technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems with specific embodiments.

[0044] An embodiment of the present disclosure provides a sense amplifier. Referring to FIG. 1 , the sense amplifier 10 includes a first signal amplifying unit 110 and a second signal amplifying unit 120 .

[0045] The first end and the second end of the first signal amplifying unit 110 are respectively used to be electrically connected to the first voltage end and the second voltage end, and the third end and the fourth end of the first signal amplifying unit 110 serve as the first node A and the second node B, respectively; the first voltage end is used to output a first voltage, and the second voltage end is used to output a second voltage, and the first voltage is greater than the second voltage.

[0046] Optionally, as shown in FIG1 , the voltage signal output by the first voltage terminal is RTO, and the voltage signal output by the second voltage terminal is SB. The first and second voltage terminals are power supply terminals, providing two power supply signals. A switching device can be provided between the first voltage terminal and the first terminal of the first signal amplification unit 110. When the switching device is turned on, the first voltage terminal is turned on and in an operating state. Similarly, a switching device can be provided between the second terminal of the first signal amplification unit 110 and the second voltage terminal. When the switching device is turned on, the second voltage terminal is turned on and in an operating state.

[0047] Optionally, the RTO is in a non-operating state at 0.5V and in an operating state at 1.0V, and the SB is in a non-operating state at 0.5V and in an operating state at 0V. In an operating state, the first voltage may be 1V and the second voltage may be 0V.

[0048] The first end, the second end, and the third end of the second signal amplifying unit 120 are respectively used to be electrically connected to the third voltage end, the fourth voltage end, and the bit line. The fourth end of the second signal amplifying unit 120 is electrically connected to the first node A. The voltage of the third voltage end is the same as the voltage of the first voltage end, and the voltage of the fourth voltage end is the same as the voltage of the second voltage end.

[0049] 1 and 7 , the bit line BL (Bit-line, BL) is used to electrically connect to the memory cell 20 of the memory array structure. The bit line can be used to transmit data and locate. The bit line BL is also used to electrically connect to the second node B.

[0050] Optionally, as shown in FIG1 , the voltage signal output by the third voltage terminal is RTO1, and the voltage signal output by the fourth voltage terminal is SB1. The third and fourth voltage terminals correspond to the first and second voltage terminals, respectively, and are also power supply terminals, providing two power supply signals. Optionally, RTO1 is the same as RTO, with a voltage of 0.5V in the non-operating state and 1.0V in the operating state. The voltage of the third voltage terminal in the operating state is the first voltage, which can be 1V, and SB1 is 0V.

[0051] The sense amplifier 10 is configured such that in a first signal amplification stage, the first terminal, the first node A, and the second terminal of the first signal amplification unit 110 are conductive, so that the voltage of the first node A is amplified to the first voltage or the second voltage; and in a second signal amplification stage, the first terminal and the third terminal or the second terminal and the third terminal of the second signal amplification unit 120 are conductive, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the memory cell 20.

[0052] Specifically, the first end and the third end or the second end and the third end of the second signal amplifying unit 120 are turned on under the control of the first node A, and the voltage of the first node A is the second voltage or the first voltage, which can correspondingly control the first end and the third end or the second end and the third end of the second signal amplifying unit 120 to be turned on.

[0053] As an example, the sense amplifier 10 can be configured such that in a first signal amplification stage, the first terminal, the first node A, and the second terminal of the first signal amplification unit 110 are turned on, so that the voltage of the first node A is amplified to the first voltage; and in a second signal amplification stage, the second terminal and the third terminal of the second signal amplification unit 120 are turned on, so that the voltage of the bit line is amplified to the second voltage to write the second voltage back to the memory cell 20.

[0054] Currently, DRAM units are 1T1C structures, which occupy a large area and have a complex manufacturing process. Sense amplifiers are generally simple MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structures, which are simple to manufacture and small in size. Since DRAM's open BL requires a reference voltage for each sensing amplification, conventional DRAMs require a reference array at the edge of the memory cell to serve as a sensing reference during reading and writing. The sense amplifier 10 provided in the disclosed embodiment is a novel structural design that utilizes only a single sense amplifier 10 to achieve sensing amplification, eliminating the need for an additional reference array and thus reducing chip area.

[0055] The sense amplifier 10 of the disclosed embodiment can, in a first signal amplification stage, amplify the voltage of the first node A to a first voltage or a second voltage through the first signal amplification unit 110. In a second signal amplification stage, the voltage of the bit line can be amplified to a second voltage or the first voltage through the second signal amplification unit 120. This allows the second voltage or the first voltage to be written back to the memory cell 20, thereby improving the data write-back effect. The disclosed embodiment designs a new sense amplifier 10. This sense amplifier 10 can implement signal sensing and amplification based on the first signal amplification unit 110 and the second signal amplification unit 120 of the sense amplifier. When this sense amplifier is applied to a memory, there is no need to set a reference array at the edge of the memory array structure of the memory. This greatly reduces the reference array area overhead required at the edge of the open bit line structure, thereby reducing the chip size. Furthermore, the disclosed embodiment can add a second signal amplification unit 120 to an existing sense amplifier. By optimizing the structure of the sense amplifier 10 to replace the edge reference array, the chip size can be reduced, thereby reducing chip cost.

[0056] Similarly, the sense amplifier 10 can also be configured such that in the first signal amplification stage, the first terminal, the first node A, and the second terminal of the first signal amplification unit 110 are turned on, so that the voltage of the first node A is amplified to the second voltage; and in the second signal amplification stage, the first terminal and the third terminal of the second signal amplification unit 120 are turned on, so that the voltage of the bit line is amplified to the first voltage, so as to write the first voltage back to the memory cell 20.

[0057] In some embodiments, as shown in FIG. 2 , the fifth terminal and the sixth terminal of the first signal amplifying unit 110 serve as the third node C and the fourth node D, respectively.

[0058] The sense amplifier 10 further includes a third signal amplifying unit 130 .

[0059] The first end, the second end, and the third end of the third signal amplifying unit 130 are respectively used to be electrically connected to the fifth voltage end, the sixth voltage end, and the first data signal line. The fourth end of the third signal amplifying unit 130 is electrically connected to the third node C. The voltage of the fifth voltage end is the same as the voltage of the first voltage end, and the voltage of the sixth voltage end is the same as the voltage of the second voltage end. The first data signal line is used to be electrically connected to the port.

[0060] As shown in Figure 2, the voltage signal output by the fifth voltage terminal is RTO2, and the voltage signal output by the sixth voltage terminal is SB2. The fifth and sixth voltage terminals correspond to the first and second voltage terminals, respectively, and are also power supply terminals, providing two power supply signals. Optionally, RTO2 is the same as RTO, with a voltage of 0.5V in the non-operating state and 1.0V in the operating state; the voltage of the fifth voltage terminal in the operating state is the first voltage, which can be 1V, and the voltage of the sixth voltage terminal in the operating state is the second voltage, which can be 0V.

[0061] The sense amplifier 10 is further configured such that in a first signal amplification stage, the first terminal, the third node C, and the second terminal of the first signal amplification unit 110 are conductive, so that the voltage of the third node C is amplified to the second voltage or the first voltage; and in a second signal amplification stage, the first terminal and the third terminal or the second terminal and the third terminal of the third signal amplification unit 130 are conductive, so that the voltage of the first data signal line is amplified to the first voltage or the second voltage, so as to output the first voltage or the second voltage to the port.

[0062] Specifically, the first end and the third end or the second end and the third end of the third signal amplifying unit 130 are turned on under the control of the third node C, and the voltage of the third node C is the second voltage or the first voltage, which can correspondingly control the first end and the third end of the third signal amplifying unit 130 to be turned on or the second end and the third end to be turned on.

[0063] As an example, the sense amplifier 10 can be configured such that in a first signal amplification stage, the first terminal, the third node C, and the second terminal of the first signal amplification unit 110 are turned on, so that the voltage of the third node C is amplified to the second voltage; and in a second signal amplification stage, the first terminal and the third terminal of the third signal amplification unit 130 are turned on, so that the voltage of the first data signal line is amplified to the first voltage to output the first voltage to the port.

[0064] Specifically, the third signal amplifying unit 130 and the second signal amplifying unit 120 have the same structure. The third signal amplifying unit 130 and the second signal amplifying unit 120 are equivalent to two inverter structures for recovering data.

[0065] Optionally, as shown in FIG2 , the third signal amplifying unit 130 and the second signal amplifying unit 120 are symmetrical structures provided on both sides of the first signal amplifying unit 110. Considering that the loads at both ends of the bit line BL and the first data signal line BLB on both sides of the first signal amplifying unit 110 are different, the bit line BL is connected to the memory cell 20, while the first data signal line BLB is not connected to the memory cell 20, to prevent data errors caused by interference during reading, a first signal amplification is performed to sense and amplify the small voltage difference between the bit line BL and the first data signal line BLB to the first node A and the third node C. Then, during the second signal amplification, the voltage signals of the bit line BL and the first data signal line BLB are amplified by the second signal amplifying unit 120 and the third signal amplifying unit 130 to ensure the reliability of the amplification process.

[0066] Similarly, the sense amplifier 10 is further configured such that in the first signal amplification stage, the first terminal, the third node C, and the second terminal of the first signal amplification unit 110 are conductive, so that the voltage of the third node C is amplified to the first voltage; and in the second signal amplification stage, the second terminal and the third terminal of the third signal amplification unit 130 are conductive, so that the voltage of the first data signal line is amplified to the second voltage, so as to output the second voltage to the port.

[0067] In some embodiments, referring to FIG. 3 , the sense amplifier 10 further includes a first isolation unit 140 .

[0068] The control end of the first isolation unit 140 is used to be electrically connected to the first isolation signal line, and the first end and the second end of the first isolation unit 140 are used to be electrically connected to the first reference voltage end and the first data signal line respectively.

[0069] The first isolation unit 140 is configured such that, in the second signal amplification phase, the first end and the second end of the first isolation unit 140 are disconnected to amplify the voltage of the first data signal line.

[0070] As an example, the first isolation unit 140 can be configured such that during the second signal amplification phase, the first end and the second end of the first isolation unit 140 are disconnected to amplify the voltage of the first data signal line to the first voltage or the second voltage. As shown in FIG7 , during the first sensing amplification process on the SABL (first node A), the voltage on the SABL will have different values ​​due to whether the memory cell 20 stores 0 or 1. If 0 is stored, the first voltage (RTO) is applied to the SABL, and the voltage of the bit line BL written back during the second signal amplification is the voltage of SB1. Conversely, if 1 is stored in the memory cell 20, the second voltage (SB) is applied to the SABL, and during the second sensing amplification, the BL writes back the RTO1 voltage.

[0071] As shown in FIG3 , the control signal received by the first isolation signal is ISO3, and the reference voltage of the first reference voltage terminal is V BLEP ISO3 can control the first and second terminals of the first isolation unit 140 to be turned on and off. When the first and second terminals of the first isolation unit 140 are disconnected, the voltage of the first data signal line BLB is isolated from the reference voltage VBLP of the first reference voltage terminal and is no longer affected by the reference voltage VBLEP, thereby eliminating the edge reference voltage signal problem. The first reference voltage terminal can be a 0.5V power supply, i.e., V BLEP It can be 0.5v.

[0072] In some embodiments, as shown in FIG. 4 , the sense amplifier 10 further includes a second isolation unit 150 .

[0073] The control end and the first end of the second isolation unit 150 are respectively used to be electrically connected to the second isolation signal line and the bit line, and the second end of the second isolation unit 150 is electrically connected to the second node B;

[0074] The second isolation unit 150 is configured such that in a working state, the first end and the second end of the second isolation unit 150 are connected; in a non-working state, the first end and the second end of the second isolation unit 150 are disconnected.

[0075] As shown in FIG4 , the control signal received by the second isolation signal line is ISO2. ISO2 can control the first and second ends of the second isolation unit 150 to be turned on and off. When the first and second ends of the second isolation unit 150 are disconnected, the bit line and the second node B are disconnected, and the sense amplifier 10 is disconnected from the port, thereby cutting off the load effect of the port and avoiding affecting the reading and writing effects.

[0076] In some embodiments, as shown in FIG. 4 , the sense amplifier 10 further includes a third isolation unit 160 .

[0077] The control end of the third isolation unit 160 is used to be electrically connected to the third isolation signal line. The first end and the second end of the third isolation unit 160 are electrically connected to the first data signal line and the fourth node D respectively. The third isolation signal line is electrically connected to the second isolation signal line.

[0078] The third isolation unit 160 is configured such that in a working state, the first end and the second end of the third isolation unit 160 are connected; in a non-working state, the first end and the second end of the third isolation unit 160 are disconnected.

[0079] As shown in FIG4 , the configuration of the third isolation unit 160 is consistent with the configuration principle of the second isolation unit 150 . The control signal received by the third isolation signal line is ISO2, which can control the first and second terminals of the third isolation unit 160 to be conductive and disconnected. When the first and second terminals of the third isolation unit 160 are disconnected, the first data signal line and the fourth node D are disconnected. Because the bit line and the first data signal line are both connected to the port and output the inverted signal I0 and I0B, the control signal ISO2 can disconnect the sense amplifier 10 from the port, eliminating the port's load effect and preventing impact on read and write performance.

[0080] In some embodiments, as shown in FIG. 5 , the sense amplifier 10 further includes a first pre-charging unit 170 , a second pre-charging unit 180 and a fourth isolation unit 190 .

[0081] The control terminal of the first pre-charging unit 170 is used to be electrically connected to the first signal line, the first terminal of the first pre-charging unit 170 is used to be electrically connected to the first reference voltage terminal, and the second terminal of the first pre-charging unit 170 is electrically connected to the third node C; the first reference voltage terminal is used to output the first reference voltage;

[0082] The control end of the second pre-charging unit 180 is used to be electrically connected to the second signal line, and the first end and the second end of the second pre-charging unit 180 are electrically connected to the first node A and the third node C respectively;

[0083] The control end of the fourth isolation unit 190 is used to be electrically connected to the fourth isolation signal line, and the first end, second end, third end and fourth end of the fourth isolation unit 190 are electrically connected to the second node B, the third node C, the first node A and the fourth node D respectively.

[0084] As shown in FIG5 , the reference voltage outputted by the first reference voltage terminal is V BLEP The control signal output by the first signal line is PRE, the control signal output by the second signal line is EQ, and the control signal output by the fourth isolation signal line is ISO1. PRE can control the conduction and disconnection of the first and second ends of the first pre-charging unit 170, EQ can control the conduction and disconnection of the first and second ends of the second pre-charging unit 180, and ISO1 can control the conduction and disconnection of the first and second ends, the third and fourth ends of the fourth isolation unit 190.

[0085] The sense amplifier 10 is further configured to control, in the first pre-charging stage, the first and second terminals of the first pre-charging unit 170 to be conductive, the first and second terminals of the second pre-charging unit 180 to be conductive, the first and second terminals of the fourth isolation unit 190 to be conductive and the third and fourth terminals to be conductive, and the first and second terminals of the first isolation unit 140 to be conductive, so as to pre-charge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage.

[0086] The sense amplifier 10 is further configured to control the first and second ends of the first pre-charging unit 170 to be disconnected and the first and second ends of the second pre-charging unit 180 to be disconnected during the charge sharing phase, so as to charge-share the predetermined voltage of the bit line with the capacitance of the memory cell 20 .

[0087] Specifically, the predetermined voltage is a reference voltage, V BLEP It can be 0.5v.

[0088] Specifically, as shown in FIG7 , each memory cell 20 in the memory array structure is composed of a 1T1C structure. By controlling the word line control signal WL, the bit line BL and the capacitor of the memory cell 20 can be controlled to share charge. A charge exchange process occurs between the load capacitor on the bit line BL and the storage capacitor of the memory cell 20, sharing the internally stored voltage on the bit line BL. After charge sharing, the bit line BL is no longer 0.5V. If the memory cell 20 stores 0V, the voltage on the bit line BL is less than 0.5V. If the memory cell 20 stores 1V, the voltage on the bit line BL is greater than 0.5V.

[0089] The sensing amplifier 10 is also configured to, in the first signal amplification stage, control the first and second ends of the fourth isolation unit 190 to be disconnected and the third and fourth ends to be disconnected, and the first end, the third node C, and the second end of the first signal amplification unit 110 to be turned on, so that the voltage of the third node C is amplified to the first voltage or the second voltage; and in the second signal amplification stage, control the first and second ends of the first isolation unit 140 to be disconnected, control the first and second ends of the fourth isolation unit 190 to be turned on and the third and fourth ends to be turned on, and the first and third ends of the third signal amplification unit 130 of the sensing amplifier 10 to be turned on or the second and third ends to be turned on, so that the voltage of the first data signal line is amplified to the second voltage or the first voltage, so as to output the second voltage or the first voltage to the port.

[0090] Optionally, the sense amplifier 10 is further configured to enter a second precharge phase, in which the first terminal, first node A, and second terminal of the first signal amplifying unit 110 are disconnected, the first terminal, third node C, and second terminal of the first signal amplifying unit 110 are disconnected, the first and third terminals, and the second and third terminals of the second signal amplifying unit 120 are disconnected, the first and third terminals, and the second and third terminals of the third signal amplifying unit 130 are disconnected, the bit line is electrically disconnected from the memory cell 20, the first and second terminals of the first precharge unit 170 are conductive, and the first and second terminals of the second precharge unit 180 are conductive, thereby precharging the first node A, third node C, bit line, and first data signal line to a predetermined voltage. The second precharge phase prepares for the next data read.

[0091] In some embodiments, as shown in FIG. 6 , the sense amplifier 10 further includes an offset cancellation unit 1100 .

[0092] The control end of the offset cancellation unit 1100 is used to be electrically connected to the offset cancellation signal line. The first end, second end, third end and fourth end of the offset cancellation unit 1100 are electrically connected to the second node B, the first node A, the third node C and the fourth node D respectively.

[0093] 6 , the control signal output by the offset cancellation signal line is OC, which can control the conduction between the first and second ends, the third and fourth ends of the offset cancellation unit 1100, and the disconnection between the first and second ends, the third and fourth ends.

[0094] As another example, the sense amplifier 10 is further configured to control, in the third pre-charging stage, the first and second ends of the first pre-charging unit 170 of the sense amplifier 10 to be turned on, the first and second ends of the second pre-charging unit 180 of the sense amplifier 10 to be turned on, the first and second ends of the offset cancellation unit 1100 of the sense amplifier 10 to be turned on and the third and fourth ends to be turned on, and the first and second ends of the first isolation unit 140 of the sense amplifier 10 to be turned on, so as to pre-charge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage.

[0095] The sense amplifier 10 is further configured to control, during the offset cancellation phase, the first and second ends of the first pre-charging unit 170 to be disconnected, the first and second ends of the second pre-charging unit 180 to be disconnected, the first and second ends of the first isolation unit 140 to be disconnected, the first end, the first node A, and the second end of the first signal amplifying unit 110 to be turned on, and the first end, the third node C, and the second end of the first signal amplifying unit 110 to be turned on, so as to cancel the offset of the threshold voltage of the switching device at the fourth and sixth ends of the first signal amplifying unit 110.

[0096] The sense amplifier 10 is further configured to control the first and second terminals of the offset cancellation unit 1100 to be disconnected and the third and fourth terminals to be disconnected during the fourth pre-charging stage, the first and second terminals of the first pre-charging unit 170 to be conductive, and the first and second terminals of the second pre-charging unit 180 to be conductive, so as to pre-charge the first node A and the third node C to a predetermined voltage.

[0097] In some embodiments, as shown in FIG. 7 , the second signal amplifying unit 120 includes a first switch module 121 and a second switch module 122 .

[0098] The control end of the first switch module 121 and the control end of the second switch module 122 serve together as the fourth end of the second signal amplifying unit 120;

[0099] The first end of the first switch module 121 serves as the first end of the second signal amplifying unit 120;

[0100] The second end of the second switch module 122 serves as the second end of the second signal amplifying unit 120;

[0101] The second end of the first switch module 121 and the first end of the second switch module 122 serve together as the third end of the second signal amplifying unit 120 .

[0102] Optionally, the first switch module 121 includes a first switch device T1, and the second switch module 122 includes a second switch device T2. The gate of the first switch device T1 is the control end of the first switch module 121, and the source and drain poles of the first switch device T1 are the first and second ends of the first switch module 121. The gate of the second switch device T2 is the control end of the second switch module 122, and the source and drain poles of the second switch device T2 are the first and second ends of the second switch module 122. The specific setting of the switch device is set according to actual circuit requirements.

[0103] As an example, the first switching device T1 can be a PMOS, the second switching device T2 can be an NMOS, the first end of the first switching module 121 is the source of the PMOS, the second end of the first switching module 121 is the drain of the PMOS, the first end of the second switching module 122 is the drain of the NMOS, and the second end of the second switching module 122 is the source of the NMOS.

[0104] In some embodiments, as shown in FIG7 , the third signal amplifying unit 130 includes a third switch module 131 and a fourth switch module 132 ;

[0105] The control end of the third switch module 131 and the control end of the fourth switch module 132 serve together as the fourth end of the third signal amplifying unit 130;

[0106] The first end of the third switch module 131 serves as the first end of the third signal amplifying unit 130 ;

[0107] The second end of the fourth switch module 132 serves as the second end of the third signal amplifying unit 130;

[0108] The second end of the third switch module 131 and the first end of the fourth switch module 132 together serve as the third end of the third signal amplifying unit 130 .

[0109] Optionally, as shown in Figure 7, the third switch module 131 includes a third switch device T3, the fourth switch module 132 includes a fourth switch device T4, the gate of the third switch device T3 is the control end of the third switch module 131, the source and drain poles of the third switch device T3 are the first and second ends of the third switch module 131, the gate of the fourth switch device T4 is the control end of the fourth switch module 132, the source and drain poles of the fourth switch device T4 are the first and second ends of the fourth switch module 132, and the specific circuit connection is set according to actual circuit requirements.

[0110] As an example, the third switch device T3 can be a PMOS, the fourth switch device T4 can be an NMOS, the first end of the third switch module 131 is the source of the PMOS, the second end of the third switch module 131 is the drain of the PMOS, the first end of the fourth switch module 132 is the drain of the NMOS, and the second end of the fourth switch module 132 is the source of the NMOS.

[0111] In some embodiments, as shown in FIG. 7 , the first signal amplifying unit 110 includes a fifth switch module 111 , a sixth switch module 112 , a seventh switch module 113 and an eighth switch module 114 .

[0112] The first end of the fifth switch module 111 and the first end of the sixth switch module 112 serve together as the first end of the first signal amplifying unit 110 ;

[0113] The second end of the fifth switch module 111 and the first end of the seventh switch module 113 serve together as the third end of the first signal amplifying unit 110 , and the second end of the sixth switch module 112 and the first end of the eighth switch module 114 serve together as the fifth end of the first signal amplifying unit 110 ;

[0114] The second end of the seventh switch module 113 and the second end of the eighth switch module 114 serve together as the second end of the first signal amplifying unit 110 ;

[0115] The control end of the fifth switch module 111 is electrically connected to the third node C, and the control end of the sixth switch module 112 is electrically connected to the first node A;

[0116] The control end of the seventh switch module 113 serves as the fourth end of the first signal amplifying unit 110 , and the control end of the eighth switch module 114 serves as the sixth end of the first signal amplifying unit 110 .

[0117] As an example, referring to FIG7 , the fifth switch module 111 includes a fifth switch device T5, the sixth switch module 112 includes a sixth switch device T6, the seventh switch module 113 includes a seventh switch device T7, and the eighth switch module 114 includes an eighth switch device T8. The fifth switch device T5 and the sixth switch device T6 can be PMOS, while the seventh switch device T7 and the eighth switch device T8 can be NMOS. The specific configuration of the switch devices is determined based on actual circuit requirements.

[0118] Optionally, the gates of the fifth switch device T5, the sixth switch device T6, the seventh switch device T7 and the eighth switch device T8 are respectively the control ends of the fifth switch module 111, the sixth switch module 112, the seventh switch module 113 and the eighth switch module 114, and the source and drain of the fifth switch device T5, the sixth switch device T6, the seventh switch device T7 and the eighth switch device T8 correspond to the first end and the second end of the fifth switch module 111, the sixth switch module 112, the seventh switch module 113 and the eighth switch module 114.

[0119] In some embodiments, as shown in FIG7 , the fourth isolation unit 190 includes: a ninth switch module 191 and a tenth switch module 192 ;

[0120] The control end of the ninth switch module 191 and the control end of the tenth switch module 192 serve together as the control end of the fourth isolation unit 190 ;

[0121] The first end and the second end of the ninth switch module 191 serve as the second end and the first end of the fourth isolation unit 190 respectively;

[0122] The first end and the second end of the tenth switch module 192 serve as the third end and the fourth end of the fourth isolation unit 190 , respectively.

[0123] As an example, referring to FIG. 7 , the ninth switch module 191 includes a ninth switch device T9, and the tenth switch module 192 includes a tenth switch device T10. The ninth switch device T9 and the tenth switch device T10 may be NMOS. The gates of the ninth switch device T9 and the tenth switch device T10 serve as control terminals of the ninth switch module 191 and the tenth switch module 192, respectively. The source and drain terminals of the ninth switch device T9 and the tenth switch device T10 serve as the first and second terminals of the ninth switch module 191 and the tenth switch module 192, respectively.

[0124] In some embodiments, as shown in FIG7 , the offset elimination unit 1100 includes: an eleventh switch module 1101 and a twelfth switch module 1102 ;

[0125] The control end of the eleventh switch module 1101 and the control end of the twelfth switch module 1102 serve together as the control end of the offset elimination unit 1100;

[0126] The first end and the second end of the eleventh switch module 1101 serve as the second end and the first end of the offset elimination unit 1100, respectively;

[0127] The first end and the second end of the twelfth switch module 1102 serve as the third end and the fourth end of the offset cancellation unit 1100 , respectively.

[0128] As an example, referring to FIG7 , the eleventh switch module 1101 includes an eleventh switch device T11, and the twelfth switch module 1102 includes a twelfth switch device T12. The eleventh switch device T11 and the twelfth switch device T12 may be NMOS devices. The gates of the eleventh switch device T11 and the twelfth switch device T12 serve as control terminals of the eleventh switch module 1101 and the twelfth switch module 1102, respectively. The source and drain electrodes of the eleventh switch device T11 and the twelfth switch device T12 serve as the first terminal and the second terminal of the eleventh switch module 1101 and the twelfth switch module 1102, respectively.

[0129] As shown in Figure 7, the first isolation unit 140 includes a thirteenth switching device T13, the second isolation unit 150 includes a fourteenth switching device T14, and the third isolation unit 160 includes a fifteenth switching device T15. The gates of the thirteenth switching device T13, the fourteenth switching device T14, and the fifteenth switching device T15 are respectively the control ends of the first isolation unit 140, the second isolation unit 150, and the third isolation unit 160. The source and drain of the thirteenth switching device T13, the fourteenth switching device T14, and the fifteenth switching device T15 correspond to the first end and the second end of the first isolation unit 140, the second isolation unit 150, and the third isolation unit 160, respectively.

[0130] Referring to FIG8 , there is shown a schematic diagram of the structure of the sense amplifier connected to the storage unit 20 and the port. IOB is the opposite signal of IO and is output to the port. The second signal amplifying unit 120 is connected to RTO1 and SB1, and the third signal amplifying unit 130 is connected to RTO2 and SB2, one for IO and the other for IOB. In the stage where RTO1 and SB1 and RTO2 and SB2 are turned on at the same time, if a data read operation is performed, RTO1 and SB1, RTO2 and SB2 can improve the data transmission effect on the port. After turning on the switch device CSL, the stability of the data on IO and IOB can be guaranteed. Turning on the switch device CSL can provide the function of data reading. After turning off the switch device CSL, the effect of the IO load affecting the reading and writing can be isolated.

[0131] Based on the same inventive concept, an embodiment of the present disclosure provides a memory array structure, as shown in FIG9 , the memory array structure includes: a plurality of bit lines, a plurality of word lines, a plurality of memory cells 20 distributed in a matrix, and a plurality of sense amplifiers 10 according to an embodiment of the present disclosure;

[0132] One bit line is electrically connected to one column of memory cells 20;

[0133] One word line is electrically connected to one row of memory cells 20;

[0134] Each bit line is electrically connected to the third terminal of the second signal amplifying unit 120 of a corresponding sense amplifier 10 .

[0135] 7 to 9 , the memory cell 20 includes a switching device 16 and a capacitor. The control end of the switching device 16 is electrically connected to the word line. The switching device 16 is turned on and off by controlling the output control signal WL of the word line to control the connection and disconnection between the memory cell 20 and the bit line BL.

[0136] It should be noted that the circuit connection method disclosed in the present invention is only an example of the sensing amplifier provided in the embodiment of the present invention. Each switching device can select different transistors such as PMOS or NMOS as needed, and the electrical connection method of each component in the sensing amplifier provided in the embodiment of the present invention can be adaptively adjusted. The adaptively adjusted electrical connection method still falls within the protection scope of the embodiment of the present invention.

[0137] Based on the same inventive concept, an embodiment of the present disclosure provides a dynamic random access memory, including: a storage array structure.

[0138] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including: a storage array structure as in the embodiment of the present disclosure or a dynamic random access memory as in the embodiment of the present disclosure.

[0139] The electronic device can be a mobile terminal such as a smart phone, a laptop computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle-mounted terminal (such as a vehicle-mounted navigation terminal), etc., as well as a fixed terminal such as a smart TV, a desktop computer, etc.

[0140] Based on the same inventive concept, an embodiment of the present disclosure provides a control method, which is applied to the sense amplifier 10 of the embodiment of the present disclosure. Referring to FIG. 10 , the control method includes:

[0141] S1001, a first signal amplification stage, controlling the first terminal, the first node A, and the second terminal of the first signal amplification unit 110 to be conductive, so that the voltage of the first node A is amplified to a first voltage or a second voltage;

[0142] S1002, second signal amplification stage, the first terminal and the third terminal of the second signal amplification unit 120 are turned on or the second terminal and the third terminal are turned on, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the memory cell 20 of the memory array structure.

[0143] In some embodiments, before the first signal amplification stage, the method further includes:

[0144] In a first precharging stage, the first and second terminals of the first precharging unit 170 of the sense amplifier 10 are controlled to be conductive, the first and second terminals of the second precharging unit 180 of the sense amplifier 10 are controlled to be conductive, the first and second terminals of the fourth isolation unit 190 of the sense amplifier 10 are controlled to be conductive, and the third and fourth terminals of the fourth isolation unit 190 of the sense amplifier 10 are controlled to be conductive, and the first and second terminals of the first isolation unit 140 of the sense amplifier 10 are controlled to be conductive, so as to precharge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage; the predetermined voltage is less than the first voltage;

[0145] In the charge sharing stage, the first and second ends of the first pre-charging unit 170 and the second pre-charging unit 180 are disconnected, and the predetermined voltage of the bit line is charged with the capacitor of the memory cell 20 .

[0146] In some embodiments, during the first signal amplification stage, the method further includes:

[0147] Controlling the first and second ends of the fourth isolation unit 190 to be disconnected and the third and fourth ends to be disconnected, and connecting the first end, the third node C, and the second end of the first signal amplification unit 110 to each other, so that the voltage of the third node C is amplified to the second voltage or the first voltage;

[0148] In the second signal amplification stage, it also includes:

[0149] The first end and the second end of the first isolation unit 140 are controlled to be disconnected, the first end and the second end of the fourth isolation unit 190 are controlled to be connected and the third end and the fourth end are controlled to be connected, and the first end and the third end of the third signal amplification unit 130 of the sense amplifier 10 are controlled to be connected or the second end and the third end are controlled, so that the voltage of the first data signal line is amplified to the first voltage or the second voltage, so as to output the first voltage or the second voltage to the port.

[0150] In some embodiments, after the second signal amplification stage, the method further includes:

[0151] In the second pre-charging stage, the first end, the first node A, and the second end of the first signal amplifying unit 110 are controlled to be disconnected, the first end, the third node C, and the second end of the first signal amplifying unit 110 are disconnected, the first end and the third end of the second signal amplifying unit 120 are disconnected, and the second end and the third end are disconnected, the first end and the third end of the third signal amplifying unit 130 are disconnected, and the second end and the third end are disconnected, the bit line is electrically disconnected from the memory cell 20, the first end and the second end of the first pre-charging unit 170 are turned on, and the first end and the second end of the second pre-charging unit 180 are turned on, so as to pre-charge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage.

[0152] As an example, referring to FIG11 , a first control method is provided, including:

[0153] S1101, in a first precharging stage, the first and second ends of the first precharging unit 170 of the sensing amplifier 10 are controlled to be turned on, the first and second ends of the second precharging unit 180 of the sensing amplifier 10 are controlled to be turned on, the first and second ends of the fourth isolation unit 190 of the sensing amplifier 10 are controlled to be turned on, and the third and fourth ends are controlled to be turned on, and the first and second ends of the first isolation unit 140 of the sensing amplifier 10 are controlled to be turned on, so as to precharge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage; the predetermined voltage is lower than the first voltage.

[0154] S1102 , charge sharing stage, controlling the first and second ends of the first pre-charging unit 170 to be disconnected, and the first and second ends of the second pre-charging unit 180 to be disconnected, so as to share charge between the predetermined voltage of the bit line and the capacitor of the memory cell 20 .

[0155] S1103, in the first signal amplification stage, the first end, the first node A, and the second end of the first signal amplifying unit 110 are controlled to be conductive, so that the voltage of the first node A is amplified to the first voltage or the second voltage; the first end and the second end of the fourth isolation unit 190 are controlled to be disconnected and the third end and the fourth end are disconnected, and the first end, the third node C, and the second end of the first signal amplifying unit 110 are controlled to be conductive, so that the voltage of the third node C is amplified to the second voltage or the first voltage.

[0156] S1104, second signal amplification stage, controlling the first and third terminals of the second signal amplification unit 120 to be turned on or the second and third terminals to be turned on, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the memory cell 20 of the memory array structure; controlling the first and second terminals of the first isolation unit 140 to be disconnected, controlling the first and second terminals of the fourth isolation unit 190 to be turned on and the third and fourth terminals to be turned on, controlling the first and third terminals of the third signal amplification unit 130 of the sense amplifier 10 to be turned on or the second and third terminals to be turned on, so that the voltage of the first data signal line is amplified to the first voltage or the second voltage, so as to output the first voltage or the second voltage to the port.

[0157] S1105, second pre-charging stage, controlling the first end, the first node A and the second end of the first signal amplifying unit 110 to be disconnected, the first end, the third node C and the second end of the first signal amplifying unit 110 to be disconnected, the first end and the third end of the second signal amplifying unit 120 to be disconnected and the second end and the third end to be disconnected, the first end and the third end of the third signal amplifying unit 130 to be disconnected and the second end and the third end to be disconnected, the bit line is electrically disconnected from the memory cell 20, the first end and the second end of the first pre-charging unit 170 to be turned on, the first end and the second end of the second pre-charging unit 180 to be turned on, so as to pre-charge the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage.

[0158] As an example, the first control method may include: in a first signal amplification stage, controlling the first end, the first node A, and the second end of the first signal amplification unit 110 to be turned on, so that the voltage of the first node A is amplified to the first voltage; controlling the first end and the second end of the fourth isolation unit 190 to be disconnected and the third end and the fourth end to be disconnected, and the first end, the third node C, and the second end of the first signal amplification unit 110 to be turned on, so that the voltage of the third node C is amplified to the second voltage.

[0159] In the second signal amplification stage, the second end and the third end of the second signal amplification unit 120 are turned on, so that the voltage of the bit line is amplified to the second voltage to write the second voltage back to the memory cell 20 of the memory array structure; the first end and the second end of the first isolation unit 140 are controlled to be disconnected, the first end and the second end of the fourth isolation unit 190 are controlled to be turned on and the third end and the fourth end are turned on, and the first end and the third end of the third signal amplification unit 130 of the sense amplifier 10 are turned on, so that the voltage of the first data signal line is amplified to the first voltage to output the first voltage to the port.

[0160] Similarly, the first control method also includes: in the first signal amplification stage, controlling the first end, the first node A, and the second end of the first signal amplification unit 110 to be turned on, so that the voltage of the first node A is amplified to the second voltage; controlling the first end and the second end of the fourth isolation unit 190 to be disconnected and the third end and the fourth end to be disconnected, and the first end, the third node C, and the second end of the first signal amplification unit 110 to be turned on, so that the voltage of the third node C is amplified to the first voltage.

[0161] In the second signal amplification stage, the first and third terminals of the second signal amplifying unit 120 are turned on, so that the voltage of the bit line is amplified to the first voltage to write the first voltage back to the memory cell 20 of the memory array structure; the first and second terminals of the first isolation unit 140 are controlled to be disconnected, the first and second terminals of the fourth isolation unit 190 are controlled to be turned on and the third and fourth terminals are turned on, and the second and third terminals of the third signal amplifying unit 130 of the sense amplifier 10 are turned on, so that the voltage of the first data signal line is amplified to the second voltage to output the second voltage to the port.

[0162] In some embodiments, before the first signal amplification stage, the method further includes:

[0163] In the third precharging stage, the first and second terminals of the first precharging unit 170 of the sense amplifier 10 are controlled to be conductive, the first and second terminals of the second precharging unit 180 of the sense amplifier 10 are controlled to be conductive, the first and second terminals of the offset cancellation unit 1100 of the sense amplifier 10 are controlled to be conductive, and the third and fourth terminals of the offset cancellation unit 1100 are controlled to be conductive, and the first and second terminals of the first isolation unit 140 of the sense amplifier 10 are controlled to be conductive, so as to precharge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage.

[0164] In the offset elimination phase, the first and second ends of the first pre-charging unit 170 are disconnected, the first and second ends of the second pre-charging unit 180 are disconnected, the first and second ends of the first isolation unit 140 are disconnected, the first end, the first node A, and the second end of the first signal amplifying unit 110 are connected, and the first end, the third node C, and the second end of the first signal amplifying unit 110 are connected, so as to eliminate the offset of the threshold voltage of the switching device at the fourth and sixth ends of the first signal amplifying unit 110;

[0165] In the fourth pre-charging stage, the first and second terminals of the offset cancellation unit 1100 are disconnected, and the third and fourth terminals are disconnected. The first and second terminals of the first pre-charging unit 170 are connected, and the first and second terminals of the second pre-charging unit 180 are connected, so as to pre-charge the first node A and the third node C to a predetermined voltage.

[0166] In the charge sharing stage, the first and second ends of the first pre-charging unit 170 and the second pre-charging unit 180 are disconnected, and the predetermined voltage of the bit line is charged with the capacitor of the memory cell 20 .

[0167] As an example, referring to FIG12 , a second control method is provided, including:

[0168] S1201, a third pre-charging stage, controlling the first and second terminals of the first pre-charging unit 170 of the sense amplifier 10 to be conductive, the first and second terminals of the second pre-charging unit 180 of the sense amplifier 10 to be conductive, the first and second terminals of the offset cancellation unit 1100 of the sense amplifier 10 to be conductive, and the third and fourth terminals to be conductive, and the first and second terminals of the first isolation unit 140 of the sense amplifier 10 to be conductive, so as to pre-charge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage

[0169] S1202, offset elimination stage, controlling the first and second ends of the first pre-charging unit 170 to be disconnected, the first and second ends of the second pre-charging unit 180 to be disconnected, the first and second ends of the first isolation unit 140 to be disconnected, the first end, the first node A, and the second end of the first signal amplifying unit 110 to be conductive, and the first end, the third node C, and the second end of the first signal amplifying unit 110 to be conductive, so as to eliminate the offset of the threshold voltage of the switching device at the fourth and sixth ends of the first signal amplifying unit 110

[0170] S1203, in the fourth pre-charging stage, the first and second ends of the offset elimination unit 1100 are controlled to be disconnected and the third and fourth ends are disconnected, the first and second ends of the first pre-charging unit 170 are connected, and the first and second ends of the second pre-charging unit 180 are connected, so as to pre-charge the first node A and the third node C to a predetermined voltage.

[0171] S1204 , charge sharing stage, controlling the first and second ends of the first pre-charging unit 170 to be disconnected, and the first and second ends of the second pre-charging unit 180 to be disconnected, so as to share charge between the predetermined voltage of the bit line and the capacitor of the memory cell 20 .

[0172] S1205, in the first signal amplification stage, the first end, the first node A, and the second end of the first signal amplifying unit 110 are controlled to be conductive, so that the voltage of the first node A is amplified to the first voltage or the second voltage; the first end and the second end of the fourth isolation unit 190 are controlled to be disconnected and the third end and the fourth end are disconnected, and the first end, the third node C, and the second end of the first signal amplifying unit 110 are controlled to be conductive, so that the voltage of the third node C is amplified to the second voltage or the first voltage.

[0173] S1206, second signal amplification stage, the first end and the third end of the second signal amplification unit 120 are turned on or the second end and the third end are turned on, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the memory cell 20 of the memory array structure; the first end and the second end of the first isolation unit 140 are controlled to remain disconnected, the first end and the second end of the fourth isolation unit 190 are controlled to be turned on and the third end and the fourth end are turned on, the first end and the third end of the third signal amplification unit 130 of the sensing amplifier 10 are turned on or the second end and the third end are turned on, so that the voltage of the first data signal line is amplified to the first voltage or the second voltage, so as to output the first voltage or the second voltage to the port.

[0174] S1207, second pre-charging stage, controlling the first end, the first node A and the second end of the first signal amplifying unit 110 to be disconnected, the first end, the third node C and the second end of the first signal amplifying unit 110 to be disconnected, the first end and the third end of the second signal amplifying unit 120 to be disconnected and the second end and the third end to be disconnected, the first end and the third end of the third signal amplifying unit 130 to be disconnected and the second end and the third end to be disconnected, the bit line is electrically disconnected from the memory cell 20, the first end and the second end of the first pre-charging unit 170 to be turned on, the first end and the second end of the second pre-charging unit 180 to be turned on, so as to pre-charge the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage.

[0175] Figures 13 and 14 show the timing diagrams of the first control method. The first control method is divided into five phases: the first pre-charge phase, the charge sharing phase, the first signal amplification phase, the second signal amplification phase, and the second pre-charge phase, corresponding to states 1, 2, 3, 4, and 5, respectively. The first control method eliminates the OC and performs signal amplification twice, achieving the effect of reading data from memory cell 20 using the timing control method of Figure 13. This method eliminates the OC enable, allowing normal reading of the stored data in memory cell 20.

[0176] 7 and 14 , the first control method includes:

[0177] First pre-charge stage: EQ, ISO1, ISO2, ISO3, PRE open, V BLEP Precharge SABL and SABLB as well as BL and BLB to 0.5V;

[0178] Charge sharing stage: EQ and PRE are turned off, WL and ISO1, ISO2, and ISO3 are still turned on, and the charge sharing state is in progress;

[0179] First signal amplification stage: ISO1 is closed, WL, ISO2, and ISO3 are still open, and RTO and SB are turned on, and SABL and SABLB are amplified for the first time using the sense amplifier SA;

[0180] Second signal amplification stage: ISO3 is turned off, the reference power supply is isolated, WL, ISO1, and ISO2 are turned on for the second signal sensing amplification. At the same time, RTO1 and SB1, RTO2, and SB2 are turned on to enable the data write-back function, and CSL is turned on to provide the data read-out function.

[0181] Second pre-charge stage: WL is turned off, then RTO, RTO1, RTO2 and SB, SB1, SB2 are turned off, and then EQ and PRE are turned on to charge BL and BLB as well as SABL and SABLB to 0.5V, so that the DRAM returns to the ideal state and prepares for the next read and write.

[0182] Figures 15 and 16 show the timing diagrams of the second control method. The second control method is divided into 7 stages. The second control method retains OC and performs signal amplification twice. The third pre-charge stage, offset elimination stage, fourth pre-charge stage, charge sharing stage, first signal amplification stage, second signal amplification stage, and second pre-charge stage correspond to state1, state2, state3, state4, state5, state6, and state7, respectively.

[0183] 7 and 16 , the second control method includes:

[0184] The third pre-charge stage: EQ, ISO2, 3, PRE, OC is turned on, VBLEP pre-charges SABL and SABLB as well as BL and BLB to 0.5V

[0185] Offset cancellation stage: EQ and PRE are turned off, OC, SB and RTO are turned on for mismatch cancellation process

[0186] Fourth pre-charge stage: turn off OC and turn on EQ and PRE to pre-charge SABL and SABLB to 0.5V

[0187] The charge sharing phase, the first signal amplification phase, the second signal amplification phase, and the second pre-charging phase of the first control method are executed. During the execution process, ISO3 needs to be kept closed to isolate the reference power supply.

[0188] The second control method is to use the timing control method of Figure 15 to read the data of the storage unit 20. This method retains the enable mode of OC, and can normally sense the mismatch voltage of the two amplifying NMOS (switching devices T7 and T8) using this method, thereby increasing the sensing accuracy and allowing the storage data of the storage unit 20 to be read normally.

[0189] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this disclosure may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this disclosure may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this disclosure may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0190] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this disclosure, unless otherwise specified, "plurality" means two or more.

[0191] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0192] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0193] The above description is only part of the embodiments of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A sense amplifier, wherein: include: A first signal amplifying unit, wherein the first end and the second end are respectively used to be electrically connected to the first voltage end and the second voltage end, and the third end and the fourth end are respectively used as the first node and the second node; The first voltage terminal is used to output a first voltage, and the second voltage terminal is used to output a second voltage, wherein the first voltage is greater than the second voltage; a second signal amplifying unit, wherein the first end, the second end and the third end are respectively used to be electrically connected to the third voltage end, the fourth voltage end and the bit line, and the fourth end is electrically connected to the first node; the voltage of the third voltage end is the same as the voltage of the first voltage end, and the voltage of the fourth voltage end is the same as the voltage of the second voltage end; and the bit line is used to be electrically connected to the storage unit of the storage array structure; The sensing amplifier is configured such that in a first signal amplification stage, the first end, the first node, and the second end of the first signal amplification unit are turned on, so that the voltage of the first node is amplified to the first voltage or the second voltage; in a second signal amplification stage, the first end and the third end or the second end and the third end of the second signal amplification unit are turned on, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the storage unit.

2. The sense amplifier according to claim 1, wherein: The fifth end and the sixth end of the first signal amplifying unit serve as the third node and the fourth node respectively; The sensing amplifier further comprises: a third signal amplifying unit, wherein the first end, the second end and the third end are respectively used to be electrically connected to the fifth voltage end, the sixth voltage end and the first data signal line, and the fourth end is electrically connected to the third node; the voltage of the fifth voltage end is the same as the voltage of the first voltage end, and the voltage of the sixth voltage end is the same as the voltage of the second voltage end; the first data signal line is used to be electrically connected to the port; The sensing amplifier is further configured that in a first signal amplification stage, the first end, the third node and the second end of the first signal amplification unit are turned on, so that the voltage of the third node is amplified to the second voltage or the first voltage; in a second signal amplification stage, the first end and the third end of the third signal amplification unit are turned on or the second end and the third end are turned on, so that the voltage of the first data signal line is amplified to the first voltage or the second voltage, so as to output the first voltage or the second voltage to the port.

3. The sense amplifier according to claim 2, wherein: Also includes: A first isolation unit, wherein the control end is used to be electrically connected to the first isolation signal line, and the first end and the second end are used to be electrically connected to the first reference voltage end and the first data signal line respectively; The first isolation unit is configured such that in the second signal amplification stage, the first end and the second end of the first isolation unit are disconnected to amplify the voltage of the first data signal line.

4. The sense amplifier according to claim 3, wherein: Also includes: A second isolation unit, wherein the control end and the first end are respectively used to be electrically connected to the second isolation signal line and the bit line, and the second end is electrically connected to the second node; The second isolation unit is configured such that in a working state, the first end and the second end of the second isolation unit are connected; in a non-working state, the first end and the second end of the second isolation unit are disconnected.

5. The sense amplifier according to claim 4, wherein: Also includes: A third isolation unit, wherein the control end is used to be electrically connected to the third isolation signal line, and the first end and the second end are electrically connected to the first data signal line and the fourth node respectively; the third isolation signal line is electrically connected to the second isolation signal line; The third isolation unit is configured such that in a working state, the first end and the second end of the third isolation unit are conductive; in a non-working state, In the working state, the first end and the second end of the third isolation unit are disconnected.

6. The sense amplifier according to claim 1, wherein: The second signal amplifying unit includes a first switch module and a second switch module; The control end of the first switch module and the control end of the second switch module are used together as the fourth end of the second signal amplifying unit; The first end of the first switch module serves as the first end of the second signal amplifying unit; The second end of the second switch module serves as the second end of the second signal amplifying unit; The second end of the first switch module and the first end of the second switch module together serve as the third end of the second signal amplifying unit.

7. The sense amplifier according to claim 2, wherein: The third signal amplifying unit includes a third switch module and a fourth switch module; The control end of the third switch module and the control end of the fourth switch module together serve as the fourth end of the third signal amplifying unit; The first end of the third switch module serves as the first end of the third signal amplifying unit; The second end of the fourth switch module serves as the second end of the third signal amplifying unit; The second end of the third switch module and the first end of the fourth switch module together serve as the third end of the third signal amplifying unit.

8. The sense amplifier according to claim 2, wherein: The first signal amplifying unit includes a fifth switch module, a sixth switch module, a seventh switch module and an eighth switch module; The first end of the fifth switch module and the first end of the sixth switch module jointly serve as the first end of the first signal amplifying unit; The second end of the fifth switch module and the first end of the seventh switch module are used together as the third end of the first signal amplifying unit, and the second end of the sixth switch module and the first end of the eighth switch module are used together as the fifth end of the first signal amplifying unit; The second end of the seventh switch module and the second end of the eighth switch module serve together as the second end of the first signal amplifying unit; The control end of the fifth switch module is electrically connected to the third node, and the control end of the sixth switch module is electrically connected to the first node; The control end of the seventh switch module serves as the fourth end of the first signal amplifying unit, and the control end of the eighth switch module serves as the sixth end of the first signal amplifying unit.

9. The sense amplifier according to any one of claims 3 to 5, wherein: Also includes: A first pre-charging unit, wherein the control end is electrically connected to the first signal line, the first end is electrically connected to the first reference voltage end, and the second end is electrically connected to the third node; the first reference voltage end is used to output a first reference voltage; A second pre-charging unit, wherein the control end is used to be electrically connected to the second signal line, and the first end and the second end are electrically connected to the first node and the third node respectively; The fourth isolation unit has a control end for electrically connecting to a fourth isolation signal line, and a first end, a second end, a third end and a fourth end for electrically connecting to a second node, a third node, a first node and a fourth node respectively.

10. The sense amplifier according to claim 9, wherein: Also includes: The offset elimination unit has a control end for electrically connecting to the offset elimination signal line, and a first end, a second end, a third end and a fourth end for electrically connecting to the second node, the first node, the third node and the fourth node respectively.

11. The sense amplifier according to claim 9, wherein: The fourth isolation unit includes: a ninth switch module and a tenth switch module; The control end of the ninth switch module and the control end of the tenth switch module jointly serve as the control end of the fourth isolation unit; The first end and the second end of the ninth switch module serve as the second end and the first end of the fourth isolation unit respectively; The first end and the second end of the tenth switch module serve as the third end and the fourth end of the fourth isolation unit, respectively.

12. The sense amplifier according to claim 10, wherein: The offset elimination unit includes: an eleventh switch module and a twelfth switch module; The control end of the eleventh switch module and the control end of the twelfth switch module are used together as the control end of the offset elimination unit; The first end and the second end of the eleventh switch module serve as the second end and the first end of the offset elimination unit respectively; The first end and the second end of the twelfth switch module serve as the third end and the fourth end of the offset elimination unit respectively.

13. A storage array structure, wherein: include: A plurality of bit lines, a plurality of word lines, a plurality of memory cells distributed in a matrix, and a plurality of sense amplifiers as claimed in any one of claims 1 to 12; One of the bit lines is electrically connected to one column of the memory cells; One of the word lines is electrically connected to one row of memory cells; Each bit line is electrically connected to a corresponding third terminal of the second signal amplifying unit of the sensing amplifier.

14. A dynamic random access memory, wherein: include: The storage array structure as claimed in claim 13.

15. An electronic device, wherein: include: The memory array structure as claimed in claim 13 or the dynamic random access memory as claimed in claim 14.

16. A control method, applied to the sensing amplifier according to any one of claims 1 to 12, wherein: include: In the first signal amplification stage, the first end, the first node, and the second end of the first signal amplification unit are controlled to be conductive, so that the voltage of the first node is amplified to the first voltage or the second voltage; In the second signal amplification stage, the first and third ends of the second signal amplification unit are turned on or the second and third ends are turned on, so that the voltage of the bit line is amplified to the second voltage or the first voltage, so as to write the second voltage or the first voltage back to the storage cell of the storage array structure.

17. The control method according to claim 16, wherein: Before the first signal amplification stage, it also includes: In a first precharging stage, the first and second ends of the first precharging unit of the sensing amplifier are controlled to be turned on, the first and second ends of the second precharging unit of the sensing amplifier are turned on, the first and second ends of the fourth isolation unit of the sensing amplifier are turned on, and the third and fourth ends are turned on, and the first and second ends of the first isolation unit of the sensing amplifier are turned on, so as to precharge the first node, the third node, the bit line and the first data signal line to a predetermined voltage; the predetermined voltage is less than the first voltage; In the charge sharing stage, the first and second ends of the first pre-charging unit are disconnected, and the first and second ends of the second pre-charging unit are disconnected, so that the predetermined voltage of the bit line and the capacitor of the storage unit are charged.

18. The control method according to claim 17, wherein: In the first signal amplification stage, it also includes: Controlling the first end and the second end of the fourth isolation unit to be disconnected and the third end and the fourth end to be disconnected, and the first end, the third node and the second end of the first signal amplification unit to be turned on, so that the voltage of the third node is amplified to the second voltage or the first voltage; In the second signal amplification stage, it also includes: The first end and the second end of the first isolation unit are controlled to be disconnected, the first end and the second end of the fourth isolation unit are controlled to be connected and the third end and the fourth end are controlled to be connected, the first end and the third end of the third signal amplification unit of the sensing amplifier are controlled to be connected or the second end and the third end are controlled to be connected, so that the voltage of the first data signal line is amplified to the first voltage or the second voltage, so as to convert the first voltage or the second voltage into Voltage output to the port.

19. The control method according to claim 18, wherein: After the second signal amplification stage, it also includes: In the second pre-charging stage, the first end, the first node and the second end of the first signal amplifying unit are controlled to be disconnected, the first end, the third node and the second end of the first signal amplifying unit are disconnected, the first end and the third end of the second signal amplifying unit are disconnected and the second end and the third end are disconnected, the first end and the third end of the third signal amplifying unit are disconnected and the second end and the third end are disconnected, the bit line is electrically disconnected from the storage unit, the first end and the second end of the first pre-charging unit are turned on, and the first end and the second end of the second pre-charging unit are turned on, so as to pre-charge the first node, the third node, the bit line and the first data signal line to a predetermined voltage.

20. The control method according to claim 16, wherein: Before the first signal amplification stage, it also includes: In a third precharging stage, the first and second ends of the first precharging unit of the sensing amplifier are controlled to be turned on, the first and second ends of the second precharging unit of the sensing amplifier are controlled to be turned on, the first and second ends of the offset cancellation unit of the sensing amplifier are controlled to be turned on and the third and fourth ends of the offset cancellation unit of the sensing amplifier are controlled to be turned on, and the first and second ends of the first isolation unit of the sensing amplifier are controlled to be turned on, so as to precharge the first node, the third node, the bit line and the first data signal line to a predetermined voltage; In the offset elimination stage, the first end and the second end of the first pre-charging unit are controlled to be disconnected, the first end and the second end of the second pre-charging unit are controlled to be disconnected, the first end and the second end of the first isolation unit are controlled to be disconnected, the first end, the first node and the second end of the first signal amplifying unit are controlled to be turned on, and the first end, the third node and the second end of the first signal amplifying unit are controlled to be turned on, so as to eliminate the offset of the threshold voltage of the switch device at the fourth end and the sixth end of the first signal amplifying unit; In a fourth pre-charging stage, the first and second ends of the offset elimination unit are controlled to be disconnected and the third and fourth ends are controlled to be disconnected, the first and second ends of the first pre-charging unit are controlled to be conductive, and the first and second ends of the second pre-charging unit are controlled to be conductive, so as to pre-charge the first node and the third node to a predetermined voltage; In the charge sharing stage, the first and second ends of the first pre-charging unit are disconnected, and the first and second ends of the second pre-charging unit are disconnected, so that the predetermined voltage of the bit line and the capacitor of the storage unit are charged.

21. The control method according to claim 20, wherein: After the second signal amplification stage, it also includes: In the second pre-charging stage, the first end, the first node and the second end of the first signal amplifying unit are controlled to be disconnected, the first end, the third node and the second end of the first signal amplifying unit are disconnected, the first end and the third end of the second signal amplifying unit are disconnected and the second end and the third end are disconnected, the first end and the third end of the third signal amplifying unit are disconnected and the second end and the third end are disconnected, the bit line is electrically disconnected from the storage unit, the first end and the second end of the first pre-charging unit are turned on, and the first end and the second end of the second pre-charging unit are turned on, so as to pre-charge the first node, the third node, the bit line and the first data signal line to a predetermined voltage.

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