Display substrate and driving method therefor, and display device

Abstract

A display substrate and a driving method therefor, and a display device. The display substrate comprises: a base substrate, and first level signal lines (VGL) and shift register units which are both arranged on the base substrate. The shift register units each comprise a first output transistor (T10), a gate driving signal output end (OUT), and a first output control node (N7); a gate (101) of the first output transistor (T10) is coupled to the first output control node (N7); a first electrode (102) of the first output transistor (T10) is coupled to a first level signal line (VGL); a second electrode (103) of the first output transistor (T10) is coupled to the gate driving signal output end (OUT); first capacitance (C_N7_OUT) is formed between the first output control node (N7) and the gate driving signal output end (OUT); second capacitance (C_N7_VGL) is formed between the first output control node (N7) and the first level signal lines (VGL); and the value of the first capacitance (C_N7_OUT) is greater than or equal to the value of the second capacitance (C_N7_VGL).

Description

Display substrate, driving method thereof, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311422427.6 filed in China on October 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0004] Currently, active-matrix organic light-emitting diode (AMOLED) flexible screen technology is becoming increasingly mature. Its bendability, high contrast, and low power consumption make it the next-generation display method to replace liquid crystal displays (LCDs).

[0005] With the continuous advancements in the OLED industry, numerous gate drive circuits have been proposed for various new functions. These gate drive circuits can be integrated on array substrates, facilitating the development of narrow-frame display products. However, current gate drive circuits often produce poor image quality when driving display products.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide a display substrate, a driving method thereof, and a display device.

[0008] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0009] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a first level signal line and a shift register unit both provided on the base substrate;

[0010] The shift register unit includes a first output transistor, a gate drive signal output terminal, and a first output control node; the gate of the first output transistor is coupled to the first output control node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate drive signal output terminal;

[0011] A first capacitor is formed between the first output control node and the gate drive signal output terminal, and a second capacitor is formed between the first output control node and the first level signal line. The capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor.

[0012] Optionally, the gate of the first output transistor includes at least one gate pattern, and the gate pattern extends along a first direction; the first electrode of the first output transistor includes at least one first electrode pattern, and the first electrode pattern extends along the first direction; the second electrode of the first output transistor includes at least one second electrode pattern, and the second electrode pattern extends along the first direction;

[0013] The first electrode pattern and the second electrode pattern are arranged along a second direction, and the second direction intersects the first direction; the orthographic projection of the gate pattern on the base substrate is located between the orthographic projection of the first electrode pattern and the orthographic projection of the second electrode pattern on the base substrate;

[0014] There is a first distance between the orthographic projection of at least one gate pattern on the base substrate and the orthographic projection of the adjacent first electrode pattern on the base substrate; there is a second distance between the orthographic projection of at least one gate pattern on the base substrate and the orthographic projection of the adjacent second electrode pattern on the base substrate; the first distance is greater than the second distance.

[0015] Optionally, the gate of the first output transistor includes a gate connection portion and at least two gate patterns respectively coupled to the gate connection portion; the first pole of the first output transistor includes a first electrode connection portion and at least two first electrode patterns respectively coupled to the first electrode connection portion; the second pole of the first output transistor includes a second electrode connection portion and at least two second electrode patterns respectively coupled to the second electrode connection portion; the first electrode pattern and the second electrode pattern are alternately arranged along the second direction; the first electrode connection portion is coupled to the first level signal line, and the second electrode connection portion is coupled to the gate drive signal output end.

[0016] Optionally, each gate pattern has the first distance between its orthographic projection on the base substrate and the orthographic projection of the adjacent first electrode pattern on the base substrate; each gate pattern has the second distance between its orthographic projection on the base substrate and the orthographic projection of the adjacent second electrode pattern on the base substrate.

[0017] Optionally, an orthographic projection of at least one of the gate patterns on the base substrate at least partially overlaps with an orthographic projection of the second electrode connecting portion on the base substrate.

[0018] Optionally, the shift register unit further includes an output terminal connection portion, which is coupled to the gate drive signal output terminal and the second electrode of the first output transistor respectively; the orthographic projection of the output terminal connection portion on the base substrate does not overlap with the orthographic projection of the gate pattern on the base substrate.

[0019] Optionally, the shift register unit further includes an output end extension portion, the output end extension portion is coupled to the output end connection portion, and an orthographic projection of the output end extension portion on the base substrate at least partially overlaps with an orthographic projection of the gate pattern on the base substrate.

[0020] Optionally, an orthographic projection of the output end extension portion on the base substrate at least partially overlaps with an orthographic projection of the second electrode connecting portion on the base substrate.

[0021] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, and a first source / drain metal layer stacked in sequence in a direction away from the base substrate;

[0022] The gate of the first output transistor is provided in the same layer and material as the first gate metal layer; the first electrode and the second electrode of the first output transistor are provided in the same layer and material as the first source-drain metal layer; the output terminal connecting portion and the output terminal extending portion are provided in the same layer and material as the second gate metal layer.

[0023] Optionally, the first output transistor further includes a first output active layer;

[0024] The shift register unit also includes a first compensation pattern, which is coupled to the gate of the first output transistor; the orthographic projection of the first compensation pattern on the base substrate does not overlap with the orthographic projection of the first output active layer on the base substrate; the orthographic projection of the first compensation pattern on the base substrate at least partially overlaps with the orthographic projection of the output end extension portion on the base substrate.

[0025] Optionally, the output end extension portion includes a first extension portion and a second extension portion coupled to each other, the first extension portion extends along a first direction, and the second extension portion extends along a second direction; the orthographic projection of the first extension portion on the base substrate at least partially overlaps with the orthographic projection of the first compensation pattern on the base substrate; the orthographic projection of the second extension portion on the base substrate at least partially overlaps with the orthographic projection of the second electrode connecting portion on the base substrate; the first compensation pattern and the gate pattern are arranged along the second direction.

[0026] Optionally, the first output transistor further includes a first output active layer, the first output active layer has a first length along the first direction, the gate pattern has a second length along the first direction, and the first length is less than or equal to 2 / 3 of the second length.

[0027] Optionally, the second electrode pattern has a third length along the first direction, and the first length is less than or equal to 2 / 3 of the third length.

[0028] Optionally, the first electrode pattern has a fourth length along the first direction, the fourth length is smaller than the third length, and / or the fourth length is smaller than the second length.

[0029] Optionally, the shift register unit further includes a compensation capacitor, the compensation capacitor including a first compensation plate and a second compensation plate, the first compensation plate being coupled to the gate of the first output transistor, the second compensation plate being coupled to the second electrode of the first output transistor, and the orthographic projection of the first compensation plate on the substrate at least partially overlaps with the orthographic projection of the second compensation plate on the substrate.

[0030] Optionally, the first compensation plate is coupled to two adjacent gate patterns respectively; the second compensation plate is coupled to the second electrode connecting portion and two adjacent second electrode patterns respectively.

[0031] Optionally, the first compensation plate and the gate pattern form an integral structure, and the second compensation plate, the second electrode connecting portion and the second electrode pattern form an integral structure.

[0032] Optionally, the first output transistor further includes a first output active layer;

[0033] At least a portion of the orthographic projection of the first output active layer on the base substrate and the orthographic projection of the first compensation plate on the base substrate are arranged along a first direction; at least a portion of the orthographic projection of the first output active layer on the base substrate and at least a portion of the orthographic projection of the first compensation plate on the base substrate are arranged along a second direction; and / or,

[0034] At least a portion of the orthographic projection of the first output active layer on the base substrate and the orthographic projection of the second compensation plate on the base substrate are arranged along a first direction; at least a portion of the orthographic projection of the first output active layer on the base substrate and at least a portion of the orthographic projection of the second compensation plate on the base substrate are arranged along a second direction.

[0035] Optionally, the display substrate also includes a second level signal line; the shift register unit also includes a second output transistor and a second output control node, the gate of the second output transistor is coupled to the second output control node, the first electrode of the second output transistor is coupled to the second level signal line, and the second electrode of the second output transistor is coupled to the gate drive signal output end.

[0036] Based on the technical solution of the above-mentioned display substrate, it can be known that the second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.

[0037] Based on the technical solution of the above-mentioned display substrate, it can be seen that a third aspect of the present disclosure provides a driving method for a display substrate, which is used to drive the above-mentioned display substrate, wherein the display substrate includes: a base substrate, and a first level signal line and a shift register unit both provided on the base substrate; the shift register unit includes a first output transistor, a gate drive signal output terminal, and a first output control node; the gate of the first output transistor is coupled to the first output control node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate drive signal output terminal; a first capacitor is formed between the first output control node and the gate drive signal output terminal, and a second capacitor is formed between the first output control node and the first level signal line, and the capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor;

[0038] The driving method includes:

[0039] The first output control node controls the first output transistor to be turned on or off.

[0040] Optionally, the display substrate includes a frame start signal line, a first clock signal line, a third level signal line, and a cascaded multi-stage shift register unit; the shift register unit further includes a first input transistor, a second input transistor, a first transfer transistor, a second transfer transistor, and a control transistor;

[0041] The gate of the first input transistor is coupled to the corresponding first clock signal line, and the second electrode of the first input transistor is coupled to the first electrode of the first transfer transistor; the gate of the first transfer transistor is coupled to the third level signal line, and the second electrode of the first transfer transistor is coupled to the first output control node; the gate of the second input transistor is coupled to the corresponding first clock signal line, and the second electrode of the second input transistor is coupled to the first electrode of the second transfer transistor; the gate of the second transfer transistor is coupled to the third level signal line, and the second electrode of the second transfer transistor is coupled to the gate and second electrode of the control transistor respectively, and the first electrode of the control transistor is coupled to the first output control node;

[0042] In the first shift register unit, the first electrode of the first input transistor is coupled to the frame start signal line; in the nth shift register unit, where n is an integer greater than or equal to 2, the first electrode of the first input transistor is coupled to the gate drive signal output terminal of the (n-1)th shift register unit;

[0043] The low level of the first clock signal transmitted by the first clock signal line is lower than the level value of the first level signal transmitted by the first level signal transmission line; and / or,

[0044] The low level of the first clock signal transmitted by the first clock signal line is lower than the level value of the frame start signal; and / or,

[0045] The level value of the third level signal transmitted by the third level signal line is lower than the level value of the first level signal transmitted by the first level signal transmission line. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0047] FIG1 is a first circuit schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0048] FIG2 is a schematic diagram showing the relationship between the gate drive signal step and C_N7_out according to an embodiment of the present disclosure;

[0049] FIG3 is a schematic diagram showing the relationship between the gate drive signal step and C_N7_VGL according to an embodiment of the present disclosure;

[0050] FIG4 is a schematic cross-sectional view of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0051] FIG5 is a schematic diagram of a first layout of an active layer in a shift register unit provided by an embodiment of the present disclosure;

[0052] FIG6 is a schematic diagram of the layout of the first gate metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0053] FIG7 is a schematic diagram of the layout of the second gate metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0054] FIG8 is a schematic diagram of the layout of the first source and drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0055] FIG9 is a schematic diagram of the layout of the second source and drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0056] FIG10 is a schematic diagram of the layout of the active layer and the first gate metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0057] FIG11 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG10;

[0058] FIG12 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG11;

[0059] FIG13 is a schematic diagram of a layout with a second source / drain metal layer added on the basis of FIG13 ;

[0060] FIG14 is a schematic diagram of the layout of the first source-drain metal layer and the second source-drain metal layer in FIG13;

[0061] FIG15 is a schematic diagram of the layout of the first gate metal layer and the first source / drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0062] FIG16 is a schematic diagram of a first layout with a second gate metal layer added on the basis of FIG15 ;

[0063] FIG17 is a schematic diagram of the layout of FIG16 with an active layer and a second source / drain metal layer added;

[0064] FIG18 is a schematic diagram showing the layout of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0065] FIG19 is a schematic diagram of a layout in which an active layer and a second source / drain metal layer are added on the basis of FIG18 ;

[0066] FIG20 is a schematic diagram of a second layout of the active layer in the shift register unit provided by an embodiment of the present disclosure;

[0067] FIG21 is a schematic diagram of the layout of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0068] FIG22 is a schematic diagram of a layout with an active layer added on the basis of FIG21;

[0069] FIG23 is a schematic diagram of a third layout of the active layer in the shift register unit provided by an embodiment of the present disclosure;

[0070] FIG24 is a schematic diagram showing the layout of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0071] FIG25 is a schematic diagram of a layout with an active layer added on the basis of FIG24;

[0072] FIG26 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG25 ;

[0073] FIG27 is a schematic diagram of a fourth layout of the active layer in the shift register unit provided by an embodiment of the present disclosure;

[0074] FIG28 is a schematic diagram showing the layout of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in the shift register unit provided by an embodiment of the present disclosure;

[0075] FIG29 is a schematic diagram of a layout with an active layer added on the basis of FIG28;

[0076] FIG30 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG29;

[0077] FIG31 is a schematic diagram of the layout of the first gate metal layer in FIG21;

[0078] FIG32 is a schematic diagram of the layout of the second gate metal layer in FIG21;

[0079] FIG33 is a first circuit schematic diagram of the shift register unit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] In order to further illustrate the display substrate and its driving method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0081] In the display product, the gate drive circuit includes multiple cascaded shift register units, the gate drive signal output end of the shift register unit is coupled to the corresponding scan line, and the scan line is coupled to the corresponding sub-pixel in the display area. The scan line is used to transmit the gate drive signal output from the gate drive signal output end to the corresponding sub-pixel, thereby realizing the driving function of the sub-pixel.

[0082] In the related art, the gate driving signal output by the shift register unit has steps, resulting in poor output stability of the gate driving signal. When such a signal is used to drive a display product, high-quality display quality cannot be achieved.

[0083] As shown in Figure 1, the present disclosure provides a shift register unit, which adopts a 16T3C (i.e., 16 transistors and 3 capacitors) circuit structure. The shift register unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor unit C1, a second capacitor unit C2 and a third capacitor unit C3.

[0084] A gate of the first transistor T1 is coupled to a first clock signal line CK, a first electrode of the first transistor T1 is coupled to a frame start signal line STV, and a second electrode of the first transistor T1 is coupled to a first node N1.

[0085] A gate of the second transistor T2 is coupled to the first node N1 , a first electrode of the second transistor T2 is coupled to the first clock signal line CK, and a second electrode of the second transistor T2 is coupled to the second node N2 .

[0086] A gate of the third transistor T3 is coupled to the first clock signal line CK, a first electrode of the third transistor T3 is coupled to the first level signal line VGL, and a second electrode of the third transistor T3 is coupled to the second node N2.

[0087] A gate of the fourth transistor T4 is coupled to the ninth node N9 , a first electrode of the fourth transistor T4 is coupled to the second clock signal line CB, and a second electrode of the fourth transistor T4 is coupled to the fifth node N5 .

[0088] A gate of the fifth transistor T5 is coupled to the second node N2 , a first electrode of the fifth transistor T5 is coupled to the second level signal line VGH, and a second electrode of the fifth transistor T5 is coupled to the fifth node N5 .

[0089] A gate of the sixth transistor T6 is coupled to the sixth node N6 , a first electrode of the sixth transistor T6 is coupled to the second clock signal line CB, and a second electrode of the sixth transistor T6 is coupled to the third node N3 .

[0090] A gate of the seventh transistor T7 is coupled to the second clock signal line CB, a first electrode of the seventh transistor T7 is coupled to the third node N3, and a second electrode of the seventh transistor T7 is coupled to the fourth node N4.

[0091] A gate of the eighth transistor T8 is coupled to the first node N1 , a first electrode of the eighth transistor T8 is coupled to the second level signal line VGH, and a second electrode of the eighth transistor T8 is coupled to the fourth node N4 .

[0092] A gate of the ninth transistor T9 is coupled to the fourth node N4 , a first electrode of the ninth transistor T9 is coupled to the second level signal line VGH, and a second electrode of the ninth transistor T9 is coupled to the gate driving signal output terminal OUT.

[0093] A gate of the tenth transistor T10 is coupled to the seventh node N7 , a first electrode of the tenth transistor T10 is coupled to the first level signal line VGL, and a second electrode of the tenth transistor T10 is coupled to the gate driving signal output terminal OUT.

[0094] A gate of the eleventh transistor T11 is coupled to the first level signal line VGL, a first electrode of the eleventh transistor T11 is coupled to the second node N2, and a second electrode of the eleventh transistor T11 is coupled to the sixth node N6.

[0095] A gate of the twelfth transistor T12 is coupled to the first level signal line VGL, a first electrode of the twelfth transistor T12 is coupled to the first node N1, and a second electrode of the twelfth transistor T12 is coupled to the seventh node N7.

[0096] A gate of the thirteenth transistor T13 is coupled to the power line VEL, a first electrode of the thirteenth transistor T13 is coupled to the second level signal line VGH, and a second electrode of the thirteenth transistor T13 is coupled to the first node N1.

[0097] A gate of the fourteenth transistor T14 is coupled to the first clock signal line CK, a first electrode of the fourteenth transistor T14 is coupled to the frame start signal line STV, and a second electrode of the fourteenth transistor T14 is coupled to the eighth node N8.

[0098] A gate of the fifteenth transistor T15 is coupled to the first level signal line VGL, a first electrode of the fifteenth transistor T15 is coupled to the eighth node N8, and a second electrode of the fifteenth transistor T15 is coupled to the ninth node N9.

[0099] A gate of the sixteenth transistor T16 is coupled to the ninth node N9 , a first electrode of the sixteenth transistor T16 is coupled to the seventh node N7 , and a second electrode of the sixteenth transistor T16 is coupled to the ninth node N9 .

[0100] The first plate C11 of the first capacitor unit C1 is coupled to the sixth node N6, the second plate C12 of the first capacitor unit C1 is coupled to the third node N3, the first plate C21 of the second capacitor unit C2 is coupled to the fourth node N4, and the second plate C22 of the second capacitor unit C2 is coupled to the second level signal line VGH.

[0101] The first plate C32 of the third capacitor unit C3 is coupled to the fifth node N5 , and the second plate C31 of the third capacitor unit C3 is coupled to the ninth node N9 .

[0102] The shift register unit structure described above can not only improve the output signal step problem, but also enhance the output signal stability, effectively improving the display quality of display products. However, in actual applications, it has been found that if the layout design of the shift register unit is not reasonable, steps will still appear.

[0103] As shown in FIG1 and FIG5 to FIG30 , an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a first level signal line VGL and a shift register unit both provided on the base substrate;

[0104] The shift register unit includes a first output transistor (such as the tenth transistor T10), a gate drive signal output terminal OUT, and a first output control node (such as the seventh node N7). A gate 101 of the first output transistor is coupled to the first output control node, a first electrode 102 of the first output transistor is coupled to the first level signal line VGL, and a second electrode 103 of the first output transistor is coupled to the gate drive signal output terminal OUT.

[0105] A first capacitor is formed between the first output control node and the gate drive signal output terminal OUT, and a second capacitor is formed between the first output control node and the first level signal line VGL. The capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor.

[0106] Exemplarily, the display substrate includes a display area and a peripheral area located around the display area. The display substrate includes a gate drive circuit, which includes a plurality of cascaded shift register units, and the plurality of shift register units are located in the peripheral area. For example, the shift register units employ the 16T3C circuit structure, but are not limited thereto.

[0107] Exemplarily, the display substrate includes a plurality of sub-pixels located in the display area, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along the second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. The plurality of columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes the horizontal direction, and the second direction includes the vertical direction. Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element for providing a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0108] Exemplarily, the display substrate includes a plurality of scan lines, the shift register unit is coupled to corresponding scan lines, and the scan lines are respectively coupled to respective sub-pixel driving circuits in a corresponding row of sub-pixel driving circuits. Taking the sub-pixel driving circuit as an example, where the sub-pixel driving circuit employs a 7T1C (i.e., including seven transistors and one capacitor) circuit structure, the scan lines may be coupled to the gates of compensation transistors in the sub-pixel driving circuit, but the present invention is not limited thereto.

[0109] Exemplarily, the first level signal line VGL includes a low level signal line, but is not limited thereto.

[0110] Exemplarily, the first electrode 102 of the first output transistor includes a drain, and the second electrode 103 of the first output transistor includes a source, but is not limited thereto.

[0111] Through simulation, it is concluded that the difference between the 16T3C circuit structure and the 12T3C circuit structure (i.e., including 12 transistors and 3 capacitors) in the related art is that the 16T3C circuit structure can bootstrap and lower the potential of the first output control node (i.e., the seventh node N7) through the first output transistor (i.e., the tenth transistor T10) and the first-level signal line VGL. Therefore, increasing the capacitance C_N7_out between the first output control node and the gate drive signal output terminal OUT is conducive to the disappearance of the step, while increasing the capacitance C_N7_VGL between the first output control node and the first-level signal line VGL is not conducive to the disappearance of the step. These two capacitances are usually generated by the first output transistor, i.e., C_N7_out corresponds to the gate-source capacitance Cgs of the first output transistor, and C_N7_VGL corresponds to the gate-drain capacitance Cgd of the first output transistor. Cgs and Cgd coexist, which means that the larger the first output transistor is, the better it is in design.

[0112] In more detail, as shown in Figure 2, increasing the first capacitor C_N7_out between the first output control node and the gate drive signal output terminal OUT is conducive to reducing the step. As shown in Figure 3, reducing the second capacitor C_N7_VGL between the first output control node and the first level signal line VGL is conducive to reducing the step. In Figures 2 and 3, Ratio represents the setting ratio of the capacitor. The basic capacitance value of C_N7_out in Figure 2 is 28.745fF. The basic capacitance value of C_N7_VGL in Figure 3 is 32.08fF. The capacitance value corresponding to each signal line is the product of the basic capacitance value and the ratio. The basic capacitance value is the reference capacitance value used in the simulation, and the specific capacitance value can be set according to actual needs. The basic capacitance value is not limited to the above value.

[0113] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, a first capacitor is formed between the first output control node and the gate drive signal output terminal OUT, and a second capacitor is formed between the first output control node and the first level signal line VGL, and the capacitance of the first capacitor is greater than the capacitance of the second capacitor; so that a larger first capacitor is formed between the first output control node and the gate drive signal output terminal OUT, and a smaller second capacitor is formed between the first output control node and the first level signal line VGL, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, display defects such as fine horizontal stripes on the display product can be avoided, thereby achieving high-quality display quality.

[0114] As shown in FIG5 to FIG14, in some embodiments, the gate 101 of the first output transistor includes at least one gate pattern 101a, and the gate pattern 101a extends along a first direction; the first electrode 102 of the first output transistor includes at least one first electrode pattern 102a, and the first electrode pattern 102a extends along the first direction; the second electrode 103 of the first output transistor includes at least one second electrode pattern 103a, and the second electrode pattern 103a extends along the first direction;

[0115] The first electrode pattern 102a and the second electrode pattern 103a are arranged along a second direction, and the second direction intersects the first direction; the orthographic projection of the gate pattern 101a on the base substrate is located between the orthographic projection of the first electrode pattern 102a and the orthographic projection of the second electrode pattern 103a on the base substrate;

[0116] There is a first distance d2 between the orthographic projection of at least one gate pattern 101a on the base substrate and the orthographic projection of the adjacent first electrode pattern 102a on the base substrate; there is a second distance d1 between the orthographic projection of at least one gate pattern 101a on the base substrate and the orthographic projection of the adjacent second electrode pattern 103a on the base substrate; the first distance d2 is greater than the second distance d1.

[0117] Exemplarily, the gate 101 of the first output transistor includes a gate connection portion 101b and at least two gate graphics 101a respectively coupled to the gate connection portion 101b; the first electrode 102 of the first output transistor includes a first electrode connection portion 102b and at least two first electrode graphics 102a respectively coupled to the first electrode connection portion 102b; the second electrode 103 of the first output transistor includes a second electrode connection portion 103b and at least two second electrode graphics 103a respectively coupled to the second electrode connection portion 103b; the first electrode graphics 102a and the second electrode graphics 103a are alternately arranged along the second direction; the first electrode connection portion 102b is coupled to the first level signal line VGL, and the second electrode connection portion 103b is coupled to the gate drive signal output terminal OUT.

[0118] Illustratively, the gate connecting portion 101b and the gate pattern 101a to which it is coupled form an integral structure. The first electrode connecting portion 102b and the first electrode pattern 102a to which it is coupled form an integral structure. The second electrode connecting portion 103b and the second electrode pattern 103a to which it is coupled form an integral structure.

[0119] Illustratively, the first electrode connecting portion 102b includes at least a portion extending along the second direction. The second electrode connecting portion 103b includes at least a portion extending along the second direction.

[0120] Exemplarily, each of the gate patterns 101a has the first distance between its orthographic projection on the base substrate and the adjacent orthographic projection of the first electrode pattern 102a on the base substrate; each of the gate patterns 101a has the second distance between its orthographic projection on the base substrate and the adjacent orthographic projection of the second electrode pattern 103a on the base substrate.

[0121] Exemplarily, a first capacitor C_N7_out between the first output control node and the gate drive signal output terminal OUT includes: a structure coupled to the gate drive signal output terminal OUT and also used to transmit the gate drive signal; and a capacitor formed between the first output control node. A second capacitor C_N7_VGL between the first output control node and the first level signal line VGL includes: a structure coupled to the first level signal line VGL and also used to transmit the first level signal; and a capacitor formed between the first output control node. The gate 101 of the first output transistor can serve as the first output control node.

[0122] Exemplarily, the first distance includes: the distance along the second direction between the orthographic projection of the gate pattern 101a on the base substrate and the orthographic projection of the adjacent first electrode pattern 102a on the base substrate; the second distance includes: the distance along the second direction between the orthographic projection of the gate pattern 101a on the base substrate and the orthographic projection of the adjacent second electrode pattern 103a on the base substrate.

[0123] Exemplarily, the first distance includes: the minimum distance between the orthographic projection of the gate pattern 101a on the base substrate and the orthographic projection of the adjacent first electrode pattern 102a on the base substrate; the second distance includes: the minimum distance between the orthographic projection of the gate pattern 101a on the base substrate and the orthographic projection of the adjacent second electrode pattern 103a on the base substrate.

[0124] Exemplarily, the value range of the first distance is between 1.5 μm and 2.5 μm, but is not limited thereto. For example, the values ​​of the first distance include: 1.5 μm, 1.7 μm, 1.9 μm, 2.1 μm, 2.3 μm, 2.5 μm, etc.

[0125] Exemplarily, the second distance has a value range of, but is not limited to, 0.3 μm to 1.1 μm. For example, the second distance may have values ​​of 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1.1 μm, and the like.

[0126] Exemplarily, a first distance is defined between the orthographic projection of the gate pattern 101a on the substrate and the orthographic projection of the adjacent first electrode pattern 102a on the substrate. The first distance is negatively correlated with the capacitance value of the gate-drain capacitance Cgd of the first output transistor, i.e., the first distance is negatively correlated with the capacitance value of the second capacitance C_N7_VGL. Specifically, the greater the first distance, the smaller the capacitance value of the second capacitance C_N7_VGL. Exemplarily, a second distance is defined between the orthographic projection of the gate pattern 101a on the substrate and the orthographic projection of the adjacent second electrode pattern 103a on the substrate. The second distance is negatively correlated with the capacitance value of the gate-source capacitance Cgs of the first output transistor, i.e., the second distance is negatively correlated with the capacitance value of the first capacitance C_N7_out. Specifically, the smaller the second distance, the larger the capacitance value of the first capacitance C_N7_out.

[0127] It should be noted that the capacitance of the second capacitor C_N7_VGL includes two parts: the first part is the capacitance of the first output transistor itself, and the size of this part of the capacitance is related to the channel length, channel width, and operating state of the first output transistor; the second part is the surface capacitance or 3D capacitance formed with other traces, which satisfies the formula C=εS / 4πkd, where ε represents the dielectric constant, S represents the facing area of ​​the two plates of the capacitor, d represents the distance between the two plates of the capacitor, and k represents a constant.

[0128] In the display substrate provided in the above embodiment, a first distance is provided between the orthographic projection of at least one gate pattern 101a on the base substrate and the orthographic projection of the adjacent first electrode pattern 102a on the base substrate; a second distance is provided between the orthographic projection of at least one gate pattern 101a on the base substrate and the orthographic projection of the adjacent second electrode pattern 103a on the base substrate, and the first distance is greater than the second distance; this arrangement brings the gate pattern 101a closer to the second electrode pattern 103a and further away from the first electrode pattern 102a, effectively increasing the capacitance value of the first capacitor C_N7_out and reducing the capacitance value of the second capacitor C_N7_VGL, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal.

[0129] Therefore, in the display substrate provided by the above embodiment, when laying out the shift register unit, the capacitance value of the first capacitor C_N7_out is increased and the capacitance value of the second capacitor C_N7_VGL is reduced through reasonable layout settings, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, it can avoid display defects such as fine horizontal stripes on the display product, thereby achieving high-quality display quality.

[0130] As shown in FIG. 15 to FIG. 17 , in some embodiments, an orthographic projection of at least one of the gate patterns 101 a on the base substrate at least partially overlaps with an orthographic projection of the second electrode connecting portion 103 b on the base substrate.

[0131] Illustratively, the orthographic projection of each gate pattern 101 a on the base substrate at least partially overlaps with the orthographic projection of the second electrode connecting portion 103 b on the base substrate.

[0132] Exemplarily, the shift register unit further includes an output terminal connection portion 20, which is respectively coupled to the gate drive signal output terminal OUT and the second electrode 103 of the first output transistor; the orthographic projection of the output terminal connection portion 20 on the substrate does not overlap with the orthographic projection of the gate graphic 101a on the substrate.

[0133] The above-mentioned setting method increases the capacitance value of the first capacitor C_N7_out by increasing the overlapping area between the gate 101 and the second electrode of the first output transistor, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, it can avoid display defects such as fine horizontal stripes on the display product, thereby achieving high-quality display quality.

[0134] As shown in Figures 18 and 19, in some embodiments, the shift register unit further includes an output end extension portion 21, which is coupled to the output end connection portion 20, and the orthographic projection of the output end extension portion 21 on the base substrate at least partially overlaps with the orthographic projection of the gate graphic 101a on the base substrate.

[0135] Exemplarily, the output end extension portion 21 and the output end connection portion 20 form an integral structure.

[0136] Illustratively, an orthographic projection of the output-end extension portion 21 on the base substrate at least partially overlaps with an orthographic projection of the second electrode connecting portion 103 b on the base substrate.

[0137] The above-mentioned setting method increases the capacitance value of the first capacitor C_N7_out, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, it can avoid display defects such as fine horizontal stripes on the display product, thereby achieving high-quality display quality.

[0138] In some embodiments, the display substrate includes a first gate metal layer gate1, a second gate metal layer gate2, and a first source-drain metal layer SD1 stacked in sequence in a direction away from the base substrate; the gate 101 of the first output transistor is arranged in the same layer and material as the first gate metal layer gate1; the first electrode 102 and the second electrode of the first output transistor are arranged in the same layer and material as the first source-drain metal layer SD1; the output terminal connection portion 20 and the output terminal extension portion 21 are arranged in the same layer and material as the second gate metal layer gate2.

[0139] As shown in FIG4 , the display substrate exemplarily includes a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include a passivation layer PVX, but is not limited thereto.

[0140] The gate 101 of the first output transistor and the first gate metal layer gate1 are set in the same layer and material, so that the gate 101 of the first output transistor and the first gate metal layer gate1 can be formed simultaneously in the same composition process, thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0141] The first electrode 102 and the second electrode 103 of the first output transistor are arranged in the same layer and material as the first source-drain metal layer SD1, so that the first electrode 102 and the second electrode 103 of the first output transistor can be formed simultaneously with the first source-drain metal layer SD1 in the same patterning process, thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0142] The output terminal connection portion 20 and the output terminal extension portion 21 are arranged in the same layer and material as the second gate metal layer gate2, so that the output terminal connection portion 20 and the output terminal extension portion 21 can be formed simultaneously with the second gate metal layer gate2 in the same composition process, thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0143] As shown in FIG. 20 to FIG. 22 , FIG. 31 and FIG. 32 , in some embodiments, the first output transistor further includes a first output active layer P10 ;

[0144] The shift register unit also includes a first compensation pattern 40, which is coupled to the gate 101 of the first output transistor; the orthographic projection of the first compensation pattern 40 on the base substrate does not overlap with the orthographic projection of the first output active layer P10 on the base substrate; the orthographic projection of the first compensation pattern 40 on the base substrate at least partially overlaps with the orthographic projection of the output end extension portion 21 on the base substrate.

[0145] Exemplarily, the first output active layer P10 includes a channel portion and a conductor portion. The orthographic projection of the channel portion on the substrate overlaps with the orthographic projection of the gate electrode 101 of the first output transistor on the substrate. The orthographic projection of the conductor portion on the substrate at least partially overlaps with the orthographic projection of the first electrode 102 of the first output transistor on the substrate. The orthographic projection of the conductor portion on the substrate at least partially overlaps with the orthographic projection of the second electrode 103 of the first output transistor on the substrate.

[0146] Exemplarily, the first compensation pattern 40 and the gate 101 of the first output transistor form an integrated structure.

[0147] Exemplarily, the first compensation pattern 40 and the gate pattern 101 a are arranged along the second direction.

[0148] Exemplarily, an orthographic projection of the first compensation pattern 40 on the base substrate and an orthographic projection of the first output active layer P10 on the base substrate are arranged along the second direction.

[0149] Exemplarily, the orthographic projection of the first compensation pattern 40 on the base substrate at least partially overlaps with the orthographic projection of the second electrode connecting portion 103 b on the base substrate.

[0150] The above-mentioned setting of the orthographic projection of the first compensation pattern 40 on the base substrate at least partially overlaps with the orthographic projection of the output end extension portion 21 on the base substrate, thereby increasing the capacitance value of the first capacitor C_N7_out, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, it can avoid display defects such as fine horizontal stripes on the display product, thereby achieving high-quality display quality.

[0151] As shown in Figures 20 to 22, in some embodiments, the output end extension portion 21 includes a first extension portion 211 and a second extension portion 212 coupled to each other, the first extension portion 211 extends along a first direction, and the second extension portion 212 extends along a second direction; the orthographic projection of the first extension portion 211 on the base substrate at least partially overlaps with the orthographic projection of the first compensation pattern 40 on the base substrate; the orthographic projection of the second extension portion 212 on the base substrate at least partially overlaps with the orthographic projection of the second electrode connection portion 103b on the base substrate; the first compensation pattern 40 and the gate pattern 101a are arranged along the second direction.

[0152] Illustratively, the first extending portion 211 and the second extending portion 212 are formed as an integral structure.

[0153] Exemplarily, the orthographic projection of the first compensation pattern 40 on the base substrate at least partially overlaps with the orthographic projection of the second electrode connecting portion 103 b on the base substrate.

[0154] The above configuration reduces the layout difficulty of the shift register unit while increasing the capacitance of the first capacitor C_N7_out through reasonable layout.

[0155] As shown in Figures 23 to 26, in some embodiments, the first output transistor further includes a first output active layer P10, the first output active layer P10 has a first length L1 along the first direction, the gate pattern 101a has a second length L2 along the first direction, and the first length L1 is less than or equal to 2 / 3 of the second length L2.

[0156] Exemplarily, the second electrode pattern 103a has a third length L3 along the first direction, and the first length L1 is less than or equal to 2 / 3 of the third length L3.

[0157] Exemplarily, the first electrode pattern 102a has a fourth length L4 along the first direction, the fourth length L4 is smaller than the third length L3, and / or the fourth length L4 is smaller than the second length L2.

[0158] The above-mentioned setting method can narrow the width of the first output active layer P10 along the first direction, which is equivalent to increasing the length of the portion of the gate pattern 101a and the second electrode pattern 103a that does not overlap with the first output active layer P10 along the first direction, thereby increasing the capacitance value of the first capacitor C_N7_out, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, it can avoid display defects such as fine horizontal stripes on the display product, thereby achieving high-quality display quality.

[0159] As shown in Figures 27 to 30, in some embodiments, the shift register unit further includes a compensation capacitor Cb, and the compensation capacitor Cb includes a first compensation plate Cb1 and a second compensation plate Cb2, the first compensation plate Cb1 is coupled to the gate 101 of the first output transistor, and the second compensation plate Cb2 is coupled to the second electrode 103 of the first output transistor, and the orthographic projection of the first compensation plate Cb1 on the substrate and the orthographic projection of the second compensation plate Cb2 on the substrate at least partially overlap.

[0160] In the display substrate provided by the above embodiment, the compensation capacitor Cb is provided to increase the capacitance value of the first capacitor C_N7_out, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display product, poor display such as fine horizontal stripes on the display product can be avoided, thereby achieving high-quality display quality.

[0161] As shown in FIG. 27 to FIG. 30 , in some embodiments, the first compensation plate Cb1 is respectively coupled to two adjacent gate patterns 101 a ; the second compensation plate Cb2 is respectively coupled to the second electrode connecting portion 103 b and two adjacent second electrode patterns 103 a .

[0162] Exemplarily, the orthographic projection of the first compensation plate Cb1 on the base substrate is located between the orthographic projections of two adjacent gate patterns 101a on the base substrate.

[0163] Illustratively, the orthographic projection of the second compensation plate Cb2 on the base substrate is located between the orthographic projections of two adjacent second electrode patterns 103a on the base substrate.

[0164] Illustratively, the second electrode connecting portion 103b and two adjacent second electrode patterns 103a are arranged around the second compensation plate Cb2.

[0165] Exemplarily, the first compensation plate Cb1 and the gate pattern 101 a form an integrated structure, and the second compensation plate Cb2, the second electrode connecting portion 103 b and the second electrode pattern 103 a form an integrated structure, but the present invention is not limited thereto.

[0166] The above configuration reduces the layout difficulty of the shift register unit while increasing the capacitance of the first capacitor C_N7_out through reasonable layout.

[0167] As shown in FIG. 27 to FIG. 30 , in some embodiments, the first output transistor further includes a first output active layer P10 ;

[0168] At least a portion of the orthographic projection of the first output active layer P10 on the base substrate is arranged along a first direction with a portion of the orthographic projection of the first compensation plate Cb1 on the base substrate; at least a portion of the orthographic projection of the first output active layer P10 on the base substrate is arranged along a second direction with at least a portion of the orthographic projection of the first compensation plate Cb1 on the base substrate; and / or, at least a portion of the orthographic projection of the first output active layer P10 on the base substrate is arranged along the first direction with a portion of the orthographic projection of the second compensation plate Cb2 on the base substrate; at least a portion of the orthographic projection of the first output active layer P10 on the base substrate is arranged along a second direction with at least a portion of the orthographic projection of the second compensation plate Cb2 on the base substrate.

[0169] Exemplarily, the first output active layer P10 is L-shaped, and the orthographic projection of the first output active layer P10 on the base substrate is arranged around at least part of the orthographic projection of the first compensation plate Cb1 and / or the second compensation plate Cb2 on the base substrate.

[0170] The above configuration reduces the layout difficulty of the shift register unit while increasing the capacitance of the first capacitor C_N7_out through reasonable layout.

[0171] As shown in Figures 1 and 5 to 14, in some embodiments, the display substrate further includes a second level signal line VGH; the shift register unit further includes a second output transistor (such as the above-mentioned ninth transistor T9) and a second output control node (such as the above-mentioned fourth node N4), the gate of the second output transistor is coupled to the second output control node, the first electrode of the second output transistor is coupled to the second level signal line VGH, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal OUT.

[0172] Exemplarily, the first level signal line VGL is used to transmit a first level signal, and the second level signal line VGH is used to transmit a second level signal. The first level signal includes a low level signal, and the second level signal includes a high level signal, but is not limited thereto.

[0173] As shown in Figure 5, Figure 5 also illustrates the first active layer P1, the second active layer P2, the third active layer P3, the fourth active layer P4, the fifth active layer P5, the sixth active layer P6, the seventh active layer P7, the eighth active layer P8, the ninth active layer P9, the eleventh active layer P11, the twelfth active layer P12, the thirteenth active layer P13, the fourteenth active layer P14, the fifteenth active layer P15, and the sixteenth active layer P16.

[0174] As shown in FIG. 7 , a first conductive connection portion 51 and a second conductive connection portion 52 are also shown.

[0175] As shown in FIG. 8 , the first conductive pattern 60 a is coupled to the first transistor T1 , the fourteenth transistor T14 , and the frame start signal line, respectively.

[0176] The second conductive pattern 60b is coupled to the gate of the second transistor T2, the first transistor T1 and the first clock signal line CK, respectively.

[0177] The third conductive pattern 60c serves as a third node N3.

[0178] The fourth conductive pattern 60d is coupled to the gate of the seventh transistor T7, the sixth transistor T6 and the second clock signal line CB, respectively.

[0179] The fifth conductive pattern 60e serves as a fourth node N4.

[0180] The sixth conductive pattern 60f is coupled to the gate of the second transistor T2 and the first transistor T1, respectively.

[0181] The seventh conductive pattern 60g serves as an eighth node N8.

[0182] The eighth conductive pattern 60h serves as a second node N2.

[0183] The ninth conductive pattern 60i is coupled to the first level signal line VGL, the gate of the eleventh transistor T11, and the second transistor T2, respectively.

[0184] The tenth conductive pattern 60j is coupled to the third capacitor unit C3 and the fifteenth transistor T15 respectively.

[0185] The eleventh conductive pattern 60k is coupled to the fourth transistor T4 and the second clock signal line CB, respectively.

[0186] The twelfth conductive pattern 60m serves as the fifth node N5 and is further coupled to the twenty-first conductive pattern 60w.

[0187] The thirteenth conductive pattern 60n is coupled to the third capacitor unit C3 and the sixteenth transistor T16 respectively.

[0188] The fourteenth conductive pattern 60 p is coupled to the gate of the second transistor T2 , the gate of the eighth transistor T8 , the thirteenth transistor T13 , and the first conductive connection portion 51 , respectively.

[0189] The fifteenth conductive pattern 60q is coupled to the second conductive connection portion 52. The second conductive connection portion 52 is also coupled to the second electrode pattern 103a.

[0190] The sixteenth conductive pattern 60s is coupled to the twelfth transistor T12 and the first conductive connection portion 51, respectively.

[0191] The seventeenth conductive pattern 60 t is coupled to the gate of the sixth transistor T6 and the eleventh transistor T11 , respectively.

[0192] The eighteenth conductive pattern 60x serves as a first electrode of the ninth transistor T9 and is coupled to the eighth transistor T8, the fifth transistor T5, and the thirteenth transistor T13 respectively.

[0193] The nineteenth conductive pattern 60y serves as the second electrode of the ninth transistor T9 and is coupled to the gate drive signal output terminal OUT.

[0194] The twentieth conductive pattern 60z serves as a seventh node N7.

[0195] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0196] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc. The display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0197] In the display substrate provided by the above embodiment, a first capacitor is formed between the first output control node and the gate drive signal output end, and a second capacitor is formed between the first output control node and the first level signal line, and the capacitance of the first capacitor is greater than the capacitance of the second capacitor; so that a larger first capacitor is formed between the first output control node and the gate drive signal output end, and a smaller second capacitor is formed between the first output control node and the first level signal line, thereby effectively reducing the step of the gate drive signal output by the shift register unit and improving the output stability of the gate drive signal. When the gate drive signal is used to drive the display of the display product, display defects such as fine horizontal stripes on the display product can be avoided, thereby achieving high-quality display quality.

[0198] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0199] As shown in FIG1 and FIG5 to FIG30, an embodiment of the present disclosure further provides a method for driving a display substrate, for driving the display substrate provided by the above embodiment, wherein the display substrate comprises: a base substrate, and a first level signal line VGL and a shift register unit both provided on the base substrate;

[0200] The shift register unit includes a first output transistor, a gate drive signal output terminal OUT, and a first output control node; a gate 101 of the first output transistor is coupled to the first output control node, a first electrode 102 of the first output transistor is coupled to the first level signal line VGL, and a second electrode 103 of the first output transistor is coupled to the gate drive signal output terminal OUT; a first capacitor is formed between the first output control node and the gate drive signal output terminal OUT, and a second capacitor is formed between the first output control node and the first level signal line VGL, wherein the capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor;

[0201] The driving method includes: the first output control node controls the first output transistor to be turned on or off.

[0202] As shown in FIG33 , in some embodiments, the display substrate includes a frame start signal line STV, a first clock signal line CK, a third level signal line VGL′, and a cascaded multi-stage shift register unit; the shift register unit further includes a first input transistor (such as the first transistor T1 described above), a second input transistor (such as the fourteenth transistor T14 described above), a first transfer transistor (such as the twelfth transistor T12 described above), a second transfer transistor (such as the fifteenth transistor T15 described above), and a control transistor (such as the sixteenth transistor T16 described above);

[0203] The gate of the first input transistor is coupled to the corresponding first clock signal line CK, and the second electrode of the first input transistor is coupled to the first electrode of the first transfer transistor; the gate of the first transfer transistor is coupled to the third level signal line VGL', and the second electrode of the first transfer transistor is coupled to the first output control node; the gate of the second input transistor is coupled to the corresponding first clock signal line CK, and the second electrode of the second input transistor is coupled to the first electrode of the second transfer transistor; the gate of the second transfer transistor is coupled to the third level signal line VGL', and the second electrode of the second transfer transistor is coupled to the gate and second electrode of the control transistor respectively, and the first electrode of the control transistor is coupled to the first output control node;

[0204] In the first shift register unit, the first electrode of the first input transistor is coupled to the frame start signal line STV; in the nth shift register unit, where n is an integer greater than or equal to 2, the first electrode of the first input transistor is coupled to the gate drive signal output terminal OUT' of the (n-1)th shift register unit;

[0205] The low level of the first clock signal transmitted by the first clock signal line CK is lower than the level value of the first level signal transmitted by the first level signal transmission line VGL; and / or,

[0206] The low level of the first clock signal transmitted by the first clock signal line CK is lower than the level value of the frame start signal STV; and / or,

[0207] The level value of the third level signal transmitted by the third level signal line VGL′ is lower than the level value of the first level signal transmitted by the first level signal transmission line VGL.

[0208] More specifically, when the level of the frame start signal transmitted by the frame start signal line STV is -6V and the low level of the first clock signal is -6V, the voltage reaching the first output control node is approximately -4V due to threshold voltage loss across the first input transistor, causing the first output transistor to turn on more slowly. When the level of the frame start signal transmitted by the frame start signal line STV is -6V and the low level of the first clock signal is -10V, even with threshold voltage loss, the voltage at the first output control node is significantly lower than in the previous case, ensuring that the first output transistor can turn on quickly.

[0209] The above setting is that the low level of the first clock signal transmitted by the first clock signal line CK is lower than the level value of the first level signal transmitted by the first level signal transmission line VGL; and / or, the low level of the first clock signal transmitted by the first clock signal line CK is lower than the level value of the frame start signal STV; so that in each shift register unit, the gate-source voltage Vgs of the first input transistor and the second input transistor are both large, ensuring that the two transistors are fully turned on.

[0210] The above-mentioned setting sets the level value of the third-level signal transmitted by the third-level signal line VGL' to be lower than the level value of the first-level signal transmitted by the first-level signal transmission line VGL; so that the gates of the first transfer transistor and the second transfer transistor receive a lower turn-on level value, ensuring that the first transfer transistor and the second transfer transistor can be fully turned on.

[0211] When the display substrate is driven by the driving method provided by the above embodiment, the potential of the first output control node can be guaranteed, thereby better controlling the turn-on condition of the first output transistor.

[0212] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0213] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0214] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0215] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0216] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0217] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0218] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0219] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate, and a first level signal line and a shift register unit both disposed on the base substrate; The shift register unit includes a first output transistor, a gate drive signal output terminal, and a first output control node; The gate of the first output transistor is coupled to the first output control node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate drive signal output terminal; A first capacitor is formed between the first output control node and the gate drive signal output terminal, and a second capacitor is formed between the first output control node and the first level signal line. The capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor.

2. The display substrate according to claim 1, wherein: The gate of the first output transistor includes at least one gate pattern, and the gate pattern extends along a first direction; the first electrode of the first output transistor includes at least one first electrode pattern, and the first electrode pattern extends along the first direction; The second electrode of the first output transistor includes at least one second electrode pattern, and the second electrode pattern extends along the first direction; The first electrode pattern and the second electrode pattern are arranged along a second direction, and the second direction intersects with the first direction; The orthographic projection of the gate pattern on the base substrate is located between the orthographic projection of the first electrode pattern on the base substrate and the orthographic projection of the second electrode pattern on the base substrate; There is a first distance between the orthographic projection of at least one of the gate patterns on the base substrate and the orthographic projection of the adjacent first electrode pattern on the base substrate; there is a second distance between the orthographic projection of at least one of the gate patterns on the base substrate and the orthographic projection of the adjacent second electrode pattern on the base substrate; the first distance is greater than the second distance.

3. The display substrate according to claim 2, wherein: The gate of the first output transistor includes a gate connection portion and at least two gate patterns respectively coupled to the gate connection portion; the first pole of the first output transistor includes a first electrode connection portion and at least two first electrode patterns respectively coupled to the first electrode connection portion; the second pole of the first output transistor includes a second electrode connection portion and at least two second electrode patterns respectively coupled to the second electrode connection portion; the first electrode patterns and the second electrode patterns are alternately arranged along the second direction; the first electrode connection portion is coupled to the first level signal line, and the second electrode connection portion is coupled to the gate drive signal output terminal.

4. The display substrate according to claim 2 or 3, wherein: Each of the gate patterns has the first distance between its orthographic projection on the base substrate and the adjacent orthographic projection of the first electrode pattern on the base substrate; each of the gate patterns has the second distance between its orthographic projection on the base substrate and the adjacent orthographic projection of the second electrode pattern on the base substrate.

5. The display substrate according to claim 3, wherein: An orthographic projection of at least one of the gate patterns on the base substrate at least partially overlaps with an orthographic projection of the second electrode connecting portion on the base substrate.

6. The display substrate according to claim 5, wherein: The shift register unit also includes an output terminal connection portion, which is coupled to the gate drive signal output terminal and the second electrode of the first output transistor respectively; the orthographic projection of the output terminal connection portion on the base substrate does not overlap with the orthographic projection of the gate pattern on the base substrate.

7. The display substrate according to claim 6, wherein: The shift register unit further includes an output end extension portion, the output end extension portion is coupled to the output end connection portion, and an orthographic projection of the output end extension portion on the base substrate at least partially overlaps with an orthographic projection of the gate pattern on the base substrate.

8. The display substrate according to claim 7, wherein: The orthographic projection of the output end extension portion on the base substrate at least partially overlaps with the orthographic projection of the second electrode connection portion on the base substrate.

9. The display substrate according to claim 7 or 8, wherein: The display substrate comprises a first gate metal layer, a second gate metal layer and a first source-drain metal layer which are sequentially stacked in a direction away from the base substrate; The gate of the first output transistor is arranged in the same layer and material as the first gate metal layer; the first electrode and the second electrode of the first output transistor are arranged in the same layer and material as the first source-drain metal layer; the output terminal connecting portion and the output terminal extending portion are arranged in the same layer and material as the second gate metal layer.

10. The display substrate according to claim 7 or 8, wherein: The first output transistor also includes a first output active layer; The shift register unit further includes a first compensation pattern, the first compensation pattern is coupled to the gate of the first output transistor; the orthographic projection of the first compensation pattern on the substrate does not overlap with the orthographic projection of the first output active layer on the substrate; The orthographic projection of the first compensation pattern on the base substrate at least partially overlaps with the orthographic projection of the output end extension portion on the base substrate.

11. The display substrate according to claim 10, wherein: The output end extension portion includes a first extension portion and a second extension portion coupled to each other, the first extension portion extends along a first direction, and the second extension portion extends along a second direction; The orthographic projection of the first extension portion on the substrate at least partially overlaps with the orthographic projection of the first compensation pattern on the substrate; The orthographic projection of the second extension portion on the base substrate at least partially overlaps with the orthographic projection of the second electrode connecting portion on the base substrate; the first compensation pattern and the gate pattern are arranged along the second direction.

12. The display substrate according to claim 5, wherein: The first output transistor further includes a first output active layer, the first output active layer has a first length along the first direction, the gate pattern has a second length along the first direction, and the first length is less than or equal to 2 / 3 of the second length.

13. The display substrate according to claim 12, wherein: The second electrode pattern has a third length along the first direction, and the first length is less than or equal to 2 / 3 of the third length.

14. The display substrate according to claim 12 or 13, wherein: The first electrode pattern has a fourth length along the first direction, the fourth length is smaller than the third length, and / or the fourth length is smaller than the second length.

15. The display substrate according to claim 3, wherein: The shift register unit also includes a compensation capacitor, which includes a first compensation plate and a second compensation plate, the first compensation plate is coupled to the gate of the first output transistor, the second compensation plate is coupled to the second electrode of the first output transistor, and the orthographic projection of the first compensation plate on the substrate at least partially overlaps with the orthographic projection of the second compensation plate on the substrate.

16. The display substrate according to claim 15, wherein: The first compensation plate is respectively coupled to two adjacent gate patterns; the second compensation plate is respectively coupled to the second electrode connecting portion and two adjacent second electrode patterns.

17. The display substrate according to claim 16, wherein: The first compensation plate and the gate pattern form an integrated structure, and the second compensation plate, the second electrode connecting portion and the second electrode pattern form an integrated structure.

18. The display substrate according to any one of claims 15 to 17, wherein: The first output transistor also includes a first output active layer; At least a portion of an orthographic projection of the first output active layer on the base substrate and an orthographic projection of the first compensation plate on the base substrate are arranged along a first direction; At least a portion of an orthographic projection of the first output active layer on the substrate and at least a portion of an orthographic projection of the first compensation plate on the substrate are arranged along a second direction; and / or, At least a portion of an orthographic projection of the first output active layer on the base substrate and an orthographic projection of the second compensation plate on the base substrate are arranged along a first direction; At least a portion of an orthographic projection of the first output active layer on the base substrate and at least a portion of an orthographic projection of the second compensation plate on the base substrate are arranged along a second direction.

19. The display substrate according to claim 1, wherein: The display substrate also includes a second level signal line; the shift register unit also includes a second output transistor and a second output control node, the gate of the second output transistor is coupled to the second output control node, the first electrode of the second output transistor is coupled to the second level signal line, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

21. A method for driving a display substrate, for driving the display substrate according to any one of claims 1 to 19, wherein the display substrate comprises: A substrate, and a first level signal line and a shift register unit both disposed on the substrate; the shift register unit comprises a first output transistor, a gate drive signal output terminal, and a first output control node; The gate of the first output transistor is coupled to the first output control node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate drive signal output terminal; a first capacitor is formed between the first output control node and the gate drive signal output terminal, and a second capacitor is formed between the first output control node and the first level signal line, and the capacitance of the first capacitor is greater than or equal to the capacitance of the second capacitor; The driving method comprises: The first output control node controls the first output transistor to be turned on or off.

22. The method for driving a display substrate according to claim 21, wherein: The display substrate includes a frame start signal line, a first clock signal line, a third level signal line and a cascaded multi-stage shift register unit; the shift register unit also includes a first input transistor, a second input transistor, a first transmission transistor, a second transmission transistor and a control transistor; The gate of the first input transistor is coupled to the corresponding first clock signal line, and the second electrode of the first input transistor is coupled to the first electrode of the first transfer transistor; the gate of the first transfer transistor is coupled to the third level signal line, and the second electrode of the first transfer transistor is coupled to the first output control node; the gate of the second input transistor is coupled to the corresponding first clock signal line, and the second electrode of the second input transistor is coupled to the first electrode of the second transfer transistor; the gate of the second transfer transistor is coupled to the third level signal line, and the second electrode of the second transfer transistor is coupled to the gate and the second electrode of the control transistor respectively, and the first electrode of the control transistor is coupled to the first output control node; In the first shift register unit, the first electrode of the first input transistor is coupled to the frame start signal line; in the nth shift register unit, n is an integer greater than or equal to 2, the first electrode of the first input transistor is coupled to the gate drive signal output terminal of the n-1th shift register unit; The low level of the first clock signal transmitted by the first clock signal line is lower than the level value of the first level signal transmitted by the first level signal transmission line; and / or, The low level of the first clock signal transmitted by the first clock signal line is lower than the level value of the frame start signal; and / or, The level value of the third level signal transmitted by the third level signal line is lower than the level value of the first level signal transmitted by the first level signal transmission line.

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