Systems and methods for built-in self-test of SFQ circuits using side-channel leakage information

Abstract

Disclosed is a built-in self-test (BIST) methodology of SFQ circuits focused on a novel readout of test signals by using side-channel leakage information. The side-channel leakage can exhibit the dependence of internal data (logical '1' and '0') on the power consumption. By measuring the variations in the power supply of an SFQ circuit at room temperature, the information about internal test signal states can be extracted. As a case study, a rapid SFQ (RSFQ) 4-to-2 priority encoder circuit is considered. The location of faults, which are artificially inserted in circuit-level simulations, is identified by applying the disclosed methodology. The BIST design is compared with a conventional shift register-based readout circuitry. The BIST design can provide 79% lower static power consumption and 65% lower layout area.

Description

SYSTEMS AND METHODS FOR BUILT-IN SELF-TEST OF SFQ CIRCUITS USING SIDE-CHANNELLEAKAGE INFORMATIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. provisional application No. 63 / 595,815 filed on November 3, 2023, incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under CCF2124453 awarded by the National Science Foundation. The government has certain rights in the invention.BACKGROUND OF THE INVENTION

[0003] Single flux quantum (SFQ) logic is a type of Josephson junction (JJ) based superconducting digital logic family that can operate at extremely high switching frequency (tens to hundreds of GHz) and consume significantly low energy per switching activity, in the order of 10“19J (see K. K. Likharev et aL, "RSFQ logic / memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems," IEEE Transactions on Applied Superconductivity, vol. 1, no. 1, pp. 3-28, March 1991)(see J. X. Przybysz et al., "Superconductor digital electronics," Applied Superconductivity: Handbook on Devices and Applications, pp. 1111-1206, 2015)(see A. I. Braginski, "Superconductor electronics: Status and outlook," Journal of Superconductivity and Novel Magnetism, vol. 32, no. 1, pp. 23-44, November 2019)(see G. Krylov et al., Single Flux Quantum Integrated Circuit Design. Springer, 2022). Such characteristics make this technology a promising candidate for beyond-CMOS large-scale data centers and cloud computing (G. Krylov et al., Single Flux Quantum IntegratedCircuit Design. Springer, 2022). Additionally, SFQ technology can be used in a superconducting quantum computing system as a scalable and energy efficient in-fridge control and readout circuitry (see O. Mukhanov et al., "Scalable quantum computing infrastructure based on superconducting electronics," in IEEE International Electron Devices Meeting (IEDM). IEEE, December 2019, pp. 31.2.1-31.2.4)(see M. R. Jokar et al., "DigiQ: A scalable digital controller for quantum computers using SFQ logic," in IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, April 2022, pp. 400-414).

[0004] Due to the pulsed-based representation of information in SFQ logic, where the presence (absence) of an SFQ pulse corresponds to a logical '1' ('0'), the existing test and verification techniques developed for CMOS technology cannot be directly applicable to SFQ circuits. Therefore, there has been a number of studies investigating design for testability (DFT) techniques such as test point insertion and set / scan chains (see G. Krylov et al., "Design for testability of SFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 27, no. 8, December 2017, Art. no. 1302307)(see A. A. Joseph et aL, "Design for the testability of superconductor electronics," Superconductor Science and Technology, vol. 16, no. 12, 2003, Art. no. 1559), JJ-based stuck-at fault detection models (see A. G. Qoutb, S. Whiteley at al., "Josephson junction stuck-at fault detection in SFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304108), structural and defect oriented testing (see A. A. Joseph et al.,"Towards structural testing of superconductor electronics," in IEEE International Test Conference (ITC). Citeseer, October 2003, pp. 1182- 1182)(see H. G. Kerkhoff et al., "Defect-oriented testing of Josephson logic circuits and systems," Physica C: Superconductivity, vol. 350, no. 3-4, pp. 261-268, 2001), automatic test pattern generation (ATPG) paradigm for dynamic timing verification and path delay fault testing (see F. Wang et al., "An effective and efficient automatic test pattern generation (ATPG) paradigm for certifying performance of RSFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 30, no. 5, August 2020, Art. no. 1300711), overflow, pulse-escape, and pattern sensitive fault models (see M. Li et al., "Data-driven fault model development for superconducting logic," in IEEE International Test Conference (ITC). IEEE, November 2020, pp. 1-5), and on-chip high-frequency testing using pseudo random binary sequence (PRBS)generator (see A. E. Lehmann et aL, "Embedded RSFQ pseudorandom binary sequence generator for multichannel high-speed digital data link testing and synchronization," IEEE Transactions on Applied Superconductivity, vol. 1 , no. 4, June 2017, Art. no. 1301806)(see L. Chen et al., "A new LFSR based high-frequency test method for RSFQ circuit," Superconductivity, vol. 2, 2022, Art. no. 100011)(see L. Chen et al., "On-chip test vector generation and downsampling for testing RSFQ circuits," Superconductor Science and Technology, vol. 35, no. 11, October 2022, Art. no. 115011)(see S. Li et al., "Demonstration and comparison of on-chip high-frequency test methods for RSFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 33, no. 5, August 2023, Art. no. 1302206).SUMMARY OF THE INVENTION

[0005] Some embodiments of the invention disclosed herein are set forth below, and any combination of these embodiments (or portions thereof) may be made to define another embodiment.

[0006] In one aspect, a method for testing superconducting digital circuits comprises: measuring side-channel leakage of the circuit via at least one superconducting output driver circuit communicatively connected to receive a test signal from the circuit; monitoring variation in power dissipation and / or electromagnetic emanations at a temperature N; and identifying correct and incorrect operation based on the variation in power dissipation and / or electromagnetic emanations.

[0007] In one embodiment, the temperature N is room temperature.

[0008] In one embodiment, the temperature N is in the range of 50 K to 70 K.

[0009] In one embodiment, the variation in power dissipation and / or electromagnetic emanations carries information related to input signals of the circuit.

[0010] In one embodiment, the method further comprises identifying a total number of circuit outputs in a high state.

[0011] In one embodiment, the total number of circuit outputs in a high state comprises a Hamming weight.

[0012] In one embodiment, the method comprises a built-in self-test where no output pins for the signals are measured.

[0013] In another aspect, a system for testing superconducting digital circuits, comprises: at least one superconducting output driver circuit communicatively connected to receive a test signal from the circuit; and a computing system communicatively connected to the at least one superconducting output driver circuit, comprising a processor and a non-transitory computer- readable medium with instructions stored thereon, which when executed by the processor, perform steps comprising: measuring side-channel leakage of the circuit; monitoring variation in power dissipation and / or electromagnetic emanations at a temperature N; and identifying correct and incorrect operation based on the variation in power dissipation and / or electromagnetic emanations.

[0014] In one embodiment, the at least one superconducting output driver circuit is communicatively connected to the circuit via at least one SFQ splitter.

[0015] In one embodiment, an output terminal of the at least one superconducting output driver circuit is floating.

[0016] In one embodiment, the system further comprising first and second power delivery networks.

[0017] In one embodiment, the first power delivery network comprises a main bias voltage for powering the circuit and the at least one SFQ splitter.

[0018] In one embodiment, the second power delivery network comprises a test bias voltage for powering the at least one superconducting output driver circuit .

[0019] In one embodiment, the first and second power delivery networks are configured to reduce power consumption during normal operation and minimize switching noise.

[0020] In one embodiment, temperature N is room temperature.

[0021] In one embodiment, the variation in power dissipation and / or electromagnetic emanations carries information related to input signals of the circuit.

[0022] In one embodiment, the computing system further performs steps comprising identifying a total number of circuit outputs in a high state.

[0023] In one embodiment, the total number of circuit outputs in a high state comprises a Hamming weight.

[0024] In one embodiment, the system comprises a built-in self-test where no output pins for the signals are measured.

[0025] In one embodiment, the at least one superconducting output driver circuit comprises at least one of a SFQ-to-DC converter, a Suzuki stack, a SQUID stack and / or other suitable circuit.

[0026] In another aspect, a method for calculating a Hamming weight of a superconducting digital circuit comprises: measuring side-channel leakage of the circuit via a superconducting output driver circuit; monitoring variation in power dissipation and / or electromagnetic emanations at a temperature N; and calculating the Hamming weight of the circuit based on the power dissipation and / or electromagnetic emanations variation.

[0027] In one embodiment, the temperature N is room temperature.BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The foregoing purposes and features, as well as other purposes and features, will become apparent with reference to the description and accompanying figures below, which are included to provide an understanding of the invention and constitute a part of the specification, in which like numerals represent like elements, and in which:

[0029] Fig. 1 shows an exemplary schematic of an SFQ-to-DC converter. The circuit parameters are available in the SuperTools / ColdFlux RSFQ cell library (see "SuperTools / ColdFlux RSFQ cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / github.com / sunmagnetics / RSFQIib).

[0030] Fig. 2 shows simulation results of an RSFQ SFQ-to-DC converter. IBis the total bias current supplied by the voltage source VB= 2.6 mV. The local and external load networks are set to / ?o=5OQ, £o=lOO pH, Co=200 fF, and / ?t=150Q (see Fig. 1 for notation).

[0031] Fig. 3 is a block diagram of the test signal readout using the SFQ-to-DC converters. The main and test bias networks are shown for RSFQ logic style.

[0032] Fig. 4 is a schematic of an RSFQ 4-to-2 priority encoder with three test signals A, B, and C. The design is taken from Mustafa et al. (see Y. Mustafa et al., "Emerging attacks on logic locking" in SFQ circuits and related countermeasures," IEEE Transactions on Applied Superconductivity, vol. 32, no. 3, April 2022, Art. no. 1300708).

[0033] Fig. 5 shows simulation results of an RSFQ4-to-2 priority encoder with three test signals A, B, and C. For each test signal, one SFQ splitter and one SFQ-to-DC converter are connected as per the disclosed BIST methodology. All SFQ gates are simulated using SuperTools / ColdFlux RSFQ cell library (see "SuperTools / ColdFlux RSFQ cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / github.com / sunmagnetics / RSFQIib), and MIT Lincoln Lab 10 kA / cm2process.

[0034] Fig. 6 shows a comparison of the extracted Hamming weight (HW) from the bias current .test of the RSFQ 4-to-2 priority encoder. The applied input signals are the same as in Fig. 5.

[0035] Fig. 7 shows a histogram of the simulated bias current lB,testcrf three SFQ-to-DC converters with thermal noise (4.2 K). IB, test is averaged over 100 ps time interval and recorded 1,000 times.

[0036] Fig. 8 is a block diagram of the test signal readout using the shift registers. The main and test bias networks are shown for RSFQ logic style. The clock signals (elk) are only shown for DFFs and AND gates.

[0037] Fig. 9 shows a comparison of the static power consumption and layout area of the disclosed BIST and shift register-based test signal readout systems.

[0038] Fig. 10 depicts an exemplary computing system in which aspects of the invention may be practiced.DETAILED DESCRIPTION OF THE INVENTION

[0039] It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clearer comprehension of the present invention, while eliminating, for the purpose of clarity, many other elements found in systems and methods of built-in self-test of Single Flux Quantum (SFQ) circuits using sidechannel leakage information. Those of ordinary skill in the art may recognize that other elements and / or steps are desirable and / or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. The disclosure herein is directed to all such variations and modifications to such elements and methods known to those skilled in the art.

[0040] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, exemplary methods and materials are described.

[0041] As used herein, each of the following terms has the meaning associated with it in this section.

[0042] The articles "a" and "an" are used herein to refer to one or to more than one (i.e., to at least one) of the grammatical object of the article. By way of example, "an element" means one element or more than one element.

[0043] "About" as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, ±1%, and ±0.1% from the specified value, as such variations are appropriate.

[0044] Ranges: throughout this disclosure, various aspects of the invention can be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Where appropriate, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 2.7, 3, 4, 5, 5.3, and 6. This applies regardless of the breadth of the range.

[0045] Referring now in detail to the drawings, in which like reference numerals indicate like parts or elements throughout the several views, in various embodiments, presented herein are systems and methods of built-in self-test of SFQ circuits using side-channel leakage information.

[0046] Disclosed is a built-in self-test (BIST), which is a Design for Testability (DFT) technique that allows the circuit-under-test to perform self-testing by using specific hardware and / or software components (see S. Bhunia et aL, "Chapter 3 - System on Chip (SoC) design and test," in Hardware Security, S. Bhunia and M. Tehranipoor, Eds. Morgan Kaufmann, 2019, pp. 47-79). This technique can enable testing of circuits that are difficult (or even impossible) to access through external pins located on chip (e.g., embedded memories (see S. Bhunia et al., "Chapter 3 - System on Chip (SoC) design and test," in Hardware Security, S. Bhunia and M.Tehranipoor, Eds. Morgan Kaufmann, 2019, pp. 47-79)). Alternatively, the BIST is useful when the number of pins dedicated for testing is limited.

[0047] A novel BIST methodology for SFQ circuits is disclosed that leverages a side-channel leakage mechanism to extract the information about readout test signals without requiring any output pins. This side-channel leakage mechanism in SFQ circuits was originally discovered in Mustafa et al. (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307) to implement malicious attacks on superconducting quantum computing systems. It has been found that by measuring the variations in the power supply of an SFQ circuit at room temperature, the applied input bits to specific logic cells, namely SFQ-to-DC converters, can be decoded. Instead of using this side-channel leakage information for malicious purposes as in Mustafa et al. (see Y. Mustafa et aL, "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307), the disclosed system and methods provide an alternative perspective on using this information in the area of DFT and BIST. Although the disclosed BIST methodology focuses only on the readout of test signals, it can also be combined with other existing DFT techniques such as test point insertion and set / scan chains (see G. Krylov et aL, "Design for testability of SFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 27, no. 8, December 2017, Art. no. 1302307).

[0048] The disclosed BIST design includes the insertion of SFQ-to-DC converters, which are an output interface circuit based on a toggle flip-flop (TFF). The SFQ-to-DC converter was first proposed in Kaplunenko et al. (see V. Kaplunenko et aL, "Experimental study of the RSFQ logic elements," IEEE Transactions on Magnetics, vol. 25, no. 2, pp. 861-864, March 1989) and is still commonly used in highspeed digital data links (see T. Ortlepp et aL, "Superconductor-to- semiconductor interface circuit for high data rates," IEEE Transactions on Applied Superconductivity, vol. 19, no. 1, pp. 28-34, February 2009)(see A. Inamdar et al. / 'Superconducting switching amplifiers for high speed digital data links," IEEE Transactions onApplied Superconductivity, vol. 19, no. 3, pp. 1026-1033, June 2009)(see D. Gupta, S. Sarwana et al., "Digital output data links from superconductor integrated circuits," IEEE Transactions on Applied Superconductivity, vol. 29, no. 5, August 2019, Art. no. 1303208) as well as superconducting qubit control and readout circuitry (see F. T. Chong et al., "DigiQ: A scalable digital controller for quantum computers using SFQ logic," in IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, April 2022, pp. 400-414)(see C. Howington et al., "Interfacing superconducting qubits with cryogenic logic: readout," IEEE Transactions on Applied Superconductivity, vol. 29, no. 5, August 2019, Art. no. 1700305). In this work, the SFQ-to-DC converter circuit is used because it has the largest side-channel leakage signal as compared to other SEQ logic gates (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307).

[0049] Further disclosed is a novel BIST methodology for SFQ circuits using side-channel leakage information. By connecting SFQ-to-DC converters to the test signals and monitoring the variations in the power dissipation at room temperature, a test engineer can identify the correct / incorrect operation. In some embodiments, correct operation is defined as a fault-free operation, where for example there are no bit errors inside the SFQ circuits. Incorrect operation may be caused by various things, for example fabrication defects and / or flux trapping issues.

[0050] As a case study, a rapid SFQ (RSFQ) 4-to-2 priority encoder is considered. By manually inserting faults in this circuit (using circuit-level simulations) and applying the disclosed BIST methodology, the locations of these faults are determined. Additionally, possible limitations in more complex SFQ circuits are discussed.

[0051] Further the effects of thermal and switching noise as well as process parameter variations on the side-channel leakage signal are analyzed, and the primary reasons for why the disclosed testing methodology can be classified as BIST are discussed.

[0052] Finally, the disclosed BIST design is compared with a conventional shift registerbased readout circuitry in terms various parameters such as power consumption, layout area,number of pins, clock distribution network, testing time, interpretation of test results, and security.Overview of side channel leakage in SFQ-to-DC converters:

[0053] A side-channel leakage mechanism in SFQ circuits, particularly, SFQ-to-DC converters, were uncovered for the first time in Mustafa et al. (see Y. Mustafa et al., "Sidechannel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307). The key concepts and findings of this leakage mechanism that has been presented in Mustafa et al. (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307) are briefly discussed below.

[0054] The schematic of an SFQ-to-DC converter is depicted in Fig. 1. This circuit is designed based on SuperTools / ColdFlux RSFQ cell library (see "SuperTools / ColdFlux RSFQ cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / github.com / sunmagnetics / RSFQIib) and MIT Lincoln Lab 10 kA / cm2process. The working principle of the SFQ-to-DC converter, which is realized in RSFQ logic style, is shown in Fig. 2. The simulation results are obtained using JoSIM tool (see J. A. Delport et al., "JoSIM — superconductor SPICE simulator," IEEE Transactions on Applied Superconductivity, vol. 29, no. 5, August 2019, Art. no. 1300905). As demonstrated in Fig. 2, the bias current lBhas different values depending on the state of the output voltage Vout(i.e., low and high voltage states). Particularly, when Vout is low (high), the average is equal to 730 juA (708 / ^A), which corresponds to 22 / A difference. By measuring the bias current of RSFQ SFQ-to-DC converter, one can identify the transitions of its output voltage and the applied SFQ input signals. Therefore, there is a side-channel leakage that carries information related to the input signals in the form of variations in the bias current.

[0055] When more than one SFQ-to-DC converters are connected to the same power delivery network, it is possible to identify the total number of outputs that are in the high state by looking at the side-channel leakage information. In this work, this number is referred to asthe Hamming weight (HW) of the SFQ-to-DC converters' output states, and will be used in the BIST methodology described below.

[0056] The effects of thermal (4.2 K) and switching noise were studied in Mustafa et al. (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307). By averaging the measured trace of bias current over 100 ps, the effect of thermal noise can be limited to ±2-3 / zA (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307). Additionally, in more complex SFQ circuits that have multiple logic gates connected to a single power supply, the effect of switching noise on the side-channel leakage signal can be suppressed with sufficient averaging (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307). Such observation is mainly caused by the SFQ-to-DC converter having a large side-channel leakage signal (around 22 / ^A) as compared to other SFQ logic gates. Therefore, the detection of side-channel leakage information in SFQ-to- DC converters can be assumed feasible in a realistic setup.

[0057] A similar side-channel leakage mechanism in ERSFQ based SFQ-to-DC converter has also been studied in Mustafa et al. (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307). Although this disclosure focuses on RSFQ logic style (see K. K. Likharev et al., "RSFQ logic / memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems," IEEE Transactions on Applied Superconductivity, vol. 1, no. 1, pp. 3-28, March 1991) during the following case studies, the disclosed BIST methodology can be also applied for ERSFQ circuits (see D. E. Kirichenko et aL, "Zero static power dissipation biasing of RSFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 21, no. 3, pp. 776-779, June 2011).

[0058] In some embodiments, the disclosed BIST methodology can be generally applied to any superconducting digital electronics logic family. This includes RQL (reciprocal quantum logic) (see Q. P. Herr at al., "Ultra- low-power superconductor logic," Journal of applied physics, vol. 109, no. 10, Art. no. 103903, 2011.), AQFP (adiabatic quantum flux parametron)(see N.Takeuchi et al. ,"An adiabatic quantum flux parametron as an ultra-low-power logic device," Superconductor Science and Technology, vol. 26, no. 3, Art. no. 035010, 2013.), and other SFQ- based logic.Test signal readout using SFQ-to-DC converters:

[0059] The disclosed BIST methodology exploits the side-channel leakage mechanism of SFQ-to-DC converters, which is discussed above. A block diagram of the disclosed test signal readout is shown in Fig. 3. To readout a test signal between two consecutive SFQ gates, one SFQ splitter and one SFQ-to-DC converter is required. It should be noted that the output terminal of SFQ-to-DC converter is not connected ( / .e., floating). Such configuration does not have a significant effect on the side-channel leakage signal as will be demonstrated below.

[0060] The testing circuit comprised two power delivery networks. In RSFQ logic style, these networks are for the main bias voltage VB,main, which powers the original SFQ circuits and testing SFQ splitters, and the test bias voltage VB,test, which powers the SFQ-to-DC converters, as shown in Fig. 3. Two power delivery networks are implemented for two main reasons: to reduce power consumption during normal operation by turning off VB / test, and to minimize the impact of switching noise from VB,main on the side-channel leakage signal in SFQ-to-DC converters.

[0061] Since all SFQ-to-DC converters are connected to VB,testlit is possible to measure the variations in the bias current / s estand extract information about the test signals (Fig. 3). Specifically, the HW of SFQ-to-DC converters' output states can be determined. This HW information is used as a metric to classify whether the circuit operates correctly or not as described below.

[0062] Assuming that VB,test is supplied from room temperature electronics, test signal readout can be performed by measuring IB, test at room temperature. This is convenient and feasible for a test engineer. For example, Octopux, which is an automated setup for testing superconducting (including SFQ) circuits (see "OCTOPUX - automated setup for testing superconductor circuits cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / www.redhitech.com / octopux.html), can supply VB, test on a dedicated pin and measure its bias current latest- Due to the data acquisition rate of up to 2 MS / s (see "OCTOPUX - automated setup for testing superconductor circuits cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / www.redhitech.com / octopux.html), this testing equipment can allow only low frequency measurements. Note thatcan be generated from any thermal zone (e.g., room temperature, 77 K, etc.) and does not affect the testing results.Case study: RSFQ 4-to-2 priority encoder:

[0063] As a case study, consider an RSFQ4-to-2 priority encoder that is depicted in Fig. 4. The working principle and possible applications of this circuit have been discussed in (see Y. Mustafa et al., "Emerging attacks on logic locking" in SFQ circuits and related countermeasures," IEEE Transactions on Applied Superconductivity, vol. 32, no. 3, April 2022, Art. no. 1300708). In this case study, the disclosed BIST methodology is applied to readout the three test signals, A, B, and C, as depicted in Fig. 4.

[0064] The simulation results of an RSFQ 4-to-2 priority encoder with three test signals are shown in Fig. 5. In this figure, Vjs,i refers to the voltage on output junction Js (see Fig. 1 for notation) of the SFQ-to-DC converter connected for the readout of test signal / . Hence, when J8is switching, the output voltage state of the corresponding SFQ-to-DC converter can be classified as high and vice versa.

[0065] During the static operation ( / .e., no input signals are applied), each SFQ-to-DC converter consumes 730 pA of bias current making the total bias current lB,test = 3 x 730 pA =2.190 mA. As mentioned above, when RSFQ SFQ-to-DC converter switch to the high output voltage state, the corresponding bias current drops by approximately 22 pA. In fact, such a dropin the bias current scales linearly with the number of converters that are in the high state. For example, when all of the three RSFQ SFQ-to-DC converters are in the high state, the lB, test drops by around 3 x 22 = 66 / zA. The same behavior can be observed in latest waveform, as shown in Fig. 5. By measuring le,test, a test engineer can map the drops in the bias current to the HW of the SFQ-to-DC converters' output states, as shown in the lowermost trace in Fig. 5. Particularly, if lB,test = 2.190 mA - 22^A = 2.168 mA, the HW is 1. Similarly, if I B, test = 2.190 mA - 66 / zA = 2.124 mA, the HW becomes 3.

[0066] Assuming that all SFQ-to-DC converters' output states are initially low, which is expected when VB,test has just been powered up and can be controlled by a test engineer, it is possible to identify the correct waveform / trace of HW for a given input sequence. This can be done using simulations similar to the ones shown in Fig. 5. If the test circuit does not operate correctly, some of the SFQ-to-DC converters may not switch due to the absence or presence of SFQ pulse. As a result, the HW trace would be different from the trace obtained during simulations.

[0067] The HW traces for both correct and incorrect operation are demonstrated in Fig. 6, where the same circuit is simulated under various fault conditions. Particularly, three open circuit faults are separately inserted right before the test signals A, B, and C (Fig. 4). By carefully analyzing the correct operation in Fig. 5, it can be observed that the HW values between 0.13 and 0.43 ns only depend on the test signal A. When the fault is located before A, the HW trace might be incorrect during this time interval as shown in the second subplot of Fig. 6 (i. e., open circuit at A).

[0068] By comparing the third subplot of Fig. 6 with the correct operation, it can be seen that the HW trace is the same between 0.13 and 0.53 ns. After 0.53 ns, the HW trace is no longer correct. From Fig. 5, VJS,B starts switching at around 0.53 ns. Therefore, the drop of HW value from 2 to 1 at this time instance signifies the fault before the test signal B (in our case, open circuit at B). Using a similar reasoning, the location of open circuit at C can be determined by comparing the fourth subplot of Fig. 6 with the correct operation. In this case, the difference starts at 0.43 ns, which is the same time when VjS,c starts switching in Fig. 5. Therefore, bycarefully examining the HW trace, it is possible to identify the location of faults in this case study. However, in more complex SFQ circuits, the disclosed BIST methodology might not precisely locate the circuit faults since all SFQ-to-DC converters share a common bias line. For example, the incorrect operation could be undetected if a pair of SFQ-to-DC converters incorrectly switch in a complementary manner at the same instance of time. Further research is necessary to identify the optimal test signal readout insertion that maximizes the probability of fault detection. Additionally, more than one latest voltage source could be used to power SFQ- to-DC converters.

[0069] To study the effect of thermal noise on the side-channel leakage signal, the IB, test of three SFQ-to-DC converters is recorded 1,000 times and averaged over 100 ps time interval. The thermal noise is inserted by setting the temperature and bandwidth parameters to 4.2 K and 10 THz, respectively, in JoSIM tool (see J. A. Delport et al., "JoSIM — superconductor SPICE simulator," IEEE Transactions on Applied Superconductivity, vol. 29, no. 5, August 2019, Art. no. 1300905). The histogram of the simulation results is depicted in Fig. 7. For a fair comparison, each combination of HW value ( / . e. , 0, 1, 2, and 3) is simulated equal number of times. As shown in Fig. 7, all four HW distributions are distinguishable from each other. The largest probability peaks are located at 2.123 / zA, 2.145 / zA, 2.168 / ^A, and 2.190 juA, which corresponds to roughly 22 / zA difference and coincides with the previous discussion. Additionally, there is no overlap between these distributions, making the / B,M>S and HW information mapping accurate even in the presence of thermal noise.

[0070] When the SFQ chip is fabricated, its bias current could deviate from the nominal design value due to the process parameter variations. To study the effect of these variations on the side-channel leakage signal, each circuit parameter of an SFQ-to-DC converter is swept assuming ±20% variation. It is determined that the bias resistors Rb3 and RM, which set the bias current / w and / in Fig. 1, and the critical current values of J? and Js have the largest effect of the side-channel leakage. Particularly, the side-channel leakage signal deviates at most by +12 / ^A and -9 / A from the nominal value of 22 / ^A. Assuming that all SFQ-to-DC converters located within one chip are subject to the global parameter variation of, e.g., critical current densityand sheet resistance, the probability peaks of each HW distribution (see Fig. 7) are expected to shift by the constant amount in the horizontal direction (i.e., these peaks would be still distinguishable from each other). In such scenario, the effect of global parameter variations on the side-channel leakage could be mitigated by adding a calibration circuit, which includes several SFQ-to-DC converters with controllable inputs. Before starting the BIST process, the calibration circuit can be tested to identify the side-channel leakage signal amplitude for a given fabricated chip.

[0071] It should be noted that 22 / ^A variation in the bias current / B,testcould be detected by using, e.g., Octopux testing setup, which has an accuracy of 0.5 A at ±5 mA scale (see D. Y. Zinoviev et al., "Octopux: An advanced automated setup for testing superconductor circuits," IEEE Transactions on Applied Superconductivity, vol. 7, no. 2, pp. 3240-3243, June 1997). Additionally, the detectable side-channel leakage in CMOS circuits is in the order of nA, which is three order of magnitude smaller than in SFQ circuits (see Y. Mustafa et aL, "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307)(see W. Yu et al., "Exploiting voltage regulators to enhance various" power attack countermeasures," IEEE Transactions on Emerging Topics in Computing, vol. 6, no. 2, pp. 244- 257, April-June 2018). If the current probe at room temperature has a limited resolution (i.e., less than 22 / ^A) or there is additional noise due to coupling effects, it is possible to further increase the side-channel leakage signal by connecting multiple SFQ-to-DC converters to a single test signal. Furthermore, one can insert another type of SFQ / CMOS interface circuit such as Suzuki stack (a.k.a., Josephson latching driver) (see Y. Mustafa et al., "Optimization of Suzuki stack circuit to reduce" power dissipation," IEEE Transactions on Applied Superconductivity, vol. 32, no. 8, November 2022, Art. no. 1301407)(see Y. Mustafa et al., "Suzuki stack circuit with differential output,"" IEEE Transactions on Applied Superconductivity, vol. 33, no. 2, March 2023, Art. no. 1300306) instead of the SFQ-to-DC converter. Due to the larger output voltage, the Suzuki stacks generate side-channel leakage signals in the order of 50 A (see Y. Mustafa et al., "Side-channel leakage in Suzuki stack circuits,"" in Quantum Computing - Circuits, Systems, Automation and Applications. Springer, 2023, (in press)). 1Discussion:

[0072] The disclosed test signal readout using the SFQ-to-DC converters (Fig. 3) is classified as BIST for several reasons that are listed below.

[0073] According to (see S. Bhunia et aL, "Chapter 3 - System on Chip (SoC) design and test," in Hardware Security, S. Bhunia and M. Tehranipoor, Eds. Morgan Kaufmann, 2019, pp. 47-79), a BIST can allow testing of circuits that do not have direct connections to external pins. In the disclosed BIST methodology, since SFQ-to-DC converters have a floating output, the only connection to an external pin is the bias voltage Ve,test, which can also be merged with the main biaS VB, main-10074] Since the SFQ-to-DC converter is switching in a toggling / latching manner, its output voltage state has a memory effect. Particularly, at any given time instance, the current state (high or low) depends on the previous state. Therefore, the failure at one time instance can propagate to the subsequent measurements. Such failure propagation has been discussed in the above (Fig. 6). By applying a sequence of input test vectors and extracting a single HW trace, it is possible to concurrently test and identify / localize faults. This feature is one of the key components of BIST circuits (see S. Bhunia et aL, "Chapter 3 - System on Chip (SoC) design and test," in Hardware Security, S. Bhunia and M. Tehranipoor, Eds. Morgan Kaufmann, 2019, pp. 47-79).

[0075] The BIST architecture comprises a signal analyzer that receives test signals, compares with the expected / correct data, and generates pass / fail information (see Fig. 3.20 in (see S. Bhunia et al., "Chapter 3 - System on Chip (SoC) design and test," in Hardware Security, S. Bhunia and M. Tehranipoor, Eds. Morgan Kaufmann, 2019, pp. 47-79)). Due to the sidechannel leakage mechanism, the disclosed BIST methodology does not require a specific SFQ comparator. Alternatively, the information about the test signals is naturally evaluated in the form of a bias current variations (HW information) that can be conveniently and efficiently compared by a test engineer.Comparison of BIST methodology with conventional shift register-based readout:

[0076] The disclosed BIST methodology is particularly useful when the number of pins (input, output, and bias) is limited. As described below, the disclosed BIST design is compared with a shift register-based readout circuitry. The shift register-based readout circuit is a conventional approach to reduce the number of pinouts (i.e., output pins) used for testing (see G. Krylov et al., "Design for testability of SFQ circuits," IEEE Transactions on Applied Superconductivity, vol. 27, no. 8, December 2017, Art. no. 1302307). The shift registers are used to convert a parallel input bit array into a serial format. A block diagram of the test signal readout using shift registers is shown in Fig. 8. This readout circuit included SFQ splitters, D flipflops (DFFs), AND gates, and SFQ mergers. The enable signal is applied to load the test signals into storage loops of DFFs.

[0077] Power consumption: The static power consumption, which is supplied by Ve,test (see Figs. 3 and 8) of the disclosed BIST (PBIST) and the shift register-based (PSR) designs can be expressed as:PBIST=PSFQ-IO-DC (1)where N is the total number of test signals, P / is the power consumption of circuit I, PsFQ-to-Dc is the power consumption of the SFQ-to-DC converter, PDFF is the power consumption of the DFF circuit, PAND is the power consumption of the AND gate, Pmer is the power consumption of the SFQ merger, and Pspiis the power consumption of the SFQ splitter. Note that the power consumption of the SFQ splitter, which is located between SFQ gates, is not included since it is connected to VB,main in both designs. By using Equations (1) and (2), the static power consumption of the two designs is plotted in Fig. 9. The power consumption data is calculated for the SuperTools / ColdFlux RSFQ cell library (see "SuperTools / ColdFlux RSFQ cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / github.com / sunmagnetics / RSFQIib). As depicted in Fig. 9, the disclosed BIST design provides approximately 79% lower static power consumption for N > 23 as compared to the shift register-based design. Additionally, Equation(2) does not account for the power consumption of the clock distribution network (for DFFs and AND gates in Fig. 8), which would make the difference even larger.

[0078] Layout area: The layout area requirement for the disclosed BIST (ABIST) and the shift register-based (ASR) designs can, respectively, be written as:ABIST = (ASFQ_tr)-DC+ Aspi) (3)where A is the cell area of circuit / , which is taken from the layouts of SuperTools / ColdFlux RSFQ cell library (see "SuperTools / ColdFlux RSFQ cell library," Accessed: Aug. 3, 2023. [Online], Available: https: / / github.com / sunmagnetics / RSFQIib), ASFQ-IO-DC is the layout area of the SFQ-to- DC converter, ADFF is the layout area of the DFF circuit, AAND is the layout area of the AND gate, Amer is the layout area of the SFQ merger, and Aspiis the layout area of the SFQ splitter. By using (3) and (4), the total layout areas of two designs are compared in Fig. 9. Accordingly, the layout area of the disclosed BIST design is roughly 65% lower when N > 21 as compared to the shift register-based design. The comparison does not include the layout area of bias, clock, and signal lines. However, one can argue that the disclosed BIST design has simpler wire routing (see Figs. 3 and 8), resulting in even greater area improvement as compared to the shift register-based design.

[0079] Short circuits: In the shift register-based design, the output signals of SFQ splitters should be routed to AND gates as shown in Fig. 8. If the selected test signals are located deep inside the SFQ chip, the probability of crossing of these wires with adjacent metal layers becomes higher. As a result, the probability of short circuits between these layers is higher (i.e., resulting in the lower yield) as compared to the disclosed BIST design, where SFQ-to-DC converters can be placed in close proximity to the output signals of SFQ splitters (Fig. 3).

[0080] Number of pins: To implement a test signal readout, the shift register-based design requires a minimum of three pins (one for bias voltage V^test, one for enable signal, and one for output signal as shown in Fig. 8). Since the disclosed BIST design does not utilize the direct measurement of the output of SFQ-to-DC converters, this design needs only one pin for the biasvoltage VB,test- The readout of I B, test does not require a separate pin and can be extracted by measuring the voltage drop on a loading resistor connected in series to the bias pin as has been implemented in Octopux testing setup (see D. Y. Zinoviev et al., "Octopux: An advanced automated setup for testing superconductor circuits," IEEE Transactions on Applied Superconductivity, vol. 7, no. 2, pp. 3240-3243, June 1997). Furthermore, the absence of an output pin eliminates the need for an SFQ-to-CMOS converter / amplifier and coaxial cables to transmit output signals to room temperature, as required in the shift register-based design. This means that the disclosed BIST design generates less heat and dissipates less power between thermal zones of the cryostat.

[0081] Clock distribution network: Each DEF and AND gate in a shift register-based design requires a clock signal to propagate the information to the output pin, as shown in Fig. 8. Therefore, an additional clock distribution network should be placed and routed for this type of design. Alternatively, the disclosed BIST design uses only SFQ-to-DC converters that do not need any clock signals, significantly simplifying the overall circuit design.

[0082] Testing time: In the shift register-based design, after the test signals are loaded into the storage loops of DFFs, one needs to wait for N clock cycles for all bits to propagate to the output pin, as shown in Fig. 8. This delay occurs once the enable signal is applied. During this time, the enable signal cannot be applied, causing the testing time to linearly increase with the number of test signals ( / V). The disclosed BIST design allows one to monitor the HW measurements in real time. As a result, multiple input test vectors can be loaded back-to-back without requiring any clearing operations (like in DFFs). In the low frequency test mode, the disclosed BIST design is faster in terms of the testing time than the shift register-based design. However, in the high frequency test mode (tens of GHz), the disclosed BIST methodology may be limited by the measurement equipment constraints such as data acquisition rate and resolution. This limitation is caused by the requirement to correctly distinguish HW values from the measured bias current. Therefore, a test engineer should carefully select the appropriate testing equipment for the desired high speed testing with the disclosed BIST design.

[0083] Interpretation of test results: Due to the pa rallel-to-seria I conversion property of bit array in the shift register-based design, the information about all test signals (i.e., logical '1' or '0') can be fully recovered. At any given time instance, the disclosed BIST methodology can provide only the information about HW of the test signal states. As a result, each individual test signal cannot be precisely categorized to a logical '1' or '0' from the obtained HW information. Although the disclosed BIST methodology can be useful in a pass / fa i I characterization during the mass production of chips. For instance, if the measured HW trace is different from the reference trace, which can be obtained from ideal simulations, the chip-under-test can be classified as failed and discarded.

[0084] Hardware security: Since the disclosed BIST methodology uses side-channel information, it is vulnerable to side-channel attacks (e.g., as explained in (see Y. Mustafa et al., "Side-channel leakage in SFQ circuits and" related attacks on qubit control and readout systems," IEEE Transactions on Applied Superconductivity, vol. 33, no. 6, September 2023, Art. no. 1304307)). The testing circuit can be protected from malicious side-channel attacks by physically disconnecting Ve,test after the testing is complete or using hardware obfuscation techniques such as SFQ logic locking (see Y. Mustafa et al., "Emerging attacks on logic locking" in SFQ circuits and related countermeasures," IEEE Transactions on Applied Superconductivity, vol. 32, no. 3, April 2022, Art. no. 1300708)(see T. Jabbari et al., "Logic locking in single flux quantum circuits," IEEE Transactions on Applied Superconductivity, vol. 31, no. 5, August 2021, Art. no. 1301605)(see T. Jabbari et al., "Hardware" security of SFQ circuits," in Design Automation of Quantum Computers. Springer, 2023, pp. 135-165).Computing environment

[0085] In some aspects of the present invention, software executing the instructions provided herein may be stored on a non-transitory computer-readable medium, wherein the software performs some or all of the steps of the present invention when executed on a processor.

[0086] Aspects of the invention relate to algorithms executed in computer software. Though certain embodiments may be described as written in particular programming languages, or executed on particular operating systems or computing platforms, it is understood that the system and method of the present invention is not limited to any particular computing language, platform, or combination thereof. Software executing the algorithms described herein may be written in any programming language known in the art, compiled or interpreted, including but not limited to C, C++, C#, Objective-C, Java, JavaScript, MATLAB, Python, PHP, Perl, Ruby, or Visual Basic. It is further understood that elements of the present invention may be executed on any acceptable computing platform, including but not limited to a server, a cloud instance, a workstation, a thin client, a mobile device, an embedded microcontroller, a television, or any other suitable computing device known in the art.

[0087] Parts of this invention are described as software running on a computing device. Though software described herein may be disclosed as operating on one particular computing device (e.g. a dedicated server or a workstation), it is understood in the art that software is intrinsically portable and that most software running on a dedicated server may also be run, for the purposes of the present invention, on any of a wide range of devices including desktop or mobile devices, laptops, tablets, smartphones, watches, wearable electronics or other wireless digita l / cel lula r phones, televisions, cloud instances, embedded microcontrollers, thin client devices, or any other suitable computing device known in the art.

[0088] Similarly, parts of this invention are described as communicating over a variety of wireless or wired computer networks. For the purposes of this invention, the words "network", "networked", and "networking" are understood to encompass wired Ethernet, fiber optic connections, wireless connections including any of the various 802.11 standards, cellular WAN infrastructures such as 3G, 4G / LTE, or 5G networks, Bluetooth®, Bluetooth® Low Energy (BLE) or Zigbee® communication links, or any other method by which one electronic device is capable of communicating with another. In some embodiments, elements of the networked portion of the invention may be implemented over a Virtual Private Network (VPN).

[0089] Fig. 10 and the following discussion are intended to provide a brief, general description of a suitable computing environment in which the invention may be implemented. While the invention is described above in the general context of program modules that execute in conjunction with an application program that runs on an operating system on a computer, those skilled in the art will recognize that the invention may also be implemented in combination with other program modules.

[0090] Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the invention may be practiced with other computer system configurations, including hand-held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0091] Fig. 10 depicts an illustrative computer architecture for a computer 1000 for practicing the various embodiments of the invention. The computer architecture shown in Fig. 10 illustrates a conventional personal computer, including a central processing unit 1050 ("CPU"), a system memory 1005, including a random-access memory 1010 ("RAM") and a readonly memory ("ROM") 1015, and a system bus 1035 that couples the system memory 1005 to the CPU 1050. A basic input / output system containing the basic routines that help to transfer information between elements within the computer, such as during startup, is stored in the ROM 1015. The computer 1000 further includes a storage device 1020 for storing an operating system 1025, application / program 1030, and data.

[0092] The storage device 1020 is connected to the CPU 1050 through a storage controller (not shown) connected to the bus 1035. The storage device 1020 and its associated computer- readable media, provide non-volatile storage for the computer 1000. Although the description of computer-readable media contained herein refers to a storage device, such as a hard disk orCD-ROM drive, it should be appreciated by those skilled in the art that computer-readable media can be any available media that can be accessed by the computer 1000.

[0093] By way of example, and not to be limiting, computer-readable media may comprise computer storage media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other solid state memory technology, CD-ROM, DVD, or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer.

[0094] According to various embodiments of the invention, the computer 1000 may operate in a networked environment using logical connections to remote computers through a network 1040, such as TCP / IP network such as the Internet or an intranet. The computer 1000 may connect to the network 1040 through a network interface unit 1045 connected to the bus 1035. It should be appreciated that the network interface unit 1045 may also be utilized to connect to other types of networks and remote computer systems.

[0095] The computer 1000 may also include an input / output controller 1055 for receiving and processing input from a number of input / output devices 1060, including a keyboard, a mouse, a touchscreen, a camera, a microphone, a controller, a joystick, or other type of input device. Similarly, the input / output controller 1055 may provide output to a display screen, a printer, a speaker, or other type of output device. The computer 1000 can connect to the input / output device 1060 via a wired connection including, but not limited to, fiber optic, ethernet, or copper wire or wireless means including, but not limited to, Bluetooth, Near-Field Communication (NFC), infrared, or other suitable wired or wireless connections.

[0096] As mentioned briefly above, a number of program modules and data files may be stored in the storage device 1020 and RAM 1010 of the computer 1000, including an operatingsystem 1025 suitable for controlling the operation of a networked computer. The storage device 1020 and RAM 1010 may also store one or more applications / programs 1030. In particular, the storage device 1020 and RAM 1010 may store an application / program 1030 for providing a variety of functionalities to a user. For instance, the application / program 1030 may comprise many types of programs such as a word processing application, a spreadsheet application, a desktop publishing application, a database application, a gaming application, internet browsing application, electronic mail application, messaging application, and the like. According to an embodiment of the present invention, the application / program 1030 comprises a multiple functionality software application for providing word processing functionality, slide presentation functionality, spreadsheet functionality, database functionality and the like.

[0097] The computer 1000 in some embodiments can include a variety of sensors 1065 for monitoring the environment surrounding and the environment internal to the computer 1000. These sensors 1065 can include a Global Positioning System (GPS) sensor, a photosensitive sensor, a gyroscope, a magnetometer, thermometer, a proximity sensor, an accelerometer, a microphone, biometric sensor, barometer, humidity sensor, radiation sensor, or any other suitable sensor.REFERENCES

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[0138] The disclosures of each and every patent, patent application, and publication cited herein are hereby incorporated herein by reference in their entirety. While this invention hasbeen disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of this invention may be devised by others skilled in the art without departing from the true spirit and scope of the invention.

Claims

CLAIMSWhat is claimed is:

1. A method for testing superconducting digital circuits, comprising: measuring side-channel leakage of the circuit via at least one superconducting output driver circuit communicatively connected to receive a test signal from the circuit; monitoring variation in power dissipation or electromagnetic emanations at a temperature N; and identifying correct and incorrect operation based on the variation in power dissipation or electromagnetic emanations.

2. The method of claim 1, wherein temperature N is room temperature.

3. The method of claim 1, wherein temperature N is in the range of 50 K to 70 K.

4. The method of claim 1, wherein the variation in power dissipation or electromagnetic emanations carries information related to input signals of the circuit.

5. The method of claim 1, further comprising identifying a total number of circuit outputs in a high state.

6. The method of claim 5, where the total number of circuit outputs in a high state comprises a Hamming weight.

7. The method of claim 1, wherein the method comprises a built-in self-test where no output pins for the signals are measured.

8. A system for testing superconducting digital circuits, comprising:at least one SFQ-to-DC converter communicatively connected to receive a test signal from the circuit; and a computing system communicatively connected to the at least one superconducting output driver circuit, comprising a processor and a non-transitory computer-readable medium with instructions stored thereon, which when executed by the processor, perform steps comprising: measuring side-channel leakage of the circuit; monitoring variation in power dissipation or electromagnetic emanations at a temperature N; and identifying correct and incorrect operation based on the variation in power dissipation or electromagnetic emanations.

9. The system of claim 8, wherein the at least one superconducting output driver circuit is communicatively connected to the circuit via at least one SFQ splitter.

10. The system of claim 8, wherein an output terminal of the at least one superconducting output driver circuit is floating.

11. The system of claim 8, further comprising first and second power delivery networks.

12. The system of claim 11, wherein the first power delivery network comprises a main bias voltage for powering the circuit and the at least one SFQ splitter.

13. The system of claim 11, wherein the second power delivery network comprises a test bias voltage for powering the at least one superconducting output driver circuit.

14. The system of claim 11, wherein the first and second power delivery networks are configured to reduce power consumption during normal operation and minimize switching noise.

15. The system of claim 8, wherein temperature N is room temperature.

16. The system of claim 8, wherein the computing system further performs steps comprising identifying a total number of circuit outputs in a high state.

17. The system of claim 8, wherein the system comprises a built-in self-test where no output pins for the signals are measured.

18. A method for calculating a Hamming weight of a superconducting digital circuit, comprising: measuring side-channel leakage of the circuit via a superconducting output driver circuit; monitoring variation in power dissipation or electromagnetic emanations at a temperature N; and calculating the Hamming weight of the circuit based on the power dissipation or electromagnetic emanations variation.

19. The method of claim 18, wherein temperature N is room temperature.

20. The method of claim 18, wherein temperature N is in the range of 50 K to 70 K.

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