Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a substrate (1), a plurality of pixel units (2), and a wire (3). The plurality of pixel units (2) are located on the substrate (1). Each of the pixel units (2) comprises a first sub-pixel (21) and a second sub-pixel (22). The first sub-pixel (21) and the second sub-pixel (22) comprise a common film layer (200). For each pixel unit (2), the orthographic projection of the first sub-pixel (21) on the substrate (1) and the orthographic projection of the second sub-pixel (22) on the substrate (1) are arranged opposite each other at two sides of the wire (3). At least part of the common film layer (200) is disconnected in an area overlapping with the wire (3) and is spaced apart from the wire (3), forming a first opening (H1). This facilitates a reduction in the current crosstalk between the first sub-pixel (21) and the second sub-pixel (22), and when applied in an anti-peeping mode, the anti-peeping effect can be improved.

Description

Display substrate and its manufacturing method, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] As users place increasing importance on personal privacy, more and more users are showing a strong demand for privacy protection features on mobile phones and other electronic products. Currently, privacy screen protectors attached to the screen of electronic products can prevent peeping, but they cannot switch between privacy protection and sharing functions. For example, when users need to share screen information with others, it is difficult to share over a wide area due to the narrow viewing angle of the privacy screen protector.

[0003] By dividing a pixel unit into privacy sub-pixels and display sub-pixels, privacy protection is achieved by illuminating only the privacy sub-pixels for image display in privacy mode; in normal mode, both privacy sub-pixels and display sub-pixels are illuminated simultaneously for image display, thus achieving sharing functionality. For example, when applied to Organic Light Emitting Diode (OLED) display substrates, because the film layers forming the privacy sub-pixels and the film layers forming the display sub-pixels are fabricated as a single unit and interconnected to form a common film layer, current crosstalk can easily occur between the privacy sub-pixels and the display sub-pixels through this common film layer, affecting the privacy protection effect.

[0004] Summary of the Invention

[0005] This disclosure provides a display substrate and its manufacturing method, and a display device, to solve the problem of current crosstalk between privacy sub-pixels and display sub-pixels caused by a common film layer.

[0006] A first aspect of this disclosure provides a display substrate, the display substrate comprising:

[0007] Substrate;

[0008] Multiple pixel units are located on a substrate; each pixel unit includes a first sub-pixel and a second sub-pixel; the first sub-pixel and the second sub-pixel include a common film layer;

[0009] For at least a portion of the pixel units, the orthographic projections of the first sub-pixel on the substrate and the orthographic projections of the second sub-pixel on the substrate are disposed opposite each other on both sides of the wire; at least a portion of the common film layer is broken in the region overlapping with the wire and spaced apart from the wire to form a first opening.

[0010] The display substrate provided in this disclosure also includes:

[0011] A pixel definition layer is located on one side of the substrate; the pixel definition layer has a first pixel opening and a second pixel opening that penetrate the pixel definition layer along the thickness direction of the pixel definition layer; a common film layer is located on the side of the pixel definition layer away from the substrate, and part of it is located between the first pixel opening and the second pixel opening;

[0012] The first sub-pixel and the second sub-pixel are separated by a partial pixel definition layer located between the first pixel opening and the second pixel opening; for each pixel unit, the orthographic projection of the first pixel opening on the substrate and the orthographic projection of the second pixel opening on the substrate are located on opposite sides of the orthographic projection of the wire on the substrate.

[0013] In the display substrate provided in this disclosure, the conductive lines are located on the side of the pixel definition layer away from the substrate.

[0014] In the display substrate provided in this disclosure, the conductive lines are located between the common film layer and the pixel definition layer.

[0015] In the display substrate provided in this disclosure, the conductive lines are located on the side of the pixel definition layer away from the common film layer;

[0016] The pixel definition layer also has a second opening; the second opening penetrates the pixel definition layer along the thickness direction and exposes the wires; at least a portion of the common film layer breaks at the location of the second opening to form a first opening.

[0017] The display substrate provided in this disclosure further includes a first electrode and a second electrode located between the pixel definition layer and the substrate; the first electrode and the second electrode are spaced apart; the first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel;

[0018] For each pixel unit, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate are located on opposite sides of the orthographic projection of the wire on the substrate.

[0019] In the display substrate provided in this disclosure, the wires, the first electrode, and the second electrode are located in the same conductive film layer; the wires, the first electrode, and the second electrode are separated by a pixel definition layer.

[0020] The display substrate provided in this disclosure further includes a heat insulation layer located on the side of the conductive wires away from the common film layer; the orthogonal projection of the conductive wires on the substrate is located within the orthogonal projection of the heat insulation layer on the substrate.

[0021] In the display substrate provided in this disclosure, the orthographic projection of the conductor on the substrate completely coincides with the orthographic projection of the heat insulation layer on the substrate.

[0022] In the display substrate provided in this disclosure, the conductors include an input terminal and an output terminal; the input terminal and the output terminal are used to apply voltage to the conductors to form current.

[0023] The display substrate provided in this disclosure includes a pixel area and a non-pixel area; the pixel unit is located within the pixel area; and the input and output terminals of the conductors are located within the non-pixel area.

[0024] In the display substrate provided in this disclosure, a wire continuously passes through each pixel unit within a pixel region, such that a first sub-pixel and a second sub-pixel within each pixel unit are located on opposite sides of the wire.

[0025] In the display substrate provided in this disclosure, the conductor includes a first connecting portion and a second connecting portion disposed opposite to each other on both sides of the pixel area and extending along a first direction; wherein the first connecting portion is connected to the input terminal and the second connecting portion is connected to the output terminal;

[0026] The conductor also includes a plurality of partitions extending along a second direction and arranged along a first direction; one end of each partition is connected to a first connection portion and the other end is connected to a second connection portion; each partition extends through pixel units located in the same row in the second direction, such that the first sub-pixel and the second sub-pixel within each pixel unit are located on opposite sides of the conductor.

[0027] In the display substrate provided in this disclosure, the common film layer portion is located between two adjacent pixel units;

[0028] At least some pixel units are positioned opposite each other on both sides of the conductor.

[0029] In the display substrate provided in this disclosure, the first sub-pixel and the second sub-pixel in the same pixel unit emit the same color light.

[0030] In the display substrate provided in this disclosure, both the first sub-pixel and the second sub-pixel are organic light-emitting diodes;

[0031] Organic light-emitting diodes include:

[0032] The first electrode layer is located on one side of the substrate;

[0033] A first functional layer is located on the side of the electrode layer opposite to the substrate; the first functional layer includes at least one film layer;

[0034] An organic light-emitting layer is located on the side of the first functional layer that is away from the first electrode layer;

[0035] The second functional layer is located on the side of the organic light-emitting layer opposite to the first functional layer; the second functional layer includes at least one film layer.

[0036] The second electrode layer is located on the side of the second functional layer that is away from the organic light-emitting layer;

[0037] The common film layer includes at least one of the film layers of the first functional layer, the second functional layer, and the second electrode layer.

[0038] In the display substrate provided in this disclosure, the first functional layer includes a hole transport layer and a hole injection layer stacked along the direction away from the organic light-emitting layer; the second functional layer includes an electron transport layer and an electron injection layer stacked along the direction away from the organic light-emitting layer.

[0039] A second aspect of this disclosure provides a display device comprising a display substrate according to any one of the above.

[0040] A third aspect of this disclosure provides a method for manufacturing a display substrate, comprising:

[0041] A first electrode and a second electrode spaced apart from each other are formed on one side of a substrate; the first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel.

[0042] A pixel definition layer is formed on the side of the first electrode and the second electrode facing away from the substrate; the pixel definition layer has a first pixel opening for exposing the first electrode and a second pixel opening for exposing the second electrode;

[0043] A wire is formed on the side of the pixel definition layer away from the substrate, such that at least a portion of the first pixel opening's orthogonal projection on the substrate and at least a portion of the second pixel opening's orthogonal projection on the substrate are disposed opposite to each other on both sides of the wire.

[0044] A first sub-pixel and a second sub-pixel are fabricated in the first pixel opening and the second pixel opening, respectively; the first sub-pixel and the second sub-pixel include a common film layer, which covers the pixel definition layer and the wire between the first pixel opening and the second pixel opening;

[0045] A voltage is applied to the conductor to heat it up and ablate at least a portion of the common film layer in the region overlapping with the conductor, forming a first opening.

[0046] A fourth aspect of this disclosure provides a method for manufacturing a display substrate, comprising:

[0047] A first electrode, a second electrode, and a wire are formed on one side of a substrate, spaced apart from each other; at least a portion of the first electrode and at least a portion of the second electrode are disposed opposite each other on both sides of the wire; the first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel;

[0048] A pixel definition layer is formed on the side of the first electrode and the second electrode facing away from the substrate; the pixel definition layer has a first pixel opening for exposing the first electrode, a second pixel opening for exposing the second electrode, and a second opening for exposing wires; the second opening is located between the first pixel opening and the second pixel opening;

[0049] A first sub-pixel and a second sub-pixel are fabricated in the first pixel opening and the second pixel opening, respectively; the first sub-pixel and the second sub-pixel include a common film layer, which covers the pixel definition layer between the first pixel opening and the second pixel opening and the wires in the second opening;

[0050] A voltage is applied to the conductor to heat it up and ablate at least a portion of the common film layer in the region overlapping with the conductor, forming a first opening.

[0051] The beneficial effects of this disclosure are as follows:

[0052] This disclosure provides a display substrate and its manufacturing method, as well as a display device. The display substrate includes a substrate, a plurality of pixel units, and conductive lines. The plurality of pixel units are located on the substrate. Each pixel unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel and the second sub-pixel include a common film layer. For each pixel unit, the orthographic projection of the first sub-pixel on the substrate and the orthographic projection of the second sub-pixel on the substrate are disposed opposite each other on both sides of the conductive lines. At least a portion of the common film layer is broken in the region overlapping with the conductive lines and is spaced apart from the conductive lines, forming a first opening. In the embodiments of this disclosure, within the same pixel unit, the portion of the common film layer located within the first sub-pixel and the portion of the common film layer located within the second sub-pixel are broken at the first opening. This can reduce crosstalk caused by the lateral flow of current along the common film layer due to the close distance between the first and second sub-pixels, thereby avoiding the risk of the second sub-pixel and the first sub-pixel being lit simultaneously due to current crosstalk when only the first sub-pixel needs to be lit for image display or only the second sub-pixel needs to be lit for image display. For example, when applied to a privacy mode, this can improve the privacy protection effect. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 is one of the top view structural schematic diagrams of the display substrate provided in the embodiments of this disclosure;

[0055] Figure 2 is one of the cross-sectional structural schematic diagrams of the display substrate provided in the embodiments of this disclosure;

[0056] Figure 3a is a schematic diagram of the fabrication process of the common film layer provided in the embodiments of this disclosure;

[0057] Figure 3b is one of the schematic diagrams of the manufacturing process of the display substrate provided in the embodiment of this disclosure;

[0058] Figure 3c is a second schematic diagram of the manufacturing process of the display substrate provided in the embodiment of this disclosure;

[0059] Figure 3d is a third schematic diagram of the manufacturing process of the display substrate provided in the embodiment of this disclosure;

[0060] Figure 4 is a schematic cross-sectional view of the organic light-emitting diode provided in the embodiment of this disclosure;

[0061] Figure 5 is a second schematic diagram of the cross-sectional structure of the display substrate provided in the embodiment of this disclosure;

[0062] Figure 6a is a third schematic diagram of the cross-sectional structure of the display substrate provided in the embodiment of this disclosure;

[0063] Figure 6b is a fourth schematic cross-sectional view of the display substrate provided in the embodiments of this disclosure;

[0064] Figure 7 is a second top view of the display substrate provided in an embodiment of this disclosure;

[0065] Figure 8a is a third top view of the display substrate provided in the embodiment of this disclosure;

[0066] Figure 8b is a top view of the fourth embodiment of the display substrate provided in this disclosure;

[0067] Figure 8c is a top view of the fifth embodiment of the display substrate provided in this disclosure;

[0068] Figure 9a is a top view of the display substrate provided in an embodiment of this disclosure;

[0069] Figure 9b is a top view of the display substrate provided in the embodiment of this disclosure (the seventh one).

[0070] Figure 9c is a top view of the display substrate provided in an embodiment of this disclosure;

[0071] Figure 10a is a top view of the display substrate provided in an embodiment of this disclosure;

[0072] Figure 10b is a top view of the display substrate provided in the embodiment of this disclosure.

[0073] Figure 10c is the fifth schematic diagram of the cross-sectional structure of the display substrate provided in the embodiment of this disclosure;

[0074] Figure 11 is a sixth schematic diagram of the cross-sectional structure of the display substrate provided in the embodiments of this disclosure;

[0075] Figure 12 is an equivalent circuit diagram of the pixel circuit provided in an embodiment of this disclosure;

[0076] Figure 13 is one of the flowcharts of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

[0077] Figure 14 is a second flowchart of the method for manufacturing a display substrate according to an embodiment of this disclosure. Detailed Implementation

[0078] To make the above-described objects, features, and advantages of this disclosure more apparent and understandable, the disclosure will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this disclosure are illustrative of the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this disclosure. The accompanying drawings of this disclosure are for illustrative purposes only and do not represent actual scale.

[0079] As users place increasing importance on personal privacy, more and more users are showing a strong demand for privacy protection features on mobile phones and other electronic products. Currently, privacy screen protectors attached to the screen of electronic products can prevent peeping, but they cannot switch between privacy protection and sharing functions. For example, when users need to share screen information with others, it is difficult to share over a wide area due to the narrow viewing angle of the privacy screen protector.

[0080] In some technical approaches, a privacy function is achieved by dividing a pixel unit into privacy sub-pixels and display sub-pixels. In privacy mode, only the privacy sub-pixels are illuminated for image display; in normal mode, both privacy sub-pixels and display sub-pixels are illuminated simultaneously for image display, thus achieving a sharing function. For example, when applied to organic light-emitting diode (OLED) display substrates, because the film layers forming the privacy sub-pixels and the film layers forming the display sub-pixels are fabricated as a single unit and interconnected to form a common film layer, current crosstalk can easily occur between the privacy sub-pixels and the display sub-pixels through this common film layer, affecting the privacy protection effect.

[0081] In view of this, embodiments of the present disclosure provide a display substrate for solving the problem of current crosstalk between privacy sub-pixels and display sub-pixels caused by a common film layer.

[0082] Figure 1 is a top view of one of the display substrates provided in the embodiments of this disclosure; Figure 2 is a cross-sectional view of one of the display substrates provided in the embodiments of this disclosure.

[0083] In this embodiment of the disclosure, as shown in Figures 1 and 2, the display substrate includes a substrate 1, a plurality of pixel units 2, and wires 3. Figure 2 is a cross-sectional view of Figure 1 along section line AA.

[0084] Substrate 1 is located at the bottom of the display substrate and is used to support pixel units 2 and wires 3 disposed thereon. The shape and size of substrate 1 are adapted to the shape and size of the display substrate. Specifically, the shape of substrate 1 can be a conventional shape such as square or rectangle, or an irregular shape such as circle, and is not limited here. In some embodiments, substrate 1 can be a rigid substrate made of a rigid material, such as glass, to fabricate a rigid display substrate. In some embodiments, substrate 1 can be a flexible substrate made of a flexible material, such as polyimide (PI), to fabricate a flexible display substrate, and is not limited here. In specific implementations, substrate 1 can be a single-layer structure or a multi-layer structure, and is not limited here.

[0085] Multiple pixel units 2 are located on the substrate 1. Each pixel unit 2 includes a first sub-pixel 21 and a second sub-pixel 22. The display substrate can have multiple display modes. In the first display mode, for a pixel unit 2, only the first sub-pixel 21 can be lit to display an image. In the second display mode, for a pixel unit 2, both the first sub-pixel 21 and the second sub-pixel 22 can be lit to display an image simultaneously. In some display modes, for a pixel unit 2, only the second sub-pixel 22 can be lit to display an image, which is not limited here. The first display mode can be a privacy mode, where the first sub-pixel 21 can be a privacy sub-pixel. In the privacy mode, only the first sub-pixel 21 is lit to display an image. The angle and brightness of the light emitted by the pixel unit 2 are small, which helps to reduce the viewing angle in the privacy mode and achieve a privacy effect. The second display mode can be a sharing mode, where both the first sub-pixel 21 and the second sub-pixel 22 are lit simultaneously. The angle and brightness of the light emitted by the pixel unit 2 are large, which is beneficial for more viewers to view the display screen at the same time. In some embodiments, in the sharing mode, for a pixel unit 2, only the second sub-pixel 22 can be lit for image display. In specific implementations, the angle and brightness of the light emitted by the second sub-pixel 22 can be improved by increasing the light-emitting area of ​​the second sub-pixel 22 and increasing the driving current, thereby enhancing the sharing effect. No limitation is made here.

[0086] In this embodiment, the first sub-pixel 21 and the second sub-pixel 22 can be fabricated using deposition processes such as evaporation and deposition. For example, a portion of the film layer in the first sub-pixel 21 and the second sub-pixel 22 can be deposited using an open mask (OM). An opening in the OM can simultaneously expose all pixel units 2 within the display area of ​​the display substrate, effectively reducing the fabrication difficulty and cost compared to a fine metal mask (FMM). When deposited using OM, the resulting film layer covers the entire display area exposed by the opening of the OM. As shown in Figures 1 and 2, the first sub-pixel 21 and the second sub-pixel 22 include a common film layer 200. During fabrication, the common film layer 200 is fabricated using a full-area deposition method. For example, the common film layer 200 can be fabricated using the OM process.

[0087] Figure 3a is a schematic diagram of the fabrication process of the common film layer provided in the embodiments of this disclosure.

[0088] As shown in Figure 3a, taking the common film layer 200 of the first sub-pixel 21 and the second sub-pixel 22, which includes a first common film layer 201 and a second common film layer 202, as an example, the process of forming the common film layer 200 using the OM process is illustrated. The first sub-pixel 21 and the second sub-pixel 22 also each include a light-emitting layer 203 located between the first common film layer 201 and the second common film layer 202. One of the first common film layer 201 and the second common film layer 202 is electrically connected to the positive terminal of a power source for hole transport, and the other is electrically connected to the negative terminal of a power source for electron transport. Holes input from the positive terminal of the power source and electrons input from the negative terminal recombine in the light-emitting layer 203 to excite and emit light. Specifically, as shown in Figure 3a, the formation process of the common film layer 200 includes at least the following steps:

[0089] 1. A first common film layer 201 is formed on one side of the substrate 1 by means of OM process; wherein the first common film layer 201 covers the area exposed by the opening of OM, so that the part of the first common film layer 201 located at the position corresponding to the first sub-pixel 21 is interconnected with the part of the first common film layer 201 located at the position corresponding to the second sub-pixel 22.

[0090] 2. Using the FMM process, a light-emitting layer 203 is formed on the side of the first common film layer 201 facing away from the substrate 1. The FMM has openings corresponding to the first sub-pixel 21 and the second sub-pixel 22. The light-emitting layer material is formed through these openings at positions corresponding to the first sub-pixel 21 and the second sub-pixel 22, forming portions of the light-emitting layer 203 belonging to the first sub-pixel 21 and the second sub-pixel 22, respectively. The light-emitting layers 203 of the first sub-pixel 21 and the second sub-pixel 22 within the same pixel unit 2 are insulated from each other and spaced apart.

[0091] 3. A second common film layer 202 is formed on the side of the light-emitting layer 203 away from the substrate 1 by means of the OM process; wherein the second common film layer 202 covers the area exposed by the opening of the OM, so that the part of the second common film layer 202 located at the position corresponding to the first sub-pixel 21 is interconnected with the part of the second common film layer 202 located at the position corresponding to the second sub-pixel 22.

[0092] In specific implementation, both the first common film layer 201 and the second common film layer 202 may include at least one film layer. In the manufacturing process shown in FIG3a, all the film layers included in the first common film layer 201 and all the film layers included in the second common film layer 202 are disposed on the entire display area of ​​the display substrate, constituting the common film layer 200.

[0093] In some embodiments, the common film layer of the first sub-pixel 21 and the second sub-pixel 22 may also be only a portion of all the film layers in the common film layer 200 formed in the fabrication process shown in FIG. 3a. For example, during the fabrication process, only a portion of the film layer in the first common film layer 201 shown in FIG. 3a may be fabricated using the OM process, so that this portion of the film layer covers the entire area exposed by the opening of the OM, while the remaining portion of the film layer in the first common film layer 201 shown in FIG. 3a may be fabricated using the FMM process, so that the remaining portion of the film layer is formed only in the area corresponding to the first sub-pixel 21 and the second sub-pixel 22, and the film layers formed in the areas corresponding to the first sub-pixel 21 and the second sub-pixel 22 are spaced apart from each other. Similarly, only a portion of the second common film layer 202 shown in FIG3a can be fabricated using the OM process, so that this portion of the film layer covers the entire area exposed by the opening of the OM, while the remaining portion of the second common film layer 202 shown in FIG3a can be fabricated using the FMM process, so that the remaining portion of the film layer is formed only in the area corresponding to the first sub-pixel 21 and the second sub-pixel 22, and the film layers formed in the areas corresponding to the first sub-pixel 21 and the second sub-pixel 22 are spaced apart from each other.

[0094] In some embodiments, the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 can be used to emit light of the same color. For example, the light-emitting layer of the first sub-pixel 21 and the light-emitting layer of the second sub-pixel 22 in the same pixel unit 2 can be made of the same material. Since the distance between the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 is relatively small, and the light-emitting layers of the first sub-pixel 21 and the second sub-pixel 22 are made of the same material, when the light-emitting layer is made using a process such as vapor deposition, it is only necessary to open openings corresponding to the first sub-pixel 21 and the second sub-pixel 22 respectively at adjacent positions on the FMM, and then the light-emitting layers of the first sub-pixel 21 and the second sub-pixel 22 can be made simultaneously in one vapor deposition process. Compared to making the light-emitting layers of the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 using different materials, the risk of crosstalk between the light-emitting layer materials of the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 due to inaccurate FMM alignment can be reduced. The first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 emit light of the same color, which can also reduce the development difficulty of the control chip and control algorithm used to control the light emission of the pixel unit 2.

[0095] The conductive wire 3 can be located on one side of the common film layer 200 and is disposed adjacent to the film layer of the common film layer 200. For at least a portion of the pixel units 2, the orthographic projection of the first sub-pixel 21 on the substrate 1 and the orthographic projection of the second sub-pixel 22 on the substrate 1 are disposed opposite to each other on both sides of the conductive wire 3. At least a portion of the film layer in the common film layer 200 is broken in the area overlapping with the conductive wire 3 and is disposed at a certain distance from the conductive wire 3, forming a first opening H1 for accommodating the conductive wire 3. The conductive wire 3 is made of a conductive material, specifically, it can be a metallic conductive layer material such as aluminum (Al), silver (Ag), or molybdenum (Mo), which is not limited here.

[0096] In this embodiment of the disclosure, at least a portion of the film layer in the common film layer 200 is disconnected at the first opening H1 within at least a portion of the pixel units 2. This reduces the number of film layers connected between the first sub-pixel 21 and the second sub-pixel 22 in at least a portion of the pixel units 2. This reduces crosstalk caused by the lateral flow of current along the common film layer 200 due to the close proximity of the first sub-pixel 21 and the second sub-pixel 22 in that portion of the pixel units 2. Consequently, it reduces the risk of the second sub-pixel 22 and the first sub-pixel 21 being simultaneously illuminated due to current crosstalk when only the first sub-pixel 21 or only the second sub-pixel 22 needs to be illuminated for image display. For example, when applied to a privacy mode, this can improve the privacy protection effect.

[0097] In some embodiments, the orthographic projections of the first sub-pixel 21 and the second sub-pixel 22 onto the substrate 1 can be disposed opposite each other on both sides of the conductor 3 only within a portion of the pixel units 2, thereby forming the first opening H1 only in the common film layer of the first sub-pixel 21 and the second sub-pixel 22 within the portion of the pixel units 2. In specific implementations, the number and position of the pixel units 2 with the conductor 3 between the first sub-pixel 21 and the second sub-pixel 22 can be flexibly selected according to requirements and are not limited here. For example, if a privacy function is only required in a specific display area of ​​the display substrate, then only the first sub-pixel 21 and the second sub-pixel 22 in the pixel units 2 within that specific area can be disposed on both sides of the conductor 2.

[0098] In some embodiments, for each pixel unit 2 on the display substrate, the orthographic projection of the first sub-pixel 21 onto the substrate 1 and the orthographic projection of the second sub-pixel 22 onto the substrate 1 can be arranged opposite each other on both sides of the conductor 3. For example, in privacy mode, the privacy effect can be improved throughout the entire display area of ​​the display substrate. No limitation is made here.

[0099] In specific fabrication, the conductor 3 can be fabricated before the formation of the common film layer 200. After the conductor 3 is fabricated, the common film layer 200 can be formed directly on the surface of the conductor 3. Alternatively, the conductor 3 can be fabricated directly on the surface of the common film layer 200 after its formation; this is not limited here. For example, after the conductor 3 and the common film layer 200 are fabricated, a voltage is applied to the conductor 3 to generate a current flowing along it. The conductor 3 generates high temperature due to the heat generated by the current, which ablates the common film layer 200 in contact with it. At least a portion of the film layer 200 breaks in the ablation area, forming a first opening H1 to accommodate the conductor 3. In specific fabrication, placing the conductor 3 in direct contact with the common film layer 200 is beneficial for the ablation of the common film layer 200 by the conductor 3. In specific implementation, the conductor 3 and the common film layer 200 can also be separated by a film layer; this is not limited here.

[0100] Figure 3b is one of the schematic diagrams of the manufacturing process of the display substrate provided in the embodiments of this disclosure.

[0101] As shown in Figure 3b, taking an example where both the first sub-pixel 21 and the second sub-pixel 22 include a first common film layer 201, a second common film layer 202, and a light-emitting layer 203 located between the first common film layer 201 and the second common film layer 202, and the common film layer 200 is formed after the fabrication of the conductive wire 3, the fabrication process of the display substrate provided in this disclosure embodiment will be described by way of example. Specifically, as shown in Figure 3b, the fabrication process of the display substrate may include the following steps:

[0102] 1. A conductive material is deposited on one side of the substrate 1 to form a conductive layer through processes such as sputtering deposition. The conductive layer is then etched through patterning processes such as exposure, development, and etching to form the pattern of the wire 3; or the pattern of the wire 3 is directly formed through a metal mask process.

[0103] 2. A first common film layer 201 is formed on the side of the wire 3 away from the substrate 1 by means of OM process;

[0104] 3. Using the FMM process, a light-emitting layer 203 is formed on the side of the first common film layer 201 facing away from the substrate 1; wherein at least a portion of the light-emitting layer 203 of the first sub-pixel 21 and at least a portion of the light-emitting layer 203 of the second sub-pixel 22 are spaced apart on both sides of the wire 3.

[0105] 4. A second common film layer 202 is formed on the side of the light-emitting layer 203 facing away from the substrate 1 using the OM process;

[0106] 5. A voltage is applied to the conductor 3 to form a current flowing through it. The conductor 3 heats up, generating high temperatures that sequentially ablate the first common film layer 201 and the second common film layer 202, causing them to disconnect in the corresponding areas of the conductor 3, thus exposing the conductor 3. In areas where the conductor 3 is not present, the first common film layer 201 remains connected, and the second common film layer 202 also remains connected.

[0107] In the fabrication process shown in Figure 3a, when a voltage is applied to the wire 3 to generate current, causing the wire 3 to heat up and ablate the common film layer 200, the high-temperature wire 3 can ablate all the film layers in the common film layer 200 in a direction away from the substrate 1, thereby forming a first opening H1 that penetrates the common film layer 200. As shown in Figure 3a, the first opening H1 exposes the wire 3, and by housing the wire 3 within the first opening H1, current crosstalk between the first sub-pixel 21 and the second sub-pixel 22 of the same pixel unit 2 can be minimized.

[0108] Figure 3c is a second schematic diagram of the manufacturing process of the display substrate provided in the embodiment of this disclosure.

[0109] In some embodiments, as shown in FIG3c, when a voltage is applied to the wire 3 to form a current, thereby heating the wire 3 and causing it to ablate the common film layer 200, the high-temperature wire 3 can ablate only a portion of the film layers in the common film layer 200 along the direction away from the substrate 1. This results in only a portion of the film layers in the common film layer 200 being ablated and disconnected, while the remaining film layers remain connected. For example, in an organic light-emitting diode (OLED) display panel, the cathode of the OLED is typically located on the side away from the substrate 1, and the OLED cathode is typically fabricated using an OM process across the entire surface, serving as a common electrode. Therefore, when the common film layer is ablated by the high-temperature wire 3, the cathode film layer of the OLED in the common film layer may not be ablated, thus preserving the common electrode function of the OLED cathode. In specific implementations, a portion of the conductive film layer adjacent to the cathode of the OLED may also be retained as an auxiliary electrode to reduce the resistance of the common electrode. As shown in Figure 3c, a first opening H1 is formed in the region corresponding to the conductor 3 in the common film layer 200, which does not penetrate the common film layer 200, and the conductor 3 is accommodated in the first opening H1.

[0110] Figure 3d is a third schematic diagram of the manufacturing process of the display substrate provided in the embodiment of this disclosure.

[0111] In some embodiments, as shown in FIG3d, a common film layer 200 can be fabricated on one side of the substrate 1 first, followed by the fabrication of the conductive wire 3. For example, a first common layer 201 is fabricated sequentially using an OM process, a light-emitting layer 203 is fabricated using an FMM process, and a second common layer 202 is fabricated using an OM process to form the common film layer 200; then, a conductive wire 3 is formed on the side of the common film layer 200 facing away from the substrate 1, with the conductive wire 3 located between at least a portion of the light-emitting layer 203 of the first sub-pixel and at least a portion of the light-emitting layer 203 of the second sub-pixel. After the conductive wire 3 is fabricated, it is electrically heated to ablate the common film layer 200, forming a first opening H1. In some embodiments, all layers in the common film layer can be ablated to form a first opening H1 that penetrates the common film layer. In some embodiments, only a portion of the layers in the common film layer can be ablated to form a first opening H1 that does not penetrate the common film layer. No limitation is made here. In some embodiments, as shown in FIG3d, after the conductor 3 ablates the common film layer located below it, the conductor 3 is suspended due to loss of support. In some embodiments, after the conductor 3 ablates the common film layer located below it, it droops down and contacts the film layer exposed by the first opening H1 after the common film layer is ablated, and is thus supported by the film layer exposed by the first opening H1. No limitation is made here.

[0112] Figure 4 is a schematic cross-sectional view of the organic light-emitting diode provided in an embodiment of this disclosure.

[0113] In some embodiments, the first sub-pixel 21 and the second sub-pixel 22 can both be organic light-emitting diodes.

[0114] As shown in Figure 4, the organic light-emitting diode (OLED) includes a first electrode layer 2011, a first functional layer 2001, an organic light-emitting layer 2014, a second functional layer 2002, and a second electrode layer 2017 stacked together. In a specific implementation, the first electrode layer 2011 can be disposed on the side closer to the substrate 1, and the second electrode layer 2017 can be disposed on the side farther from the substrate 1. The first functional layer 2001 includes at least one film layer; the second functional layer 2002 includes at least one film layer. At least one of the film layers of the first functional layer 2001, the second functional layer 2002, and the second electrode layer 2017 can be fabricated using an OM (Organic Oxidation) process, thereby ensuring that the common film layer 200 includes at least one of the film layers of the first functional layer 2001, the second functional layer 2002, and the second electrode layer 2017.

[0115] In some embodiments, the first electrode layer 2011 serves as the anode of the organic light-emitting diode (OLED) and is connected to the positive terminal of the power supply for inputting holes; the second electrode layer 2017 serves as the cathode of the OLED and is connected to the negative terminal of the power supply for inputting electrons. Holes and electrons are input into the organic light-emitting layer 2014 through the first functional layer 2001 and the second functional layer 2002, respectively, and recombine in the organic light-emitting layer 2014 to excite emitted light. In some embodiments, the first functional layer 2001 may include a hole transport layer 2014 and a hole injection layer 2013 stacked in a direction away from the organic light-emitting layer 2014; the second functional layer 2002 includes an electron transport layer 2015 and an electron injection layer 2016 stacked in a direction away from the organic light-emitting layer. In specific implementations, the first functional layer 2001 and the second functional layer 2002 may also include more or fewer film layers, which is not limited here.

[0116] In some embodiments, the first electrode layer 2011 serves as the cathode of the organic light-emitting diode (OLED) and is connected to the negative terminal of the power supply for inputting electrons; the second electrode layer 2017 serves as the anode of the OLED and is connected to the positive terminal of the power supply for inputting holes. Electrons and holes are input into the organic light-emitting layer 2014 through the first functional layer 2001 and the second functional layer 2002, respectively, and recombine in the organic light-emitting layer 2014 to excite emitted light. In some embodiments, the first functional layer 2001 may include an electron transport layer 2015 and an electron injection layer 2016 stacked in a direction away from the organic light-emitting layer 2014; the second functional layer 2002 includes a hole transport layer 2013 and a hole injection layer 2012 stacked in a direction away from the organic light-emitting layer. In specific implementations, the first functional layer 2001 and the second functional layer 2002 may also include more or fewer film layers, which is not limited here.

[0117] Typically, the first electrode layer 2011 can be disposed as the anode of the organic light-emitting diode (OLED) on the side close to the substrate 1, and the second electrode layer 2017 can be disposed as the cathode of the OLED on the side away from the substrate 1. No specific limitations are imposed here.

[0118] In specific implementation, the first sub-pixel 21 and the second sub-pixel 22 can also be other light-emitting elements besides organic light-emitting diodes, which are not limited here.

[0119] In some embodiments, as shown in FIG2, the display substrate further includes a pixel definition layer 4. The pixel definition layer 4 is located on one side of the substrate 1. The pixel definition layer 4 has a first pixel opening 401 and a second pixel opening 402 that penetrate the pixel definition layer 4 along the thickness direction h. A common film layer 200 is located on the side of the pixel definition layer 4 facing away from the substrate 1, and is partially located between the first pixel opening 401 and the second pixel opening 402. The orthographic projection of the common film layer 200 located between the first pixel opening 401 and the second pixel opening 402 on the substrate 1 overlaps with the orthographic projection of the pixel definition layer 4 on the substrate 1.

[0120] The first sub-pixel 21 is at least partially located within the first pixel opening 401. The second sub-pixel 22 is at least partially located within the second pixel opening 402. Specifically, this means that each of the film layers forming the first sub-pixel 21 is at least partially located within the first pixel opening 401, and each of the film layers forming the second sub-pixel 22 is at least partially located within the second pixel opening 402. For example, the common film layer 200 used to form the first sub-pixel 21 and the second sub-pixel 22 is partially located within the first pixel opening 401 and the second pixel opening 402, and partially located on the surface of the pixel definition layer 4 outside the first pixel opening 401 and the second pixel opening 402. For example, the light-emitting layers 203 used to form the first sub-pixel 21 and the second sub-pixel 22 may be entirely located within the first pixel opening 401 and the second pixel opening 402. In a specific implementation, the first sub-pixel 21 and the second sub-pixel 22 are separated by a partial pixel definition layer 4 located between the first pixel opening 401 and the second pixel opening 402.

[0121] In specific implementation, for each pixel unit 2, the orthographic projection of the first pixel opening 401 on the substrate 1 and the orthographic projection of the second pixel opening 402 on the substrate 1 are located on both sides of the orthographic projection of the wire 3 on the substrate 1.

[0122] In some embodiments, as shown in FIG2, the wire 3 is located on the side of the pixel definition layer 4 facing away from the substrate 1. In specific fabrication, the wire 3 can be fabricated after the pixel definition layer 4 is fabricated. The wire 3 can be fabricated on the surface of the pixel definition layer 4, avoiding the need to create openings in the pixel definition layer 4 to expose the wire 3.

[0123] In some embodiments, as shown in FIG2, the wire 3 is located between the common film layer 200 and the pixel definition layer 4. Specifically, the wire 3 is located between the common film layer 200 and the pixel definition layer 4 before the common film layer 200 is fabricated. The wire 3 is first formed on the side of the pixel definition layer 4 facing away from the substrate 1, and then the common film layer 200 is formed on the side of the wire 3 facing away from the pixel definition layer 4. Thus, after the common film layer 200 is ablated by the wire 3, the wire 3 can still be supported by the underlying pixel definition layer 4, improving the stability of the structure.

[0124] In some embodiments, as shown in FIG3d, the conductive line 3 is located on the side of the common film layer 200 facing away from the pixel definition layer 4. Specifically, the conductive line 3 is located on the side of the common film layer 200 facing away from the pixel definition layer 4 before fabricating the conductive line 3. This means that the common film layer 200 is first formed on the side of the pixel definition layer 4 facing away from the substrate 1, and then the conductive line 3 is formed on the side of the common film layer 200 facing away from the pixel definition layer 4. Using this arrangement, the process steps for fabricating the pixel definition layer 4 and the common film layer 200 in related technologies do not need to be changed, and the coating process of the common film layer 200 is relatively mature in related technologies.

[0125] Figure 5 is a second schematic diagram of the cross-sectional structure of the display substrate provided in the embodiments of this disclosure.

[0126] In some embodiments, as shown in FIG5, the wire 3 is located on the side of the pixel definition layer 4 away from the common film layer 200. Specifically, the wire 3 is fabricated before the pixel definition layer 4 is fabricated, and then the pixel definition layer 4 is formed on the side of the wire 3 away from the substrate 1, and the common film layer 200 is formed on the side of the pixel definition layer 4 away from the wire 3.

[0127] As shown in Figure 5, the pixel definition layer 4 also has a second opening H2. The second opening H2 penetrates the pixel definition layer 4 along the thickness direction h and exposes the conductive wire 3. At least a portion of the common film layer 200 is broken at the location of the second opening H2, forming a first opening H1. In specific fabrication, the common film layer 200 is filled into the second opening H2 and contacts the conductive wire 3. After the conductive wire 3 is energized, the common film layer 200 in contact with it is ablated, thereby causing at least a portion of the common film layer 200 to break at the location of the second opening H2, forming the first opening H1. In specific implementation, the area of ​​the orthographic projection of the first opening H1 onto the substrate 1 depends on the material and width of the conductive wire 3, the magnitude of the current applied to the conductive wire 3, and the heating time, and does not limit the size relationship between the area of ​​the orthographic projection of the first opening H1 onto the substrate 1 and the area of ​​the orthographic projection of the second opening H2 onto the substrate 1.

[0128] In a specific implementation, as shown in Figure 5, the display substrate further includes a first electrode 211 and a second electrode 221 located between the pixel definition layer 4 and the substrate 1. The first electrode 211 and the second electrode 221 are spaced apart. The orthographic projection of the first electrode 211 onto the substrate 1 at least partially overlaps with the orthographic projection of the first pixel opening 401 onto the substrate 1, and the orthographic projection of the second electrode 221 onto the substrate 1 at least partially overlaps with the orthographic projection of the second pixel opening 402 onto the substrate 1. The first electrode 211 is used to form a first sub-pixel 21, and the second electrode 221 is used to form a second sub-pixel 22. When both the first sub-pixel 21 and the second sub-pixel 22 are organic light-emitting diodes (OLEDs), as shown in Figures 4 and 5, the first electrode 211 and the second electrode 221 are configured as a first electrode layer 2011 located on the side of the OLED closer to the substrate 1. Specifically, the first electrode 211 can be the anode or cathode of the first sub-pixel 21, and the second electrode 221 can be the anode or cathode of the second sub-pixel 22; no specific limitation is made here.

[0129] In specific implementation, as shown in Figure 5, for each pixel unit 2, the orthographic projection of the first electrode 211 on the substrate 1 and the orthographic projection of the second electrode 221 on the substrate 1 are located on both sides of the orthographic projection of the wire 3 on the substrate 1.

[0130] In some embodiments, as shown in FIG5, the conductive wire 3, the first electrode 211, and the second electrode 221 are located in the same conductive film layer. The conductive wire 3, the first electrode 211, and the second electrode 221 are separated by a partial pixel definition layer 4 located between the conductive wire 3 and the first electrode 211, and a partial pixel definition layer 4 located between the conductive wire 3 and the second electrode 221. Since the conductive wire 3, the first electrode 211, and the second electrode 221 are located in the same conductive film layer, specifically, the conductive wire 3, the first electrode 211, and the second electrode 221 can be fabricated in the same conductive film layer formed in the same process step using the same patterning process. This helps to reduce the number of film layers in the display substrate, reduce the fabrication difficulty of the display substrate, and reduce the thickness of the display substrate.

[0131] In some embodiments, as shown in FIG5, the width W1 of the wire 3 between the first electrode 211 and the second electrode 221 is smaller than the width W2 of the first electrode 211 and the width W3 of the second electrode 221. While ensuring that the common film layer can achieve the predetermined ablation effect, minimizing the width of the wire 3 can prevent the wire 3 from occupying too much of the area where the first electrode 211 and the second electrode 221 are located. This is beneficial for increasing the orthogonal projection area of ​​the first sub-pixel 21 and the second sub-pixel 22 on the substrate 1, thereby increasing the display area. Specifically, the width W1 of the wire 3, the width W2 of the first electrode 211, and the width W3 of the second electrode 221 refer to the width in the direction perpendicular to the extension of the wire 3.

[0132] In some embodiments, the width W4 of the second opening H2 of the pixel definition layer 4 corresponding to the conductor 3 is smaller than the width W5 of the first pixel opening 401 and the width W6 of the second pixel opening 402 located on both sides of the second opening H2. This is beneficial to improving the space utilization of the display substrate and increasing the area occupied by the display area. Specifically, the width W4 of the second opening H2, the width W5 of the first pixel opening 401, and the width W6 of the second pixel opening 402 refer to the width in the extension direction perpendicular to the second opening H2.

[0133] In some embodiments, as shown in FIG5, the distance D1 between the conductor 3 and the first electrode 211 is smaller than the distance D2 between the conductor 3 and the second electrode 221. This design helps to ensure the isolation of the conductor 3 from the first sub-pixel 21. For example, it can minimize crosstalk to the second sub-pixel 22 when only the first sub-pixel 21 is lit for image display in the first display mode. Similarly, the width of the pixel delimiting layer 4 between the conductor 3 and the first electrode 211 is smaller than the width of the pixel delimiting layer 4 between the conductor 3 and the second electrode 221, and smaller than the width of the pixel delimiting layer 4 between adjacent pixel units 2.

[0134] Figure 6a is a third schematic diagram of the cross-sectional structure of the display substrate provided in the embodiment of this disclosure; Figure 6b is a fourth schematic diagram of the cross-sectional structure of the display substrate provided in the embodiment of this disclosure.

[0135] In some embodiments, the display substrate further includes a heat insulation layer. The heat insulation layer is located on the side of the conductive wire 3 opposite to the common film layer 200. The orthographic projection of the conductive wire 3 on the substrate 1 lies within the orthographic projection of the heat insulation layer on the substrate 1. For example, the heat insulation layer is disposed in contact with the conductive wire 3 to prevent the film layer on the side of the conductive wire 3 opposite to the common film layer 200 from being ablated when the conductive wire 3 is heated by electricity.

[0136] In some embodiments, as shown in Figures 6a and 6b, the heat insulation layer 5 is disposed on the side of the common film layer 200 facing the substrate 1, and the wire 3 is located between the heat insulation layer and the common film layer 200. Specifically, before fabricating the wire 3, the heat insulation layer 5 can be fabricated first, then the wire 3 can be fabricated on the side of the heat insulation layer 5 facing away from the substrate 1, and the common film layer 200 can be fabricated on the side of the wire 3 facing away from the heat insulation layer 5. When energizing the wire 3 to ablate the common film layer 200, the common film layer 200 can be ablated immediately after its fabrication, or it can be ablated after the common film layer 200 and other films located on the side of the common film layer 200 facing away from the substrate 1 are fabricated; no limitation is made here.

[0137] In some embodiments, a heat insulation layer may be disposed on the side of the common film layer 200 facing away from the substrate 1, and the conductive wire 3 is located between the heat insulation layer and the common film layer 200. Specifically, after the common film layer 200 is fabricated, the conductive wire 3 and the heat insulation layer are fabricated sequentially. After the heat insulation layer is fabricated, other film layers of the display substrate located on the side of the heat insulation layer facing away from the substrate 1 can be fabricated. After the film layers of the display substrate are fabricated, the common film layer 200 is ablated by applying current to the conductive wire 3. The heat insulation layer can prevent the conductive wire 3 from ablating the other film layers located on the side of the heat insulation layer facing away from the substrate 1.

[0138] In some embodiments, as shown in Figures 6a and 6b, the orthographic projection of the wire 3 on the substrate 1 completely coincides with the orthographic projection of the heat insulation layer 5 on the substrate 1, which can reduce the influence of the heat insulation layer on the thickness of the display substrate and is beneficial to the reduction of the thickness of the display substrate.

[0139] Figure 7 is a second top view of the display substrate provided in an embodiment of this disclosure.

[0140] In some embodiments, as shown in FIG7, the wire 3 includes an input terminal 31 and an output terminal 32. The input terminal 31 and the output terminal 32 are connected to a high potential terminal and a low potential terminal, respectively. After energization, a potential difference is formed between the input terminal 31 and the output terminal 32, forming a current flowing into the input terminal 31, passing through the wire 3, and then flowing out of the output terminal 32. According to the formula for the work done by current: P = UI, since the resistance of the wire 3 changes relatively little, the larger the potential difference U between the input terminal 31 and the output terminal 32, the larger the current I flowing through the wire 3, and therefore the greater the power P done by the current flowing through the wire 3. The smaller the resistance of the wire 3, the greater the power P done by the current flowing through the wire 3. Because the resistance of the wire 3 is very small, the input terminal 31 and the output terminal 32 are equivalent to a short circuit, resulting in a large power of the current flowing through the wire 3 doing work. The wire 3 can quickly heat up and generate high temperature, thereby ablating the common film layer in contact with it. In specific implementations, input terminal 31 and output terminal 32 are electrically connected to the positive and negative terminals of the power supply, respectively, thereby applying voltage to the conductor 3 to form current. In some embodiments, input terminal 31 and output terminal 32 can be directly connected to an external power supply. During the ablation of the common film layer, the positive and negative terminals of the power supply are directly connected to input terminal 31 and output terminal 32, respectively, thereby directly applying voltage to the conductor 3 to form current. After ablation, the power supply can be disconnected from input terminal 31 and output terminal 32 and removed, thus reducing the difficulty of routing signal lines. In some embodiments, input terminal 31 and output terminal 32 can be connected to signal lines in the display substrate, and then connected to the power supply through the signal lines; this is not limited here.

[0141] In a specific implementation, as shown in Figure 7, the display substrate includes a pixel area S1 and a non-pixel area S2. Pixel units 2 are disposed within the pixel area S1, while the non-pixel area S2 is used to house drive lines such as gate-on-array (GOA) circuits or drive chips. The input terminals 31 and 32 of the conductive wires 3 are also located in the non-pixel area S2, which avoids the input terminals 31 and 32 of the conductive wires 3 occupying the area where the pixel units 2 are located, thus increasing the display area.

[0142] Figure 8a is a third top view of the display substrate provided in the embodiment of this disclosure; Figure 8b is a fourth top view of the display substrate provided in the embodiment of this disclosure; Figure 8c is a fifth top view of the display substrate provided in the embodiment of this disclosure.

[0143] In some embodiments, the conductor 3 continuously passes through each pixel unit 2 within the pixel region, such that the first sub-pixel 21 and the second sub-pixel 22 within each pixel unit 2 are located on opposite sides of the conductor 3. For example, the display substrate only needs to provide one continuous conductor 3 to ablate the common film layer 200 within all pixel units 2 in the pixel region S1, reducing the difficulty of setting the conductor 3. Furthermore, the current flowing through the conductor 3 is the same at all points, which is beneficial for the common film layer 200 to form a first opening H1 of uniform size.

[0144] For example, as shown in Figure 8a, the multiple pixel units of the display substrate include multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203. Adjacent first pixel units 201, second pixel units 202, and third pixel units 203 form a pixel group P. The first pixel unit 201 can emit green light, the second pixel unit 202 can emit red light, and the third pixel unit 203 can emit blue light, thereby achieving the display of a color image. Specifically, the multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203 can be arranged according to an RGB pattern. Specifically, as shown in Figure 8a, the first pixel units 201, second pixel units 202, and third pixel units 203 in the same pixel group P are arranged side-by-side along the first direction x, and the multiple pixel groups P within the pixel region S1 are arranged in an array along the first direction x and the second direction y, respectively. The first direction x and the second direction y intersect. As shown in Figure 8a, the wire 3 can extend along the first direction x and pass through multiple pixel units located in the same row, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit in the row are located on both sides of the wire 3; after the wire 3 bends along the second direction y on one side of the pixel region S1, it passes through the adjacent row of pixel units again. The wire 3 continuously passes through each row of pixel units in the pixel region S1, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit in the pixel region S1 are located on both sides of the wire 3.

[0145] In a specific implementation, the conductor 3 can also pass through each column of pixel units in the pixel region S1 along the second direction y, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit in the pixel region S1 are located on both sides of the conductor 3. No limitation is made here.

[0146] As shown in Figure 8b, the display substrate comprises multiple pixel units, including multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203. Adjacent first pixel units 201, second pixel units 202, and third pixel units 203 form a pixel group P. The first pixel unit 201 emits green light, the second pixel unit 202 emits red light, and the third pixel unit 203 emits blue light, thus achieving the display of a color image. Specifically, the multiple first pixel units 201, second pixel units 202, and third pixel units 203 can be arranged in an S-Stripe pattern. Specifically, as shown in Figure 8b, the first pixel units 201 and second pixel units 202 in the same pixel group P are arranged side-by-side along the second direction y on the same side of the third pixel unit 203. Multiple pixel groups P within the pixel region S1 are arranged in an array along the first direction x and the second direction y, respectively. The first direction x and the second direction y intersect. As shown in Figure 8b, in multiple pixel groups P arranged in the same column along the second direction y, the first pixel unit 201 and the second pixel unit 202, located on the same side of the third pixel unit 203, are arranged in a column along the second direction y. The third pixel unit 203 in the multiple pixel groups P is also arranged in a column along the second direction y. The wire 3 extends along the second direction y, passing through the first pixel unit 201 and the second pixel unit 202 located in the same column, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit in the column are located on both sides of the wire 3. After the wire 3 bends along the first direction x on one side of the pixel region S1, it passes through the adjacent third pixel unit 203 located in the same column again. The wire 3 continuously passes through each column of pixel units in the pixel region S1, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit in the pixel region S1 are located on both sides of the wire 3.

[0147] As shown in Figure 8c, the multiple pixel units of the display substrate include multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203. Adjacent first pixel units 201, second pixel units 202, and third pixel units 203 form a pixel group P. The first pixel unit 201 can emit green light, the second pixel unit 202 can emit red light, and the third pixel unit 203 can emit blue light, thereby achieving the display of a color image. Specifically, the multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203 can be arranged in an S-Stripe pattern. In some embodiments, as shown in Figure 8c, the first pixel units 201 and second pixel units 202 in the same pixel group P are arranged side-by-side along a first direction x on the same side of the third pixel unit 203. Multiple pixel groups P within the pixel region S1 are arranged in an array along the first direction x and the second direction y, respectively. The first direction x and the second direction y intersect. As shown in Figure 8c, in a pixel group P, the first pixel unit 201 and the second pixel unit 202 are arranged side by side along the first direction x on the same side of the third pixel unit 203. The wire 3 includes a first branch 331 that passes through the first pixel unit 201 and a second branch 332 that passes through the second pixel unit 202. After passing through the first pixel unit 201 and the second pixel unit 202 respectively, the first branch 331 and the second branch 332 merge into a single wire to pass through the third pixel unit 203, so that in all pixel units within the pixel region S1, the first sub-pixel 21 and the second sub-pixel 22 are located on both sides of the wire 3. Using the method shown in Figure 8c, the wire 3 passes through the first pixel unit 201 and the second pixel unit 202 in parallel. This design allows the first pixel unit 201 and the second pixel unit 202 to be ablated synchronously, ensuring that the ablation degree of the first pixel unit 201 and the second pixel unit 202 is basically the same, and also saving the overall ablation time. Of course, using the method shown in Figure 8c, the annular structure formed by the wire 3 in the first pixel unit 201 and the second pixel unit 202 can also be separated between adjacent pixel units 2. For example, the wire 3 includes a first branch 351 that passes through the first pixel unit 201 and a second branch 352 that passes through the second pixel unit 202. The first branch 351 can separate the first pixel unit 201 and the third pixel unit 203, and the second branch 352 can separate the second pixel unit 202 and the third pixel unit 203.

[0148] In the embodiments shown in Figures 8a to 8c, the wire 3 is not limited to passing through pixel units located in the same row along the first direction x or passing through pixel units located in the same column along the second direction y. The wire 3 can also pass through each pixel unit in the pixel region in other ways, such as passing through each pixel unit in the pixel region along a third direction located between the first direction x and the second direction y (such as the direction where the diagonal of the array is located), which is not limited here.

[0149] In the embodiments shown in Figures 8a and 8c, taking the RGB and S-Stripe arrangements of pixel units as examples, the specific arrangement of the conductor 3 continuously penetrating each pixel unit 2 within the pixel region, so that the first sub-pixel 21 and the second sub-pixel 22 within each pixel unit 2 are located on both sides of the conductor 3, is illustrated. In specific implementations, the arrangement of pixel units is not limited to the RGB or S-Stripe arrangement. For example, pixel units can also be arranged in PenTile, Diamond, Delta, Triangular PenTile, etc. Specific arrangements for these various arrangements can be found in related technologies and will not be elaborated here. When pixel units are arranged in any of the above arrangements, the conductor 3 can be set to continuously penetrate each pixel unit 2 within the pixel region, so that the first sub-pixel 21 and the second sub-pixel 22 within each pixel unit 2 are located on both sides of the conductor 3. Specific arrangements can be found in the embodiments shown in Figures 8a and 8b and will not be elaborated here.

[0150] In the embodiments shown in Figures 8a to 8c, the multiple pixel units in the display substrate include multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203 as an example for illustration. In actual implementation, the multiple pixel units in the display substrate may include more or fewer types of pixel units. For example, the multiple pixel units in the display substrate may be pixel units that emit light of the same color, thereby achieving monochrome display, which is not limited here.

[0151] Figure 9a is a top view of the display substrate provided in the embodiment of this disclosure (sixth); Figure 9b is a top view of the display substrate provided in the embodiment of this disclosure (seventh); Figure 9c is a top view of the display substrate provided in the embodiment of this disclosure (eighth).

[0152] In some embodiments, the conductor 3 includes a first connecting portion and a second connecting portion disposed opposite to each other on both sides of the pixel region S1 and extending along a first direction; wherein the first connecting portion is connected to an input terminal and the second connecting portion is connected to an output terminal. The conductor 3 also includes a plurality of partition portions extending along a second direction and arranged along the first direction. One end of each partition portion is connected to the first connecting portion and the other end is connected to the second connecting portion. Each partition portion passes through pixel units located in the same row in the second direction, so that the first sub-pixel and the second sub-pixel in each pixel unit are located on both sides of the conductor. Since each partition portion is connected in parallel with each other through the first connecting portion and the second connecting portion, it is beneficial to reduce the internal resistance of the conductor 3 and reduce the voltage applied between the input terminal 31 and the output terminal 32 of the conductor 3 when energized. In specific implementations, since the current flowing through the first connecting portion and the second connecting portion is greater than the current flowing through a single partition portion, the first connecting portion and the second connecting portion can be set to have a larger linewidth than a single partition portion to improve the current carrying capacity of the first connecting portion and the second connecting portion.

[0153] For example, as shown in Figure 9a, the multiple pixel units of the display substrate include multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203. Adjacent first pixel units 201, second pixel units 202, and third pixel units 203 form a pixel group P. The first pixel unit 201 can emit green light, the second pixel unit 202 can emit red light, and the third pixel unit 203 can emit blue light, thereby achieving the display of a color image. Specifically, the multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203 can be arranged according to an RGB pattern. Specifically, as shown in Figure 9a, the first pixel units 201, second pixel units 202, and third pixel units 203 in the same pixel group P are arranged side-by-side along the second direction y, and the multiple pixel groups P within the pixel region S1 are arranged in an array along the first direction x and the second direction y, respectively. The first direction x and the second direction y intersect. As shown in Figure 9a, the first connecting portion 33 of the wire 3 is disposed on the first side of the pixel region S1. One end of the first connecting portion 33 is connected to the input end 31 of the wire 3, and the other end extends along the first direction x. The second connecting portion 34 of the wire 3 is disposed on the second side of the pixel region S1 opposite to the first side. One end of the second connecting portion 34 is connected to the output end 31 of the wire 3, and the other end extends along the first direction x. The wire 3 also includes a plurality of dividing portions 35 extending along the second direction y and arranged along the first direction x. As shown in Figure 9a, one end of each dividing portion 35 is connected to the first connecting portion 33, and the other end is connected to the second connecting portion 34. Each dividing portion 35 passes through pixel units located in the same row in the second direction y, so that the first sub-pixel 21 and the second sub-pixel 22 within the pixel unit are located on both sides of the wire.

[0154] In a specific implementation, the first connecting portion 33 and the second connecting portion 34 of the conductor 3 may also extend along the second direction y, and the separating portion 35 may extend along the first direction x, and the separating portion 35 may pass through the pixel units located in the same column in the first direction x, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit are located on both sides of the conductor 3. No limitation is made here.

[0155] As shown in Figure 9b, the display substrate comprises multiple pixel units, including multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203. Adjacent first pixel units 201, second pixel units 202, and third pixel units 203 form a pixel group P. The first pixel unit 201 emits green light, the second pixel unit 202 emits red light, and the third pixel unit 203 emits blue light, thus achieving the display of a color image. Specifically, the multiple first pixel units 201, second pixel units 202, and third pixel units 203 can be arranged in an S-Stripe pattern. Specifically, as shown in Figure 9b, the first pixel units 201 and second pixel units 202 in the same pixel group P are arranged side-by-side along the second direction y on the same side of the third pixel unit 203. Multiple pixel groups P within the pixel region S1 are arranged in an array along the first direction x and the second direction y, respectively. The first direction x and the second direction y intersect. As shown in Figure 9b, the first connecting portion 33 of the wire 3 is disposed on the first side of the pixel region S1. One end of the first connecting portion 33 is connected to the input end 31 of the wire 3, and the other end extends along the first direction x. The second connecting portion 34 of the wire 3 is disposed on the second side of the pixel region S1 opposite to the first side. One end of the second connecting portion 34 is connected to the output end 31 of the wire 3, and the other end extends along the first direction x. The wire 3 also includes a plurality of dividing portions 35 extending along the second direction y and arranged along the first direction x. One end of each dividing portion 35 is connected to the first connecting portion 33, and the other end is connected to the second connecting portion 34. As shown in Figure 9b, in a plurality of pixel groups P arranged in the same column along the second direction y, the first pixel unit 201 and the second pixel unit 202 disposed on the same side of the third pixel unit 203 are arranged in a column along the second direction y, and the third pixel unit 203 in the plurality of pixel groups P is arranged in a column along the second direction y. Partially separating portion 35 passes through the first pixel unit 201 and the second pixel unit 202 located in the same column in the second direction y, and the remaining partially separating portion 35 passes through the first three pixel unit 203 located in the same column in the second direction y, so that in all pixel units within the pixel region S1, the first sub-pixel 21 and the second sub-pixel 22 are located on both sides of the conductor 3.

[0156] As shown in Figure 9c, the display substrate comprises multiple pixel units, including multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203. Adjacent first pixel units 201, second pixel units 202, and third pixel units 203 form a pixel group P. The first pixel unit 201 emits green light, the second pixel unit 202 emits red light, and the third pixel unit 203 emits blue light, thus achieving the display of a color image. Specifically, the multiple first pixel units 201, second pixel units 202, and third pixel units 203 can be arranged in an S-Stripe pattern. Specifically, as shown in Figure 9c, the first pixel units 201 and second pixel units 202 in the same pixel group P are arranged side-by-side along the first direction x on the same side of the third pixel unit 203. Multiple pixel groups P within the pixel region S1 are arranged in an array along the first direction x and the second direction y, respectively. The first direction x and the second direction y intersect. As shown in Figure 9c, the first connecting portion 33 of the wire 3 is disposed on the first side of the pixel region S1. One end of the first connecting portion 33 is connected to the input terminal 31 of the wire 3, and the other end extends along the first direction x. The second connecting portion 34 of the wire 3 is disposed on the second side of the pixel region S1 opposite to the first side. One end of the second connecting portion 34 is connected to the output terminal 31 of the wire 3, and the other end extends along the first direction x. The wire 3 also includes a plurality of dividing portions 35 extending along the second direction y and arranged along the first direction x. One end of each dividing portion 35 is connected to the first connecting portion 33, and the other end is connected to the second connecting portion 34. As shown in Figure 9c, in a pixel group P, the first pixel unit 201 and the second pixel unit 202 are arranged side by side along the first direction x on the same side of the third pixel unit 203. Each dividing part 35 includes a first branch 351 that passes through the first pixel unit 201 and a second branch 352 that passes through the second pixel unit 202. After the first branch 331 and the second branch 332 pass through the first pixel unit 201 and the second pixel unit 202 respectively, they merge into a wire to pass through the third pixel unit 203, so that in all pixel units in the pixel region S1, the first sub-pixel 21 and the second sub-pixel 22 are located on both sides of the wire 3.

[0157] Using the methods shown in Figures 9a and 9b, the design of conductor 3 is easier, and it allows for simultaneous ablation of multiple columns or rows. Using the method shown in Figure 9c, it can be seen that it combines the methods shown in Figures 8c and 9a, further demonstrating the advantages of Figures 8c and 9a, such as: allowing simultaneous ablation of multiple rows, and simultaneously creating a certain degree of separation between adjacent pixel units 2.

[0158] In the embodiments shown in Figures 9a to 9c, the first connecting portion 33 and the second connecting portion 34 may both be disposed outside the pixel region S1. In some embodiments, the first connecting portion 33 and the second connecting portion 34 may both be disposed within the pixel region S1. In some embodiments, one of the first connecting portion 33 and the second connecting portion 34 may be disposed within the pixel region S1, and the other may be disposed outside the pixel region S1; this is not limited here.

[0159] In the embodiments shown in Figures 9a and 9c, the arrangement of the wire 3 in this disclosure is illustrated by examples of pixel units arranged in RGB and S-Stripe patterns, respectively. In specific implementations, the arrangement of pixel units is not limited to RGB or S-Stripe patterns. For example, pixel units can also be arranged in PenTile, Diamond, Delta, Triangular PenTile, etc. Specific arrangements for these various patterns can be found in existing technologies and will not be elaborated here. When pixel units are arranged in any of the above patterns, the wire 3 can be configured to include a first connecting portion, a second connecting portion, and multiple separating portions, with one end of each separating portion connected to the first connecting portion and the other end connected to the second connecting portion, so that the first sub-pixel 21 and the second sub-pixel 22 in each pixel unit 2 are located on both sides of the wire 3. Specific arrangements can be found in the embodiments shown in Figures 9a and 9c and will not be elaborated here.

[0160] In the embodiments shown in Figures 9a and 9c, the multiple pixel units in the display substrate include multiple first pixel units 201, multiple second units 202, and multiple third pixel units 203 as an example for illustration. In actual implementation, the multiple pixel units in the display substrate may include more or fewer types of pixel units. For example, the multiple pixel units in the display substrate may be pixel units that emit light of the same color, thereby achieving monochrome display, which is not limited here.

[0161] Figure 10a is a top view of the display substrate provided in the embodiment of this disclosure (nine); Figure 10b is a top view of the display substrate provided in the embodiment of this disclosure (tenth); Figure 10c is a cross-sectional view of the display substrate provided in the embodiment of this disclosure (fifth).

[0162] In this embodiment of the invention, since the common film layer 200 is fabricated on the entire surface using OM (Operating Machine), a portion of the common film layer 200 is located between two adjacent pixel units 2, connecting the two adjacent pixel units 2. As the resolution of the display substrate increases, the distance between adjacent pixel units 2 decreases, increasing the risk of current crosstalk between adjacent pixel units 2 due to the connected common film layer 200. In some embodiments, at least some adjacent pixel units 2 can be disposed opposite each other on both sides of the conductor 3, and the common film layer connecting adjacent pixel units 2 can be disconnected by heating the conductor 3, reducing the risk of current crosstalk between adjacent pixel units 2.

[0163] In some embodiments, as shown in FIG10a, the conductor 3 passes through multiple pixel units located in the same row and through the middle region between two adjacent rows of pixel units. As shown in FIG10c, where FIG10c is a cross-sectional view of FIG10a along section line BB, the common film layer has a first opening H1 formed by ablation of the conductor 3 at the position corresponding to the conductor 3 located between adjacent pixel units 2.

[0164] In some embodiments, as shown in FIG10b, the separator 35 extends through multiple pixel units located in the same row and through the middle region of two adjacent rows of pixel units. As shown in FIG10c, where FIG10c is a cross-sectional view of FIG10a along section line BB, the common film layer has a first opening H1 formed by ablation of the wire 3 at the position corresponding to the wire 3 located between adjacent pixel units 2.

[0165] In specific implementation, in the embodiments shown in Figures 8a-8c and 9a-9c, the wire 3 can be set according to the setting method of the wire 3 in the embodiments shown in Figures 10a and 10b, which will not be described in detail here.

[0166] In some embodiments, as shown in Figures 10a-10c, the width of the first opening H1 at the position corresponding to the wire 3 between the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 is smaller than the width of the first opening H1 at the position corresponding to the wire 3 between adjacent rows of pixel units 2. Similarly, the width of the wire 3 between the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit 2 is smaller than the width of the wire 3 between adjacent rows of pixel units 2. For example, as shown in Figure 10b, the width of the dividing portion 35 passing through the same row of pixel units is smaller than the width of the dividing portion 35 between adjacent rows of pixel units 2. Typically, the spacing between adjacent rows of pixel units 2 is usually greater than the spacing between the first sub-pixel 21 and the second sub-pixel 22 in the same pixel unit. This design helps to widen the spacing of the first opening H1 where the common film layer in the middle region of two adjacent rows of pixel units is broken, further reducing crosstalk between adjacent rows of pixel units.

[0167] Figure 11 is a sixth schematic diagram of the cross-sectional structure of the display substrate provided in the embodiments of this disclosure.

[0168] In some embodiments, the display substrate further includes a driving circuit layer 5. As shown in FIG11, the driving circuit layer 5 is located between the substrate 1 and the pixel unit. The driving circuit layer 5 includes a plurality of pixel circuits, which are electrically connected to the pixel unit and are used to drive the pixel unit to emit light for image display.

[0169] In some embodiments, within the same pixel unit, a first sub-pixel 21 is connected to a pixel circuit, and a second sub-pixel 22 is connected to a pixel circuit. The first sub-pixel 21 and the second sub-pixel 22 can be driven independently through their respective connected pixel circuits.

[0170] In some embodiments, within the same pixel unit, the first sub-pixel 21 and the second sub-pixel 22 are connected to the same pixel circuit, thereby reducing the number of pixel circuits in the driving circuit layer 5 and lowering the manufacturing difficulty. Specifically, the pixel circuit can employ a thin-film transistor (TFT) pixel circuit. A TFT pixel circuit includes multiple thin-film transistors; for example, the most basic 2T1C pixel circuit includes two thin-film transistors and one capacitor. A TFT pixel circuit can also include a larger number of thin-film transistors to form a 6T1C pixel circuit, a 7T1C pixel circuit, etc., to achieve more refined control. The specific structure of the TFT pixel circuit can be found in related technologies and will not be elaborated here. The driving circuit layer 5 also includes multiple switching thin-film transistors (SW). Specifically, the output terminal of the pixel circuit is connected to the first electrode 211 of the first sub-pixel 21, the drain of the switching thin-film transistors (SW) is connected to the second electrode 221 of the second sub-pixel 22, and the source of the switching thin-film transistors (SW) is connected to the first electrode 211 of the first sub-pixel 21. When the switching thin-film transistors (SW) are turned off, the driving signal output by the pixel circuit only drives the first sub-pixel 21 to light up for image display. When the switching thin-film transistor SW is turned on, the driving signal output by the pixel circuit can simultaneously drive the first sub-pixel 21 and the second sub-pixel 22 to light up for image display, thereby switching between the privacy mode and the sharing mode by turning the switching thin-film transistor SW on and off.

[0171] Figure 12 is an equivalent circuit diagram of the pixel circuit provided in an embodiment of this disclosure.

[0172] For example, as shown in FIG12, the first sub-pixel 21 and the second sub-pixel 22 share the same pixel circuit PXC. For example, as shown in FIG12, in the display substrate provided in this embodiment, the driving circuit layer 5 includes a switching thin-film transistor SW, the pixel circuit PXC is connected to the first sub-pixel 21, and the pixel circuit PXC is connected to the second sub-pixel 22 via the switching thin-film transistor SW. For example, as shown in FIG12, the pixel circuit PXC is connected to the first electrode 211 of the first sub-pixel 21, and the pixel circuit PXC is connected to the second electrode 221 of the second sub-pixel 22 via the switching thin-film transistor SW. In the display substrate provided in the disclosed embodiments, the specific process of switching between the privacy mode and the sharing mode by means of the switching thin-film transistor SW is as follows: when the switching thin-film transistor SW is off, the pixel circuit PXC is disconnected from the second sub-pixel 22, and the driving signal output by the pixel circuit PXC only drives the first sub-pixel 21 to light up for image display; when the switching thin-film transistor SW is on, the pixel circuit PXC is connected to the second sub-pixel 22, and the driving signal output by the pixel circuit PXC can simultaneously drive the first sub-pixel 21 and the second sub-pixel 22 to light up for image display.

[0173] As shown in Figure 12, the pixel circuit PXC includes six switching thin-film transistors (T1-T2, T4-T7), one driving thin-film transistor T3, and one storage capacitor Cst. The six switching thin-film transistors are, respectively, the data writing thin-film transistor T4, the threshold compensation thin-film transistor T2, the light emission control thin-film transistor T5, the light emission control thin-film transistor T6, the reset thin-film transistor T1, and the reset thin-film transistor T7.

[0174] As shown in Figure 12, the gates of the light-emitting control thin-film transistors T5 and T6 are both connected to the light-emitting control signal line EML. The gate of the data writing thin-film transistor T4 is connected to the scan line GT2. The gate of the reset thin-film transistor T7 is connected to the reset control signal line RST2. The gate of the threshold compensation thin-film transistor T2 is connected to the gate line GT1. The gate of the reset thin-film transistor T1 is connected to the reset control signal line RST1.

[0175] As shown in Figure 12, one end of the storage capacitor Cst is connected to the gate of the driving thin film transistor T3, and the other end of the storage capacitor Cst is connected to the power supply line PL1. One terminal of the light-emitting control thin film transistor T5 is connected to the driving thin film transistor T3, and the other terminal of the light-emitting control thin film transistor T5 is connected to the power supply line PL1.

[0176] The embodiment shown in Figure 12 uses a 7T1C pixel circuit as an example for illustration. However, the embodiments of this disclosure do not limit the structure of the pixel circuit, and a suitable pixel circuit can be selected as needed, that is, the arrangement of thin-film transistors and capacitors in the pixel circuit can be determined as needed.

[0177] In this embodiment of the invention, the display substrate further includes a thin film encapsulation (TFE) layer 6. The TFE layer 6 is located on the side of the pixel unit facing away from the substrate 1, and is used to protect the pixel unit from water and oxygen intrusion into the film layer of the pixel unit, which could lead to material oxidation and failure, preventing normal illumination. Specifically, the TFE layer 6 may include at least one film layer. For example, the TFE layer 6 may be a sandwich structure comprising a first inorganic layer, an organic layer, and a second inorganic layer stacked along a direction away from the substrate 1. Specific configurations can be found in related technologies and are not limited here.

[0178] In this embodiment, the display substrate further includes a first black matrix layer 71, an insulating material layer 8, and a second black matrix layer 72 stacked along a direction away from the substrate 1. The insulating material layer 8 can be made of organic or inorganic insulating materials. The first black matrix layer 71 and the second black matrix layer 72 can be made of black light-shielding materials, and this is not limited thereto.

[0179] In a specific implementation, the first black matrix layer 71 can be disposed on the side of the thin film encapsulation layer 6 facing away from the substrate 1. The first black matrix layer 71 has a third opening H3 corresponding to the first sub-pixel 21 and a fourth opening H4 corresponding to the second sub-pixel 22. The second black matrix layer 72 has a fifth opening H5 corresponding to the first sub-pixel 21 and a sixth opening H6 corresponding to the second sub-pixel 22. The orthographic projection of the first sub-pixel 21 on the substrate 1 at least partially overlaps with the orthographic projection of the third opening H3 on the substrate 1, the orthographic projection of the first sub-pixel 21 on the substrate 1 at least partially overlaps with the orthographic projection of the fifth opening H5 on the substrate 1, the orthographic projection of the second sub-pixel 22 on the substrate 1 at least partially overlaps with the orthographic projection of the fourth opening H4 on the substrate 1, and the orthographic projection of the second sub-pixel 22 on the substrate 1 at least partially overlaps with the orthographic projection of the sixth opening H6 on the substrate 1. The third opening H3 and the fifth opening H5 are used to transmit light emitted from the first sub-pixel 21, and the fourth opening H4 and the sixth opening H6 are used to transmit light emitted from the second sub-pixel 22.

[0180] In specific implementation, the area of ​​the orthographic projection of the fifth opening H5 onto the substrate 1 can be set to be less than or equal to the area of ​​the orthographic projection of the third opening H3 onto the substrate 1. This facilitates the blocking of large-angle light emitted from the first sub-pixel 21 by the first black matrix layer 71 and the second black matrix layer 72, reducing the viewing angle during privacy mode display and improving the privacy effect. The area of ​​the orthographic projection of the sixth opening H6 onto the substrate 1 can be set to be greater than or equal to the area of ​​the orthographic projection of the fourth opening H4 onto the substrate 1. This facilitates the diffusion of light emitted from the second sub-pixel 22, increasing the viewing angle during shared mode display and promoting screen sharing.

[0181] In specific implementation, the area of ​​the orthographic projection of the fourth opening H4 onto the substrate 1 and the area of ​​the orthographic projection of the sixth opening H6 onto the substrate 1 can be set to be larger than the area of ​​the orthographic projection of the third opening H3 onto the substrate 1, and both can be larger than the area of ​​the orthographic projection of the fifth opening H5 onto the substrate 1. This helps to reduce the viewing angle when displaying in privacy mode, improve the privacy effect, and increase the viewing angle when displaying in sharing mode, which is beneficial for sharing the display screen.

[0182] In some embodiments, as shown in FIG11, the orthographic projection of the conductor 3 on the substrate 1 at least partially falls within the orthographic projection of the first black matrix layer 71 on the substrate 1. The conductor 3 can be partially blocked by the first black matrix layer 71, thereby reducing the light reflected by the conductor 3 and improving the display effect. Furthermore, it can also reduce the area occupied by the conductor 3 in the pixel setting area, which is beneficial to improving the resolution. For example, the orthographic projection of the conductor 3 on the substrate 1 can be configured to fall entirely within the orthographic projection of the first black matrix layer 71 on the substrate 1, which is not limited here.

[0183] In some embodiments, as shown in FIG11, the orthographic projection of the conductor 3 on the substrate 1 at least partially falls within the orthographic projection of the second black matrix layer 72 on the substrate 1. The conductor 3 can be partially blocked by the second black matrix layer 72, thereby reducing the light reflected by the conductor 3 and improving the display effect. Furthermore, it can also reduce the area occupied by the conductor 3 in the pixel setting area, which is beneficial to improving the resolution. For example, the orthographic projection of the conductor 3 on the substrate 1 can be configured to fall entirely within the orthographic projection of the second black matrix layer 72 on the substrate 1, which is not limited here.

[0184] In some embodiments, the orthographic projection of the conductor 2 on the substrate 1 can partially fall within the orthographic projection of the first black matrix layer 71 on the substrate 1, while the remaining portion falls within the orthographic projection of the second black matrix layer 72 on the substrate 1. This allows both the first and second black matrix layers 71 to simultaneously block the light reflected from the conductor 3, improving the display effect. Furthermore, it reduces the area occupied by the conductor 3 in the pixel area, which is beneficial for improving resolution. For example, if the orthographic projections of the first and second black matrix layers 71 on the substrate 1 only partially overlap, the first black matrix layer 71 can partially block the conductor 3, and the portion of the conductor 3 not blocked by the first black matrix layer 71 can be blocked by the portion of the second black matrix layer 72 that does not overlap with the first black matrix layer 71. No limitation is made here.

[0185] In some embodiments, the conductor 3 may be made of a non-transparent conductive material. The conductor 3 is located between the first sub-pixel 21 and the second sub-pixel 22 within the same pixel unit, or between two adjacent pixel units. Therefore, the conductor 3 is made of a non-transparent conductive material. For example, in privacy mode, the conductor 3 can block light emitted from the first sub-pixel 21 to the area where the second sub-pixel 22 is located, avoiding light crosstalk and improving the privacy effect. For example, in sharing mode, the conductor 3 can block light emitted from one pixel unit to adjacent pixel units, reducing crosstalk between light emitted from different pixel units and improving the display effect. For example, the conductor 3 may be made of a black light-blocking material; this is not limited to this.

[0186] In some embodiments, the display substrate further includes a light filter layer 73. Specifically, as shown in FIG11, the light filter layer 73 may be entirely disposed in the fifth opening H5 and the sixth opening H6 of the second black matrix layer 72. In some embodiments, the light filter layer 73 may be entirely disposed in the third opening H3 and the fourth opening H4 of the first black matrix layer 71. In some embodiments, the light filter layer 73 may be simultaneously disposed in the third opening H3, the fourth opening H4, the fifth opening H5, and the sixth opening H6; this is not limited thereto. The light filter layer 73 may include multiple light filter sections, one of which corresponds to a first sub-pixel 21 or a second sub-pixel 22. The light filter section is used to transmit light of the same color as the light emitted from the corresponding first sub-pixel 21 or second sub-pixel 22, and to filter out light of a different color than the light emitted from the corresponding first sub-pixel 21 or second sub-pixel 22, thereby optimizing the display effect.

[0187] To clearly illustrate the main inventive features of the display substrate provided in the embodiments of this disclosure, some film layer structures of the display substrate are omitted in the accompanying drawings of the embodiments of this disclosure. The display substrate provided in the embodiments of this disclosure also includes other film layer structures not mentioned in this disclosure that are necessary to achieve specific functions. These film layer structures are widely existing in the prior art, and relevant technologies can be referred to in specific implementations, and will not be described in detail here.

[0188] This disclosure also provides a display device. The display device provided in this disclosure includes the display substrate provided in any of the above embodiments. In specific implementations, the display device provided in this disclosure has the same or similar technical effects as any of the above embodiments, and will not be described in detail here.

[0189] The display devices provided in this disclosure include, but are not limited to, OLED display devices. Specifically, the display devices provided in this disclosure can be televisions, mobile phones, tablet computers, laptops, smartwatches, digital cameras, etc., that use the display substrate provided in any of the above embodiments, and are not limited thereto.

[0190] Figure 13 is one of the flowcharts of a method for manufacturing a display substrate according to an embodiment of this disclosure.

[0191] This disclosure also provides a method for manufacturing a display substrate, as shown in FIG13. The method for manufacturing a display substrate includes the following steps:

[0192] S131: A first electrode and a second electrode spaced apart from each other are formed on one side of the substrate; the first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel;

[0193] S132: A pixel definition layer is formed on the side of the first electrode and the second electrode away from the substrate; the pixel definition layer has a first pixel opening for exposing the first electrode and a second pixel opening for exposing the second electrode;

[0194] S133: A wire is formed on the side of the pixel definition layer away from the substrate, such that the orthographic projection of at least a portion of the first pixel opening on the substrate and the orthographic projection of at least a portion of the second pixel opening on the substrate are disposed opposite to each other on both sides of the wire.

[0195] S134: Create a first sub-pixel and a second sub-pixel in the first pixel opening and the second pixel opening respectively; the first sub-pixel and the second sub-pixel include a common film layer, which covers the pixel definition layer and the wire between the first pixel opening and the second pixel opening.

[0196] S135: Apply voltage to the conductor to heat up the conductor and ablate at least a portion of the common film layer in the region overlapping with the conductor, forming a first opening.

[0197] The method for manufacturing a display substrate provided in this disclosure firstly fabricates a conductive line in the pixel definition layer in the region between at least a portion of the first pixel opening and at least a portion of the second pixel opening before forming the common film layer of the first and second sub-pixels. The first and second pixel openings on either side of the conductive line can be used to fabricate the first and second sub-pixels within the same pixel unit, respectively. Then, a common film layer is formed on the side of the conductive line away from the pixel definition layer. By heating the conductive line to ablate at least a portion of the common film layer in contact with the conductive line, at least a portion of the common film layer is broken at the position corresponding to the conductive line, forming a first opening. This effectively reduces the risk of current crosstalk between the first and second sub-pixels within the same pixel unit. For example, in privacy mode, this improves privacy protection. Furthermore, the method for manufacturing a display substrate provided in this disclosure forms the conductive line on the side of the pixel definition layer away from the substrate, avoiding the need to create openings in the pixel definition layer to expose the conductive line, simplifying the process steps, and improving the structural strength of the pixel definition layer.

[0198] In specific implementation, the specific steps of the manufacturing method of the display substrate provided in the embodiments of this disclosure can be referred to the specific structure of the display substrate provided in the embodiments of this disclosure, and will not be repeated here.

[0199] Figure 14 is a second flowchart of the method for manufacturing a display substrate according to an embodiment of this disclosure.

[0200] This disclosure also provides a method for manufacturing a display substrate, as shown in FIG14. The method for manufacturing a display substrate includes the following steps:

[0201] S141: A first electrode, a second electrode, and a wire spaced apart from each other are formed on one side of a substrate; at least a portion of the first electrode and at least a portion of the second electrode are disposed opposite to each other on both sides of the wire; the first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel;

[0202] S142: A pixel definition layer is formed on the side of the first electrode and the second electrode away from the substrate; the pixel definition layer has a first pixel opening for exposing the first electrode, a second pixel opening for exposing the second electrode, and a second opening for exposing wires; the second opening is located between the first pixel opening and the second pixel opening;

[0203] S143: A first sub-pixel and a second sub-pixel are fabricated in the first pixel opening and the second pixel opening respectively; the first sub-pixel and the second sub-pixel include a common film layer, which covers the pixel definition layer between the first pixel opening and the second pixel opening and the wires in the second opening;

[0204] S144: Apply voltage to the conductor to heat up the conductor and ablate at least a portion of the common film layer in the region overlapping with the conductor, forming a first opening.

[0205] The method for manufacturing a display substrate provided in this disclosure involves fabricating a conductive line in the region between at least a portion of the first electrode and at least a portion of the second electrode before forming a common film layer for the first and second sub-pixels. The first and second electrodes on either side of the conductive line can be used to fabricate the first and second sub-pixels within the same pixel unit, respectively. A pixel definition layer is then formed on the side of the conductive line facing away from the substrate. This pixel definition layer has a first pixel opening for exposing the first electrode, a second pixel opening for exposing the second electrode, and a second opening for exposing the conductive line. A common film layer is then formed on the side of the pixel definition layer facing away from the substrate, covering the pixel definition layer between the first and second pixel openings and the conductive line in the second opening. By heating the conductive line to ablate at least a portion of the common film layer in contact with the conductive line, at least a portion of the common film layer is broken at the position corresponding to the conductive line, forming the first opening. This effectively reduces the risk of current crosstalk between the first and second sub-pixels within the same pixel unit. For example, in privacy mode, this improves privacy protection. Furthermore, in the above-described method for manufacturing a display substrate provided in this disclosure, the conductive wires and the first and second electrodes can be fabricated in the same conductive film layer, which helps to reduce the number of film layers in the display substrate and reduce the thickness of the display substrate.

[0206] In specific implementation, the specific steps of the manufacturing method of the display substrate provided in the embodiments of this disclosure can be referred to the specific structure of the display substrate provided in the embodiments of this disclosure, and will not be repeated here.

[0207] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0208] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate; a plurality of pixel units on the substrate; the pixel units comprise a first sub-pixel and a second sub-pixel; the first sub-pixel and the second sub-pixel comprise a common film layer; a wire opposite to the wire on both sides of the wire for at least part of the pixel units, the first sub-pixel and the second sub-pixel on the substrate; at least part of the film layer in the common film layer is disconnected in the area overlapping with the wire and is spaced from the wire to form a first opening. 2.The display substrate of claim 1, wherein, The display substrate further comprises: a pixel definition layer on one side of the substrate; the pixel definition layer is provided with a first pixel opening and a second pixel opening penetrating the pixel definition layer along the thickness direction of the pixel definition layer; the common film layer is located on the side of the pixel definition layer away from the substrate and partially located between the first pixel opening and the second pixel opening; the first sub-pixel and the second sub-pixel are separated by the part of the pixel definition layer between the first pixel opening and the second pixel opening; for each pixel unit, the projection of the first pixel opening on the substrate and the projection of the second pixel opening on the substrate are located on both sides of the projection of the wire on the substrate. 3.The display substrate of claim 2, wherein, The wire is located on the side of the pixel definition layer away from the substrate. 4.The display substrate of claim 3, wherein, The wire is located between the common film layer and the pixel definition layer. 5.The display substrate of claim 2, wherein, The wire is located on the side of the pixel definition layer away from the common film layer; The pixel definition layer is further provided with a second opening; the second opening penetrates the pixel definition layer along the thickness direction of the pixel definition layer and exposes the wire; at least part of the film layer in the common film layer is disconnected at the position of the second opening to form the first opening. The display substrate further comprises a first electrode and a second electrode between the pixel definition layer and the substrate; the first electrode and the second electrode are spaced apart; the first electrode is used to form the first sub-pixel and the second electrode is used to form the second sub-pixel; 6.The display substrate of claim 5, wherein, for each pixel unit, the projection of the first electrode on the substrate and the projection of the second electrode on the substrate are located on both sides of the projection of the wire on the substrate. The wire, the first electrode and the second electrode are located in the same conductive film layer; the wire, the first electrode and the second electrode are separated by the pixel definition layer. 7.The display substrate of claim 6, wherein, The display substrate further comprises a heat insulation layer on the side of the wire away from the common film layer; the projection of the wire on the substrate is located within the projection of the heat insulation layer on the substrate.

8. The display substrate of any one of claims 1-7, wherein, The projection of the wire on the substrate and the projection of the heat insulation layer on the substrate are completely coincident. 9.The display substrate of claim 8, wherein, The wire comprises an input end and an output end; the input end and the output end are used to load voltage on the wire to form current.

10. The display substrate according to any one of claims 1 to 9, wherein The display substrate comprises a pixel area and a non-pixel area; the pixel units are located within the pixel area; the input end and the output end of the wire are located within the non-pixel area. 11.The display substrate of claim 10, wherein, ​ 12.The display substrate of claim 11, wherein, The conductive line continuously passes through each of the pixel units in the pixel region, so that the first sub-pixel and the second sub-pixel in each of the pixel units are located on two sides of the conductive line. 13.The display substrate of claim 11, wherein, The conductive line comprises a first connecting portion and a second connecting portion oppositely arranged on two sides of the pixel region and extending along a first direction; the first connecting portion is connected with the input end, and the second connecting portion is connected with the output end. The conductive line further comprises a plurality of separating portions extending along a second direction and arranged along the first direction; one end of each of the separating portions is connected with the first connecting portion, and the other end is connected with the second connecting portion; each of the separating portions passes through the pixel units located in the same row in the second direction, so that the first sub-pixel and the second sub-pixel in each of the pixel units are located on two sides of the conductive line.

14. The display substrate of any one of claims 1-13, wherein, The common film layer portion is located between two adjacent pixel units. At least part of the pixel units are oppositely arranged on two sides of the conductive line.

15. The display substrate of any one of claims 1-14, wherein, In the same pixel unit, the first sub-pixel and the second sub-pixel have the same light-emitting color.

16. The display substrate of any one of claims 1-15, wherein, The first sub-pixel and the second sub-pixel are both organic light-emitting diodes. The organic light-emitting diode comprises: A first electrode layer located on one side of the substrate; A first functional layer located on a side of the electrode layer away from the substrate; the first functional layer comprises at least one film layer; An organic light-emitting layer located on a side of the first functional layer away from the first electrode layer; A second functional layer located on a side of the organic light-emitting layer away from the first functional layer; the second functional layer comprises at least one film layer; A second electrode layer located on a side of the second functional layer away from the organic light-emitting layer; The common film layer comprises at least one film layer of all the film layers of the first functional layer, the second functional layer and the second electrode layer.

17. The display substrate of claim 16, wherein, The first functional layer comprises a hole transport layer and a hole injection layer arranged in a direction away from the organic light-emitting layer in a stacked manner; and the second functional layer comprises an electron transport layer and an electron injection layer arranged in a direction away from the organic light-emitting layer in a stacked manner.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for manufacturing a display substrate, comprising: Comprise: Forming a first electrode and a second electrode spaced apart from each other on one side of a substrate; The first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel; Forming a pixel definition layer on a side of the first electrode and the second electrode away from the substrate; The pixel definition layer is provided with a first pixel opening for exposing the first electrode and a second pixel opening for exposing the second electrode; Forming a conductive line on a side of the pixel definition layer away from the substrate, so that at least part of the first pixel opening and at least part of the second pixel opening are oppositely arranged on two sides of the conductive line. The first sub-pixel and the second sub-pixel are respectively manufactured in the first pixel opening and the second pixel opening; the first sub-pixel and the second sub-pixel comprise a common film layer, the common film layer covers the pixel definition layer and the conductive wire between the first pixel opening and the second pixel opening; A voltage is applied to the conductive wire to make the conductive wire heat and ablate at least part of the common film layer in the overlapping area with the conductive wire, to form the first opening.

20. A method for manufacturing a display substrate, comprising: Comprise: A first electrode, a second electrode and a conductive wire are formed on one side of a substrate; at least part of the first electrode and at least part of the second electrode are oppositely arranged on both sides of the conductive wire; the first electrode is used to form a first sub-pixel, and the second electrode is used to form a second sub-pixel; A pixel definition layer is formed on the side of the first electrode and the second electrode away from the substrate; The pixel definition layer is provided with a first pixel opening for exposing the first electrode, a second pixel opening for exposing the second electrode, and a second opening for exposing the conductive wire; The second opening is located between the first pixel opening and the second pixel opening; The first sub-pixel and the second sub-pixel are respectively manufactured in the first pixel opening and the second pixel opening; the first sub-pixel and the second sub-pixel comprise a common film layer, the common film layer covers the pixel definition layer and the conductive wire in the second opening between the first pixel opening and the second pixel opening; A voltage is applied to the conductive wire to make the conductive wire heat and ablate at least part of the common film layer in the overlapping area of the conductive wire, to form the first opening.

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