Display substrate and display device

Abstract

A display substrate and a display device. The display substrate has a display area and a non-display area, and comprises a base, and a driving circuit group and a virtual driving circuit group which are arranged on the base and located in the non-display area. The driving circuit group comprises at least one shift register. The virtual driving circuit group comprises at least one virtual shift register. The virtual shift register comprises a plurality of virtual active patterns and a plurality of virtual control electrodes. The shift register comprises a plurality of transistors, wherein each transistor comprises an active pattern and a control electrode. The shape of at least part of at least one virtual active pattern is the same as the shape of at least part of the active pattern of at least one transistor; the shape of at least part of at least one virtual control electrode is the same as the shape of at least part of the control electrode of at least one transistor; and the orthographic projection of at least one virtual active pattern on the substrate does not have an overlapping area with the orthographic projection of at least one virtual control electrode on the substrate.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 10, 2023, with application number 202311499769.8 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area, comprising: a substrate; and a pixel driving circuit disposed on the substrate and located in the display area, and a driving circuit group and a dummy driving circuit group located in the non-display area, wherein the pixel driving circuit is electrically connected to the driving circuit group, the driving circuit group comprising: at least one shift register, the dummy driving circuit group comprising: at least one dummy shift register, the dummy shift register comprising: a plurality of dummy active patterns and a plurality of dummy control electrodes, the shift register comprising: a plurality of transistors, each transistor comprising: an active pattern and a control electrode;

[0007] The shape of at least a portion of at least one dummy active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, the shape of at least a portion of at least one dummy control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, and there is no overlapping area between the orthographic projection of at least one of the dummy active patterns and the orthographic projection of at least one of the dummy control electrodes on the substrate.

[0008] In an exemplary embodiment, a distance between an orthographic projection of the at least one dummy active pattern on the substrate and the target dummy control electrode ranges from 0.8 micrometers to 2 micrometers;

[0009] The orthographic projection of the dummy active pattern on the substrate is adjacent to the orthographic projection of the target dummy control electrode on the substrate.

[0010] In an exemplary embodiment, the non-display area includes at least one corner area and at least one linear border area, the driving circuit group includes a plurality of driving circuits, the plurality of driving circuits are sequentially arranged in a direction close to the display area, the driving circuits include a plurality of cascaded shift registers, and the dummy driving circuit group includes a plurality of dummy driving circuits, the plurality of dummy driving circuits are sequentially arranged in a direction close to the display area, the dummy driving circuits include a plurality of cascaded dummy shift registers;

[0011] The virtual driving circuit group is at least partially located in the corner area, the driving circuit group is located in the corner area and the straight line frame area, the driving circuit group and the virtual driving circuit group are located on the first side and the second side of the display area, and the first side and the second side of the display area are arranged opposite to each other.

[0012] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one reset signal line, the pixel driving circuit including: a driving transistor and a reset transistor, the reset transistor being electrically connected to a control electrode of the driving transistor, and the reset signal line being electrically connected to the control electrode of the reset transistor; the multiple driving circuits including: a reset driving circuit, the reset driving circuit being located on one of a first side and a second side of the display area; the multiple dummy driving circuits including: a dummy reset driving circuit;

[0013] The length of the reset driving circuit along a first direction is greater than the length of the dummy reset driving circuit along the first direction. The first direction is an arrangement direction of the plurality of driving circuits.

[0014] In an exemplary embodiment, the reset driving circuit includes: a plurality of cascaded reset shift registers, and the virtual reset driving circuit includes: at least one virtual reset shift register, wherein the at least one virtual reset shift register is located between adjacent reset shift registers;

[0015] The reset shift register includes: at least one reset transistor and at least one reset capacitor; at least one virtual driving unit also includes: a plurality of virtual source and drain electrodes;

[0016] At least a portion of at least one virtual active pattern in at least one virtual reset shift register has the same shape as at least a portion of an active pattern of at least one reset transistor, at least a portion of at least one virtual control electrode in at least one virtual reset shift register has the same shape as at least a portion of a control electrode of at least one reset transistor or at least a portion of a reset capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual reset shift register has the same shape as at least a portion of at least one electrode of the first electrode and the second electrode of at least one reset transistor.

[0017] In an exemplary embodiment, the non-display area is further provided with a reset cascade signal line, a reset initial signal line, a first reset clock signal line, a second reset clock signal line, a first reset power line, two second reset power lines, and a third reset power line;

[0018] At least one of the reset initial signal line, the first reset clock signal line, the second reset clock signal line, the first reset power line, the second reset power line, the third reset power line, and the reset cascade signal line extends along a second direction, and the first direction intersects the second direction;

[0019] The orthographic projections of the reset initial signal line, the first second reset power line, the third reset power line, the first reset clock signal line, the second reset clock signal line, the first reset power line and the second second reset power line on the substrate are arranged in sequence along the direction close to the display area.

[0020] In an exemplary embodiment, the non-display area is provided with the reset cascade signal line, two second reset power lines and a third reset power line, and the reset shift register includes: an input terminal and an output terminal;

[0021] The reset cascade signal line is electrically connected to the output end of at least one stage of reset shift register and the input end of at least one stage of reset shift register, respectively. The orthographic projection of the reset cascade signal line on the substrate is between the orthographic projection of the first and second reset power lines on the substrate and the orthographic projection of the third reset power line on the substrate.

[0022] In an exemplary embodiment, the non-display area is provided with the reset cascade signal line and a first reset power line;

[0023] The virtual reset shift register is located on a side of the reset cascade signal line close to the display area, and at least one virtual source and drain electrode in the virtual reset shift register is electrically connected to the first reset power line.

[0024] In an exemplary embodiment, the present invention further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0025] The reset cascade signal line, the reset initial signal line and the two second reset power lines are located in the fourth conductive layer, and the first reset clock signal line, the second reset clock signal line, the first reset power line and the third reset power line are located in the fifth conductive layer.

[0026] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one light-emitting signal line, the pixel driving circuit including: a driving transistor and a light-emitting transistor, the light-emitting transistor being electrically connected to at least one of a first electrode and a second electrode of the driving transistor, and the light-emitting signal line being electrically connected to a control electrode of the light-emitting transistor; the multiple driving circuits including: a light-emitting driving circuit, the light-emitting driving circuit being located on the other of the first side and the second side of the display area; the multiple dummy driving circuits including: a dummy light-emitting driving circuit;

[0027] The length of the light-emitting driving circuit along the first direction is greater than or equal to the length of the virtual light-emitting driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

[0028] In an exemplary embodiment, the light emitting driving circuit includes: a plurality of cascaded light emitting shift registers, and the virtual light emitting driving circuit includes: at least one virtual light emitting shift register, and the at least one virtual light emitting shift register is located between adjacent light emitting shift registers;

[0029] The light-emitting shift register includes: at least one light-emitting transistor and at least one light-emitting capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes;

[0030] At least a portion of at least one virtual active pattern in at least one virtual light-emitting shift register has the same shape as at least a portion of the active pattern of at least one light-emitting transistor, at least a portion of at least one virtual control electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of the control electrode of at least one light-emitting transistor or at least a portion of the light-emitting capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one light-emitting transistor.

[0031] In an exemplary embodiment, the non-display area is further provided with a light emitting cascade signal line, a light emitting initial signal line, a first light emitting clock signal line, a second light emitting clock signal line, a first light emitting power line, two second light emitting power lines, and a third light emitting power line;

[0032] At least one of the light emitting initial signal line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power line, the second light emitting power line, the third light emitting power line, and the light emitting cascade signal line extends along a second direction, and the first direction intersects the second direction;

[0033] The positive projections of the initial light-emitting signal line, the first second light-emitting power line, the third light-emitting power line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line and the second first light-emitting power line on the substrate are arranged in sequence along the direction close to the display area.

[0034] In an exemplary embodiment, the non-display area is provided with the light emitting cascade signal line, two second light emitting power lines and a third light emitting power line, and the light emitting shift register includes: an input terminal and an output terminal;

[0035] The light-emitting cascade signal line is electrically connected to the output end of at least one level of light-emitting shift register and the input end of at least one level of light-emitting shift register, respectively. The orthographic projection of the light-emitting cascade signal line on the substrate is between the orthographic projection of the first and second light-emitting power lines on the substrate and the orthographic projection of the third light-emitting power line on the substrate.

[0036] In an exemplary embodiment, the non-display area is provided with the light emitting cascade signal line and the first light emitting power line;

[0037] The virtual light emitting shift register is located on a side of the light emitting cascade signal line close to the display area, and at least one virtual source and drain electrode in the virtual light emitting shift register is electrically connected to the first light emitting power line.

[0038] In an exemplary embodiment, the present invention further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0039] The light cascade signal line, the light initial signal line and the two second light power lines are located in the fourth conductive layer, and the first light clock signal line, the second light clock signal line, the first light power line and the third light power line are located in the fifth conductive layer.

[0040] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one control signal line, the pixel driving circuit includes: a driving transistor and a compensation transistor, the compensation transistor is electrically connected to the control electrode and the second electrode of the driving transistor, and the control signal line is electrically connected to the control electrode of the compensation transistor; the multiple driving circuits include: a control driving circuit, the control driving circuit is located on the first side and the second side of the display area, and the multiple dummy driving circuits include: a dummy control driving circuit;

[0041] The length of the control driving circuit along the first direction is greater than or equal to the length of the virtual control driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

[0042] In an exemplary embodiment, the control driving circuit includes: a plurality of cascaded control shift registers, and the virtual control driving circuit includes: at least one virtual control shift register, and the at least one virtual control shift register is located between adjacent control shift registers;

[0043] The control shift register includes: at least one control transistor and at least one control capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes;

[0044] At least a portion of at least one virtual active pattern in at least one virtual control shift register has the same shape as at least a portion of the active pattern of at least one control transistor, at least a portion of at least one virtual control electrode in at least one virtual control shift register has the same shape as at least a portion of the control electrode of at least one control transistor or at least a portion of the control capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual control shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one control transistor.

[0045] In an exemplary embodiment, the non-display area is further provided with a control cascade signal line, two control initial signal lines, a first control clock signal line, a second control clock signal line, three first control power lines, two second control power lines, and a third control power line;

[0046] at least one of the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the second control power line, the third control power line, and the control cascade signal line extends along a second direction, the first direction intersecting the second direction;

[0047] The first control initial signal line, the first second control power line, the second control initial signal line, the first control clock signal line, the second control clock signal line, the first first control power line, the third control power line, the second first control power line, the third first control power line and the second second control power line are arranged in sequence along the direction close to the display area.

[0048] In an exemplary embodiment, the non-display area is further provided with a control cascade signal line, two control initial signal lines and a first control clock signal line, and the control shift register includes: an input terminal and an output terminal;

[0049] The control cascade signal line is electrically connected to the output end of at least one level of control shift register and the input end of at least one level of control shift register respectively, and the positive projection of the control cascade signal line on the substrate is between the positive projection of the second control initial signal line on the substrate and the positive projection of the first control clock signal line on the substrate.

[0050] In an exemplary embodiment, the non-display area is further provided with a control cascade signal line, three first control power lines and two second control power lines; the control cascade signal line divides the area where the virtual control shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the first and second control power lines, and at least one virtual source-drain electrode located in the second area is connected to at least one first control power line.

[0051] In an exemplary embodiment, the present invention further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0052] The control cascade signal line is located in the fourth conductive layer, and the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the two second control power lines, and the third control power line are located in the fifth conductive layer.

[0053] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one scanning signal line, the pixel driving circuit includes: a driving transistor and a writing transistor, the writing transistor is electrically connected to the control electrode and the first electrode of the driving transistor, and the scanning signal line is electrically connected to the control electrode of the writing transistor; the multiple driving circuits include: a scanning driving circuit, the scanning driving circuit is located on the first side and the second side of the display area, and the multiple dummy driving circuits include: a dummy scanning driving circuit;

[0054] The length of the scan driving circuit along a first direction is greater than or equal to the length of the dummy scan driving circuit along the first direction. The first direction is an arrangement direction of the plurality of driving circuits.

[0055] In an exemplary embodiment, the scan driving circuit includes: a plurality of cascaded scan shift registers, and the virtual scan driving circuit includes: at least one virtual scan shift register, and the at least one virtual scan shift register is located between adjacent scan shift registers;

[0056] The scanning shift register includes: at least one scanning transistor and at least one scanning capacitor; at least one dummy shift register also includes: a plurality of dummy source and drain electrodes;

[0057] At least a portion of at least one virtual active pattern in at least one virtual scan shift register has the same shape as at least a portion of the active pattern of at least one scan transistor, at least a portion of at least one virtual control electrode in at least one virtual scan shift register has the same shape as at least a portion of the control electrode of at least one scan transistor or at least a portion of the scan capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual scan shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one scan transistor.

[0058] In an exemplary embodiment, the non-display area is further provided with a scan cascade signal line, a scan initial signal line, a first scan clock signal line, a second scan clock signal line, a first scan power line, and a second scan power line;

[0059] At least one of the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line, the second scan power line, and the scan cascade signal line extends along a second direction, and the first direction intersects the second direction;

[0060] The second scan power line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power line are sequentially arranged in a direction close to the display area.

[0061] In an exemplary embodiment, the non-display area is further provided with a scan cascade signal line, a scan initial signal line, and a second scan clock signal line, and the scan shift register includes: an input terminal and an output terminal;

[0062] The scan cascade signal line is electrically connected to the output end of at least one level of scan shift register and the input end of at least one level of scan shift register, respectively, and the positive projection of the scan cascade signal line on the substrate is between the positive projection of the second scan clock signal line on the substrate and the positive projection of the scan initial signal line on the substrate.

[0063] In an exemplary embodiment, the non-display area is further provided with a scan cascade signal line, a first scan power line, and a second scan power line;

[0064] The scan cascade signal line divides the area where the virtual scan shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the second scan power line, and at least one virtual source-drain electrode located in the second area is connected to the first scan power line.

[0065] In an exemplary embodiment, the present invention further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0066] The scan cascade signal line is located in the fourth conductive layer, and the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line and the second scan power line are located in the fifth conductive layer.

[0067] In an exemplary embodiment, the driving circuit group includes: a scanning driving circuit, a control driving circuit, a light emitting driving circuit, and a reset driving circuit;

[0068] The reset drive circuit, the control drive circuit, and the scan drive circuit located on the first side of the display area are sequentially arranged in a direction close to the display area, and the light emitting drive circuit, the control drive circuit, and the scan drive circuit located on the second side of the display area are sequentially arranged in a direction close to the display area;

[0069] The scan drive circuit located on the first side of the display area and the scan drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction; the control drive circuit located on the first side of the display area and the control drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction; the reset drive circuit located on the first side of the display area and the light-emitting drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, and the second direction intersects with the first direction.

[0070] In an exemplary embodiment, the driving circuit group includes: at least one transistor and at least one capacitor; the dummy driving circuit group includes: a plurality of dummy active patterns, a plurality of dummy control electrodes, and a dummy source and drain electrode; the display substrate further includes: a signal output line located in a non-display area, at least one cascade signal line, and a plurality of signal lines, the plurality of signal lines being connected to the driving circuit group and the dummy circuit group, respectively; and the signal output line being connected to the driving circuit group;

[0071] The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0072] The semiconductor layer includes at least: an active pattern of at least one transistor and at least one dummy active pattern among a plurality of dummy active patterns;

[0073] The first conductive layer at least includes: a control electrode of at least one transistor, a plate of at least one capacitor, and at least one virtual active pattern among a plurality of virtual control electrodes;

[0074] The second conductive layer includes at least: another plate of at least one capacitor;

[0075] The third conductive layer at least includes: a signal output line;

[0076] The fourth conductive layer at least includes: at least one signal line and a cascade signal line;

[0077] The fifth conductive layer at least includes: at least one signal line.

[0078] In an exemplary embodiment, further comprising: at least one initial signal line located in the non-display area;

[0079] At least one initial signal line is located on a side of at least one of the plurality of signal lines close to the display area and is located in the fifth conductive layer;

[0080] An orthographic projection of at least one initial signal line on the substrate at least partially overlaps with orthographic projections of the driving circuit group and the dummy driving circuit group on the substrate.

[0081] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0082] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0083] Summary of the Figures

[0084] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0085] FIG1 is a schematic structural diagram of a display substrate;

[0086] FIG2 shows a partial border area of ​​a display substrate;

[0087] FIG3 is a schematic diagram of a partial structure of a first side of a display area of ​​a display substrate provided by an embodiment of the present disclosure;

[0088] FIG4 is a schematic diagram of a portion of the structure of the second side of the display area of ​​the display substrate provided by an embodiment of the present disclosure;

[0089] FIG5 is a schematic diagram of a portion of the film layer in FIG3 ;

[0090] FIG6 is a schematic diagram of a portion of the film layer in FIG4 ;

[0091] FIG7A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0092] FIG7B is an operation timing diagram of the pixel driving circuit provided in FIG7A ;

[0093] FIG8A is an equivalent circuit diagram of a scan shift register provided by an exemplary embodiment;

[0094] FIG8B is a timing diagram of the scan shift register provided in FIG8A ;

[0095] FIG9A is an equivalent circuit diagram of a control shift register provided in an exemplary embodiment;

[0096] FIG9B is a timing diagram of the control shift register provided in FIG9A ;

[0097] FIG10A is an equivalent circuit diagram of a reset shift register provided by an exemplary embodiment;

[0098] FIG10B is a timing diagram of the reset shift register provided in FIG10A ;

[0099] FIG11A is an equivalent circuit diagram of a light-emitting shift register provided by an exemplary embodiment;

[0100] FIG11B is a timing diagram of the light-emitting shift register provided in FIG11A ;

[0101] FIG12A is a schematic diagram of a portion of the film layers of the reset shift register and the dummy reset shift register;

[0102] FIG12B is a second schematic diagram of a portion of the membrane layers of the reset shift register and the dummy reset shift register;

[0103] FIG13A is a schematic diagram of a portion of the film layers of a light-emitting shift register and a virtual light-emitting shift register;

[0104] FIG13B is a second schematic diagram of a portion of the film layers of the light-emitting shift register and the virtual light-emitting shift register;

[0105] FIG14A is a schematic diagram of a portion of the membrane layers of the control shift register and the dummy control shift register;

[0106] FIG14B is a second schematic diagram of a portion of the membrane layers of the control shift register and the virtual control shift register;

[0107] FIG15A is a schematic diagram of a portion of the film layers of a scanning shift register and a virtual scanning shift register;

[0108] FIG15B is a second schematic diagram of a portion of the film layers of the scanning shift register and the dummy scanning shift register;

[0109] FIG16 is a schematic diagram of a scanning shift register and a dummy scanning shift register after forming a semiconductor layer pattern;

[0110] FIG17 is a schematic diagram of a control shift register and a dummy control shift register after forming a semiconductor layer pattern;

[0111] FIG18 is a schematic diagram of a reset shift register and a dummy reset shift register after forming a semiconductor layer pattern;

[0112] FIG19 is a schematic diagram of a first conductive layer pattern in a scan shift register and a dummy scan shift register;

[0113] FIG20 is a schematic diagram of a scan shift register and a dummy scan shift register after forming a first conductive layer pattern;

[0114] FIG21 is a schematic diagram of a first conductive layer pattern in a control shift register and a dummy control shift register;

[0115] FIG22 is a schematic diagram of a control shift register and a dummy control shift register after the first conductive layer pattern;

[0116] FIG23 is a schematic diagram of forming a first conductive layer pattern of a reset shift register and a dummy reset shift register;

[0117] FIG. 24 is a schematic diagram of a reset shift register and a dummy reset shift register after forming a first conductive layer pattern.

[0118] FIG25 is a schematic diagram of a second conductive layer pattern in a scan shift register and a dummy scan shift register;

[0119] FIG26 is a schematic diagram of a scan shift register and a dummy scan shift register after forming a second conductive layer pattern;

[0120] FIG27 is a schematic diagram of the second conductive layer pattern in the control shift register and the dummy control shift register;

[0121] FIG28 is a schematic diagram of a control shift register and a dummy control shift register after forming a second conductive layer pattern;

[0122] FIG29 is a schematic diagram of a second conductive layer pattern in a reset shift register and a dummy reset shift register;

[0123] FIG30 is a schematic diagram of the reset shift register and the dummy reset shift register after forming the second conductive layer pattern;

[0124] FIG31 is a schematic diagram of a third conductive layer pattern in a control shift register and a dummy control shift register;

[0125] FIG32 is a schematic diagram of a control shift register and a dummy control shift register after forming a third conductive layer pattern;

[0126] FIG33 is a schematic diagram of a reset shift register and a dummy reset shift register after the third conductive layer pattern is formed;

[0127] FIG34 is a schematic diagram of the reset shift register and the dummy reset shift register after forming a third conductive layer pattern;

[0128] FIG35 is a schematic diagram of the scan shift register and the dummy scan shift register after forming a fourth insulating layer;

[0129] FIG36 is a schematic diagram of a control shift register and a dummy control shift register after a fourth insulating layer is formed;

[0130] FIG37 is a schematic diagram of the reset shift register and the dummy reset shift register after forming a fourth insulating layer;

[0131] FIG38 is a schematic diagram of a fourth conductive layer pattern in a scan shift register and a dummy scan shift register;

[0132] FIG39 is a schematic diagram of the scan shift register and the dummy scan shift register after forming a fourth conductive layer pattern;

[0133] FIG40 is a schematic diagram of a fourth conductive layer pattern in a control shift register and a dummy control shift register;

[0134] FIG41 is a schematic diagram of a control shift register and a dummy control shift register after forming a fourth conductive layer pattern;

[0135] FIG42 is a schematic diagram of a fourth conductive layer pattern in a reset shift register and a dummy reset shift register;

[0136] FIG43 is a schematic diagram of the reset shift register and the dummy reset shift register after forming a fourth conductive layer pattern;

[0137] FIG44 is a schematic diagram of a scanning shift register and a dummy scanning shift register after forming a flat layer;

[0138] FIG45 is a schematic diagram of a control shift register and a dummy control shift register after forming a flat layer;

[0139] FIG46 is a schematic diagram of a reset shift register and a dummy reset shift register after forming a flat layer;

[0140] FIG47 is a schematic diagram of a fifth conductive layer pattern in a scan shift register and a dummy scan shift register;

[0141] FIG48 is a schematic diagram of the scan shift register and the dummy scan shift register after forming a fifth conductive layer pattern;

[0142] FIG49 is a schematic diagram of a fifth conductive layer pattern in a control shift register and a dummy control shift register;

[0143] FIG50 is a schematic diagram of the control shift register and the dummy control shift register after forming a fifth conductive layer pattern;

[0144] FIG51 is a schematic diagram of a fifth conductive layer pattern in a reset shift register and a dummy reset shift register;

[0145] FIG52 is a schematic diagram of the reset shift register and the dummy reset shift register after the fifth conductive layer pattern is formed.

[0146] Details

[0147] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0148] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0149] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0150] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0151] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0152] In this specification, a transistor refers to a device that includes at least three terminals: a control electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0153] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0154] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0155] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0156] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0157] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0158] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0159] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0160] The display substrate uses low-temperature polysilicon (LTPS) technology, which has advantages such as high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption. At this time, the low-temperature polycrystalline oxide combination (LTPO+Oxide) technology solution came into being. Compared with LTPS technology, LTPO technology has lower leakage current and faster pixel response. The display substrate adds an extra layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed. However, compared with display products using LTPS technology, display products using LTPO technology will cause afterimages due to the bias of the threshold voltage of the driving transistor in the pixel circuit, which reduces the display effect of the display product.

[0161] To achieve display, display products are equipped with multiple gate drive circuits, matched to the pixel design of the display area. Generally, at least one gate drive circuit is installed on the left and right borders. Today, most display products have special designs such as rounded corners, and the borders of display products include straight edges and corner areas, such as mobile phones, watches, tablets, and laptops. For panel design, the gate drive circuit is generally a row scan circuit. The gate drive circuit is generally arranged in a rectangular shape. In the corner area, the multi-stage shift registers in the gate drive circuit are generally arranged in a fan-shaped manner according to the arc shape of the display area to save frame size. In this case, the number of shift registers densely packed per unit must be greater than the number of pixel rows to be connected to the shift register. Generally, the shift register closest to the pixel is selected for connection. The redundant shift registers are not deleted but replaced with virtual shift registers that are not connected to the display area. The provision of virtual shift registers can ensure the etching uniformity of the display product and avoid display unevenness caused by process differences caused by different pattern densities.

[0162] During the design process, the layout of the virtual shift register is basically the same as that of the shift register. Part of the structure of the same transistor in the virtual shift register may be connected to high-level signals and low-level signals at the same time, resulting in a short circuit problem, thereby reducing the reliability of the product.

[0163] Figure 1 is a schematic diagram of the structure of a display substrate, Figure 2 is a partial frame area of ​​the display substrate, Figure 3 is a schematic diagram of the partial structure of the first side of the display area of ​​the display substrate provided in an embodiment of the present disclosure, Figure 4 is a schematic diagram of the partial structure of the second side of the display area of ​​the display substrate provided in an embodiment of the present disclosure, Figure 5 is a schematic diagram of a portion of the film layer of Figure 3, and Figure 6 is a schematic diagram of a portion of the film layer of Figure 4. As shown in Figures 1 to 6, an embodiment of the present disclosure provides a display substrate having a display area 100 and a non-display area 200, including: a substrate, and a pixel driving circuit P disposed on the substrate and located in the display area 100, and a driving circuit group and a dummy driving circuit group located in the non-display area, the pixel driving circuit being electrically connected to the driving circuit group, the driving circuit group including: at least one shift register, the dummy driving circuit group including: at least one dummy shift register, the dummy shift register including: a plurality of dummy active patterns DA and a plurality of dummy control electrodes DG, the shift register including: a plurality of transistors, and the transistors including: active patterns and control electrodes. As shown in Figures 5 and 6, the shape of at least a portion of at least one virtual active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, the shape of at least a portion of at least one virtual control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, and there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate.

[0164] In an exemplary embodiment, as shown in FIG. 5 and FIG. 6 , a control electrode of at least one transistor in the shift register at least partially overlaps with an orthographic projection of an active pattern of the control electrode on the substrate.

[0165] In an exemplary embodiment, the shape of at least a portion of at least one dummy active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, and the shape of at least a portion of at least one dummy control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, which can ensure the etching uniformity of the display substrate and improve the display effect of the display substrate.

[0166] The present disclosure avoids the short circuit phenomenon caused by the conduction between devices connected to different signal terminals in the virtual shift register unit due to the existence of the virtual active pattern by ensuring that there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate, thereby improving the reliability of the display substrate.

[0167] In example embodiments, the display substrate may be an LTPO display substrate.

[0168] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 5T1C, 5T2C, 7T1C, or 8T1C circuit structure.

[0169] In an exemplary embodiment, FIG7A is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG7A , the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7), one capacitor C, and eight signal terminals (data signal terminal Data, control signal terminal Scan, scan signal terminal Gate, reset signal terminal Reset, emission signal terminal EM, initial signal terminal VINIT, first power terminal VDD, and second power terminal VSS). FIG7A uses 7T1C as an example for illustration.

[0170] In an exemplary embodiment, a first plate of capacitor C is connected to a first power supply terminal VDD, and a second plate of capacitor C is connected to a first node N1. A control electrode of the first transistor M1 is connected to a reset signal terminal Reset, a first electrode of the first transistor M1 is connected to an initial signal terminal VINIT, and a second electrode of the first transistor is connected to the first node N1. A control electrode of the second transistor M2 is connected to a scan signal terminal Gate, a first electrode of the second transistor M2 is connected to the first node N1, and a second electrode of the second transistor M2 is connected to a second node N2. A control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to the second node N2, and a second electrode of the third transistor M3 is connected to a third node N3. A control electrode of the fourth transistor M4 is connected to a control signal terminal Scan, a first electrode of the fourth transistor M4 is connected to a data signal terminal Data, and a second electrode of the fourth transistor M4 is connected to a third node N3. The control electrode of the fifth transistor M5 is connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor M5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor M5 is connected to the third node N3. The control electrode of the sixth transistor M6 is connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device. The control electrode of the seventh transistor M7 is connected to the control signal terminal Scan, the first electrode of the seventh transistor M7 is connected to the initial signal terminal VINIT, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the second power supply terminal VSS.

[0171] In an exemplary embodiment, the first transistor M1 may be referred to as a reset transistor, and when a valid level signal is input to the reset signal terminal Reset, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0172] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor. When a valid level signal is input to the control signal terminal Scan, the second transistor M2 is turned on to compensate for the signal of the first node N1.

[0173] In an exemplary embodiment, the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS according to a potential difference between the control electrode and the first electrode.

[0174] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor, etc., and when the scan signal terminal Gate inputs an active level signal, the fourth transistor M4 inputs a data voltage of the data signal terminal Data to the pixel driving circuit.

[0175] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light emission control transistors. When the light emission signal terminal EM inputs an active level signal, the fifth transistor M5 and the sixth transistor M6 form a driving current path between the first power supply terminal VDD and the second power supply terminal VSS to enable the light emitting device to emit light.

[0176] In an exemplary embodiment, the signal of the first power supply terminal VDD is a continuously high-level signal, and the signal of the second power supply terminal VSS is a low-level signal.

[0177] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are metal oxide transistors and are N-type transistors, and the third transistor M3 to the seventh transistor M7 are low temperature polysilicon transistors and are P-type transistors.

[0178] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are oxide transistors, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce power consumption of the pixel driving circuit.

[0179] In an exemplary embodiment, the first power supply terminal VDD is configured to continuously provide a high level signal, and the second power supply terminal VSS is configured to continuously provide a low level signal.

[0180] FIG7B is an operating timing diagram of the pixel driving circuit shown in FIG7A. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit shown in FIG7B. The pixel driving circuit in FIG7A includes seven transistors (first transistor M1 to seventh transistor M7), one capacitor C, and eight signal terminals (data signal terminal Data, control signal terminal Scan, scan signal terminal Gate, reset signal terminal Reset, emission signal terminal EM, initial signal terminal VINIT, first power terminal VDD, and second power terminal VSS).

[0181] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0182] The first phase A1 is called the reset phase. The signals at the reset signal terminal Reset, the control signal terminal Scan, and the emission signal terminal EM are all high-level signals, and the signal at the scan signal terminal Gate is a low-level signal. The signal at the reset signal terminal Reset is a high-level signal, the first transistor M1 is turned on, and the signal at the initial signal terminal VINIT is provided to the first node N1, initializing the capacitor C and clearing the original data voltage in the capacitor C. The signals at the control signal terminal Scan and the emission signal terminal EM are high-level signals, the signal at the scan signal terminal Gate is a low-level signal, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off. During this phase, the OLED does not emit light.

[0183] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signals at the control signal terminal Scan and the reset signal terminal Reset are low-level signals, the signals at the emission signal terminal EM and the scan signal terminal Gate are high-level signals, and the data signal terminal Data outputs a data voltage. During this phase, since the first node N1 is at a low-level signal, the third transistor M3 is turned on. The signal at the control signal terminal Scan is low-level, the fourth transistor M4 and the seventh transistor M7 are turned on, the signal at the scan signal terminal Gate is high-level, and the second transistor M2 is turned on. The second transistor M2 and the fourth transistor M4 are turned on, causing the data voltage output by the data signal terminal Data to be supplied to the first node N1 via the third node N3, the turned-on third transistor M3, the second node N2, and the turned-on second transistor M2. The difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd - |Vth|, where Vd is the data voltage output by the data signal terminal Data and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on, so that the initial voltage at the initialization signal terminal VINIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal at the reset signal terminal Reset is a low-level signal, and the first transistor M1 is turned off. The signal at the emission signal terminal EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0184] In the third phase A3, referred to as the light-emitting phase, the signals at the control signal terminal Scan, the scanning signal terminal Gate, the light-emitting signal terminal EM, and the reset signal terminal Reset are all low-level signals. The signal at the light-emitting signal terminal EM is low-level, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the OLED to emit light.

[0185] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0186] I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*(Vdd-Vd)2

[0187] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0188] In an exemplary embodiment, as shown in Figures 5 and 6, the distance L between the orthographic projection of at least one virtual active pattern on the substrate and the target virtual control electrode ranges from 0.8 microns to 2 microns; the orthographic projection of the virtual active pattern on the substrate is adjacent to the orthographic projection of the target virtual control electrode on the substrate.

[0189] In an exemplary embodiment, as shown in FIG2 , the non-display area 200 includes: at least one corner area CR and at least one linear border area LR; the driving circuit group includes: a plurality of driving circuits, the plurality of driving circuits being arranged sequentially in a direction approaching the display area, and the driving circuits including: a plurality of cascaded shift registers. The dummy driving circuit group includes: a plurality of dummy driving circuits, the plurality of dummy driving circuits being arranged sequentially in a direction approaching the display area, and the dummy driving circuits including: a plurality of cascaded dummy shift registers. The dummy driving circuit group is at least partially located in the corner area CR, the driving circuit group is located in the corner area CR and the linear border area LR, and the driving circuit group and the dummy driving circuit group are located on a first side and a second side of the display area, with the first side and the second side of the display area being arranged relative to each other.

[0190] In an exemplary embodiment, the boundary of the corner area may be in an arc shape, which is not limited in the present disclosure.

[0191] In an exemplary embodiment, as shown in FIG1 , the display area 100 is further provided with a reset signal line RL, a light-emission signal line EL, a control signal line SL, and a scan signal line GL. The reset signal line RL is electrically connected to the control electrode of the reset transistor, the light-emission signal line EL is electrically connected to the control electrode of the light-emission transistor, the control signal line SL is electrically connected to the control electrode of the compensation transistor, and the scan signal line GL is electrically connected to the control electrode of the write transistor. The multiple drive circuits include: a reset drive circuit, a scan drive circuit, a control drive circuit, and a light-emission drive circuit. The multiple dummy drive circuits include: a dummy reset drive circuit, a dummy scan drive circuit, a dummy control drive circuit, and a dummy light-emission drive circuit.

[0192] In an exemplary embodiment, a dummy reset driver circuit and a reset driver circuit are located on a first side of the display area; a dummy scan driver circuit, a dummy control driver circuit, a scan driver circuit, and a control driver circuit are located on a first side and a second side of the display area; and a dummy light driver circuit and a light driver circuit are located on a second side of the display area. The control driver circuits located on the first and second sides of the display area are symmetrically arranged relative to a midline of the display area extending along a second direction D2. The scan driver circuits located on the first and second sides of the display area are symmetrically arranged relative to a midline of the display area extending along the second direction D2. The reset driver circuit located on the first side of the display area and the light driver circuit located on the second side of the display area are symmetrically arranged relative to a midline of the display area extending along the second direction D2.

[0193] In an exemplary embodiment, the reset driving circuit, the control driving circuit, and the scan driving circuit located at the first side of the display area are sequentially arranged in a direction approaching the display area.

[0194] In an exemplary embodiment, the dummy reset driving circuit, the dummy control driving circuit, and the dummy scan driving circuit located at the first side of the display area are sequentially arranged in a direction approaching the display area.

[0195] In an exemplary embodiment, the light emitting driving circuit, the control driving circuit, and the scan driving circuit located at the second side of the display area are sequentially arranged in a direction approaching the display area.

[0196] In an exemplary embodiment, the dummy light emitting driving circuit, the dummy control driving circuit, and the dummy scanning driving circuit located at the second side of the display area are sequentially arranged in a direction approaching the display area.

[0197] In an exemplary embodiment, the display substrate may further include a timing controller and a source driving circuit. The timing controller and the source driving circuit may be located in the non-display area.

[0198] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the source driver circuit to the source driver circuit, can provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit to the scan driver circuit, can provide clock signals, control start signals, etc. suitable for the specifications of the control driver circuit to the control driver circuit, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver circuit to the light-emitting driver circuit.

[0199] In an exemplary embodiment, the source driver circuit may generate data voltages to be supplied to the data signal lines DL1, DL2, DL3, ..., and DLN using the grayscale values ​​and control signals received from the timing controller. For example, the source driver circuit may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines DL1 to DLN in units of pixel rows.

[0200] In an exemplary embodiment, the scan driver circuit may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver circuit may sequentially provide a scan signal having an on-level pulse to the scan signal line. For example, the scan driver circuit may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal.

[0201] In an exemplary embodiment, the control drive circuit may generate a control signal to be provided to the control signal line by receiving a clock signal, a control start signal, etc. from a timing controller. For example, the control drive circuit may sequentially provide a control signal having an on-level pulse to the control signal line. For example, the control drive circuit may be configured in the form of a shift register and may generate the control signal by sequentially transmitting the control start signal provided in the form of an on-level pulse to the next stage circuit under the control of the clock signal.

[0202] In an exemplary embodiment, the light-emitting driver circuit may generate an emission signal to be provided to the light-emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver circuit may sequentially provide emission signals having an off-level pulse to the light-emitting signal line. For example, the light-emitting driver circuit may be configured as a shift register and may generate the light-emitting signal by sequentially transmitting the emission stop signal provided in the form of an off-level pulse to the next-stage circuit under the control of a clock signal.

[0203] In an exemplary embodiment, the reset driver circuit may generate a transmission signal to be provided to the reset signal line by receiving a clock signal, a transmission stop signal, etc. from a timing controller. For example, the reset driver circuit may sequentially provide a transmission signal having an off-level pulse to the reset signal line. For example, the reset driver circuit may be configured in the form of a shift register and may generate the reset signal by sequentially transmitting the reset stop signal provided in the form of an off-level pulse to the next stage circuit under the control of the clock signal.

[0204] In an exemplary embodiment, as shown in Figures 3 and 4, the reset drive circuit includes multiple cascaded reset shift registers (R-GOAs), the scan drive circuit includes multiple cascaded scan shift registers (P-GOAs), the control drive circuit includes multiple cascaded control shift registers (N-GOAs), and the light drive circuit includes multiple cascaded light shift registers (E-GOAs). At least one reset shift register stage is connected to at least one reset signal line, at least one scan shift register stage is connected to at least one scan signal line, at least one control shift register stage is connected to at least one control signal line, and at least one light shift register stage is connected to at least one light signal line. The at least one shift register located on the first side of the display area includes at least one reset shift register stage, at least one control shift register stage, and at least one scan shift register stage. Figure 3 illustrates an example in which the at least one shift register located on the first side of the display area includes a single reset shift register, a single control shift register, and two scan shift register stages. The at least one shift register located on the second side of the display area includes at least one light shift register stage, at least one control shift register stage, and at least one scan shift register stage. FIG4 illustrates an example in which the at least one shift register located at the second side of the display area includes a one-stage light-emitting shift register, a one-stage control shift register, and a two-stage scanning shift register.

[0205] In an exemplary embodiment, as shown in Figures 3 and 4, a virtual reset drive circuit includes multiple cascaded virtual reset shift registers DR-GOA, a virtual scan drive circuit includes multiple cascaded virtual scan shift registers DP-GOA, a virtual control drive circuit includes multiple cascaded virtual control shift registers DN-GOA, and a virtual light-emitting drive circuit includes multiple cascaded virtual light-emitting shift registers DE-GOA. At least one virtual reset shift register is connected to at least one virtual reset signal line, at least one virtual scan shift register is connected to at least one virtual scan signal line, at least one virtual control shift register is connected to at least one virtual control signal line, and at least one virtual light-emitting shift register is connected to at least one virtual light-emitting signal line. At least one virtual shift register located on the first side of the display area includes at least one virtual reset shift register, at least one virtual control shift register, and at least one virtual scan shift register. Figure 3 illustrates an example in which the at least one virtual shift register located on the first side of the display area includes a single virtual reset shift register, a single virtual control shift register, and two virtual scan shift registers. The at least one virtual shift register located on the second side of the display area includes: at least one virtual light-emitting shift register, at least one virtual control shift register, and at least one virtual scan shift register. FIG4 illustrates an example in which the at least one virtual shift register located on the second side of the display area includes: a one-stage virtual light-emitting shift register, a one-stage virtual control shift register, and two-stage virtual scan shift registers.

[0206] In an exemplary embodiment, the circuit structure of the reset shift register R-GOA, the scanning shift register P-GOA, the control shift register N-GOA and the light emitting shift register E-GOA can be 8T2C, 10T3C, 12T3C, 13T3C, 16T3C or 16T4C, and the present disclosure does not impose any limitation on this.

[0207] Figure 8A is an equivalent circuit diagram of a scan shift register according to an exemplary embodiment. As shown in Figure 8A , the scan shift register includes first through eighth scan transistors PT1 through PT8, and first and second scan capacitors PC1 and PC2. Figure 8A illustrates the circuit structure of an 8T2C scan shift register as an example.

[0208] In an exemplary embodiment, a control electrode of the first scanning transistor PT1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first scanning transistor PT1 is electrically connected to the input terminal PIN, and a second electrode of the first scanning transistor PT1 is electrically connected to the first node N1; a control electrode of the second scanning transistor PT2 is electrically connected to the first node N1, a first electrode of the second scanning transistor PT2 is electrically connected to the first clock signal terminal CK, and a second electrode of the second scanning transistor PT2 is electrically connected to the second node N2; a control electrode of the third scanning transistor PT3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third scanning transistor PT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third scanning transistor PT3 is electrically connected to the second node N2; a control electrode of the fourth scanning transistor PT4 is electrically connected to the second node N2, and a fourth scanning transistor PT4 is electrically connected to the second node N2. The first electrode of the scanning transistor PT6 is electrically connected to the first power supply terminal VGH, the second electrode of the fourth scanning transistor PT4 is electrically connected to the output terminal POUT; the control electrode of the fifth scanning transistor PT5 is electrically connected to the third node N3, the first electrode of the fifth scanning transistor PT5 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fifth scanning transistor PT5 is electrically connected to the output terminal POUT; the control electrode of the sixth scanning transistor PT6 is electrically connected to the second node N2, the first electrode of the sixth scanning transistor PT6 is electrically connected to the first power supply terminal VGH, the second electrode of the sixth scanning transistor PT6 is electrically connected to the first electrode of the seventh scanning transistor PT7; the control electrode of the seventh scanning transistor PT7 is electrically connected to the second clock signal terminal CK2 The terminal PCK2 is electrically connected, the second electrode of the seventh scanning transistor PT7 is electrically connected to the first node N1; the control electrode of the eighth scanning transistor PT8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth scanning transistor PT8 is electrically connected to the first node N1, and the second electrode of the eighth scanning transistor PT8 is electrically connected to the third node N3; the first plate PC11 of the first scanning capacitor PC1 is electrically connected to the first power supply terminal VGH, and the second plate PC12 of the first scanning capacitor PC1 is electrically connected to the second node N2; the first plate PC21 of the second scanning capacitor PC2 is electrically connected to the output terminal POUT, and the second plate PC22 of the second scanning capacitor PC2 is electrically connected to the third node N3.

[0209] In an exemplary embodiment, the first to eighth scanning transistors PT1 to PT8 may be P-type transistors or may be N-type transistors.

[0210] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal.

[0211] FIG8B is a timing diagram of the scan shift register provided in FIG8A. Taking the first scan transistor PT1 to the eighth scan transistor PT8 as P-type transistors as an example, as shown in FIG8B, the operation process of the scan shift register provided by an exemplary embodiment includes the following stages:

[0212] During input phase B1, the signals at the first clock signal terminal CK1 and the input terminal PIN are low-level signals, while the signal at the second clock signal terminal CK2 is high-level. Since the signal at the first clock signal terminal CK1 is low-level, the first scan transistor PT1 is turned on, and the signal at the input terminal PIN is transmitted to the first node N1 via the first scan transistor PT1. Since the signal at the eighth scan transistor PT8 receives the low-level signal from the second power supply terminal VGL, the eighth scan transistor PT8 is turned on. The voltage level at the third node N3 causes the fifth scan transistor PT5 to turn on, and the signal at the second clock signal terminal CK2 is transmitted to the output terminal POUT via the fifth scan transistor PT5. That is, during input phase D1, the signal at the second clock signal terminal CK2 is high-level at the output terminal POUT. Furthermore, since the signal at the first clock signal terminal CK1 is low-level, the third scan transistor PT3 is turned on, and the low-level signal from the second power supply terminal VGL is transmitted to the second node N2 via the third scan transistor PT3. At this time, the fourth scan transistor PT4 and the sixth scan transistor PT6 are both turned on. Since the signal at the second clock signal terminal PCK2 is high-level, the seventh scan transistor PT7 is turned off.

[0213] During output phase B2, the signal at the first clock signal terminal CK1 is high, the signal at the second clock signal terminal CK2 is low, and the signal at the input terminal PIN is high. The fifth scan transistor PT5 is turned on, and the signal at the second clock signal terminal CK2 is transmitted through the fifth scan transistor PT5 as the signal at the output terminal POUT. During output phase D2, the voltage level at the end of the second scan capacitor PC2 connected to the output terminal OUT changes to the voltage level at the second power supply terminal VGL. Due to the bootstrap effect of the second scan capacitor PC2, the eighth scan transistor PT8 is turned off, allowing the fifth scan transistor PT5 to turn on more effectively, and the signal at the output terminal POUT becomes low. Furthermore, the signal at the first clock signal terminal CK1 is high, turning off both the first scan transistor PT1 and the third scan transistor PT3. The second scan transistor PT2 is turned on, and the high-level signal at the first clock signal terminal CK1 is transmitted to the second node N2 via the second scan transistor PT2. Consequently, the fourth scan transistor PT4 and the sixth scan transistor PT6 are both turned off. Because the signal at the second clock signal terminal CK2 is low, the seventh scan transistor PT7 is turned on.

[0214] During buffering phase B3, the signals at both the first clock signal terminal CK1 and the second clock signal terminal CK2 are high-level signals, the signal at the input terminal PIN is high-level, the fifth scanning transistor PT5 is turned on, and the second clock signal terminal CK2 is output as the output signal POUT via the fifth scanning transistor PT5. Due to the bootstrap effect of the second scanning capacitor C2, the voltage of the signal at the first node N1 increases. Furthermore, the signal at the first clock signal terminal CK1 is high-level, causing the first scanning transistor PT1 and the third scanning transistor PT3 to be turned off. The eighth scanning transistor PT8 is turned on, and the second scanning transistor PT2 is turned on. The high-level signal at the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor PT2, thereby turning off the fourth scanning transistor PT4 and the sixth scanning transistor PT6. Because the signal at the second clock signal terminal CK2 is high-level, the seventh scanning transistor PT7 is turned off.

[0215] In the first sub-phase B41 of the stable phase B4, the signal at the first clock signal terminal CK1 is a low-level signal, while the signals at the second clock signal terminal CK2 and the input terminal PIN are high-level signals. Since the signal at the first clock signal terminal CK1 is a low-level signal, the first scan transistor PT1 is turned on, and the signal at the input terminal PIN is transmitted to the first node N1 via the first scan transistor PT1. The second scan transistor PT2 is turned off. Since the eighth scan transistor PT8 is turned on, the fifth scan transistor PT5 is turned off. Since the signal at the first clock signal terminal CK1 is a low-level signal, the third scan transistor PT3 is turned on, and the fourth and sixth scan transistors PT4 and PT6 are both turned on. The high-level signal at the first power supply terminal VGH is transmitted to the output terminal POUT via the fourth scan transistor PT4, resulting in a high-level signal at the output terminal POUT.

[0216] In the second sub-phase t42 of the stable phase t4, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal PIN is a high-level signal. The fifth scanning transistor PT5 and the second scanning transistor PT2 are both turned off. The signal at the first clock signal terminal PCK1 is a high-level signal, thereby turning off the first scanning transistor PT1 and the third scanning transistor PT3. Due to the holding effect of the first scanning capacitor PC1, the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned on, and the high-level signal is transmitted to the output terminal POUT via the fourth scanning transistor PT4. That is, the signal at the output terminal POUT is a high-level signal.

[0217] In the second sub-stage t42, since the signal at the second clock signal terminal CK2 is a low-level signal, the seventh scanning transistor PT7 is turned on, so that the high-level signal is transmitted to the third node N3 and the first node N1 via the sixth scanning transistor PT6 and the seventh scanning transistor PT7, so that the signals at the third node N3 and the first node N1 remain high-level signals.

[0218] In the third sub-phase t43, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high-level signals, and the signal at the input terminal PIN is also high-level. The fifth scanning transistor PT5 and the second scanning transistor PT2 are turned off. The signal at the first clock signal terminal CK1 is high-level, so the first scanning transistor PT1 and the third scanning transistor PT3 are both turned off, and the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned on. The high-level signal is transmitted to the output terminal POUT via the fourth scanning transistor PT4, that is, the signal at the output terminal POUT is also high-level.

[0219] In an exemplary embodiment, as shown in FIG3 and FIG4 , the display substrate may further include: a scan initialization signal line PSTV, a first scan clock signal line PCK1, a second scan clock signal line PCK2, a first scan power supply line PVGH, a second scan power supply line PVGL, and a scan cascade signal line PCL extending along a second direction D2. The input terminal of the first-stage scan shift register is electrically connected to the scan initialization signal line PSTV, the scan cascade signal line PCL is electrically connected to the output terminal of the i-th stage scan shift register and the input terminal of the (i+1)-th stage scan shift register; the first clock signal terminal of the i-th stage scan shift register is electrically connected to the first scan clock signal line PCK1, and the second clock signal terminal is electrically connected to the second scan clock signal line PCK2; the first clock signal terminal of the i+1-th stage scan shift register is electrically connected to the second scan clock signal line PCK2, and the second clock signal terminal is electrically connected to the first scan clock signal line PCK1; the first power terminal of the i-th stage scan shift register is electrically connected to the first scan power supply line PVGH, and the second power terminal of the i-th stage scan shift register is electrically connected to the second scan power supply line PVGL.

[0220] Figure 9A is an equivalent circuit diagram of a control shift register provided in an exemplary embodiment. As shown in Figure 9A , in this exemplary embodiment, the control shift register may include first through sixteenth control transistors NT1 through NT16 and first through fourth control capacitors NC1 through NC4. Each of the first through fourth control capacitors NC1 through NC4 includes a first plate and a second plate. Figure 9A illustrates a control shift register with a 16T3C circuit structure as an example.

[0221] As shown in FIG9A , the control electrode of the first control transistor NT1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first control transistor NT1 is electrically connected to the signal input terminal NIN, and the second electrode of the first control transistor NT1 is electrically connected to the fourth node N4; the control electrode of the second control transistor NT2 is electrically connected to the fourth node N4, the first electrode of the second control transistor NT2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second control transistor NT2 is electrically connected to the fifth node N5; the control electrode of the third control transistor NT3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third control transistor NT3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third control transistor NT3 is electrically connected to the fifth node N5. The control electrode of the fourth control transistor NT4 is electrically connected to the sixth node N6, the first electrode of the fourth control transistor NT4 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fourth control transistor NT4 is electrically connected to the seventh node N7; the control electrode of the fifth control transistor NT5 is electrically connected to the fifth node N5, the first electrode of the fifth control transistor NT5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth control transistor NT5 is electrically connected to the seventh node N7; the control electrode of the sixth control transistor NT6 is electrically connected to the ninth node N9, the first electrode of the sixth control transistor NT6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth control transistor NT6 is electrically connected to the eighth node N8 The control electrode of the seventh control transistor NT7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh control transistor NT7 is electrically connected to the eighth node N8, and the second electrode of the seventh control transistor NT7 is electrically connected to the first node N1; the control electrode of the eighth control transistor NT8 is electrically connected to the fourth node N4, the first electrode of the eighth control transistor NT8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth control transistor NT8 is electrically connected to the first node N1; the control electrode of the ninth control transistor NT9 is electrically connected to the first node N1, the first electrode of the ninth control transistor NT9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth control transistor NT9 is electrically connected to the output terminal NOUT; the tenth control transistor A control electrode of the transistor NT10 is electrically connected to the second node N2, a first electrode of the tenth control transistor NT10 is electrically connected to the second power supply terminal VGL, and a second electrode of the tenth control transistor NT10 is electrically connected to the output terminal NOUT; a control electrode of the eleventh control transistor NT11 is electrically connected to the second power supply terminal VGL, a first electrode of the eleventh control transistor NT11 is electrically connected to the fifth node N5, and a second electrode of the eleventh control transistor NT11 is electrically connected to the ninth node N9; a control electrode of the twelfth control transistor NT12 is electrically connected to the second power supply terminal VGL, a first electrode of the twelfth control transistor NT12 is electrically connected to the fourth node N4, and a second electrode of the twelfth control transistor NT12 is electrically connected to the second node N2;A control electrode of the thirteenth control transistor NT13 is electrically connected to the third power supply terminal VCX, a first electrode of the thirteenth control transistor NT13 is electrically connected to the first power supply terminal VGH, and a second electrode of the thirteenth control transistor NT13 is electrically connected to the fourth node N4; a control electrode of the fourteenth control transistor NT14 is electrically connected to the first clock signal terminal CK1, a first electrode of the fourteenth control transistor NT14 is electrically connected to the signal input terminal NIN, and a second electrode of the fourteenth control transistor NT14 is electrically connected to the tenth node N10; a control electrode of the fifteenth control transistor NT15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth control transistor NT15 is electrically connected to the tenth node N10, and a second electrode of the fifteenth control transistor NT15 is electrically connected to the sixth node N6. A control electrode of a sixteenth control transistor NT16 is electrically connected to a sixth node N6, a first electrode of the sixteenth control transistor NT16 is electrically connected to a sixth node N6, and a second electrode of the sixteenth control transistor NT16 is electrically connected to a second node N2. A first plate NC11 of the first control capacitor NC1 is electrically connected to a ninth node N9, and a second plate NC12 of the first control capacitor NC1 is electrically connected to an eighth node N8. A first plate NC21 of the second control capacitor NC2 is electrically connected to the first node N1, and a second plate NC22 of the second control capacitor NC2 is electrically connected to the first power supply terminal VGH. A first plate C31 of the third control capacitor NC3 is electrically connected to a sixth node N6, and a second plate NC32 of the third control capacitor NC3 is electrically connected to a seventh node N7.

[0222] In an exemplary embodiment, the second clock signal terminal CK2 is a low-level signal during the power-on initialization phase to prevent the ninth control transistor NT9 and the tenth control transistor NT10 of the last reset shift register from being simultaneously turned on due to a delay in the output signal. Alternatively, the second clock signal terminal CK2 is a low-level signal during the abnormal shutdown phase to prevent the ninth control transistor NT9 and the tenth control transistor NT10 from being simultaneously turned on. The second clock signal terminal CK2 continuously provides a high-level signal during the normal display phase, i.e., during the normal display phase, the thirteenth control transistor NT13 is continuously turned off.

[0223] FIG9B is a timing diagram of the control shift register provided in FIG9A. FIG9B takes the first control transistor NT1 to the sixteenth control transistor NT16 as an example of P-type control transistors. As shown in FIG9B , the operation process of the control shift register may include the following stages:

[0224] In the first phase C1, the signals at the signal input terminal NIN and the second clock signal terminal CK2 are high-level signals, and the signal at the first clock signal terminal CK1 is low-level. The signal at the first clock signal terminal CK1 is low-level, and the first control transistor NT1, the third control transistor NT3, and the twelfth control transistor NT12 are turned on. The turned-on first control transistor NT1 transmits the high-level signal at the signal input terminal NIN to the fourth node N4, and the signal at the fourth node N4 is a high-level signal. The turned-on twelfth control transistor NT12 transmits the high-level signal at the fourth node N4 to the second node N2. The turned-on fourteenth control transistor NT14 transmits the high-level signal at the signal input terminal NIN to the tenth node N10, and the signal at the tenth node N10 is a high-level signal. The turned-on fifteenth control transistor NT15 transmits the high-level signal at the tenth node N10 to the sixth node N6. The second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, the tenth control transistor NT10, and the sixteenth control transistor NT16 are turned off. In addition, the conductive third control transistor NT3 transmits the low-level signal from the second power supply terminal VGL to the fifth node N5, resulting in a low-level signal. The conductive eleventh control transistor NT11 transmits the low-level signal from the fifth node N5 to the ninth node N9, resulting in a low-level signal. The fifth control transistor NT5 and the sixth control transistor NT6 are conductive. Although the signal from the second clock signal terminal CK2 is a high-level signal, the seventh control transistor NT7 is disconnected, so the signal from the first node N1 is not pulled high and remains a low-level signal. The ninth control transistor NT9 is disconnected, and the signal from the output terminal NOUT remains at the previous low level. In the first phase C1, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal from the output terminal NOUT remains at the previous low level.

[0225] In the second phase C2, the signal at the second clock signal terminal CK2 is low, while the signals at the signal input terminal NIN and the first clock signal terminal CK1 are high. The signal at the second clock signal terminal CK2 is low, turning on the seventh control transistor NT7. The signal at the first clock signal terminal CK1 is high, turning off the first control transistor NT1 and the third control transistor NT3. Under the action of the third control capacitor NC3, the fourth node N4, the second node N2, the sixth node N6, and the tenth node N10 can continue to maintain the high-level signals from the previous phase. Under the action of the first control capacitor NC1, the fifth node N5 and the ninth node N9 can continue to maintain the low-level signals from the previous phase, turning on the fifth control transistor NT5 and the sixth control transistor NT6. The second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, and the tenth control transistor NT10 are turned off. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the conductive sixth control transistor NT6 and the seventh control transistor NT7, the ninth control transistor NT9 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the output terminal NOUT through the conductive ninth control transistor NT9. Therefore, in this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the output terminal NOUT is a high-level signal.

[0226] In the third phase C3, the signal at the first clock signal terminal CK1 is a low-level signal, and the signals at the signal input terminal NIN and the second clock signal terminal CK2 are high-level signals. The signal at the second clock signal terminal CK2 is a high-level signal, and the seventh control transistor NT7 is turned off. Under the action of the second control capacitor NC2, the first node N1 maintains the low-level signal of the previous phase. The ninth control transistor NT remains on, and the high-level signal at the first power supply terminal VGH is transmitted to the output terminal NOUT through the turned-on ninth control transistor NT9. The signal of the first clock signal terminal CK1 is a low-level signal, the first control transistor NT1, the third control transistor NT3 and the twelfth control transistor NT12 are turned on, the turned-on first control transistor NT1 transmits the high-level signal of the signal input terminal NIN to the fourth node N4, and the signal of the fourth node N4 is a high-level signal, the turned-on twelfth control transistor NT12 transmits the high-level signal of the fourth node N4 to the second node N2, the turned-on fourteenth control transistor NT14 transmits the high-level signal of the signal input terminal NIN to the tenth node N10, and the signal of the tenth node N10 is a high-level signal, the turned-on fifteenth control transistor NT15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, the tenth control transistor NT10 and the sixteenth control transistor NT16 are disconnected. In addition, the conductive third control transistor NT3 transmits the low-level signal of the second power supply terminal VGL to the fifth node N5, and the signal of the fifth node N5 is a low-level signal. The conductive eleventh control transistor NT11 transmits the low-level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low-level signal. The fifth control transistor NT5 and the sixth control transistor NT6 are turned on. In this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the output terminal NOUT is a high-level signal.

[0227] In the fourth phase C4, the signals at the signal input terminal NIN and the second clock signal terminal CK2 are low-level signals, and the signal at the first clock signal terminal CK1 is high-level. The signal at the first clock signal terminal CK1 is high-level, and the first control transistor NT1 and the third control transistor NT3 are turned off. The signal at the second clock signal terminal CK2 is low-level, and the seventh control transistor NT7 is turned on. Due to the storage function of the third control capacitor NC3, the signals at the fourth node N4, the second node N2, the sixth node N6, and the tenth node N10 remain high-level signals from the previous phase. The second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, and the tenth control transistor NT10 are turned off. Due to the storage function of the first control capacitor NC1, the ninth node N9 continues to maintain the low-level signal from the previous phase, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. In addition, the low-level signal at the second clock signal terminal CK2 is transmitted to the first node N1 via the conductive sixth control transistor NT6 and the conductive seventh control transistor NT7. The high-level signal at the first power supply terminal VGH is transmitted to the output terminal NOUT via the conductive ninth control transistor NT9. The signal at the output terminal NOUT remains high. In this stage, the first node N1 is a high-level signal, the second node N2 is a low-level signal, and the output terminal NOUT is a high-level signal.

[0228] In the fifth phase C5, the signal at the second clock signal terminal CK2 is a high-level signal, and the signals at the signal input terminal NIN and the first clock signal terminal CK1 are low-level signals. The signal at the first clock signal terminal CK1 is a low-level signal, and the first control transistor NT1, the third control transistor NT3, and the fourteenth control transistor NT14 are turned on. The signal at the second clock signal terminal CK2 is a high-level signal, and the seventh control transistor NT7 is turned off. The first control transistor NT1 is turned on and transmits the low-level signal from the signal input terminal NIN to the fourth node N4, which becomes a low-level signal. The twelfth control transistor NT12 is turned on and transmits the low-level signal from the fourth node N4 to the first node N1, which changes the signal from the first node N1 to a low-level signal. The fourteenth control transistor NT14 is turned on and transmits the low-level signal from the signal input terminal NIN to the tenth node N10, which becomes a low-level signal. The fifteenth control transistor NT15 is turned on and transmits the low-level signal from the tenth node N10 to the sixth node N6, which becomes a low-level signal. The second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, and the tenth control transistor NT10 are turned on. The second control transistor NT2 is turned on and transmits the low-level signal from the first clock signal terminal CK1 to the fifth node N5, which becomes a low-level signal. Therefore, the fifth node N5 and the ninth node N9 continue to maintain the low-level signals from the previous stage, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. The signal at the second clock signal terminal CK2 is high, and the seventh control transistor NT7 is off. Furthermore, the high signal at the first power supply terminal VGH is transmitted to the first node N1 via the conductive eighth control transistor NT8, and the ninth control transistor NT9 is off. The low signal at the second power supply terminal VGL is transmitted to the output terminal NOUT via the conductive tenth control transistor NT10, causing the signal at the output terminal NOUT to become low. In this phase, the first node N1 is high, the second node N2 is low, and the output terminal NOUT is low.

[0229] In an exemplary embodiment, as shown in Figures 3 and 4, the display substrate may further include: two control initial signal lines NSTV extending along the second direction D2, a first control clock signal line NCK1, a second control clock signal line NCK2, three first control power lines NVGH, two second control power lines NVGL, a third control power line NVCX and a control cascade signal line NCL. Among them, the input end of the first-level control shift register is electrically connected to the control initial signal line NSTV, and the control cascade signal line NCL is electrically connected to the output end of the i-th level control shift register and the input end of the i+1-th level control shift register; the first clock signal end of the i-th level control shift register is electrically connected to the first control clock signal line NCK1, the second clock signal end is electrically connected to the second control clock signal line NCK2, the first clock signal end of the i+1-th level control shift register is electrically connected to the second control clock signal line NCK2, the second clock signal end is electrically connected to the first control clock signal line NCK1, the first power supply end of the i-th level control shift register is electrically connected to the first control power supply line NVGH, the second power supply end of the i-th level control shift register is electrically connected to the second control power supply line NVGL, and the third power supply end of the i-th level control shift register is electrically connected to the third control power supply line NVCX.

[0230] Figure 10A is an equivalent circuit diagram of a reset shift register according to an exemplary embodiment. As shown in Figure 10A , in this exemplary embodiment, the reset shift register includes first through thirteenth reset transistors RT1 through RT13 and first through third reset capacitors RC1 through RC3. Figure 10A illustrates the circuit structure of a reset shift register 13T3C as an example.

[0231] In an exemplary embodiment, a control electrode of the first reset transistor RT1 is electrically connected to the second clock signal terminal CK2, a first electrode of the first reset transistor RT1 is electrically connected to the input terminal RIN, and a second electrode of the first reset transistor RT1 is electrically connected to the first node N1. A control electrode of the second reset transistor RT2 is electrically connected to the first node N1, a first electrode of the second reset transistor RT2 is electrically connected to the second clock signal terminal CK2, and a second electrode of the second reset transistor RT2 is electrically connected to the second node N2. A control electrode of the third reset transistor RT3 is electrically connected to the second clock signal terminal CK2, a first electrode of the third reset transistor RT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third reset transistor RT3 is electrically connected to the second node N2. A control electrode of the fourth reset transistor RT4 is electrically connected to the third node N3, a first electrode of the fourth reset transistor RT4 is electrically connected to the first clock signal terminal CK1, and a second electrode of the fourth reset transistor RT4 is electrically connected to the fifth node N5. A control electrode of the fifth reset transistor RT5 is electrically connected to the fourth node N4, a first electrode of the fifth reset transistor RT5 is electrically connected to the fifth node N5, and a second electrode of the fifth reset transistor RT5 is electrically connected to the first power supply terminal VGH. A control electrode of the sixth reset transistor RT6 is electrically connected to the fourth node N4, a first electrode of the sixth reset transistor RT6 is electrically connected to the first clock signal terminal CK1, and a second electrode of the sixth reset transistor RT6 is electrically connected to the sixth node N6. A control electrode of the seventh reset transistor RT7 is electrically connected to the first clock signal terminal CK1, a first electrode of the seventh reset transistor RT7 is electrically connected to the sixth node N6, and a second electrode of the seventh reset transistor RT7 is electrically connected to the seventh node N7. A control electrode of the eighth reset transistor RT8 is electrically connected to the first node N1, a first electrode of the eighth reset transistor RT8 is electrically connected to the first power supply terminal VGH, and a second electrode of the eighth reset transistor RT8 is electrically connected to the seventh node N7. A control electrode of the ninth reset transistor RT9 is electrically connected to the seventh node N7, a first electrode of the ninth reset transistor RT9 is electrically connected to the first power supply terminal VGH, and a second electrode of the ninth reset transistor RT9 is electrically connected to the output terminal ROUT. A control electrode of the tenth reset transistor RT10 is electrically connected to the third node N3, a first electrode of the tenth reset transistor RT10 is electrically connected to the second power supply terminal VGL, and a second electrode of the tenth reset transistor RT10 is electrically connected to the output terminal ROUT. A control electrode of the eleventh reset transistor RT11 is electrically connected to the second power supply terminal VGL, a first electrode of the eleventh reset transistor RT11 is electrically connected to the second node N2, and a second electrode of the eleventh reset transistor RT11 is electrically connected to the fourth node N4. A control electrode of the twelfth reset transistor RT12 is electrically connected to the second power supply terminal VGL, a first electrode of the twelfth reset transistor RT12 is electrically connected to the first node N1, and a second electrode of the twelfth reset transistor RT12 is electrically connected to the third node N3.A control electrode of the thirteenth reset transistor RT13 is electrically connected to the second clock signal terminal CK2, a first electrode of the thirteenth reset transistor RT13 is electrically connected to the first node N1, and a second electrode of the thirteenth reset transistor RT13 is electrically connected to the first power supply terminal VGH. A first plate RC11 of the first reset capacitor RC1 is electrically connected to the fourth node N4, and a second plate RC12 of the first reset capacitor RC1 is electrically connected to the sixth node N6. A first plate RC21 of the second reset capacitor RC2 is electrically connected to the seventh node N7, and a second plate RC22 of the second reset capacitor RC2 is electrically connected to the first power supply terminal VGH. A first plate RC31 of the third reset capacitor RC3 is electrically connected to the third node N3, and a second plate RC32 of the third reset capacitor RC3 is electrically connected to the fifth node N5.

[0232] In example embodiments, the first to thirteenth reset transistors RT1 to RT13 may be P-type transistors or may be N-type transistors.

[0233] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal and the second power supply terminal VGL continuously provides a low level signal. Since the second power supply terminal VGL continuously provides a low level signal, the eleventh reset transistor RT11 and the twelfth reset transistor RT12 are continuously turned on.

[0234] In an exemplary embodiment, the second clock signal terminal CK2 is a low-level signal during the power-on initialization phase to prevent the ninth reset transistor RT9 and the tenth reset transistor RT10 of the last reset shift register from being simultaneously turned on due to a delay in the output signal. Alternatively, the second clock signal terminal CK2 is a low-level signal during the abnormal shutdown phase to prevent the ninth reset transistor RT9 and the tenth reset transistor RT10 from being simultaneously turned on. The second clock signal terminal CK2 continuously provides a high-level signal during the normal display phase, i.e., during the normal display phase, the thirteenth reset transistor RT13 is continuously turned off.

[0235] FIG10B is a timing diagram of the reset shift register provided in FIG10A. FIG10B takes the first reset transistor RT1 to the thirteenth reset transistor RT13 as P-type transistors as an example, and the operation process of the reset shift register provided by an exemplary embodiment includes the following stages:

[0236] In the first phase D1, the signal at the first clock signal terminal CK1 is a high-level signal, and the signal at the second clock signal terminal CK2 is a low-level signal. The signal at the second clock signal terminal CK2 is a low-level signal. The first reset transistor RT1, the third reset transistor RT3, and the twelfth reset transistor RT12 are turned on. The turned-on first reset transistor RT1 transmits the high-level signal at the input terminal RIN to the first node N1, thereby changing the level of the first node N1 to a high-level signal. The turned-on twelfth reset transistor RT12 transmits the high-level signal at the first node N1 to the third node N2. The second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8, and the tenth reset transistor RT10 are turned off. In addition, the turned-on third reset transistor RT3 transmits the low-level signal from the third power supply terminal VGL to the second node N2, thereby changing the level of the second node N2 to a low level. The turned-on eleventh reset transistor RT11 transmits the low-level signal from the second node N2 to the fourth node N4, thereby changing the level of the fourth node N4 to a low level. The fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. The signal at the first clock signal terminal CK1 is high, and the seventh reset transistor RT7 is turned off. Furthermore, the third reset capacitor RC3 turns off the ninth reset transistor RT9. During the first phase P1, since both the ninth reset transistor RT9 and the tenth reset transistor RT10 are turned off, the signal at the output terminal ROUT remains at the previous low level.

[0237] In the second stage D2, the first clock signal terminal CK1 is a low-level signal, and the signal of the second clock signal terminal CK2 is a high-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, and the seventh reset transistor RT7 is turned on. The signal of the second clock signal terminal CK2 is a high-level signal, and the first reset transistor RT1 and the third reset transistor RT3 are turned off. Under the action of the third reset capacitor RC3, the first node N1 and the third node N3 can continue to maintain the high-level signal of the previous stage. Under the action of the first reset capacitor RC1, the fourth node N4 can continue to maintain the low level of the previous stage, so the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. The second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned off. In addition, the low-level signal of the first clock signal terminal CK1 is transmitted to the seventh node N7 through the turned-on sixth reset transistor RT6 and the seventh reset transistor RT7, and the ninth reset transistor RT9 is turned on. The turned-on ninth reset transistor RT9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal ROUT is a high-level signal. In addition,

[0238] In the third phase D3, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the first clock signal terminal CK1 is a high-level signal. The signal at the first clock signal terminal CK1 is a high-level signal, and the seventh reset transistor RT7 is turned off. The second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8, and the tenth reset transistor RT10 are turned off. The signal at the second clock signal terminal CK2 is a low-level signal, and the first reset transistor RT1 and the third reset transistor RT3 are turned on. Under the action of the second reset capacitor RC3, the ninth reset transistor RT9 remains on. The turned-on ninth reset transistor RT9 outputs the high-level signal from the first power supply terminal VGH, so the signal at the output terminal ROUT remains a high-level signal.

[0239] In the fourth phase D4, the signal at the first clock signal terminal CK1 is low, and the signal at the second clock signal terminal CK2 is high. The signal at the second clock signal terminal CK2 is high, turning off the first reset transistor RT1 and the third reset transistor RT3. The signal at the first clock signal terminal CK1 is low, turning on the seventh reset transistor RT7. Due to the storage function of the third reset capacitor RC3, the levels at the first node N1 and the third node N3 remain high from the previous phase, turning off the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8, and the tenth reset transistor RT10. Due to the storage function of the first reset capacitor RC1, the fourth node N4 continues to maintain the low level from the previous phase, turning on the fifth reset transistor RT5 and the sixth reset transistor RT6. Furthermore, the low level signal at the first clock signal terminal CK1 is transmitted to the seventh node N7 via the turned-on sixth reset transistor RT6 and the seventh reset transistor RT7. The turned-on ninth reset transistor RT9 outputs the high level signal from the first power supply terminal VGH, so the signal at the output terminal ROUT remains high.

[0240] In the fifth phase D5, the signal at the first clock signal terminal CK1 is a high-level signal, and the signal at the second clock signal terminal CK2 is a low-level signal. The signal at the second clock signal terminal CK2 is a low-level signal, turning on the first reset transistor RT1 and the third reset transistor RT3. The signal at the first clock signal terminal CK1 is a high-level signal, and the seventh reset transistor RT7 is turned off. The turned-on first reset transistor RT1 transmits the low-level signal at the input terminal RIN to the first node N1, thereby changing the level of the first node N1 to a low level. The turned-on twelfth reset transistor RT12 transmits the low-level signal at the first node N1 to the third node N3, thereby changing the level of the third node N3 to a low level. The second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8, and the tenth reset transistor RT10 are turned on. The turned-on second reset transistor RT2 transmits the low-level signal from the second clock signal terminal CK2 to the second node N2, thereby further lowering the level of the second node N2. Therefore, the second node N2 and the fourth node N4 continue to maintain the low level from the previous stage, thereby turning on the fifth reset transistor RT5 and the sixth reset transistor RT6. The signal from the first clock signal terminal CK1 is a high-level signal, and the seventh reset transistor RT7 is turned off. Furthermore, the turned-on eighth reset transistor RT8 transmits the high-level signal from the first power supply terminal VGH to the seventh node N7, and the ninth reset transistor RT9 is turned off. The turned-on tenth reset transistor RT10 outputs the low-level signal from the second power supply terminal VGL, so the signal at the output terminal ROUT becomes low.

[0241] In an exemplary embodiment, as shown in Figures 3 and 4, the display substrate may further include: a reset initial signal line RSTV extending along the second direction D2, a first reset clock signal line RCK1, a second reset clock signal line RCK2, a first reset power line RVGH, two second reset power lines RVGL, a third reset power line RVCX and a reset cascade signal line RCL. Among them, the input end of the first-level reset shift register is electrically connected to the reset initial signal line RSTV, the reset cascade signal line RCL is electrically connected to the output end of the i-th level reset shift register and the input end of the i+1-th level reset shift register; the first clock signal end of the i-th level reset shift register is electrically connected to the first reset clock signal line RCK1, the second clock signal end is electrically connected to the second reset clock signal line RCK2, the first clock signal end of the i+1-th level reset shift register is electrically connected to the second reset clock signal line RCK2, the second clock signal end is electrically connected to the first reset clock signal line RCK1, the first power supply end of the i-th level reset shift register is electrically connected to the first reset power supply line RVGH, the second power supply end of the i-th level reset shift register is electrically connected to the second reset power supply line RVGL, and the third power supply end of the i-th level reset shift register is electrically connected to the third reset power supply line RVCX.

[0242] Figure 11A is an equivalent circuit diagram of a light-emitting shift register provided by an exemplary embodiment. As shown in Figure 11A , in this exemplary embodiment, the light-emitting shift register includes first to thirteenth light-emitting transistors ET1 to ET13 and first to third light-emitting capacitors EC1 to EC3. Figure 11A illustrates the circuit structure of a light-emitting shift register using the 13T3C structure as an example. The circuit structure of the light-emitting shift register is identical to that of the reset register and will not be further described in this disclosure.

[0243] Figure 11B is a timing diagram of the light emitting shift register provided in Figure 11 A. The operation process of the light emitting shift register from the first stage E1 to the fifth stage E5 is the same as the operation process of the reset shift register, and will not be described in detail herein.

[0244] In an exemplary embodiment, as shown in FIG. 3 and FIG. 4 , the length of the reset driving circuit along a first direction D1 is greater than the length of the dummy reset driving circuit along the first direction D1 , where the first direction is the arrangement direction of the plurality of driving circuits.

[0245] In an exemplary embodiment, at least one dummy reset shift register is located between adjacent reset shift registers.

[0246] Figure 12A is a partial film layer schematic diagram (I) of a reset shift register and a dummy reset shift register, and Figure 12B is a partial film layer schematic diagram (II) of a reset shift register and a dummy reset shift register. As shown in Figures 12A and 12B, the reset shift register includes: at least one reset transistor and at least one reset capacitor; the at least one dummy driving unit also includes: a plurality of dummy source and drain electrodes. At least a portion of at least one dummy active pattern in the at least one dummy reset shift register has the same shape as at least a portion of the active pattern of the at least one reset transistor; at least a portion of at least one dummy control electrode in the at least one dummy reset shift register has the same shape as at least a portion of the control electrode of the at least one reset transistor or at least a portion of the reset capacitor; and at least a portion of at least one dummy source and drain electrode in the at least one dummy reset shift register has the same shape as at least a portion of at least one of the first and second electrodes of the at least one reset transistor.

[0247] In an exemplary embodiment, as shown in FIG12A , at least one dummy reset register includes first to twenty-first dummy active patterns DRA1 to DRA21 and first to eighth dummy control electrodes DRG11 to DRG18. The at least one reset register includes active patterns RT1-1 and control electrodes RT1-2 of a first reset transistor to active patterns RT13-1 and control electrodes RT13-2 of a thirteenth reset transistor. The first dummy active pattern DRA1 has the same shape as a portion of the active pattern RT6-1 of the sixth reset transistor. The second dummy active pattern DRA2 has the same shape as a portion of the active pattern RT2-1 of the second reset transistor. The third dummy active pattern DRA3 has the same shape as a portion of the active pattern RT6-1 of the sixth reset transistor. The fourth dummy active pattern DRA4 has the same shape as a portion of the active pattern RT7-1 of the seventh reset transistor. The fifth dummy active pattern DRA5 has the same shape as a portion of the active pattern RT2-1 of the second reset transistor. The sixth dummy active pattern DRA6 has the same shape as a portion of the active pattern RT8-1 of the eighth reset transistor. The seventh dummy active pattern DRA7 has the same shape as a portion of the active pattern RT13-1 of the thirteenth reset transistor. The eighth dummy active pattern DRA8 has the same shape as a portion of the active pattern RT5-1 of the fifth reset transistor. The ninth dummy active pattern DRA9 has the same shape as a portion of the active pattern RT11-1 of the eleventh reset transistor and a portion of the active pattern RT12-1 of the twelfth reset transistor. The tenth dummy active pattern DRA10 has the same shape as a portion of the active pattern RT12-1 of the twelfth reset transistor. The eleventh dummy active pattern DRA11 has the same shape as a portion of the active pattern RT11-1 of the eleventh reset transistor. The twelfth dummy active pattern DRA10 has the same shape as a portion of the active pattern RT4-1 of the fourth reset transistor. The shape of any of the thirteenth to twenty-first dummy active patterns DRA13 to DRA21 is identical to the shape of the active pattern of the ninth reset transistor and the portion of the integrated structure of the tenth reset transistor. The shape of the first dummy control electrode DRG11 is identical to the shape of the portion of the integrated structure of the control electrode RT1-2 of the first reset transistor and the control electrode RT3-2 of the third reset transistor. The shape of the second dummy control electrode DRG12 is identical to the portion of the integrated structure of the control electrode RT6-2 of the sixth reset transistor and the first electrode plate RC11 of the first reset capacitor. The shape of the second dummy control electrode DRG12 is identical to the shape of the portion of the integrated structure of the control electrode RT2-2 of the second reset transistor. The shape of the third dummy control electrode DRG13 is identical to the shape of the portion of the control electrode RT7-2 of the seventh reset transistor.The shape of the fourth dummy control electrode DRG14 is identical to the portion of the control electrode RT2-2 of the second reset transistor. The shape of the fifth dummy control electrode DRG52 is identical to the portion of the control electrode RT8-2 of the eighth reset transistor. The shape of the sixth dummy control electrode DRG62 is identical to the portion of the control electrode RT13-2 of the thirteenth reset transistor. The shape of the seventh dummy control electrode DRG17 is identical to the portion of the integrated structure of the control electrode RT11-2 of the eleventh reset transistor and the control electrode RT12-2 of the twelfth reset transistor. The shape of the seventh dummy control electrode DRG17 is identical to the portion of the control electrode RT5-2 of the fifth reset transistor. The shape of the seventh dummy control electrode DRG17 is identical to the portion of the integrated structure of the control electrode RT9-2 of the ninth reset transistor and the first plate RC21 of the second reset capacitor. The shape of the seventh dummy control electrode DRG17 is identical to the portion of the integrated structure of the control electrode RT4-2 of the fourth transistor, the control electrode RT10-2 of the tenth reset transistor, and the first plate RC31 of the third reset capacitor.

[0248] In an exemplary embodiment, as shown in FIG12B , at least one dummy reset register includes: first to ninth dummy active patterns DRS9. The first dummy source-drain electrode DRS1 has the same shape as the first electrode RT1-3 of the first reset transistor, the same shape as the second electrode RT6-4 of the sixth reset transistor and the first electrode RT7-3 of the seventh reset transistor, the same shape as the first electrode RT5-3 of the fifth reset transistor, the first electrode RT8-3 of the eighth reset transistor, the first electrode RT9-3 of the ninth reset transistor, and the first electrode RT13-3 of the thirteenth reset transistor, the same shape as the first electrode RT7-7 of the seventh reset transistor and the first electrode RT8-4 of the eighth reset transistor, and the same shape as the second electrode RT13-4 of the thirteenth reset transistor. The second dummy source-drain electrode DRS2 has the same shape as the second electrode RT11-4 of the eleventh reset transistor. The shape of a portion of the second dummy source-drain electrode DRS2 is the same as the shape of a portion of the integrated structure of the second electrode RT2-4 of the second reset transistor, the second electrode RT3-4 of the third reset transistor, and the first electrode RT11-3 of the eleventh reset transistor. The shape of a portion of the third dummy source-drain electrode DRS3 is the same as the shape of a portion of the integrated structure of the first electrode RT4-3 of the fourth reset transistor and the first electrode RT6-3 of the sixth reset transistor. The shape of a portion of the fourth dummy source-drain electrode DRS4 is the same as the shape of a portion of the integrated structure of the second electrode RT4-4 of the fourth reset transistor and the second electrode RT5-4 of the fifth reset transistor. The shape of a portion of any source-drain electrode from the fifth dummy source-drain electrode DRS5 to the ninth dummy source-drain electrode DRS is the same as the shape of a portion of the second electrode RT10-4 of the tenth reset transistor.

[0249] In an exemplary embodiment, as shown in FIG. 3 and FIG. 12B , the orthographic projection of the reset cascade signal line RCL on the substrate is between the orthographic projection of the first second reset power line RVGL and the orthographic projection of the third reset power line RVCX on the substrate.

[0250] In an exemplary embodiment, as shown in FIG3 and FIG12B , the dummy reset shift register is located on a side of the reset cascade signal line RCL close to the display area, and at least one dummy source and drain electrode in the dummy reset shift register is electrically connected to the first reset power line RVGH.

[0251] In an exemplary embodiment, as shown in Figures 3 and 12B, it also includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; the reset cascade signal line RCL, the reset initial signal line RSTV and the two second reset power lines RVGL are located in the fourth conductive layer, and the first reset clock signal line RCK1, the second reset clock signal line RCK2, the first reset power line RVGH and the third reset power line RVCX are located in the fifth conductive layer.

[0252] In an exemplary embodiment, as shown in FIG. 4 , the length of the light emitting driving circuit along the first direction D1 is greater than or equal to the length of the dummy light emitting driving circuit along the first direction D1 , where the first direction is the arrangement direction of the plurality of driving circuits.

[0253] FIG13A is a partial film layer schematic diagram (I) of a light-emitting shift register and a dummy light-emitting shift register, and FIG13B is a partial film layer schematic diagram (II) of a light-emitting shift register and a dummy light-emitting shift register. As shown in FIG13A and FIG13B , a light-emitting driving circuit includes: a plurality of cascaded light-emitting shift registers; a dummy light-emitting driving circuit includes: at least one dummy light-emitting shift register, the at least one dummy light-emitting shift register being located between adjacent light-emitting shift registers; the light-emitting shift register includes: at least one light-emitting transistor and at least one light-emitting capacitor; the at least one dummy shift register further includes: a plurality of dummy source-drain electrodes; at least a portion of at least one dummy active pattern in the at least one dummy light-emitting shift register has the same shape as at least a portion of an active pattern of at least one light-emitting transistor; at least a portion of at least one dummy control electrode in the at least one dummy light-emitting shift register has the same shape as at least a portion of a control electrode of at least one light-emitting transistor or at least a portion of a light-emitting capacitor; and at least a portion of at least one dummy source-drain electrode in the at least one dummy light-emitting shift register has the same shape as at least a portion of at least one of the first and second electrodes of at least one light-emitting transistor.

[0254] In an exemplary embodiment, as shown in FIG13A , at least one dummy light-emitting register includes first to twenty-first dummy active patterns DEA1 to DEA21 and first to eighth dummy gate electrodes DEG11 to DEG18. The at least one light-emitting register includes active patterns ET1-1 and gate electrodes ET1-2 of a first light-emitting transistor, and active patterns ET13-1 and gate electrodes ET13-2 of a thirteenth light-emitting transistor. The first dummy active pattern DEA1 has the same shape as a portion of the active pattern ET6-1 of the sixth light-emitting transistor. The second dummy active pattern DEA2 has the same shape as a portion of the active pattern ET2-1 of the second light-emitting transistor. The third dummy active pattern DEA3 has the same shape as a portion of the active pattern ET6-1 of the sixth light-emitting transistor. The fourth dummy active pattern DEA4 has the same shape as a portion of the active pattern ET7-1 of the seventh light-emitting transistor. The fifth dummy active pattern DEA5 has the same shape as a portion of the active pattern ET2-1 of the second light-emitting transistor. The sixth dummy active pattern DEA6 has the same shape as a portion of the active pattern ET8-1 of the eighth light-emitting transistor. The seventh dummy active pattern DEA7 has the same shape as a portion of the active pattern ET13-1 of the thirteenth light-emitting transistor. The eighth dummy active pattern DEA8 has the same shape as a portion of the active pattern ET5-1 of the fifth light-emitting transistor. The ninth dummy active pattern DEA9 has the same shape as a portion of the active pattern ET11-1 of the eleventh light-emitting transistor and the active pattern ET12-1 of the twelfth light-emitting transistor. The tenth dummy active pattern DEA10 has the same shape as a portion of the active pattern ET12-1 of the twelfth light-emitting transistor. The eleventh dummy active pattern DEA11 has the same shape as a portion of the active pattern ET11-1 of the eleventh light-emitting transistor. The twelfth dummy active pattern DEA10 has the same shape as a portion of the active pattern ET4-1 of the fourth light-emitting transistor. The shape of any active pattern from the thirteenth to twenty-first dummy active patterns DEA13 to DEA21 is identical to the shape of the active pattern of the ninth light-emitting transistor and the portion of the integrated structure of the tenth light-emitting transistor. The shape of the first dummy control electrode DEG11 is identical to the shape of the portion of the integrated structure of the control electrode ET1-2 of the first light-emitting transistor and the control electrode ET3-2 of the third light-emitting transistor. The shape of the second dummy control electrode DEG12 is identical to the portion of the integrated structure of the control electrode ET6-2 of the sixth light-emitting transistor and the first electrode plate EC11 of the first light-emitting capacitor. The shape of the second dummy control electrode DEG12 is identical to the shape of the portion of the integrated structure of the control electrode ET2-2 of the second light-emitting transistor. The shape of the third dummy control electrode DEG13 is identical to the shape of the portion of the control electrode ET7-2 of the seventh light-emitting transistor.The shape of the fourth virtual control electrode DEG14 is identical to the partial shape of the control electrode ET2-2 of the second light-emitting transistor. The shape of the fifth virtual control electrode DEG52 is identical to the partial shape of the control electrode ET8-2 of the eighth light-emitting transistor. The shape of the sixth virtual control electrode DEG62 is identical to the partial shape of the control electrode ET13-2 of the thirteenth light-emitting transistor. The shape of the seventh virtual control electrode DEG17 is identical to the partial shape of the integrated structure of the control electrode ET11-2 of the eleventh light-emitting transistor and the control electrode ET12-2 of the twelfth light-emitting transistor. The shape of the seventh virtual control electrode DEG17 is identical to the partial shape of the control electrode ET5-2 of the fifth light-emitting transistor. The shape of the seventh virtual control electrode DEG17 is identical to the partial shape of the integrated structure of the control electrode ET9-2 of the ninth light-emitting transistor and the first electrode plate EC21 of the second light-emitting capacitor. The shape of the seventh virtual control electrode DEG17 is identical to the partial shape of the integrated structure of the control electrode ET4-2 of the fourth transistor, the control electrode ET10-2 of the tenth light-emitting transistor, and the first electrode plate EC31 of the third light-emitting capacitor.

[0255] In an exemplary embodiment, as shown in FIG13B , at least one dummy light-emitting register includes: first to ninth dummy active patterns DES9. The first dummy source-drain electrode DES1 has the same shape as the first electrode ET1-3 of the first light-emitting transistor, the same shape as the second electrode ET6-4 of the sixth light-emitting transistor and the first electrode ET7-3 of the seventh light-emitting transistor, the same shape as the first electrode ET5-3 of the fifth light-emitting transistor, the first electrode ET8-3 of the eighth light-emitting transistor, the first electrode ET9-3 of the ninth light-emitting transistor, and the first electrode ET13-3 of the thirteenth light-emitting transistor, the same shape as the first electrode ET7-7 of the seventh light-emitting transistor and the first electrode ET8-4 of the eighth light-emitting transistor, the same shape as the second electrode ET13-4 of the thirteenth light-emitting transistor, and the same shape as the second electrode ET11-4 of the eleventh light-emitting transistor. The shape of a portion of the second dummy source-drain electrode DES2 is identical to the shape of a portion of the integrated structure of the second electrode ET2-4 of the second light-emitting transistor, the second electrode ET3-4 of the third light-emitting transistor, and the first electrode ET11-3 of the eleventh light-emitting transistor. The shape of a portion of the third dummy source-drain electrode DES3 is identical to the shape of a portion of the integrated structure of the first electrode ET4-3 of the fourth light-emitting transistor and the first electrode ET6-3 of the sixth light-emitting transistor. The shape of a portion of the fourth dummy source-drain electrode DES4 is identical to the shape of a portion of the integrated structure of the second electrode ET4-4 of the fourth light-emitting transistor and the second electrode ET5-4 of the fifth light-emitting transistor. The shape of a portion of any of the fifth to ninth dummy source-drain electrodes DES5 to DES5 is identical to the shape of a portion of the second electrode ET10-4 of the tenth light-emitting transistor.

[0256] In an exemplary manner, as shown in Figures 4 and 13B, the light-emitting initial signal line ESTV, the first second light-emitting power line EVGL, the third light-emitting power line EVCX, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH and the second first light-emitting power line EVGH are arranged in sequence along the direction close to the display area.

[0257] In an exemplary embodiment, as shown in Figures 4 and 13B , the light-emitting cascade signal line ECL is electrically connected to the output terminal of at least one light-emitting shift register and the input terminal of at least one light-emitting shift register, respectively. The orthographic projection of the light-emitting cascade signal line ECL on the substrate is between the orthographic projections of the first and second light-emitting power lines EVGL and the orthographic projections of the third light-emitting power line EVCX on the substrate. A dummy light-emitting shift register is located on the side of the light-emitting cascade signal line ECL closest to the display area. At least one dummy source and drain electrode in the dummy light-emitting shift register is electrically connected to the first light-emitting power line EVGH.

[0258] In an exemplary embodiment, the display substrate further includes a driving structure layer comprising a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The emission cascade signal line ECL, the emission start signal line ESTV, and two second emission power lines EVGL are located on the fourth conductive layer, while the first emission clock signal line ECK1, the second emission clock signal line ECK2, the first emission power line EVGH, and the third emission power line EVCX are located on the fifth conductive layer.

[0259] In an exemplary embodiment, as shown in FIG. 3 and FIG. 4 , the length of the control driving circuit along the first direction D1 is greater than or equal to the length of the dummy control driving circuit along the first direction D1 , which is the arrangement direction of the plurality of driving circuits.

[0260] FIG14A is a partial film layer schematic diagram (I) of a control shift register and a dummy control shift register, and FIG14B is a partial film layer schematic diagram (II) of a control shift register and a dummy control shift register. As shown in FIG14A and FIG14B , the control drive circuit includes: a plurality of cascaded control shift registers; the dummy control drive circuit includes: at least one dummy control shift register, the at least one dummy control shift register being located between adjacent control shift registers; the control shift register includes: at least one control transistor and at least one control capacitor; the at least one dummy shift register further includes: a plurality of dummy source and drain electrodes; at least a portion of at least one dummy active pattern in the at least one dummy control shift register has the same shape as at least a portion of an active pattern of at least one control transistor; at least a portion of at least one dummy control electrode in the at least one dummy control shift register has the same shape as at least a portion of a control electrode of at least one control transistor or at least a portion of a control capacitor; and at least a portion of at least one dummy source and drain electrode in the at least one dummy control shift register has the same shape as at least a portion of at least one of the first and second electrodes of at least one control transistor.

[0261] In an exemplary embodiment, as shown in FIG14A , at least one dummy control register includes first to thirtieth dummy active patterns DNA1 to DNA30 and first to ninth dummy gates DNG11 to DNG19. The at least one control register includes active patterns NT1-1 and gates NT1-2 of a first control transistor to active patterns NT16-1 and gates NT16-2 of a sixteenth control transistor. The first dummy active pattern DNA1 has the same shape as a portion of the active pattern NT14-1 of the fourteenth control transistor. The second dummy active pattern DNA2 has the same shape as a portion of the active pattern NT1-1 of the first control transistor. The third dummy active pattern DNA3 has the same shape as a portion of the active pattern NT14-1 of the fourteenth control transistor. The fourth dummy active pattern DNA4 has the same shape as a portion of the active pattern NT1-1 of the first control transistor. The fifth dummy active pattern DNA5 has the same shape as a portion of the active pattern NT3-1 of the third control transistor. The shape of the sixth dummy active pattern DNA6 is identical to the shape of part of the active pattern NT3-1 of the third control transistor. The shape of the seventh dummy active pattern DNA7 is identical to the shape of part of the active pattern NT14-1 of the fifteenth control transistor. The shape of the eighth dummy active pattern DNA8 is identical to the shape of part of the active pattern NT15-1 of the fifteenth control transistor. The shape of the ninth dummy active pattern DNA9 is identical to the shape of part of the active pattern NT4-1 of the fourth control transistor. The shape of the tenth dummy active pattern DNA10 is identical to the shape of part of the active pattern NT4-1 of the fourth control transistor. The shapes of the eleventh dummy active pattern DNA11 and the fourteenth dummy active pattern DNA14 are identical to the shape of part of the active pattern NT7-1 of the seventh control transistor. The shapes of the twelfth dummy active pattern DNA12 and the thirteenth dummy active pattern DNA13 are identical to the shape of part of the active pattern NT6-1 of the sixth control transistor. The shapes of the fifteenth dummy active pattern DNA15 and the seventeenth dummy active pattern DNA17 are identical to the shape of part of the active pattern NT8-1 of the eighth control transistor. The shape of the sixteenth dummy active pattern DNA16 and the eighteenth dummy active pattern DNA18 is identical to the shape of part of the active pattern NT5-1 of the fifth control transistor. The shape of the twelfth dummy active pattern DNA12 and the thirteenth dummy active pattern DNA13 is identical to the shape of part of the active pattern NT6-1 of the sixth control transistor. The shape of the nineteenth dummy active pattern DNA19 is identical to the shape of part of the active pattern NT13-1 of the thirteenth control transistor. The shape of the twentieth dummy active pattern DNA20 is identical to the shape of part of the active pattern NT16-1 of the sixteenth control transistor.The shape of the twenty-first dummy active pattern DNA21 is identical to a portion of the shape of the active pattern NT12-1 of the twelfth control transistor. The shape of any active pattern from the twenty-second to thirtieth dummy active patterns DNA22 to DNA30 is identical to a portion of the shape of the active pattern of the ninth control transistor and the integral structure of the tenth control transistor. The shape of the first dummy control electrode DNG11 is identical to a portion of the shape of the integral structure of the control electrode NT1-2 of the first control transistor, the control electrode NT3-2 of the third control transistor, and the control electrode NT14-2 of the fourteenth control transistor. The shape of the second dummy control electrode DNG12 is identical to a portion of the shape of the integral structure of the control electrode NT6-2 of the sixth control transistor and the first electrode plate EC11 of the first control capacitor. The shape of the third dummy control electrode DNG13 is identical to a portion of the shape of the control electrode NT7-2 of the seventh control transistor. The shape of the third dummy control electrode DNG13 is identical to a portion of the shape of the integral structure of the control electrode NT8-2 of the ninth control transistor and the first electrode plate NC11 of the second control capacitor. The shape of the fourth dummy control electrode DNG14 is identical to the partial shape of the control electrode NT11-2 of the eleventh control transistor and the control electrode NT15-2 of the fifteenth control transistor. The shape of the fifth dummy control electrode DNG15 is identical to the partial shape of the control electrode NT5-2 of the fifth control transistor. The shape of the fifth dummy control electrode DNG15 is identical to the partial shape of the control electrode NT2-2 of the second control transistor. The shape of the sixth dummy control electrode DNG62 is identical to the partial shape of the control electrode NT13-2 of the thirteenth control transistor. The shape of the seventh dummy control electrode DNG17 is identical to the partial shape of the integrated structure of the control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor, and the first electrode plate NC31 of the third control capacitor. The shape of the eighth dummy control electrode DNG18 is identical to the partial shape of the control electrode NT12-2 of the twelfth control transistor. The shape of the ninth dummy control electrode DNG19 is identical to the partial shape of the control electrode NT5102 of the tenth control transistor. Part of the shape of the ninth dummy gate DNG19 is the same as part of the shape of the integrated structure of the control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor, and the first plate NC31 of the third control capacitor.

[0262] In an exemplary embodiment, as shown in FIG14B , at least one dummy control register includes first to fifth dummy source-drain electrodes DNS1 to DNS5. A portion of the first dummy source-drain electrode DNS1 has the same shape as a portion of the integral structure of the first electrode NT1-3 of the first control transistor and the first electrode NT14-3 of the fourteenth control transistor. A portion of the second dummy source-drain electrode DNS2 has the same shape as a portion of the second electrode NT1-4 of the first control transistor, a portion of the second dummy source-drain electrode DNS2 has the same shape as a portion of the first electrode NT3-3 of the third control transistor, a portion of the second dummy source-drain electrode DNS2 has the same shape as a portion of the first electrode NT4-3 of the fourth control transistor, a portion of the second dummy source-drain electrode DNS2 has the same shape as a portion of the second electrode NT15-4 of the fifteenth control transistor, a portion of the second dummy source-drain electrode DNS2 has the same shape as a portion of the integral structure of the second electrode NT14-2 of the fourteenth control transistor and the first electrode NT15-3 of the fifteenth control transistor, and a portion of the third dummy source-drain electrode DNS3 has the same shape as a portion of the first electrode NT6-3 of the sixth control transistor. The shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the second electrode NT7-4 of the seventh control transistor and the second electrode NT8-4 of the eighth control transistor, the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the second electrode NT9-4 of the ninth control transistor and the second electrode NT10-4 of the tenth control transistor, the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the first electrode NT10-3 of the tenth control transistor, the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the first electrode NT8-3 of the eighth control transistor, the first electrode NT9-9 of the ninth control transistor and the first electrode NT13-3 of the thirteenth control transistor, and the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the first electrode NT12-3 of the twelfth control transistor and the second electrode NT13-4 of the thirteenth control transistor. The shape of a portion of the fifth virtual source-drain electrode DNS5 is the same as the shape of a portion of the second electrode NT5-4 of the fifth control transistor, the shape of a portion of the fifth virtual source-drain electrode DNS5 is the same as the shape of a portion of the first electrode NT3-3 of the third control transistor, and the shape of a portion of the fifth virtual source-drain electrode DNS5 is the same as the shape of a portion of the first electrode NT16-3 of the sixteenth control transistor.

[0263] In an exemplary embodiment, as shown in Figures 3, 4 and 14B, at least one of the control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first control power line NVGH, the second control power line NVGL, the third control power line NVCX and the control cascade signal line NCL extends along the second direction, and the first direction intersects the second direction; wherein, the first control initial signal line NSTV, the first second control power line NVGL, the second control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first first control power line NVGH, the third control power line NVCX, the second first control power line NVGH, the third first control power line NVGH and the second second control power line NVGL are arranged in sequence along a direction close to the display area.

[0264] In an exemplary embodiment, as shown in Figures 3, 4 and 14B, the control cascade signal line NCL is electrically connected to the output end of at least one stage of control shift register and the input end of at least one stage of control shift register, respectively, and the positive projection of the control cascade signal line NCL on the substrate is between the positive projection of the second control initial signal line NSTV on the substrate and the positive projection of the first control clock signal line NCK1 on the substrate.

[0265] In an exemplary embodiment, as shown in Figure 14B, the control cascade signal line NCL divides the area where the virtual control shift register is located into a first area NR1 and a second area NR2, and at least one virtual source-drain electrode located in the first area NR1 is connected to the first-second control power line NVGL, and at least one virtual source-drain electrode located in the second area NR2 is connected to at least one first control power line NVGH.

[0266] In an exemplary embodiment, the device further includes a driving structure layer comprising a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The control cascade signal line NCL is located in the fourth conductive layer, and the control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first control power line NVGH, the two second control power lines NVGL, and the third control power line NVCX are located in the fifth conductive layer.

[0267] In an exemplary embodiment, as shown in FIG. 3 and FIG. 4 , the length of the scan driving circuit along the first direction is greater than or equal to the length of the dummy scan driving circuit along the first direction D1 , which is the arrangement direction of the plurality of driving circuits.

[0268] Figure 15A is a partial film layer schematic diagram (I) of a scan shift register and a dummy scan shift register, and Figure 15B is a partial film layer schematic diagram (II) of a scan shift register and a dummy scan shift register. As shown in Figures 15A and 15B, in an exemplary embodiment, a scan drive circuit includes: a plurality of cascaded scan shift registers; a dummy scan drive circuit includes: at least one dummy scan shift register, the at least one dummy scan shift register being located between adjacent scan shift registers; the scan shift register includes: at least one scan transistor and at least one scan capacitor; and the at least one dummy shift register further includes: a plurality of dummy source and drain electrodes. In particular, at least a portion of at least one dummy active pattern in the at least one dummy scan shift register has the same shape as at least a portion of an active pattern of at least one scan transistor; at least a portion of at least one dummy control electrode in the at least one dummy scan shift register has the same shape as at least a portion of a control electrode of at least one scan transistor or at least a portion of a scan capacitor; and at least a portion of at least one dummy source and drain electrode in the at least one dummy scan shift register has the same shape as at least a portion of at least one of the first and second electrodes of at least one scan transistor.

[0269] In an exemplary embodiment, as shown in FIG15A , at least one dummy scan register includes first to thirteenth dummy active patterns DPA1 to DPA13 and first to fifth dummy gates DPG11 to DPG15. The at least one scan register includes active patterns PT1-1 and gates PT1-2 of a first scan transistor to active patterns PT8-1 and gates PT8-2 of an eighth scan transistor. The shapes of the first dummy active pattern DPA1 and the second dummy active pattern DPA2 are partially identical to the shapes of the active pattern PT1-1 of the first scan transistor. The shapes of the third dummy active pattern DPA3 and the fourth dummy active pattern DPA4 are partially identical to the shapes of the active pattern PT2-1 of the second scan transistor. The shapes of the fifth dummy active pattern DPA5 and the sixth dummy active pattern DPA6 are partially identical to the shapes of the active pattern PT3-1 of the third scan transistor. The shapes of the seventh to tenth dummy active patterns DPA7 to DPA10 are identical to portions of the active pattern PT4-1 of the fourth scan transistor and the active pattern PT5-1 of the fifth scan transistor. The shapes of the eleventh dummy active pattern DPA11 are identical to portions of the active pattern PT1-1 of the first scan transistor, and the shapes of the eleventh dummy active pattern DPA11 are identical to portions of the active pattern PT6-1 of the sixth scan transistor. The shapes of the twelfth dummy active pattern DPA12 are identical to portions of the active pattern PT7-1 of the seventh scan transistor. The shapes of the thirteenth dummy active pattern DPA13 are identical to portions of the active pattern PT8-1 of the eighth scan transistor. The shapes of the first dummy gate DPG11 are identical to portions of the integrated structure of the control gate PT1-2 of the first scan transistor and the control gate PT3-2 of the third scan transistor. The shapes of the second dummy gate DPG12 are identical to portions of the integrated structure of the control gate PT2-2 of the second scan transistor. The shapes of the third dummy gate DPG13 are identical to portions of the control gate PT8-2 of the eighth scan transistor. The shape of the fourth dummy gate DPG14 is identical to a portion of the shape of the control gate PT7-2 of the seventh scan transistor. The shape of the fifth dummy gate DPG15 is identical to a portion of the shape of the control gate PT5-2 of the fifth scan transistor. The shape of the fifth dummy gate DPG15 is identical to a portion of the shape of the integrated structure of the control gate PT2-2 of the fourth scan transistor, the control gate PT6-2 of the sixth scan transistor, and the first plate PC11 of the first scan capacitor. The shape of the fifth dummy gate DPG15 is identical to a portion of the shape of the integrated structure of the control gate PT5- of the fifth scan transistor and the first plate PC21 of the second scan capacitor.

[0270] In an exemplary embodiment, as shown in FIG15B , at least one dummy scan register includes first to fourth dummy source-drain electrodes DPS1 to DPS4. A portion of the first dummy source-drain electrode DPS1 has the same shape as a portion of the integral structure of the first electrode PT1-3 of the first scan transistor and the first electrode PT14-3 of the fourteenth scan transistor. A portion of the second dummy source-drain electrode DPS2 has the same shape as a portion of the second electrode PT1-4 of the first scan transistor, a portion of the second dummy source-drain electrode DPS2 has the same shape as a portion of the first electrode PT3-3 of the third scan transistor, a portion of the second dummy source-drain electrode DPS2 has the same shape as a portion of the first electrode PT4-3 of the fourth scan transistor, a portion of the second dummy source-drain electrode DPS2 has the same shape as a portion of the second electrode PT15-4 of the fifteenth scan transistor, a portion of the second dummy source-drain electrode DPS2 has the same shape as a portion of the integral structure of the second electrode PT14-2 of the fourteenth scan transistor and the first electrode PT15-3 of the fifteenth scan transistor, and a portion of the third dummy source-drain electrode DPS3 has the same shape as a portion of the first electrode PT6-3 of the sixth scan transistor. The shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the second pole PT7-4 of the seventh scanning transistor and the second pole PT8-4 of the eighth scanning transistor, the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the second pole PT9-4 of the ninth scanning transistor and the second pole PT10-4 of the tenth scanning transistor, the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the first pole PT10-3 of the tenth scanning transistor, the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the first pole PT8-3 of the eighth scanning transistor, the first pole PT9-9 of the ninth scanning transistor and the first pole PT13-3 of the thirteenth scanning transistor, and the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the first pole PT12-3 of the twelfth scanning transistor and the second pole PT13-4 of the thirteenth scanning transistor.

[0271] 3 , 4 and 15B , the second scan power line PVGL, the first scan clock signal line PCK1 , the second scan clock signal line PCK2 , the scan initial signal line PSTV and the first scan power line PVGH are sequentially arranged in a direction close to the display area.

[0272] In an exemplary embodiment, as shown in Figures 3, 4 and 15B, the scan cascade signal line PCL is electrically connected to the output end of at least one stage of scan shift register and the input end of at least one stage of scan shift register, respectively, and the positive projection of the scan cascade signal line PCL on the substrate is between the positive projection of the second scan clock signal line PCK2 on the substrate and the positive projection of the scan initial signal line PSTV on the substrate.

[0273] In an exemplary embodiment, as shown in FIG15B , the scan cascade signal line PCL divides the region where the virtual scan shift register is located into a first region PR1 and a second region PR2, at least one virtual source-drain electrode located in the first region PR1 is connected to the second scan power line PVGL, and at least one virtual source-drain electrode located in the second region PR2 is connected to the first scan power line PVGH.

[0274] In an exemplary embodiment, the display substrate may further include a driving structure layer. The driving structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The scan cascade signal line PCL is located on the fourth conductive layer, and the scan initial signal line PSTV, the first scan clock signal line PCK1, the second scan clock signal line PCK2, the first scan power line PVGH, and the second scan power line PVGL are located on the fifth conductive layer.

[0275] In an exemplary embodiment, there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate, so that the area of ​​the virtual active pattern in the virtual driving circuit group is smaller than the area of ​​the active pattern in the driving circuit group, thereby reducing the overlapping area between at least one signal line (for example, a clock signal line) in the display substrate and the virtual active pattern, reducing the coupling capacitance between the signal line and the active pattern, avoiding potential leakage in the display substrate, and reducing the power consumption of the display substrate.

[0276] In an exemplary embodiment, since there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate, there is no complete transistor structure in the virtual driving circuit group. Therefore, the display substrate does not need to be connected to a test circuit for verifying the virtual driving circuit group, which can improve the testing efficiency of the display substrate.

[0277] In an exemplary embodiment, the driving circuit group includes at least one transistor and at least one capacitor, the dummy driving circuit group includes multiple dummy active patterns, multiple dummy control electrodes, and dummy source and drain electrodes, and the display substrate further includes a signal output line located in a non-display area, at least one cascade signal line, and multiple signal lines, the multiple signal lines being connected to the driving circuit group and the dummy circuit group, respectively, and the signal output line being connected to the driving circuit group. The driving structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer.

[0278] The semiconductor layer includes at least: an active pattern of at least one transistor and at least one dummy active pattern among a plurality of dummy active patterns;

[0279] The first conductive layer at least includes: a control electrode of at least one transistor, a plate of at least one capacitor, and at least one dummy active pattern among a plurality of dummy control electrodes;

[0280] The second conductive layer includes at least: another plate of at least one capacitor;

[0281] The third conductive layer at least includes: a signal output line;

[0282] The fourth conductive layer at least includes: at least one signal line and a cascade signal line;

[0283] The fifth conductive layer at least includes: at least one signal line.

[0284] In an exemplary embodiment, the driving structure layer may further include: a first insulating layer located between the semiconductor layer and the first conductive layer, a second insulating layer located between the first conductive layer and the second conductive layer, a third insulating layer located between the second conductive layer and the third conductive layer, a fourth insulating layer located between the third conductive layer and the fourth conductive layer, and a fifth insulating layer and a planar layer located between the fourth conductive layer and the fifth conductive layer.

[0285] In an exemplary embodiment, as shown in Figures 3 and 4 , the device further includes at least one initial signal line located in the non-display area. The at least one initial signal line is located on a side of at least one of the multiple signal lines that is closer to the display area and is located in the fifth conductive layer. The orthographic projection of the at least one initial signal line on the substrate at least partially overlaps with the orthographic projections of the drive circuit group and the dummy drive circuit group on the substrate. Figures 3 and 4 illustrate the two initial signal lines INIL1 and INIL2 as examples.

[0286] In an exemplary embodiment, two adjacent virtual scan shift registers are arranged along an arc-shaped boundary in a corner region, and at least one level of scan shift register may be provided between the two adjacent virtual scan shift registers or they may be directly adjacent to each other. One of the two adjacent virtual scan shift registers may be referred to as a first adjacent virtual scan shift register, and the other may be referred to as a second adjacent virtual scan shift register. At least one virtual source-drain electrode in the first adjacent virtual scan shift register may be electrically connected to one of the first scan clock signal line and the second scan clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual scan shift register may be electrically connected to the other of the first scan clock signal line and the second scan clock signal line.

[0287] In an exemplary embodiment, two adjacent virtual control shift registers are arranged along an arc-shaped boundary in a corner region, and at least one level of control shift register may be provided between the two adjacent virtual control shift registers or they may be directly adjacent to each other. One of the two adjacent virtual control shift registers may be referred to as a first adjacent virtual control shift register, and the other may be referred to as a second adjacent virtual control shift register. At least one virtual source-drain electrode in the first adjacent virtual control shift register may be electrically connected to one of the first control clock signal line and the second control clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual control shift register may be electrically connected to the other of the first control clock signal line and the second control clock signal line.

[0288] In an exemplary embodiment, two adjacent virtual reset shift registers are arranged along an arc-shaped boundary in a corner region, and at least one reset shift register stage may be provided between the two adjacent virtual reset shift registers or the two adjacent virtual reset shift registers may be directly adjacent to each other. One of the two adjacent virtual reset shift registers may be referred to as a first adjacent virtual reset shift register, and the other may be referred to as a second adjacent virtual reset shift register. At least one virtual source-drain electrode in the first adjacent virtual reset shift register may be electrically connected to one of the first reset clock signal line and the second reset clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual reset shift register may be electrically connected to the other of the first reset clock signal line and the second reset clock signal line.

[0289] In an exemplary embodiment, two adjacent virtual light-emitting shift registers are arranged along the arc-shaped boundary of a corner region, and at least one level of light-emitting shift register may be provided between the two adjacent virtual light-emitting shift registers or they may be directly adjacent to each other. One of the two adjacent virtual light-emitting shift registers may be referred to as a first adjacent virtual light-emitting shift register, and the other may be referred to as a second adjacent virtual light-emitting shift register. At least one virtual source-drain electrode in the first adjacent virtual light-emitting shift register may be electrically connected to one of the first light-emitting clock signal line and the second light-emitting clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual light-emitting shift register may be electrically connected to the other of the first light-emitting clock signal line and the second light-emitting clock signal line.

[0290] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In the exemplary embodiment, the structure of the light-emitting shift register is the same as that of the reset shift register, and the structure of the virtual light-emitting shift register is the same as that of the virtual reset shift register. The following only describes the manufacturing method of the scanning shift register and the virtual scanning shift register, the control shift register and the virtual control shift register, the reset shift register and the virtual reset shift register. The manufacturing method of the light-emitting shift register and the virtual light-emitting shift register is the same as the manufacturing method of the reset shift register and the virtual reset shift register, and will not be repeated here.

[0291] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. As shown in Figures 16 to 18, Figure 16 is a schematic diagram of the scan shift register and the dummy scan shift register after forming a semiconductor layer pattern, Figure 17 is a schematic diagram of the control shift register and the dummy control shift register after forming a semiconductor layer pattern, and Figure 18 is a schematic diagram of the reset shift register and the dummy reset shift register after forming a semiconductor layer pattern.

[0292] In an exemplary embodiment, as shown in Figures 16 to 18, the semiconductor layer pattern may include at least: an active pattern PT1-1 of the first scan transistor to the active pattern PT8-1 of the eighth scan transistor located in the scan shift register, a first virtual active pattern DPA1 to the thirteenth virtual active pattern DPA13 located in the virtual scan shift register, an active pattern NT1-1 of the first control transistor to the sixteenth control transistor located in the control shift register, a first virtual active pattern DNA1 to the thirtieth virtual active pattern DNA30 located in the virtual control shift register, an active pattern RT1-1 of the first reset transistor to the active pattern RT13-1 of the thirteenth reset transistor located in the reset shift register, and a first virtual active pattern DRA1 to the twenty-first virtual active pattern DRA21 located in the virtual reset shift register.

[0293] In an exemplary embodiment, the active pattern PT4-1 of the fourth scanning transistor and the active pattern PT5-1 of the fifth scanning transistor are an integrated structure, the active pattern PT6-1 of the sixth scanning transistor, the active pattern PT7-1 of the seventh scanning transistor, and the active pattern PT8-1 of the eighth scanning transistor are an integrated structure, and the active pattern PT1-1 of the first scanning transistor, the active pattern PT2-1 of the second scanning transistor, and the active pattern PT3-1 of the third scanning transistor are separately set.

[0294] In an exemplary embodiment, any one of the first to thirteenth dummy active patterns DPA1 to DPA13 located in the dummy scan shift register is individually provided.

[0295] In an exemplary embodiment, the active pattern NT2-1 of the second control transistor and the active pattern NT11-1 of the eleventh control transistor are integrally formed, the active pattern NT9-1 of the ninth control transistor and the active pattern NT10-1 of the tenth control transistor are integrally formed, and the active pattern NT8-1 of the eighth control transistor, the active pattern NT12-1 of the twelfth control transistor, the active pattern NT13-1 of the thirteenth control transistor, and the active pattern NT16-1 of the sixteenth control transistor are integrally formed. The active pattern NT1-1 of the first control transistor, the active pattern NT3-1 of the third control transistor, the active pattern NT4-1 of the fourth control transistor, the active pattern NT5-1 of the fifth control transistor, the active pattern NT6-1 of the sixth control transistor, the active pattern NT7-1 of the seventh control transistor, and the active pattern NT15-1 of the fifteenth control transistor are separately provided.

[0296] In an exemplary embodiment, any one active pattern among the first to thirtieth dummy active patterns DNA1 to DNA30 located in the dummy control shift register is individually provided.

[0297] In an exemplary embodiment, the active pattern RT4-1 of the fourth reset transistor, the active pattern RT5-1 of the fifth reset transistor, the active pattern RT7-1 of the seventh reset transistor, the active pattern RT8-1 of the eighth reset transistor, and the active pattern RT13-1 of the thirteenth reset transistor are integrally formed. The active pattern RT9-1 of the ninth reset transistor and the active pattern RT10-1 of the tenth reset transistor are active patterns. The active pattern RT1-1 of the first reset transistor, the active pattern RT2-1 of the second reset transistor, the active pattern RT3-1 of the third reset transistor, the active pattern RT6-1 of the sixth reset transistor, the active pattern RT11-1 of the eleventh reset transistor, and the active pattern RT12-1 of the twelfth reset transistor are separately provided.

[0298] In an exemplary embodiment, any one of the first to twenty-first dummy active patterns DRA1 to DRA21 located in the dummy reset shift register is individually provided.

[0299] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on a substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 19 to 24, Figure 19 is a schematic diagram of the first conductive layer pattern in the scan shift register and the virtual scan shift register, Figure 20 is a schematic diagram of the scan shift register and the virtual scan shift register after the first conductive layer pattern is formed, Figure 21 is a schematic diagram of the first conductive layer pattern in the control shift register and the virtual control shift register, Figure 22 is a schematic diagram of the control shift register and the virtual control shift register after the first conductive layer pattern is formed, Figure 23 is a schematic diagram of the reset shift register and the virtual reset shift register after the first conductive layer pattern is formed, and Figure 24 is a schematic diagram of the reset shift register and the virtual reset shift register after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0300] In an exemplary embodiment, the first conductive layer pattern may include at least: the control electrode PT1-2 of the first scan transistor to the control electrode PT8-2 of the eighth scan transistor and the first plate PC11 of the first scan capacitor and the first plate PC21 of the second scan capacitor located in the scan shift register, the first virtual control electrode DPA11 to the fifth virtual control electrode DPG15 located in the virtual scan shift register, the control electrode NT1-2 of the first control transistor to the sixteenth control transistor NT16-2 and the first plate NC11 of the first control capacitor to the first plate NC31 of the third control capacitor located in the control shift register, the first virtual control electrode DNG11 to the ninth virtual control electrode DNG19 located in the virtual control shift register, the control electrode RT1-2 of the first reset transistor to the control electrode RT13-2 of the thirteenth reset transistor located in the reset shift register and the first plate RC11 of the first reset capacitor to the first plate RC31 of the third reset capacitor located in the virtual reset shift register, and the first virtual control electrode DRG11 to the eighth virtual control electrode DRG18 located in the virtual reset shift register.

[0301] In an exemplary embodiment, the control electrode PT1-2 of the first scan transistor and the control electrode PT3-2 of the third scan transistor are integrally formed. The control electrode PT4-2 of the fourth scan transistor, the control electrode PT6-2 of the sixth scan transistor, and the first plate PC11 of the first scan capacitor are integrally formed. The control electrode PT5-2 of the fifth scan transistor and the first plate PC21 of the second scan capacitor are integrally formed. The control electrode PT2-2 of the second scan transistor, the control electrode PT7-2 of the seventh scan transistor, and the control electrode PT8-2 of the eighth scan transistor are separately provided.

[0302] In an exemplary embodiment, any one of the first to fifth dummy gate electrodes DPA11 to DPG15 located in the dummy scan shift register is independently provided.

[0303] In an exemplary embodiment, the control electrode NT1-2 of the first control transistor, the control electrode NT3-2 of the third control transistor, and the control electrode NT14-2 of the fourteenth control transistor are integrally formed. The control electrode NT2-2 of the second control transistor and the control electrode NT8-2 of the eighth control transistor are integrally formed. The control electrode NT6-2 of the sixth control transistor and the first plate NC11 of the first control capacitor are integrally formed. The control electrode NT5-2 of the fifth control transistor and the control electrode NT11-2 of the eleventh control transistor are integrally formed. The control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor, and the first plate NC31 of the third control capacitor are integrally formed, and the control electrode NT9-2 of the ninth control transistor and the first plate NC21 of the second control capacitor are integrally formed. The control electrode NT5-2 of the fifth control transistor, the control electrode NT7-2 of the seventh control transistor, the control electrode NT10-2 of the tenth control transistor, the control electrode NT12-2 of the twelfth control transistor, and the control electrode NT13-2 of the thirteenth control transistor are separately provided.

[0304] In an exemplary embodiment, any one of the first to ninth dummy control electrodes DNG11 to DNG19 located in the dummy control shift register is independently provided.

[0305] In an exemplary embodiment, the control electrode RT1-2 of the first reset transistor and the control electrode RT3-2 of the third reset transistor are integrally formed. The control electrode RT6-2 of the sixth reset transistor and the first plate RC11 of the first reset capacitor are integrally formed. The control electrode RT11-2 of the eleventh reset transistor and the control electrode RT12-2 of the twelfth reset transistor are integrally formed. The control electrode RT4-2 of the fourth reset transistor, the control electrode RT10-2 of the tenth reset transistor, and the first plate RC31 of the third reset capacitor are integrally formed, and the control electrode RT9-2 of the ninth reset transistor and the first plate RC21 of the second reset capacitor are integrally formed. The control electrode RT2-2 of the second reset transistor, the control electrode RT5-2 of the fifth reset transistor, the control electrode RT7-2 of the seventh reset transistor, the control electrode RT8-2 of the eighth reset transistor, and the control electrode RT13-2 of the thirteenth reset transistor are separately provided.

[0306] In an exemplary embodiment, any one of the first to eighth dummy control electrodes DRG11 to DRG18 located in the dummy reset shift register is independently provided.

[0307] In an exemplary embodiment, an extension direction of the control electrode of at least one transistor is perpendicular to an extension direction of the active pattern. An orthographic projection of any virtual control electrode on the substrate does not overlap with an orthographic projection of the virtual active pattern on the substrate.

[0308] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process to form a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in Figures 25 to 30, Figure 25 is a schematic diagram of the second conductive layer pattern in the scan shift register and the virtual scan shift register, Figure 26 is a schematic diagram of the scan shift register and the virtual scan shift register after the second conductive layer pattern is formed, Figure 27 is a schematic diagram of the second conductive layer pattern in the control shift register and the virtual control shift register, Figure 28 is a schematic diagram of the control shift register and the virtual control shift register after the second conductive layer pattern is formed, Figure 29 is a schematic diagram of the reset shift register and the virtual reset shift register after the second conductive layer pattern is formed, and Figure 30 is a schematic diagram of the reset shift register and the virtual reset shift register after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0309] In an exemplary embodiment, the second conductive layer pattern may include at least: the second plate PC12 of the first scan capacitor, the second plate PC22 of the second scan capacitor and the first scan connection line PL1 located in the scan shift register, the first virtual electrode DPG21, the second virtual electrode DPG22 and the third virtual electrode DPG23 located in the virtual scan shift register, the second plate NC12 of the first control capacitor to the second plate NC32 of the third control capacitor and the first scan connection line NL1 located in the control shift register, the first virtual electrode DNG11 to the fourth virtual control electrode DNG14 located in the virtual control shift register, the second plate RC12 of the first reset capacitor to the first plate RC32 of the third reset capacitor located in the reset shift register, and the first virtual electrode DRG21 to the third virtual electrode DRG23 located in the virtual reset shift register.

[0310] In an exemplary embodiment, the shape of the first dummy electrode DPG21 located in the dummy scan shift register is the same as the shape of a portion of the first scan signal line PL1. The shape of the second dummy electrode DPG22 located in the dummy scan shift register is the same as the shape of a portion of the second plate PC12 of the first scan capacitor. The shape of the third dummy electrode DPG23 located in the dummy scan shift register is the same as the shape of a portion of the second plate PC22 of the second scan capacitor.

[0311] In an exemplary embodiment, the shape of the first dummy electrode DNG21 located in the dummy control shift register is the same as the shape of a portion of the second plate NC12 of the first control capacitor. The shape of the second dummy electrode DNG22 located in the dummy control shift register is the same as the shape of a portion of the second plate NC22 of the second control capacitor. The shape of the third dummy electrode DNG23 and the shape of the fourth dummy electrode DNG24 located in the dummy control shift register are the same as the shape of a portion of the first plate NC32 of the third control capacitor.

[0312] In an exemplary embodiment, the shape of the first dummy electrode DRG21 located in the dummy reset shift register is the same as the shape of a portion of the second plate RC12 of the first reset capacitor. The shape of the second dummy electrode DRG22 located in the dummy reset shift register is the same as the shape of a portion of the second plate RC22 of the second reset capacitor. The shape of the third dummy electrode DRG23 located in the dummy reset shift register is the same as the shape of a portion of the first plate RC32 of the third reset capacitor.

[0313] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third insulating film and a third conductive film on a substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process to form a third insulating layer pattern covering the second conductive layer pattern and a third conductive layer pattern located on the third insulating layer pattern, as shown in Figures 31 to 34, Figure 31 is a schematic diagram of the third conductive layer pattern in the control shift register and the virtual control shift register, Figure 32 is a schematic diagram of the control shift register and the virtual control shift register after the third conductive layer pattern is formed, Figure 33 is a schematic diagram of the third conductive layer pattern in the reset shift register and the virtual reset shift register, and Figure 34 is a schematic diagram of the reset shift register and the virtual reset shift register after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0314] In an exemplary embodiment, the third conductive layer pattern may include at least a dummy electrode DNG31 located in the dummy control shift register, a second reset link line RL2 located in the reset shift register, and a dummy electrode DRG31 located in the dummy reset shift register.

[0315] In an exemplary embodiment, the shape of the dummy electrode DRG31 located at the dummy reset shift register is the same as a portion of the second reset link line RL2 .

[0316] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, wherein the fourth insulating layer is provided with a plurality of via patterns, as shown in Figures 35 to 37. Figure 35 is a schematic diagram of the scan shift register and the dummy scan shift register after the fourth insulating layer is formed, Figure 36 is a schematic diagram of the control shift register and the dummy control shift register after the fourth insulating layer is formed, and Figure 37 is a schematic diagram of the reset shift register and the dummy reset shift register after the fourth insulating layer is formed.

[0317] In an exemplary embodiment, the fourth insulation layer pattern may include at least: the first via V1 to the fourteenth via V14 located in the scanning shift register, the first virtual via DV1 to the nineteenth virtual via V19 located in the virtual scanning shift register, the first via H1 to the twenty-fourth via H24 located in the control shift register, the first virtual via DH1 to the forty-second virtual via DH42 located in the virtual control shift register, the first via K1 to the twenty-second via K22 located in the reset shift register, and the first virtual via DK1 to the thirty-first virtual via DK31 located in the reset scanning shift register.

[0318] (6) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern located on the fourth insulating layer pattern, as shown in Figures 38 to 43, Figure 38 is a schematic diagram of the fourth conductive layer pattern in the scan shift register and the virtual scan shift register, Figure 39 is a schematic diagram of the scan shift register and the virtual scan shift register after the fourth conductive layer pattern is formed, Figure 40 is a schematic diagram of the fourth conductive layer pattern in the control shift register and the virtual control shift register, Figure 41 is a schematic diagram of the control shift register and the virtual control shift register after the fourth conductive layer pattern is formed, Figure 42 is a schematic diagram of the fourth conductive layer pattern in the reset shift register and the virtual reset shift register, and Figure 43 is a schematic diagram of the reset shift register and the virtual reset shift register after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0319] In an exemplary embodiment, the fourth conductive layer pattern may include at least: the first electrode PT1-3 and the second electrode PT1-4 of the first scan transistor located in the scan shift register to the first electrode PT8-3 and the second electrode PT8-4 of the eighth scan transistor, the first virtual source-drain electrode DPS1 to the fourth virtual source-drain electrode DPS4 located in the dummy scan shift register, the first electrode NT1-3 and the second electrode NT1-4 of the first control transistor located in the control shift register to the first electrode NT8-3 and the second electrode NT8-4 of the eighth control transistor, the first virtual source-drain electrode DNS1 to the fifth virtual source-drain electrode DNS5 located in the dummy control shift register, the first electrode RT1-3 and the second electrode RT1-4 of the first reset transistor located in the reset shift register to the first electrode RT8-3 and the second electrode RT8-4 of the eighth reset transistor, the first virtual source-drain electrode DRS1 to the ninth virtual source-drain electrode DRS9 located in the dummy reset shift register, the scan cascade signal line PCL, the control cascade signal line NCL, the reset cascade signal line RCL, the reset initial signal line RSTV and two second reset power lines RVGL.

[0320] In an exemplary embodiment, the first virtual source-drain electrode DPS1 to the third virtual source-drain electrode DPS3 located in the virtual scan shift register are located on a side of the scan cascade signal line PCL away from the display area, and the fourth virtual source-drain electrode DPS4 located in the virtual scan shift register is located on a side of the scan cascade signal line PCL close to the display area.

[0321] In an exemplary embodiment, the first electrodes RT1-3 and the second electrodes RT1-4 of the first reset transistor to the first electrodes RT8-3 and the second electrodes RT8-4 of the eighth reset transistor in the reset shift register and the first dummy source-drain electrodes DRS1 to the ninth dummy source-drain electrodes DRS9 in the dummy reset shift register are disposed between the two second reset power lines RVGL.

[0322] In an exemplary embodiment, the first virtual source-drain electrode DNS1 and the second virtual source-drain electrode DNS2 located in the virtual control shift register are located on a side of the control cascade signal line NCL away from the display area, and the third virtual source-drain electrode DNS3 to the fifth virtual source-drain electrode DNS5 located in the virtual control shift register are located on a side of the control cascade signal line NCL close to the display area.

[0323] In an exemplary embodiment, the first to ninth dummy source-drain electrodes DRS1 to DRS9 located in the dummy reset shift register are located on a side of the reset cascade signal line RCL close to the display area.

[0324] (7) Forming a flat layer pattern. In an exemplary embodiment, forming the flat layer pattern may include: depositing a fifth insulating film and coating a flat film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film and the flat film through a patterning process to form a fifth insulating layer pattern and a flat layer pattern covering the aforementioned structure, wherein the flat layer is provided with a plurality of via patterns, as shown in Figures 44 to 46. Figure 44 is a schematic diagram of the scan shift register and the virtual scan shift register after the flat layer is formed, Figure 45 is a schematic diagram of the control shift register and the virtual control shift register after the flat layer is formed, and Figure 46 is a schematic diagram of the reset shift register and the virtual reset shift register after the flat layer is formed.

[0325] In an exemplary embodiment, the multiple vias in the flat layer may include at least: the fifteenth via V15 to the sixteenth via V16 located in the scanning shift register, the twentieth virtual via DV20 to the twenty-first virtual via VD21 located in the virtual scanning shift register, the twenty-fifth via H25 to the thirty-first via H31 located in the control shift register, the forty-third virtual via DH43 to the forty-fifth virtual via DH45 located in the virtual control shift register, the twenty-third via K23 to the twenty-fourth via K24 located in the reset shift register, and the thirty-second virtual via DK32 located in the reset scanning shift register.

[0326] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the fifth insulating layer, as shown in Figures 47 to 52, Figure 47 is a schematic diagram of the fifth conductive layer pattern in the scan shift register and the virtual scan shift register, Figure 48 is a schematic diagram of the scan shift register and the virtual scan shift register after the fifth conductive layer pattern is formed, Figure 49 is a schematic diagram of the fifth conductive layer pattern in the control shift register and the virtual control shift register, Figure 50 is a schematic diagram of the control shift register and the virtual control shift register after the fifth conductive layer pattern is formed, Figure 51 is a schematic diagram of the reset shift register and the virtual reset shift register after the fifth conductive layer pattern is formed, and Figure 52 is a schematic diagram of the reset shift register and the virtual reset shift register after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0327] In an exemplary embodiment, the fifth conductive layer pattern may include at least: a scan initial signal line PSTV, a first scan clock signal line PCK1, a second scan clock signal line PCK2, a first scan power line PVGH, a second scan power line PVGL, a first initial signal line INIL1 and a second initial signal line INIL2, a control initial signal line NSTV, a first control clock signal line NCK1, a second control clock signal line NCK2, a first control power line NVGH, a second control power line NVGL, a third control power line NVCX, a reset initial signal line RSTV, a first reset clock signal line RCK1, a second reset clock signal line RCK2, a first reset power line RVGH, a second reset power line RVGL, and a third reset power line RVCX.

[0328] At this point, the drive circuit layer is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple shift registers and multiple dummy shift registers. In a plane perpendicular to the display substrate, the drive circuit layer may be disposed on the substrate. The drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a planar layer, and a fifth conductive layer, sequentially disposed on the substrate.

[0329] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0330] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0331] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0332] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0333] In exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer, the third insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fourth insulating layer may be referred to as a passivation (PVX) layer.

[0334] In an exemplary embodiment, the planar layer may be made of an organic material such as resin.

[0335] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0336] An anode conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned using a patterning process to form an anode conductive layer pattern arranged on the second flat layer. A pixel definition film is deposited on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0337] At this point, the light-emitting structure layer is prepared on the substrate.

[0338] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns. The plurality of anode patterns may include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device, wherein the anode of the first light-emitting device is located in a red sub-pixel emitting red light, the anode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the anode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the anode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0339] In an exemplary embodiment, the anode of the first light-emitting device and the anode of the second light-emitting device may be alternately arranged along the first direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device may be alternately arranged along the first direction. Alternatively, the anode of the first light-emitting device and the anode of the second light-emitting device may be alternately arranged along the second direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device may be alternately arranged along the second direction.

[0340] In an exemplary embodiment, the shapes and areas of the anode electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.

[0341] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0342] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0343] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0344] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0345] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0346] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0347] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0348] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0349] In an exemplary embodiment, the display device may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0350] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0351] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0352] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate having a display area and a non-display area, comprising: A substrate and a pixel driving circuit disposed on the substrate and located in a display area, a driving circuit group and a dummy driving circuit group located in a non-display area, wherein the pixel driving circuit is electrically connected to the driving circuit group, the driving circuit group includes at least one shift register, the dummy driving circuit group includes at least one dummy shift register, the dummy shift register includes a plurality of dummy active patterns and a plurality of dummy control electrodes, the shift register includes a plurality of transistors, and the transistors include active patterns and control electrodes; The shape of at least a portion of at least one dummy active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, the shape of at least a portion of at least one dummy control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, and there is no overlapping area between the orthographic projection of at least one of the dummy active patterns and the orthographic projection of at least one of the dummy control electrodes on the substrate.

2. The display substrate according to claim 1, wherein A distance between an orthographic projection of the at least one virtual active pattern on the substrate and a target virtual control electrode is in a range of 0.8 micrometers to 2 micrometers; The orthographic projection of the dummy active pattern on the substrate is adjacent to the orthographic projection of the target dummy control electrode on the substrate.

3. The display substrate according to claim 1, wherein: The non-display area includes at least one corner area and at least one straight border area. The driving circuit group includes a plurality of driving circuits, which are sequentially arranged in a direction close to the display area, and the driving circuits include a plurality of cascaded shift registers. The virtual driving circuit group includes a plurality of virtual driving circuits, which are sequentially arranged in a direction close to the display area, and the virtual driving circuits include a plurality of cascaded virtual shift registers. The virtual driving circuit group is at least partially located in the corner area, the driving circuit group is located in the corner area and the straight line frame area, the driving circuit group and the virtual driving circuit group are located on the first side and the second side of the display area, and the first side and the second side of the display area are arranged opposite to each other.

4. The display substrate according to claim 3, wherein: The display area is provided with a pixel driving circuit and at least one reset signal line, the pixel driving circuit includes: a driving transistor and a reset transistor, the reset transistor is electrically connected to the control electrode of the driving transistor, and the reset signal line is electrically connected to the control electrode of the reset transistor; the multiple driving circuits include: a reset driving circuit, the reset driving circuit is located on one of the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual reset driving circuit; The length of the reset driving circuit along a first direction is greater than the length of the dummy reset driving circuit along the first direction. The first direction is an arrangement direction of the plurality of driving circuits.

5. The display substrate according to claim 4, wherein: The reset driving circuit includes: a plurality of cascaded reset shift registers; the virtual reset driving circuit includes: at least one virtual reset shift register, and the at least one virtual reset shift register is located between adjacent reset shift registers; The reset shift register includes: at least one reset transistor and at least one reset capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual reset shift register has the same shape as at least a portion of an active pattern of at least one reset transistor, at least a portion of at least one virtual control electrode in at least one virtual reset shift register has the same shape as at least a portion of a control electrode of at least one reset transistor or at least a portion of a reset capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual reset shift register has the same shape as at least a portion of at least one electrode of the first electrode and the second electrode of at least one reset transistor.

6. The display substrate according to claim 4, wherein: The non-display area is further provided with a reset cascade signal line, a reset initial signal line, a first reset clock signal line, a second reset clock signal line, a first reset power line, two second reset power lines and a third reset power line; At least one of the reset initial signal line, the first reset clock signal line, the second reset clock signal line, the first reset power line, the second reset power line, the third reset power line, and the reset cascade signal line extends along a second direction, and the first direction intersects the second direction; The orthographic projections of the reset initial signal line, the first second reset power line, the third reset power line, the first reset clock signal line, the second reset clock signal line, the first reset power line and the second second reset power line on the substrate are arranged in sequence along the direction close to the display area.

7. The display substrate according to claim 5, wherein: The non-display area is provided with the reset cascade signal line, two second reset power lines and a third reset power line, and the reset shift register includes: an input end and an output end; The reset cascade signal line is electrically connected to the output end of at least one stage of reset shift register and the input end of at least one stage of reset shift register, respectively. The orthographic projection of the reset cascade signal line on the substrate is between the orthographic projection of the first and second reset power lines on the substrate and the orthographic projection of the third reset power line on the substrate.

8. The display substrate according to claim 5, wherein: The non-display area is provided with the reset cascade signal line and the first reset power line; The virtual reset shift register is located on a side of the reset cascade signal line close to the display area, and at least one virtual source and drain electrode in the virtual reset shift register is electrically connected to the first reset power line.

9. The display substrate according to claim 6, further comprising: Drive structure layer; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The reset cascade signal line, the reset initial signal line and the two second reset power lines are located in the fourth conductive layer, and the first reset clock signal line, the second reset clock signal line, the first reset power line and the third reset power line are located in the fifth conductive layer.

10. The display substrate according to claim 3, wherein: The display area is provided with a pixel driving circuit and at least one light-emitting signal line, the pixel driving circuit includes: a driving transistor and a light-emitting transistor, the light-emitting transistor is electrically connected to at least one of the first electrode and the second electrode of the driving transistor, and the light-emitting signal line is electrically connected to the control electrode of the light-emitting transistor; the multiple driving circuits include: a light-emitting driving circuit, the light-emitting driving circuit is located on the other of the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual light-emitting driving circuit; The length of the light-emitting driving circuit along the first direction is greater than or equal to the length of the virtual light-emitting driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

11. The display substrate according to claim 10, wherein: The light-emitting driving circuit includes: a plurality of cascaded light-emitting shift registers; the virtual light-emitting driving circuit includes: at least one virtual light-emitting shift register, and the at least one virtual light-emitting shift register is located between adjacent light-emitting shift registers; The light-emitting shift register includes: at least one light-emitting transistor and at least one light-emitting capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual light-emitting shift register has the same shape as at least a portion of the active pattern of at least one light-emitting transistor, at least a portion of at least one virtual control electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of the control electrode of at least one light-emitting transistor or at least a portion of the light-emitting capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one light-emitting transistor.

12. The display substrate according to claim 10, wherein: The non-display area is further provided with a light emitting cascade signal line, a light emitting initial signal line, a first light emitting clock signal line, a second light emitting clock signal line, a first light emitting power line, two second light emitting power lines and a third light emitting power line; At least one of the light emitting initial signal line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power line, the second light emitting power line, the third light emitting power line, and the light emitting cascade signal line extends along a second direction, and the first direction intersects the second direction; The positive projections of the initial light-emitting signal line, the first second light-emitting power line, the third light-emitting power line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line and the second first light-emitting power line on the substrate are arranged in sequence along the direction close to the display area.

13. The display substrate according to claim 11, wherein: The non-display area is provided with the light emitting cascade signal line, two second light emitting power lines and a third light emitting power line, and the light emitting shift register includes: an input end and an output end; The light-emitting cascade signal line is electrically connected to the output end of at least one level of light-emitting shift register and the input end of at least one level of light-emitting shift register, respectively. The orthographic projection of the light-emitting cascade signal line on the substrate is between the orthographic projection of the first and second light-emitting power lines on the substrate and the orthographic projection of the third light-emitting power line on the substrate.

14. The display substrate according to claim 11, wherein: The non-display area is provided with the light emitting cascade signal line and the first light emitting power line; The virtual light emitting shift register is located on a side of the light emitting cascade signal line close to the display area, and at least one virtual source and drain electrode in the virtual light emitting shift register is electrically connected to the first light emitting power line.

15. The display substrate according to claim 12, further comprising: Drive structure layer; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The light cascade signal line, the light initial signal line and the two second light power lines are located in the fourth conductive layer, and the first light clock signal line, the second light clock signal line, the first light power line and the third light power line are located in the fifth conductive layer.

16. The display substrate according to claim 3, wherein: The display area is provided with a pixel driving circuit and at least one control signal line, the pixel driving circuit includes: a driving transistor and a compensation transistor, the compensation transistor is electrically connected to the control electrode and the second electrode of the driving transistor, and the control signal line is electrically connected to the control electrode of the compensation transistor; the multiple driving circuits include: a control driving circuit, the control driving circuit is located on the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual control driving circuit; The length of the control driving circuit along the first direction is greater than or equal to the length of the virtual control driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

17. The display substrate according to claim 16, wherein: The control driving circuit includes: a plurality of cascaded control shift registers, and the virtual control driving circuit includes: at least one virtual control shift register, and the at least one virtual control shift register is located between adjacent control shift registers; The control shift register includes: at least one control transistor and at least one control capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual control shift register has the same shape as at least a portion of the active pattern of at least one control transistor, at least a portion of at least one virtual control electrode in at least one virtual control shift register has the same shape as at least a portion of the control electrode of at least one control transistor or at least a portion of the control capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual control shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one control transistor.

18. The display substrate according to claim 16, wherein: The non-display area is further provided with a control cascade signal line, two control initial signal lines, a first control clock signal line, a second control clock signal line, three first control power lines, two second control power lines and a third control power line; Control initial signal line, first control clock signal line, second control clock signal line, first control power line, At least one of the second control power line, the third control power line, and the control cascade signal line extends along a second direction, and the first direction intersects the second direction; The first control initial signal line, the first second control power line, the second control initial signal line, the first control clock signal line, the second control clock signal line, the first first control power line, the third control power line, the second first control power line, the third first control power line and the second second control power line are arranged in sequence along the direction close to the display area.

19. The display substrate according to claim 17, wherein: The non-display area is further provided with a control cascade signal line, two control initial signal lines and a first control clock signal line, and the control shift register includes: an input end and an output end; The control cascade signal line is electrically connected to the output end of at least one level of control shift register and the input end of at least one level of control shift register respectively, and the positive projection of the control cascade signal line on the substrate is between the positive projection of the second control initial signal line on the substrate and the positive projection of the first control clock signal line on the substrate.

20. The display substrate according to claim 17, wherein The non-display area is further provided with a control cascade signal line, three first control power lines and two second control power lines; The control cascade signal line divides the area where the virtual control shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the first second control power line, and at least one virtual source-drain electrode located in the second area is connected to at least one first control power line.

21. The display substrate according to claim 18, further comprising: Drive structure layer; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The control cascade signal line is located in the fourth conductive layer, and the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the two second control power lines, and the third control power line are located in the fifth conductive layer.

22. The display substrate according to claim 3, wherein: The display area is provided with a pixel driving circuit and at least one scanning signal line, the pixel driving circuit includes: a driving transistor and a writing transistor, the writing transistor is electrically connected to the control electrode and the first electrode of the driving transistor, and the scanning signal line is electrically connected to the control electrode of the writing transistor; the multiple driving circuits include: a scanning driving circuit, the scanning driving circuit is located on the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual scanning driving circuit; The length of the scan driving circuit along a first direction is greater than or equal to the length of the dummy scan driving circuit along the first direction. The first direction is an arrangement direction of the plurality of driving circuits.

23. The display substrate according to claim 22, wherein: The scan driving circuit includes: a plurality of cascaded scan shift registers; the virtual scan driving circuit includes: at least one virtual scan shift register, and the at least one virtual scan shift register is located between adjacent scan shift registers; The scanning shift register includes: at least one scanning transistor and at least one scanning capacitor; at least one dummy shift register also includes: a plurality of dummy source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual scan shift register has the same shape as at least a portion of the active pattern of at least one scan transistor, at least a portion of at least one virtual control electrode in at least one virtual scan shift register has the same shape as at least a portion of the control electrode of at least one scan transistor or at least a portion of the scan capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual scan shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one scan transistor.

24. The display substrate according to claim 22, wherein: The non-display area is further provided with a scan cascade signal line, a scan initial signal line, a first scan clock signal line, a second scan clock signal line, a first scan power line and a second scan power line; At least one of the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line, the second scan power line, and the scan cascade signal line extends along a second direction, and the first direction intersects the second direction; The second scan power line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power line are sequentially arranged in a direction close to the display area.

25. The display substrate according to claim 23, wherein The non-display area is further provided with a scan cascade signal line, a scan initial signal line and a second scan clock signal line, and the scan shift register includes: an input end and an output end; The scan cascade signal line is electrically connected to the output end of at least one level of scan shift register and the input end of at least one level of scan shift register, respectively, and the positive projection of the scan cascade signal line on the substrate is between the positive projection of the second scan clock signal line on the substrate and the positive projection of the scan initial signal line on the substrate.

26. The display substrate according to claim 23, wherein The non-display area is further provided with a scan cascade signal line, a first scan power line and a second scan power line; The scan cascade signal line divides the area where the virtual scan shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the second scan power line, and at least one virtual source-drain electrode located in the second area is connected to the first scan power line.

27. The display substrate according to claim 24, further comprising: Drive structure layer; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The scan cascade signal line is located in the fourth conductive layer, and the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line and the second scan power line are located in the fifth conductive layer.

28. The display substrate according to claim 3, wherein: The driving circuit group includes: a scanning driving circuit, a control driving circuit, a light-emitting driving circuit and a reset driving circuit; The reset drive circuit, the control drive circuit, and the scan drive circuit located on the first side of the display area are sequentially arranged in a direction close to the display area, and the light emitting drive circuit, the control drive circuit, and the scan drive circuit located on the second side of the display area are sequentially arranged in a direction close to the display area; The scan drive circuit located on the first side of the display area and the scan drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction; the control drive circuit located on the first side of the display area and the control drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction; the reset drive circuit located on the first side of the display area and the light-emitting drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, and the second direction intersects with the first direction.

29. The display substrate according to claim 3, wherein: The driving circuit group includes: at least one transistor and at least one capacitor; the dummy driving circuit group includes: a plurality of dummy active patterns, a plurality of dummy control electrodes, and a dummy source and drain electrode; the display substrate further includes: a signal output line located in a non-display area, at least one cascade signal line, and a plurality of signal lines, the plurality of signal lines being connected to the driving circuit group and the dummy circuit group, respectively; and the signal output line being connected to the driving circuit group; The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The semiconductor layer includes at least: an active pattern of at least one transistor and at least one dummy active pattern among a plurality of dummy active patterns; The first conductive layer at least includes: a control electrode of at least one transistor, a plate of at least one capacitor, and at least one virtual active pattern among a plurality of virtual control electrodes; The second conductive layer includes at least: another plate of at least one capacitor; The third conductive layer at least includes: a signal output line; The fourth conductive layer includes: at least one signal line and a cascade signal line; The fifth conductive layer includes at least one signal line.

30. The display substrate according to claim 29, further comprising: at least one initial signal line located in the non-display area; At least one initial signal line is located on a side of at least one of the plurality of signal lines close to the display area and is located in the fifth conductive layer; An orthographic projection of at least one initial signal line on the substrate at least partially overlaps with orthographic projections of the driving circuit group and the dummy driving circuit group on the substrate.

31. A display device comprising: The display substrate according to any one of claims 1 to 30.

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