Display substrate and driving method therefor, and display device

Abstract

The present invention provides a display substrate and a driving method therefor, and a display device. The display substrate comprises a plurality of sub-pixels; each sub-pixel comprises a sub-pixel driving circuit, and the sub-pixel driving circuit comprises a driving transistor, a data writing transistor, a first capacitor, and a second capacitor; a first electrode plate of the first capacitor is coupled to a gate electrode of the driving transistor, a second electrode plate of the first capacitor is coupled to a second electrode of the data writing transistor, and a first electrode of the data writing transistor is coupled to a corresponding data line; a first electrode plate of the second capacitor is coupled to the second electrode plate of the first capacitor, and a second electrode plate of the second capacitor is coupled to a corresponding power line; and in sub-pixel driving circuits located in a same row in a first direction, second electrode plates of second capacitors comprised in the sub-pixel driving circuits are sequentially arranged in the first direction, a spacing area is provided between second electrode plates of every two adjacent second capacitors, and the orthographic projections of data lines on a base substrate at least partially overlap with the orthographic projections of the spacing areas on the base substrate.

Description

Display substrate, driving method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display products offer advantages such as high brightness and self-luminescence, making them widely used in various fields. However, current OLED display products have a low refresh rate, making them unsuitable for high-refresh-rate scenarios. To achieve high-frequency display in OLED display products, a separate sub-pixel driver circuit solution is used in OLED display products. This solution independently controls the compensation and data writing stages of the sub-pixel driver circuit. This control method achieves high-frequency display to a certain extent.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a display substrate, a driving method thereof, and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and power lines, data lines, and a plurality of sub-pixels, all disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element coupled thereto, the sub-pixel driving circuit comprising a driving transistor, a data writing transistor, a first capacitor, and a second capacitor;

[0007] The first plate of the first capacitor is coupled to the gate of the driving transistor, the second plate of the first capacitor is coupled to the second electrode of the data writing transistor, and the first electrode of the data writing transistor is coupled to the corresponding data line;

[0008] The first plate of the second capacitor is coupled to the second plate of the first capacitor, and the second plate of the second capacitor is coupled to the corresponding power line;

[0009] In the sub-pixel driving circuits located in the same row along the first direction, the second plates of the second capacitors included in each sub-pixel driving circuit are arranged sequentially along the first direction, there is a spacing area between the second plates of adjacent second capacitors, and the orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the spacing area on the base substrate.

[0010] Optionally, the second plates of the second capacitors adjacent to each other along the first direction are coupled through a plate connecting portion, and between the second plates of the adjacent second capacitors, the spacer area and the plate connecting portion are arranged along a second direction, and the second direction intersects with the first direction; the orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the plate connecting portion on the base substrate.

[0011] Optionally, the display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes a first compensation transistor and a first reset transistor; a first electrode of the first compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the first compensation transistor is coupled to a gate of the driving transistor; a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first compensation transistor includes a first compensation active layer, and the first reset transistor includes a first reset active layer;

[0012] The plate connecting portion includes a connecting main portion and a connecting extension portion coupled to each other, the connecting main portion being coupled to the second plate of the adjacent second capacitor, respectively, and an orthographic projection of the connecting extension portion on the substrate at least partially overlapping with an orthographic projection of the first compensation active layer included in one of two sub-pixel driving circuits adjacent along the first direction, and / or at least partially overlapping with an orthographic projection of the first reset active layer included in the other of two sub-pixel driving circuits adjacent along the first direction, on the substrate;

[0013] The orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the connecting main portion on the base substrate; and / or, the orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the connecting extension portion on the base substrate.

[0014] Optionally, the first compensation active layer includes two first compensation channel portions and first compensation conductor portions respectively coupled to the two first compensation channel portions; the first reset active layer includes two first reset channel portions and first reset conductor portions respectively coupled to the two first reset channel portions;

[0015] The orthographic projection of the connecting extension on the base substrate at least partially overlaps with the orthographic projection of the first compensation conductor portion included in one of the two sub-pixel driving circuits adjacent along the first direction on the base substrate, and / or at least partially overlaps with the orthographic projection of the first reset conductor portion included in the other of the two sub-pixel driving circuits adjacent along the first direction on the base substrate.

[0016] Optionally, the display substrate further includes a plurality of first reference signal connection lines and a plurality of second reference signal connection lines, and the first reference signal connection lines and the second reference signal connection lines are alternately arranged along the first direction; the orthographic projection of at least part of the data lines on the base substrate is located between the orthographic projection of the first reference signal connection line and the orthographic projection of the second reference signal connection line on the base substrate; the data lines and the first reference signal connection lines are arranged in different layers; and / or the data lines and the second reference signal connection lines are arranged in different layers.

[0017] Optionally, the display substrate also includes multiple first reference signal lines; the sub-pixel driving circuit also includes a second reset transistor, the first electrode of the second reset transistor is coupled to the corresponding first reference signal line, and the second electrode of the second reset transistor is coupled to the second plate of the first capacitor; the first reference signal connection line is coupled to multiple first reference signal lines respectively.

[0018] Optionally, the display substrate also includes multiple second reference signal lines; the sub-pixel driving circuit also includes a third reset transistor, the first electrode of the third reset transistor is coupled to the corresponding second reference signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor; the second reference signal connection line is respectively coupled to multiple second reference signal lines.

[0019] Optionally, the display substrate further includes a plurality of first initialization signal connection lines and a plurality of second initialization signal connection lines, and the first initialization signal connection lines and the second initialization signal connection lines are alternately arranged along the first direction; the orthographic projection of at least part of the data lines on the base substrate is located between the orthographic projection of the first initialization signal connection line on the base substrate and the orthographic projection of the second initialization signal connection line on the base substrate; the data line and the first initialization signal connection line are arranged in different layers; and / or the data line and the second initialization signal connection line are arranged in different layers.

[0020] Optionally, the display substrate also includes multiple first initialization signal lines; the sub-pixel driving circuit also includes a first reset transistor, the first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and the second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first initialization signal connection line is respectively coupled to multiple first initialization signal lines.

[0021] Optionally, the display substrate also includes multiple second initialization signal lines; the sub-pixel driving circuit also includes a fourth reset transistor, the first electrode of the fourth reset transistor is coupled to the corresponding second initialization signal line, and the second electrode of the fourth reset transistor is coupled to the anode of the light-emitting element; the second initialization signal connection line is respectively coupled to multiple second initialization signal lines.

[0022] Optionally, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0023] The data line is provided in the same layer and material as the third source-drain metal layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line and the second initialization signal connection line are all provided in the same layer and material as the second source-drain metal layer.

[0024] Optionally, the display substrate further includes a plurality of data line leads; the display substrate includes a plurality of data lines arranged along the first direction, and the plurality of data lines are divided into a first data line group, a second data line group, and a third data line group arranged along the first direction;

[0025] The data lines in the first data line group are coupled to corresponding data line leads, and the data line leads extend from locations where the data lines to which they are coupled are located to a middle area of ​​the display substrate, and then extend from the middle area to a lower frame area of ​​the display substrate;

[0026] The data lines in the third data line group are coupled to corresponding data line leads, which extend from the location of the coupled data lines to the middle area, and then extend from the middle area to the lower frame area.

[0027] Optionally, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0028] The data line is provided in the same layer and material as the second source-drain metal layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line and the second initialization signal connection line are all provided in the same layer and material as the third source-drain metal layer.

[0029] Optionally, the display substrate includes a light shielding layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0030] The data line is provided in the same layer and material as the light shielding layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line and the second initialization signal connection line are all provided in the same layer and material as the second source / drain metal layer.

[0031] Optionally, the display substrate further includes a plurality of power connection lines, the power connection line includes at least a portion extending along the first direction, and the power connection line is coupled to the plurality of power lines respectively.

[0032] Optionally, the power connection line includes a plurality of first power supply parts and a plurality of second power supply parts, and the first power supply parts and the second power supply parts are alternately arranged along the first direction;

[0033] The first power supply part includes a first sub-part and a second sub-part, the first sub-part is coupled to the second sub-part and the power line respectively, the adjacent second sub-part is coupled to the second power supply part, the width of the second power supply part along the second direction is greater than the width of the second sub-part, and the orthographic projection of the second power supply part on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0034] Optionally, the sub-pixel also includes a first scan line and a control signal line; the sub-pixel driving circuit also includes a first compensation transistor and a second compensation transistor, the gate of the first compensation transistor is coupled to the corresponding first scan line, the first electrode of the first compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first compensation transistor is coupled to the gate of the driving transistor; the gate of the second compensation transistor is coupled to the corresponding control signal line, the first electrode of the second compensation transistor is coupled to the corresponding power line, and the second electrode of the second compensation transistor is coupled to the first electrode of the driving transistor.

[0035] Optionally, in the same sub-pixel driving circuit, the control signal line to which the gate of the second compensation transistor is coupled is multiplexed as the first scanning line to which the gate of the first compensation transistor is coupled.

[0036] Optionally, the plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the driving transistor included in the sub-pixel driving circuit in the red sub-pixel has a first channel width-to-length ratio; the driving transistor included in the sub-pixel driving circuit in the green sub-pixel has a second channel width-to-length ratio; and the driving transistor included in the sub-pixel driving circuit in the blue sub-pixel has a third channel width-to-length ratio;

[0037] The third channel width-to-length ratio is greater than the first channel width-to-length ratio; and / or the third channel width-to-length ratio is greater than the second channel width-to-length ratio.

[0038] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0039] Based on the technical solution of the above display substrate, a third aspect of the present disclosure provides a method for driving a display substrate, for driving the above display substrate, the driving method comprising:

[0040] In the data writing phase, the data writing transistor is turned on to write the data signal transmitted by the data line into the second plate of the first capacitor, and the first capacitor couples the potential jump of its second plate to the first plate it includes.

[0041] Optionally, in the following case: the sub-pixel driving circuit further includes a first compensation transistor and a second compensation transistor, and in the same sub-pixel driving circuit, a control signal line coupled to the gate of the second compensation transistor is multiplexed as a first scan line coupled to the gate of the first compensation transistor; the driving method further includes:

[0042] During the compensation stage, the control signal transmitted by the control signal line is at a valid level, and the control signal controls the first compensation transistor and the second compensation transistor to be turned on; there is a first time interval t1 between the time when the valid level of the control signal ends and the time when the data writing transistor is controlled to be turned on, and t1 satisfies: t1≤m, where m represents a first threshold value. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0044] FIG1 is a schematic diagram of a first circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0045] FIG2 is a first driving timing diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0046] FIG3 is a schematic diagram of a second circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0047] FIG4 is a schematic diagram of a third circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0048] FIG5 is a second driving timing diagram of the sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0049] FIG6 is a schematic diagram of the active layer layout of a driving transistor in the related art;

[0050] FIG7 is a schematic diagram of a first layout of an active layer of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0051] FIG8 is a schematic diagram of a second layout of the active layer of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0052] FIG9 is a schematic diagram of a first layout of an active layer and a first gate metal layer of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0053] FIG10 is a schematic diagram of a first layout of a second gate metal layer of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0054] FIG11 is a schematic diagram of a first layout with a second gate metal layer added on the basis of FIG9 ;

[0055] FIG12 is a schematic diagram of a first layout of vias in the first source / drain metal layer and the interlayer insulating layer added on the basis of FIG11 ;

[0056] FIG13 is a schematic diagram of a first layout of vias in the first source / drain metal layer and the interlayer insulating layer added in FIG12 ;

[0057] FIG14 is a schematic diagram of a first layout in which a second source / drain metal layer and vias in the first planar layer are added on the basis of FIG12 ;

[0058] FIG15 is a schematic diagram of a first layout of vias in the second source / drain metal layer and the first planar layer added in FIG14 ;

[0059] FIG16 is a schematic cross-sectional view along the F1F2 direction in FIG14 ;

[0060] FIG17 is a schematic diagram of a second layout of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0061] FIG18 is a schematic cross-sectional view along the F3F4 direction in FIG17 ;

[0062] FIG19 is a schematic diagram of a third layout of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0063] FIG20 is a schematic cross-sectional view along the F5F6 direction in FIG19 ;

[0064] FIG21 is a schematic diagram of a fourth layout of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0065] FIG22 is a schematic diagram of the layout of the light shielding layer provided in an embodiment of the present disclosure;

[0066] FIG23 is a schematic cross-sectional view along the F7F8 direction in FIG21 ;

[0067] FIG24 is a fifth schematic diagram of a layout of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0068] FIG25 is a schematic diagram of the layout of the first source and drain metal layer in FIG24;

[0069] FIG26 is a schematic diagram of a third layout of the active layer of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0070] FIG27 is a schematic diagram of a layout in which a first gate metal layer is added on the basis of FIG26;

[0071] FIG28 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG27;

[0072] FIG29 is a schematic diagram showing a layout of vias in the first source / drain metal layer and the interlayer insulating layer added on the basis of FIG28;

[0073] FIG30 is a schematic diagram showing a layout of vias in the second source / drain metal layer and the first planar layer added on the basis of FIG29;

[0074] FIG31 is a schematic diagram of the layout of the second source / drain metal layer and the via holes in the first planar layer added in FIG30 ;

[0075] FIG32 is a schematic diagram of a fourth layout of the active layer of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0076] FIG33 is a schematic diagram of a fifth layout of the active layer of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0077] FIG34 is a schematic diagram of the layout of data lines and data line leads provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] In order to further illustrate the display substrate and its driving method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0079] An embodiment of the present disclosure provides a display substrate, which includes a plurality of sub-pixels. The sub-pixels include a sub-pixel driving circuit and a light-emitting element coupled to each other.

[0080] As shown in FIG. 1 , illustratively, the sub-pixel driving circuit adopts a 9T2C circuit structure (including 9 transistors and 2 capacitors), but is not limited thereto.

[0081] The display substrate further includes: a first reference signal line Vref1, a second reference signal line Vref2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a power line VDD, a data line DA, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a first scan line Scan1, a second scan line Scan2, a third scan line Scan3 and a fourth scan line Scan4.

[0082] The 9T2C circuit structure includes: a data writing transistor T1, a first compensation transistor T2, a driving transistor T3, a first reset transistor T4, a power control transistor T5, a light emitting control transistor T6, a second reset transistor T7, a third reset transistor T9, a fourth reset transistor T8, a first capacitor C1 and a second capacitor C2.

[0083] The gate of the data writing transistor T1 is coupled to the corresponding fourth scan line Scan4, the first electrode of the data writing transistor T1 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T1 is coupled to the second plate C12 of the first capacitor C1.

[0084] The gate of the first compensation transistor T2 is coupled to the corresponding first scan line Scan1, the first electrode of the first compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the first compensation transistor T2 is coupled to the gate T3-g (N1 node) of the driving transistor T3.

[0085] The gate of the first reset transistor T4 is coupled to the corresponding second scan line Scan2, the first electrode of the first reset transistor T4 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T4 is coupled to the gate T3-g of the driving transistor T3.

[0086] The gate of the power control transistor T5 is coupled to the corresponding first light emitting control signal line EM1, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0087] The gate of the light-emitting control transistor T6 is coupled to the corresponding second light-emitting control signal line EM2, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light-emitting control transistor T6 is coupled to the anode of the light-emitting element.

[0088] A gate of the second reset transistor T7 is coupled to the corresponding first scan line Scan1 , a first electrode of the second reset transistor T7 is coupled to the corresponding first reference signal line Vref1 , and a second electrode of the second reset transistor T7 is coupled to the second plate C12 of the first capacitor C1 .

[0089] A gate of the third reset transistor T9 is coupled to the corresponding third scan line Scan3 , a first electrode of the third reset transistor T9 is coupled to the corresponding second reference signal line Vref2 , and a second electrode of the third reset transistor T9 is coupled to the first electrode of the driving transistor T3 .

[0090] The gate of the fourth reset transistor T8 is coupled to the corresponding third scan line Scan3, the first electrode of the fourth reset transistor T8 is coupled to the corresponding second initialization signal line Vinit2, and the second electrode of the fourth reset transistor T8 is coupled to the anode of the light-emitting element. The cathode of the light-emitting element receives the negative power signal line VSS.

[0091] The first plate C11 of the first capacitor C1 is coupled to the gate T3-g of the driving transistor T3, the second plate C12 of the first capacitor C1 is coupled to the first plate C21 of the second capacitor C2, and the second plate C22 of the second capacitor C2 is coupled to the corresponding power line VDD.

[0092] As shown in FIG2 , the driving method of the sub-pixel driving circuit includes: a first reset phase A, a compensation phase B, a data writing phase C, a second reset phase D and a light emitting phase E.

[0093] In the first reset stage A, the second scan signal transmitted by the second scan line Scan2 is at an effective level, the first reset transistor T4 is turned on, and the gate T3-g of the driving transistor T3 is reset, so that the voltage value of the gate T3-g of the driving transistor T3 is the same as the voltage value of the first initialization signal transmitted by the first initialization signal line Vinit1, and the driving transistor T3 is turned on.

[0094] In the compensation stage B, the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 is at an effective level, the first scanning signal transmitted by the first scanning line Scan1 is at an effective level, the second reset transistor T7, the compensation transistor and the power control transistor T5 are all turned on. At this time, the voltage value of the second plate C12 of the first capacitor C1 is the same as the voltage value of the first reference signal transmitted by the first reference signal line Vref1. In this stage, the power signal transmitted by the power line VDD is written into the gate T3-g of the driving transistor T3. When the potential of the gate T3-g of the driving transistor T3 becomes Vdd+Vth, the driving transistor T3 is turned off and the compensation ends; Vdd represents the voltage value of the power signal, and Vth represents the threshold voltage of the driving transistor T3.

[0095] In the data writing phase C, the fourth scanning signal transmitted by the fourth scanning line Scan4 is at a valid level, and the data writing transistor T1 is turned on. At this time, the voltage value of the second plate C12 of the first capacitor C1 becomes Vdata, where Vdata represents the voltage value of the data signal transmitted by the data line DA. The voltage jump value of the second plate C12 of the first capacitor C1 is Vdata-V1, where V1 represents the voltage value of the first reference signal. The voltage of the gate T3-g of the driving transistor T3 is Vdd+Vth+Vdata-V1.

[0096] In the second reset stage D, the third scan signal transmitted by the third scan line Scan3 is at an effective level, the third reset transistor T9 and the fourth reset transistor T8 are turned on, and the first electrode of the driving transistor T3 and the anode of the light emitting element are reset.

[0097] In the light-emitting stage E, the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 is at an effective level, the second light-emitting control signal transmitted by the second light-emitting control signal line EM2 is at an effective level, the power control transistor T5 and the light-emitting control transistor T6 are both turned on, the gate-source voltage Vgs of the driving transistor T3 satisfies: Vgs=Vth+Vdata-V1, the light-emitting element emits light, and the leakage current generated is k / 2(Vdata-V1). 2 .

[0098] Between the compensation stage and the data writing stage, there is a floating stage in which no signal is written (such as the solid line frame in Figure 2). During this stage, no signal is written to the N1 node, and the potential of the N1 node is easily disturbed by the data signal (for example, the data signal line can affect the potential of the N1 node by affecting the first capacitor C1), and is recorded in the N1 node, thereby affecting the display effect. In more detail, the conventional sub-pixel driving circuit does not have the above problem, because the fluctuation of the data signal in one light-emitting cycle will be recorded in the compensation process, and the integral of the data signal change has little effect on the potential of the N1 node. In the separate circuit, after the compensation is completed, the instantaneous change of the data signal will be recorded in the N1 node, so the impact is greater.

[0099] To reduce the impact of the data signal on the potential of node N1 during the floating phase, a functional layer with a constant potential is considered around the data line DA to reduce the impact of data signal transitions on node N1. However, while this approach reduces the impact of the data signal on node N1, it also increases the loading of the data line DA, causing the potential at the far end of the data line DA to drop, thus affecting the display uniformity of the display product.

[0100] Referring to Figures 3, 7 to 16, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a power line VDD, a data line DA, and a plurality of sub-pixels, all disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element coupled thereto, the sub-pixel driving circuit comprising a driving transistor T3, a data writing transistor T1, a first capacitor C1, and a second capacitor C2;

[0101] The first plate C11 of the first capacitor C1 is coupled to the gate T3-g of the driving transistor T3, the second plate C12 of the first capacitor C1 is coupled to the second electrode of the data writing transistor T1, and the first electrode of the data writing transistor T1 is coupled to the corresponding data line DA;

[0102] The first plate C21 of the second capacitor C2 is coupled to the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 is coupled to the corresponding power line VDD;

[0103] In the sub-pixel driving circuits located in the same row along the first direction, the second plates C22 of the second capacitors C2 included in each sub-pixel driving circuit are arranged sequentially along the first direction, and there is a spacing area J1 between the second plates C22 of adjacent second capacitors C2. The orthographic projection of the data line DA on the base substrate at least partially overlaps with the orthographic projection of the spacing area J1 on the base substrate.

[0104] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0105] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0106] Exemplarily, the display substrate includes a plurality of power lines VDD and a plurality of data lines DA. The plurality of power lines VDD are sequentially arranged along the first direction, and the power lines VDD include at least a portion extending along the second direction. The plurality of data lines DA are arranged along the first direction, and the data lines DA include at least a portion extending along the second direction.

[0107] Exemplarily, the plurality of power lines VDD correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the power lines VDD are respectively coupled to the sub-pixel driving circuits in the corresponding column. The plurality of data lines DA correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the data lines DA are respectively coupled to the sub-pixel driving circuits in the corresponding column.

[0108] Illustratively, an orthographic projection of the first plate C11 of the first capacitor C1 on the substrate at least partially overlaps with an orthographic projection of the second plate C12 of the first capacitor C1 on the substrate. An orthographic projection of the first plate C21 of the second capacitor C2 on the substrate at least partially overlaps with an orthographic projection of the second plate C22 of the second capacitor C2 on the substrate.

[0109] Exemplarily, the first plate C11 of the first capacitor C1 is reused as the gate T3 - g of the driving transistor T3 , but the present invention is not limited thereto.

[0110] Exemplarily, the width of the spacing region J1 along the second direction is less than or equal to the width of the second electrode C22 of the second capacitor C2.

[0111] For example, as shown in Figures 6 and 7, Figure 6 illustrates a schematic layout diagram of the driving active layer 23' included in the driving transistor T3 in the related art. Figure 7 illustrates a schematic layout diagram of the driving active layer 23 included in the driving transistor T3 in the present application. By comparison, it is found that the driving active layer 23 in the present application protrudes toward the light-emitting control active layer 26 and the power control active layer 25, which helps to reduce the overall layout space occupied by the active layer in the sub-pixel driving circuit, thereby facilitating the development of high-resolution display substrates.

[0112] For example, as shown in Figures 7 and 8, in Figure 7, one end of the second reset active layer 27 (the end coupled to the first reference signal line) included in each sub-pixel driving circuit located in the same row along the first direction is formed into an integrated structure. This configuration can reduce the number of connecting vias used to connect the first reference signal line and one end of the second reset active layer 27, thereby helping to reduce the layout space occupied by the sub-pixel driving circuit. In Figure 8, the second reset active layers 27 included in each sub-pixel driving circuit located in the same row along the first direction are separated from each other. This configuration allows one end of each second reset active layer 27 to be connected to the first reference signal line through a connecting via.

[0113] For example, as shown in FIG. 3 and FIG. 12 to FIG. 14 , a parasitic capacitor C3 is formed between the second conductive connection portion 32 and the power line VDD, which greatly improves the stability of the second conductive connection portion 32 and the structures coupled thereto.

[0114] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, a functional layer with a constant potential is provided around the data line DA to reduce the influence of the data signal jump on the N1 node. By setting the orthographic projection of the data line DA on the base substrate and the orthographic projection of the spacer area J1 on the base substrate to at least partially overlap, the overlapping area between the orthographic projection of the data line DA on the base substrate and the orthographic projection of the second plate C22 of the second capacitor C2 on the base substrate is reduced, thereby achieving the goal of reducing the loading of the data line DA while reducing the influence of the data signal on the N1 node, thereby avoiding the low potential at the far end of the data line DA and ensuring the display uniformity of the display product.

[0115] As shown in Figures 9 to 16, in some embodiments, the second plates C22 of the second capacitors C2 adjacent to each other along the first direction are coupled through the plate connecting portion 10, and between the second plates C22 of adjacent second capacitors C2, the spacer J1 and the plate connecting portion 10 are arranged along a second direction, and the second direction intersects with the first direction; the orthographic projection of the data line DA on the base substrate at least partially overlaps with the orthographic projection of the plate connecting portion 10 on the base substrate.

[0116] Illustratively, the plate connecting portion 10 and the second plate C22 of the second capacitor C2 coupled thereto form an integrated structure, but the present invention is not limited thereto.

[0117] Illustratively, the greater the width of the portion of the plate connecting portion 10 located between the adjacent second plates C22 of the second capacitor C2 along the first direction, the smaller the width of the spacer J1 along the first direction; the smaller the width of the portion of the plate connecting portion 10 located between the adjacent second plates C22 of the second capacitor C2 along the first direction, the greater the width of the spacer J1 along the first direction.

[0118] In the display substrate provided in the above embodiment, the second plate C22 of the second capacitor C2 is coupled to the power line VDD, and the second plates C22 of the second capacitors C2 adjacent to each other along the first direction are connected together through the plate connecting portion 10, so that the second plates C22 of the second capacitor C2 can form a grid structure together with the power line VDD. The grid structure is used to transmit a power signal with a stable potential, which is beneficial to reducing the loading of the power line VDD and improving the uniformity of the power signal.

[0119] As shown in Figures 7 to 16, in some embodiments, the display substrate further includes a first initialization signal line Vinit1; the sub-pixel driving circuit further includes a first compensation transistor T2 and a first reset transistor T4; a first electrode of the first compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and a second electrode of the first compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3; a first electrode of the first reset transistor T4 is coupled to the corresponding first initialization signal line Vinit1, and a second electrode of the first reset transistor T4 is coupled to the gate T3-g of the driving transistor T3; the first compensation transistor T2 includes a first compensation active layer 22, and the first reset transistor T4 includes a first reset active layer 24;

[0120] The plate connecting portion 10 includes a connecting main body portion 101 and a connecting extension portion 102 coupled to each other, the connecting main body portion 101 being respectively coupled to the second plate C22 of the adjacent second capacitor C2, and the orthographic projection of the connecting extension portion 102 on the substrate at least partially overlaps with the orthographic projection of the first compensation active layer 22 included in one of the two sub-pixel driving circuits adjacent along the first direction on the substrate, and / or at least partially overlaps with the orthographic projection of the first reset active layer 24 included in the other of the two sub-pixel driving circuits adjacent along the first direction on the substrate.

[0121] Exemplarily, the first compensation active layer 22 includes two first compensation channel portions and first compensation conductor portions respectively coupled to the two first compensation channel portions; the first reset active layer 24 includes two first reset channel portions and first reset conductor portions respectively coupled to the two first reset channel portions; the orthographic projection of the connecting extension portion 102 on the substrate at least partially overlaps with the orthographic projection of the first compensation conductor portion included in one of two sub-pixel driving circuits adjacent along the first direction on the substrate, and / or at least partially overlaps with the orthographic projection of the first reset conductor portion included in the other of two sub-pixel driving circuits adjacent along the first direction on the substrate.

[0122] In the display substrate provided in the above embodiment, the first compensation transistor T2 and / or the first reset transistor T4 both include dual-gate transistors, and the connection extension portion 102 can shield the corresponding conductor portions included in the first compensation transistor T2 and / or the first reset transistor T4, thereby ensuring the operating stability of the first compensation transistor T2 and / or the first reset transistor T4.

[0123] As shown in Figure 14, in some embodiments, the orthographic projection of the data line DA on the base substrate is set to at least partially overlap with the orthographic projection of the connecting main body portion 101 on the base substrate; and / or, the orthographic projection of the data line DA on the base substrate is set to at least partially overlap with the orthographic projection of the connecting extension portion 102 on the base substrate.

[0124] Illustratively, the connecting main portion 101 and the connecting extension portion 102 form an integrated structure, and the connecting main portion 101 is located between the second plates C22 of adjacent second capacitors C2.

[0125] Because both the connecting main portion 101 and the connecting extension portion 102 have stable potentials, this configuration helps reduce the impact of data signal transitions on node N1. Furthermore, by providing a spacer J1 between the second plates C22 of adjacent second capacitors C2, the orthographic projection of the data line DA on the substrate at least partially overlaps with the orthographic projection of the spacer J1 on the substrate. This reduces the impact of the data signal on node N1 while also reducing the loading of the data line DA. This prevents the potential at the far end of the data line DA from decreasing, ensuring display uniformity across the display product.

[0126] As shown in Figures 10 to 15, in some embodiments, the display substrate further includes a plurality of first reference signal connection lines Vref1' and a plurality of second reference signal connection lines Vref2', and the first reference signal connection lines Vref1' and the second reference signal connection lines Vref2' are alternately arranged along the first direction; the orthographic projection of at least part of the data line DA on the base substrate is located between the adjacent orthographic projections of the first reference signal connection lines Vref1' on the base substrate and the orthographic projections of the second reference signal connection lines Vref2' on the base substrate.

[0127] Exemplarily, the first reference signal connection line Vref1 ′ is used to transmit a first reference signal having a stable voltage, and the second reference signal connection line Vref2 ′ is used to transmit a second reference signal having a stable voltage.

[0128] Exemplarily, the plurality of first reference signal connection lines Vref1' are arranged along the first direction, and the first reference signal connection lines Vref1' include at least a portion extending along the second direction. The plurality of second reference signal connection lines Vref2' are arranged along the first direction, and the second reference signal connection lines Vref2' include at least a portion extending along the second direction.

[0129] In the display substrate provided by the above embodiment, by arranging the orthographic projection of at least a portion of the data line DA on the base substrate, it is located between the orthographic projection of the adjacent first reference signal connection line Vref1' and the orthographic projection of the second reference signal connection line Vref2' on the base substrate; so that signal lines for transmitting stable signals are provided on both sides of the data line DA, which is beneficial to reducing the impact of data signal jumps on the N1 node.

[0130] Exemplarily, the data line DA and the first reference signal connection line Vref1 ' are provided at the same layer; or the data line DA and the first reference signal connection line Vref1 ' are provided at different layers;

[0131] Exemplarily, the data line DA and the second reference signal connection line Vref2 ′ are provided at the same layer; or, the data line DA and the second reference signal connection line Vref2 ′ are provided at different layers.

[0132] Exemplarily, the data line DA and the first reference signal connection line Vref1 ′ are provided at different layers; and / or the data line DA and the second reference signal connection line Vref2 ′ are provided at different layers.

[0133] The above configuration can reduce the impact of data signal transitions on the N1 node while flexibly laying out the first reference signal connection line Vref1 ′ and the second reference signal connection line Vref2 ′, thereby effectively reducing the layout difficulty of the display substrate.

[0134] As shown in Figures 10 to 15, in some embodiments, the display substrate further includes multiple first reference signal lines Vref1; the sub-pixel driving circuit further includes a second reset transistor T7, a first electrode of the second reset transistor T7 is coupled to the corresponding first reference signal line Vref1, and a second electrode of the second reset transistor T7 is coupled to the second plate C12 of the first capacitor C1; the first reference signal connection line Vref1' is coupled to multiple first reference signal lines Vref1 respectively.

[0135] Exemplarily, the plurality of first reference signal lines Vref1 are arranged along the second direction, and the first reference signal lines Vref1 include at least a portion extending along the first direction. The plurality of first reference signal lines Vref1 correspond one-to-one to multiple rows of sub-pixel driving circuits, and the first reference signal line Vref1 is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0136] The above-mentioned setting of coupling the first reference signal connection line Vref1' with multiple first reference signal lines Vref1 respectively enables the first reference signal connection line Vref1' to form a grid structure with the first reference signal line Vref1, thereby helping to reduce the loading of the first reference signal line Vref1 and ensure the uniformity of the first reference signal it transmits.

[0137] As shown in Figures 10 to 15, in some embodiments, the display substrate further includes a plurality of second reference signal lines Vref2; the sub-pixel driving circuit further includes a third reset transistor T9, a first electrode of the third reset transistor T9 is coupled to the corresponding second reference signal line Vref2, and a second electrode of the third reset transistor T9 is coupled to the first electrode of the driving transistor T3; the second reference signal connection line Vref2' is respectively coupled to a plurality of second reference signal lines Vref2.

[0138] Illustratively, the plurality of second reference signal lines Vref2 are arranged along the second direction, and the second reference signal lines Vref2 include at least a portion extending along the first direction. The plurality of second reference signal lines Vref2 correspond one-to-one to multiple rows of sub-pixel driving circuits, and the second reference signal lines Vref2 are respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0139] The above-mentioned arrangement of coupling the second reference signal connection line Vref2' to a plurality of second reference signal lines Vref2 respectively enables the second reference signal connection line Vref2' to form a grid structure with the second reference signal line Vref2, thereby facilitating reduction of the loading of the second reference signal line Vref2 and ensuring uniformity of the second reference signal transmitted thereby.

[0140] As shown in Figures 10 to 15, in some embodiments, the display substrate further includes a plurality of first initialization signal connection lines Vinit1' and a plurality of second initialization signal connection lines Vinit2', and the first initialization signal connection lines Vinit1' and the second initialization signal connection lines Vinit2' are alternately arranged along the first direction; the orthographic projection of at least part of the data line DA on the base substrate is located between the orthographic projection of the adjacent first initialization signal connection line Vinit1' on the base substrate and the orthographic projection of the second initialization signal connection line Vinit2' on the base substrate; the data line DA and the first initialization signal connection line Vinit1' are arranged in different layers; and / or the data line DA and the second initialization signal connection line Vinit2' are arranged in different layers.

[0141] Exemplarily, the first initialization signal connection line Vinit1 ′ is used to transmit a first initialization signal having a stable voltage, and the second initialization signal connection line Vinit2 ′ is used to transmit a second initialization signal having a stable voltage.

[0142] Exemplarily, the plurality of first initialization signal connection lines Vinit1' are arranged along the first direction, and the first initialization signal connection line Vinit1' includes at least a portion extending along the second direction. The plurality of second initialization signal connection lines Vinit2' are arranged along the first direction, and the second initialization signal connection line Vinit2' includes at least a portion extending along the second direction.

[0143] In the display substrate provided by the above embodiment, by arranging the orthographic projection of at least a portion of the data line DA on the base substrate, it is located between the orthographic projection of the adjacent first initialization signal connection line Vinit1' and the orthographic projection of the second initialization signal connection line Vinit2' on the base substrate; so that signal lines for transmitting stable signals are provided on both sides of the data line DA, which is beneficial to reducing the impact of data signal jumps on the N1 node.

[0144] Exemplarily, the data line DA and the first initialization signal connection line Vinit1 ' are provided at the same layer; or the data line DA and the first initialization signal connection line Vinit1 ' are provided at different layers;

[0145] Exemplarily, the data line DA and the second initialization signal connection line Vinit2 ′ are provided at the same layer; or, the data line DA and the second initialization signal connection line Vinit2 ′ are provided at different layers.

[0146] Exemplarily, the data line DA and the first initialization signal connection line Vinit1 ′ are provided at different layers; and / or the data line DA and the second initialization signal connection line Vinit2 ′ are provided at different layers.

[0147] The above configuration can reduce the impact of data signal transitions on the N1 node while flexibly laying out the first initialization signal connection line Vinit1 ′ and the second initialization signal connection line Vinit2 ′, thereby effectively reducing the layout difficulty of the display substrate.

[0148] As shown in Figures 10 to 15, in some embodiments, the display substrate further includes multiple first initialization signal lines Vinit1; the sub-pixel driving circuit further includes a first reset transistor T4, the first electrode of the first reset transistor T4 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T4 is coupled to the gate T3-g of the driving transistor T3; the first initialization signal connection line Vinit1' is respectively coupled to multiple first initialization signal lines Vinit1.

[0149] Exemplarily, the plurality of first initialization signal lines Vinit1 are arranged along the second direction, and the first initialization signal line Vinit1 includes at least a portion extending along the first direction. The plurality of first initialization signal lines Vinit1 correspond one-to-one to multiple rows of sub-pixel driver circuits, and the first initialization signal line Vinit1 is respectively coupled to each sub-pixel driver circuit in a corresponding row of sub-pixel driver circuits.

[0150] The above-mentioned setting couples the first initialization signal connection line Vinit1' with multiple first initialization signal lines Vinit1 respectively, so that the first initialization signal connection line Vinit1' can form a grid structure with the first initialization signal line Vinit1, which is beneficial to reduce the loading of the first initialization signal line Vinit1 and ensure the uniformity of the first initialization signal it transmits.

[0151] As shown in Figures 10 to 15, in some embodiments, the display substrate further includes multiple second initialization signal lines Vinit2; the sub-pixel driving circuit further includes a fourth reset transistor T8, the first electrode of the fourth reset transistor T8 is coupled to the corresponding second initialization signal line Vinit2, and the second electrode of the fourth reset transistor T8 is coupled to the anode of the light-emitting element; the second initialization signal connection line Vinit2' is respectively coupled to multiple second initialization signal lines Vinit2.

[0152] Exemplarily, the plurality of second initialization signal lines Vinit2 are arranged along the second direction, and the second initialization signal lines Vinit2 include at least a portion extending along the first direction. The plurality of second initialization signal lines Vinit2 correspond one-to-one to multiple rows of sub-pixel driver circuits, and the second initialization signal lines Vinit2 are respectively coupled to each sub-pixel driver circuit in a corresponding row of sub-pixel driver circuits.

[0153] The above-mentioned setting of the second initialization signal connection line Vinit2' is coupled to multiple second initialization signal lines Vinit2 respectively, so that the second initialization signal connection line Vinit2' can form a grid structure with the second initialization signal line Vinit2, which is beneficial to reducing the loading of the second initialization signal line Vinit2 and ensuring the uniformity of the second initialization signal it transmits.

[0154] As shown in Figures 10 to 15, in some embodiments, the plurality of first reference signal connection lines Vref1' and the plurality of second reference signal connection lines Vref2' are divided into a plurality of reference signal connection line groups arranged along a first direction, each reference signal connection line group including one first reference signal connection line Vref1' and one second reference signal connection line Vref2'. The plurality of first initialization signal connection lines Vinit1' and the plurality of second initialization signal connection lines Vinit2' are divided into a plurality of initialization signal connection line groups arranged along the first direction, each initialization signal connection line group including one first initialization signal connection line Vinit1' and one second initialization signal connection line Vinit2'. The reference signal connection line groups and the initialization signal connection line groups are alternately arranged along the first direction.

[0155] Exemplarily, a portion of the data lines DA in the display substrate corresponds one-to-one to the multiple groups of reference signal connection line groups, and the orthographic projections of the data lines DA on the base substrate are located between the orthographic projections of the first reference signal connection line Vref1' and the second reference signal connection line Vref2' in the corresponding group of reference signal connection line on the base substrate. Exemplarily, another portion of the data lines DA in the display substrate corresponds one-to-one to the multiple groups of initialization signal connection line groups, and the orthographic projections of the data lines DA on the base substrate are located between the orthographic projections of the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2' in the corresponding group of initialization signal connection line on the base substrate.

[0156] The above configuration can reduce the loading of the first reference signal line Vref1, the second reference signal line Vref2, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 while more reasonably planning the layout space of the display substrate, thereby reducing the layout difficulty of the display substrate.

[0157] As shown in FIG17 and FIG18 , in some embodiments, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0158] The data line DA is provided in the same layer and material as the third source-drain metal layer, and the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2' are all provided in the same layer and material as the second source-drain metal layer.

[0159] Exemplarily, the display substrate includes a light-shielding layer LS, an insulating layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a first planarizing layer, a second source-drain metal layer, a second planarizing layer, a third source-drain metal layer, a third planarizing layer, an anode layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, etc. The display substrate may further include a passivation layer, but is not limited thereto.

[0160] This arrangement enables the data line DA to be formed simultaneously with the third source / drain metal layer during the same patterning process; the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1', and the second initialization signal connection line Vinit2' to be formed simultaneously with the second source / drain metal layer during the same patterning process; thereby effectively simplifying the display substrate manufacturing process and reducing the display substrate manufacturing cost. Furthermore, this arrangement increases the distance between the data line DA and the N1 node, effectively shielding the N1 node from the effects of data signal transitions.

[0161] As shown in FIG34 , in some embodiments, the display substrate further includes a plurality of data line leads DA′; the display substrate includes a plurality of data lines DA arranged along the first direction, and the plurality of data lines DA are divided into a first data line group, a second data line group, and a third data line group arranged along the first direction;

[0162] The data line DA in the first data line group is coupled to a corresponding data line lead DA', and the data line lead DA' extends from the location where the data line DA is coupled to the data line to the middle area of ​​the display substrate, and then extends from the middle area to the lower frame area of ​​the display substrate;

[0163] The data lines DA in the third data line group are coupled to corresponding data line leads DA'. The data line leads DA' extend from the location of the coupled data lines DA to the middle area, and then extend from the middle area to the lower frame area.

[0164] Exemplarily, the data line lead DA′ and the data line DA are provided in different layers.

[0165] Exemplarily, the display substrate includes a display area and a peripheral area located around the display area, the peripheral area including an upper frame area, a lower frame area, a left frame area and a right frame area; the first group of data line groups is close to the left frame area, and the third group of data line groups is close to the right frame area.

[0166] The above-mentioned setting method enables the data lines DA near the left border area and the right border area of ​​the display substrate to be coupled to the driving chip in the display substrate through the data line leads DA', avoiding the data lines DA near the left border area and the right border area of ​​the display substrate to be directly extended to the lower border area through the fan-out lines, thereby effectively narrowing the width of the lower border area of ​​the display substrate.

[0167] As shown in FIG19 and FIG20 , in some embodiments, the display substrate includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0168] The data line DA is provided in the same layer and material as the second source-drain metal layer, and the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2' are all provided in the same layer and material as the third source-drain metal layer.

[0169] The above-mentioned setting method enables the data line DA to be formed simultaneously with the second source-drain metal layer in the same patterning process; the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2' can all be formed simultaneously with the third source-drain metal layer in the same patterning process; thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0170] As shown in FIG21 to FIG23 , in some embodiments, the display substrate includes a light shielding layer LS, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0171] The data line DA is provided in the same layer and material as the light shielding layer LS, and the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2' are all provided in the same layer and material as the second source and drain metal layer.

[0172] Exemplarily, the light shielding layer LS is also used to shield the driving transistor T3 , thereby stabilizing the driving transistor T3 .

[0173] The above-mentioned setting method enables the data line DA to be formed simultaneously with the light-shielding layer LS in the same patterning process; the first reference signal connection line Vref1', the second reference signal connection line Vref2', the first initialization signal connection line Vinit1' and the second initialization signal connection line Vinit2' can all be formed simultaneously with the second source-drain metal layer in the same patterning process; thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0174] The above configuration method arranges the data line DA and the light shielding layer LS in the same layer and with the same material, which is beneficial to reducing the layout space occupied by the sub-pixels, thereby improving the resolution of the display substrate.

[0175] As shown in FIG. 13 to FIG. 15 , in some embodiments, the display substrate further includes a plurality of power connection lines VDD′, each of the power connection lines VDD′ including at least a portion extending along the first direction, and the power connection line VDD′ is respectively coupled to the plurality of power lines VDD.

[0176] Exemplarily, the power connection line VDD′ is provided in the same layer and made of the same material as the first source / drain metal layer, but is not limited thereto.

[0177] Exemplarily, the plurality of power connection lines VDD′ are arranged along the second direction.

[0178] The power connection line VDD′ is coupled to a plurality of power lines VDD respectively, so that the power connection line VDD′ and the power supply form a grid structure, thereby reducing the loading of the power line VDD and improving the uniformity of the power signal.

[0179] As shown in FIG24 and FIG25 , in some embodiments, the power connection line VDD′ includes a plurality of first power portions VDD1′ and a plurality of second power portions VDD2′, and the first power portions VDD1′ and the second power portions VDD2′ are alternately arranged along the first direction;

[0180] The first power supply part VDD1' includes a first sub-part VDD11' and a second sub-part VDD12'. The first sub-part VDD11' is coupled to the second sub-part VDD12' and the power line VDD, respectively. The adjacent second sub-part VDD12' is coupled to the second power supply part VDD2'. The width of the second power supply part VDD2' along the second direction is greater than the width of the second sub-part VDD12'. The orthographic projection of the second power supply part VDD2' on the base substrate at least partially overlaps with the orthographic projection of the data line DA on the base substrate.

[0181] Exemplarily, the first power supply part VDD1 ′ and the second power supply part VDD2 ′ are formed into an integrated structure.

[0182] Exemplarily, the first sub-portion VDD11 ′ extends along the second direction, but is not limited thereto.

[0183] The above configuration widens the power line VDD' near the area where it overlaps with the data line DA, further reducing the impact of data signal changes on the N1 node, while also further reducing the loading of the power line VDD and improving the uniformity of the power signal.

[0184] As shown in Figures 3, 4, 5, 26 to 31, in some embodiments, the sub-pixel further includes a first scan line Scan1 and a control signal line GC; the sub-pixel driving circuit further includes a first compensation transistor T2 and a second compensation transistor T10, the gate of the first compensation transistor T2 is coupled to the corresponding first scan line Scan1, the first electrode of the first compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the first compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3; the gate of the second compensation transistor T10 is coupled to the corresponding control signal line GC, the first electrode of the second compensation transistor T10 is coupled to the corresponding power line VDD, and the second electrode of the second compensation transistor T10 is coupled to the first electrode of the driving transistor T3.

[0185] Exemplarily, in the same sub-pixel driving circuit, the control signal line GC to which the gate of the second compensation transistor T10 is coupled is multiplexed as the first scan line Scan1 to which the gate of the first compensation transistor T2 is coupled.

[0186] To be more specific, the main reason why the data signal change affects the N1 node is that there is a floating stage between the compensation stage and the data writing stage. If the compensation time is simply increased, it is necessary to adjust the turn-on duration (i.e., the effective level duration) of the first light-emitting control signal transmitted by the first light-emitting control signal line EM1. This adjustment method will easily increase the pulse of the first light-emitting control signal, increase the loading of the first light-emitting control signal, affect the turn-on sensitivity of the remote first light-emitting control signal, and cause uneven display.

[0187] In the display substrate provided by the above embodiment, a control signal line GC and a second compensation transistor T10 are added. The control signal line GC is configured to control the first compensation transistor T2 and the second compensation transistor T10. During the compensation phase, the control signal transmitted by the control signal line GC is at an effective level, and the control signal controls the first compensation transistor T2 and the second compensation transistor T10 to be turned on. There is a first time interval t1 between the time when the effective level of the control signal ends and the time when the data write transistor T1 is turned on. t1 satisfies the following: t1 ≤ m, where m represents a first threshold. The above configuration allows the effective level of the control signal to cover the compensation phase and at least part of the floating phase, thereby improving the impact of data signal changes on the N1 node. More specifically, the above configuration is equivalent to extending the duration of the compensation phase and shortening the duration of the floating phase.

[0188] In the display substrate provided by the above embodiment, the influence of data signal changes on the N1 node is improved by adding the control signal line GC and the second compensation transistor T10. There is no need to adjust the turn-on duration of the first light-emitting control signal transmitted by the first light-emitting control signal line EM1, thereby ensuring the turn-on sensitivity of the first light-emitting control signal and the display uniformity of the display substrate.

[0189] It should be noted that, when t1≤m, t1 can be negative, that is, the compensation phase and the data writing phase can partially overlap. The value of the first threshold must be sufficient to reduce the impact of data signal changes on the N1 node.

[0190] The T10 transistor is added without adding an extra mask, and the addition of this transistor does not increase the process difficulty. T10 and T2 are controlled by the same gate line.

[0191] As shown in FIG32 and FIG33 , in some embodiments, the plurality of sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The driving transistor T3 included in the sub-pixel driving circuit of the red sub-pixel has a first channel width-to-length ratio, the driving transistor T3 included in the sub-pixel driving circuit of the green sub-pixel has a second channel width-to-length ratio, and the driving transistor T3 included in the sub-pixel driving circuit of the blue sub-pixel has a third channel width-to-length ratio.

[0192] The third channel width-to-length ratio is set to be greater than the first channel width-to-length ratio; and / or the third channel width-to-length ratio is set to be greater than the second channel width-to-length ratio.

[0193] Since the luminous efficiency of the blue sub-pixel is relatively low, the above configuration enables the blue sub-pixel to have a larger driving current, effectively improving the brightness of the blue sub-pixel and enhancing the uniformity of the display substrate.

[0194] In more detail, as shown in Figures 6 and 7, the data write active layer 21 included in the data write transistor T1, the first compensation active layer 22 included in the first compensation transistor T2, the driving active layer 23 included in the driving transistor T3, the first reset active layer 24 included in the first reset transistor T4, the power control active layer 25 included in the power control transistor T5, the light emission control active layer 26 included in the light emission control transistor T6, the second reset active layer 27 included in the second reset transistor T7, the third reset active layer 29 included in the third reset transistor T9, and the fourth reset active layer 28 included in the fourth reset transistor T8 are schematically shown. As shown in Figure 26, the second compensation active layer 20 included in the second compensation transistor T10 is also schematically shown. By way of example, the above active layers all use low-temperature polycrystalline silicon (LTPS) active layers, but are not limited thereto.

[0195] Exemplarily, the driving active layer 23 included in the driving transistor T3 adopts an inverted "X"-shaped structure. This channel design is beneficial to reducing the area occupied by the sub-pixel driving circuit. For high refresh rate display products, an important application scenario is to reduce the size occupied by the sub-pixel driving circuit. This design can improve the display resolution.

[0196] As shown in Figures 9 and 27, the first gate metal layer is located on the side of the active layer away from the substrate. To reduce leakage current at nodes N1 and N2 in the sub-pixel driver circuit, the data write transistor T1, the second reset transistor T7, the first compensation transistor T2, and the first reset transistor T4 all utilize dual-gate LTPS transistors. In other embodiments, the data write transistor T1, the second reset transistor T7, the first compensation transistor T2, and the first reset transistor T4 may also utilize oxide transistors. The gates of the data write transistor T1, the second reset transistor T7, the first compensation transistor T2, and the first reset transistor T4 and the scan lines to which they are coupled may be arranged in layers. Because the alternating frequency of the signals connected to these four transistors is relatively high, in NB-sized display devices, the scan lines may be fabricated using a first source and drain metal layer with a lower resistivity to reduce loading caused by signal variations and improve the uniformity of NB-sized display products. The material of the first gate metal layer includes, but is not limited to, Mo.

[0197] It should be noted that when doping the active layer, the first gate metal layer can be used as a mask to implement the doping process, or a separate mask layer can be formed, which is not limited here. Taking Figure 9 as an example, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 can only form the power control transistor T5 and the light-emitting control transistor T6 with the active layer, without forming other abnormal transistors. When the first gate metal layer is used as a mask to implement the doping process, in order to avoid the formation of other abnormal transistors, the signal lines located in the area where abnormal transistors may be formed can be jumpered with the first source and drain metal layer to avoid the formation of abnormal transistors.

[0198] As shown in Figures 10, 11, and 28, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference signal line Vref1, and the second reference signal line Vref2 are all disposed in the second gate metal layer. Simultaneously, the second electrode plate C12 and the second electrode plate C22 are both disposed in the second gate metal layer. The second electrode plate C12 and the second electrode plate C22 each include an opening for exposing the first electrode plate C11 and the first electrode plate C21 to achieve connection between the first electrode plate C11 and the first electrode plate C21 and the first source / drain metal layer. As shown in Figures 9 and 11, the second reference signal line may include a covering portion for covering the conductive portion of the active layer between the dual gates of the data write transistor T1 and the second reset transistor T7. This arrangement can reduce the leakage current of the dual-gate transistor and improve the stability of the transistor.

[0199] Exemplarily, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference signal line Vref1 and the second reference signal line Vref2 are all constant electrical signals. For example, the voltage of the signal transmitted by the first initialization signal line Vinit1 and the second initialization signal line Vinit2 is a negative value, and the voltage of the signal transmitted by the first reference signal line Vref1 and the second reference signal line Vref2 is a positive value.

[0200] For example, the second gate metal layer may use a stacked structure of Ti / Al / Ti, which is beneficial for reducing the loading of NB-sized display products.

[0201] As shown in Figures 12, 13, and 29, the black dots in the figures represent vias. The first scan line Scan1, the second scan line Scan2, and the fourth scan line Scan are all set in the first source-drain metal layer. Setting them in different layers from other signal lines helps improve crosstalk between signal lines. Considering that the signal transition process of the first scan line Scan1, the second scan line Scan2, and the fourth scan line Scan has a large loading, when the first source-drain metal layer adopts a Ti / Al / Ti stacked structure, the above setting method helps to improve the large loading problem.

[0202] As shown in Figures 12, 13 and 29, the fourth scan line Scan4 is coupled to the gate of the data writing transistor T1 through the first via Via1. The first scan line Scan1 is coupled to the gate of the second reset transistor T7 through the second via Via2.

[0203] The second conductive connection portion 32 is coupled to the second electrode of the data write transistor T1 and the second electrode of the second reset transistor T7 through the third via Via3. The second conductive connection portion 32 is coupled to the first plate C21 of the second capacitor C2 through the seventh via Via7. The second conductive connection portion 32 is coupled to the second plate C12 of the first capacitor C1 through the ninth via Via9.

[0204] The third conductive connection portion 33 is coupled to the first reference signal line Vref1 through a fourth via Via4 . The third conductive connection portion 33 is coupled to the first electrode of the second reset transistor T7 through a fifth via Via5 .

[0205] The first conductive connection portion 31 is coupled to the first electrode of the data writing transistor T1 through the sixth via hole Via6. As shown in Figures 14 and 15, the first conductive connection portion 31 is coupled to the data line DA through the twenty-first via hole Via21.

[0206] The power connection line VDD' is coupled to the second plate C22 of the second capacitor C2 through the eighth via Via8. The second scan line Scan2 is coupled to the gate of the first reset transistor T4 through the tenth via Via10. The first scan line Scan1 is coupled to the gate of the first compensation transistor T2 through the thirteenth via Via13.

[0207] The fourth conductive connection portion 34 is coupled to the first electrode C11 of the first capacitor C1 through the eleventh via Via11 , and the fourth conductive connection portion 34 is coupled to the second electrode of the first compensation transistor T2 through the twelfth via Via12 .

[0208] The fifth conductive connection portion 35 is coupled to the first electrode of the first reset transistor T4 through the fourteenth via hole Via14. The fifth conductive connection portion 35 is coupled to the first initialization signal line Vinit1 through the fifteenth via hole Via15.

[0209] The sixth conductive connection portion 36 is coupled to the second initialization signal line Vinit2 through the sixteenth via Via16 , and the sixth conductive connection portion 36 is coupled to the first electrode of the fourth reset transistor T8 through the seventeenth via Via17 .

[0210] The seventh conductive connection portion 37 is coupled to the second reference signal line Vref2 through the eighteenth via Via18 , and the seventh conductive connection portion 37 is coupled to the first electrode of the third reset transistor T9 through the nineteenth via Via19 .

[0211] As shown in Figures 14 and 15 , the black dots represent vias. The power line VDD is fabricated using the second source / drain metal layer and is used to shield the N1 node (corresponding to the fourth conductive connection portion 34 ) and the N2 node (corresponding to the second conductive connection portion 32 ), preventing voltage jumps at these two nodes.

[0212] As shown in Figures 14 and 15, the second reference signal connection line Vref2' is coupled to the second reference signal line Vref2 through the 20th via Via20. The first reference signal connection line Vref1' is coupled to the first reference signal line Vref1 through the 22nd via Via22. The power line VDD is coupled to the power connection line VDD' through the 23rd via Via23. The power line VDD is coupled to the first electrode of the power control transistor T5 through the 24th via Via24. The first initialization signal connection line Vinit1' is coupled to the first initialization signal line Vinit1 through the 26th via Via26. The second initialization signal connection line Vinit2' is coupled to the second initialization signal line Vinit2 through the 27th via Via27.

[0213] As shown in FIG31 , the power line VDD is coupled to the first electrode of the second compensation transistor T10 through the twenty-eighth via Via28 .

[0214] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0215] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0216] Exemplarily, the display device is suitable for notebook-sized display devices, and is particularly suitable for medium- and large-sized OLED display devices with a high refresh rate.

[0217] In the display substrate provided by the above embodiment, a functional layer with a constant potential is provided around the data line DA to reduce the influence of the data signal jump on the N1 node. By setting the orthographic projection of the data line DA on the base substrate and the orthographic projection of the spacer area J1 on the base substrate to at least partially overlap, the overlapping area between the orthographic projection of the data line DA on the base substrate and the orthographic projection of the second plate C22 of the second capacitor C2 on the base substrate is reduced, thereby reducing the loading of the data line DA while reducing the influence of the data signal on the N1 node, thereby avoiding the low potential of the far end of the data line DA and ensuring the display uniformity of the display product.

[0218] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0219] The present disclosure also provides a method for driving a display substrate, which is used to drive the display substrate provided by the above embodiment. The method includes:

[0220] In the data writing phase, the data writing transistor T1 is turned on to write the data signal transmitted by the data line DA into the second plate C12 of the first capacitor C1. The first capacitor C1 couples the potential jump of its second plate to the first plate it includes.

[0221] As shown in FIG4 and FIG5 , in some embodiments, under the following circumstances: the sub-pixel driving circuit further includes a first compensation transistor T2 and a second compensation transistor T10, and in the same sub-pixel driving circuit, the control signal line GC coupled to the gate of the second compensation transistor T10 is multiplexed as the first scan line Scan1 coupled to the gate of the first compensation transistor T2; the driving method further includes:

[0222] During the compensation stage, the control signal transmitted by the control signal line GC is at a valid level, and the control signal controls the first compensation transistor T2 and the second compensation transistor T10 to be turned on; there is a first time interval t1 between the time when the valid level of the control signal ends and the time when the data writing transistor T1 is controlled to be turned on, and t1 satisfies: t1≤m, where m represents a first threshold value.

[0223] In the driving method provided in the above embodiment, the effective level of the control signal can cover the compensation phase and at least part of the floating phase, thereby reducing the impact of data signal changes on the N1 node. More specifically, the above configuration is equivalent to extending the duration of the compensation phase and shortening the duration of the floating phase.

[0224] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0225] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0226] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0227] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0228] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0229] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0230] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0231] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate, and power lines, data lines, and a plurality of sub-pixels all disposed on the base substrate; The sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled to each other, wherein the sub-pixel driving circuit includes a driving transistor, a data writing transistor, a first capacitor and a second capacitor; The first plate of the first capacitor is coupled to the gate of the driving transistor, the second plate of the first capacitor is coupled to the second electrode of the data writing transistor, and the first electrode of the data writing transistor is coupled to the corresponding data line; The first plate of the second capacitor is coupled to the second plate of the first capacitor, and the second plate of the second capacitor is coupled to the corresponding power line; In the sub-pixel driving circuits located in the same row along the first direction, the second plates of the second capacitors included in each sub-pixel driving circuit are arranged sequentially along the first direction, there is a spacing area between the second plates of adjacent second capacitors, and the orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the spacing area on the base substrate.

2. The display substrate according to claim 1, wherein The second plates of the second capacitors adjacent to each other along the first direction are coupled via plate connecting portions, and between the second plates of the adjacent second capacitors, the spacer and the plate connecting portions are arranged along a second direction, and the second direction intersects the first direction; The orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the electrode connecting portion on the base substrate.

3. The display substrate according to claim 2, wherein: The display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes a first compensation transistor and a first reset transistor; a first electrode of the first compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the first compensation transistor is coupled to a gate of the driving transistor; a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first compensation transistor includes a first compensation active layer, and the first reset transistor includes a first reset active layer; The plate connecting portion includes a connecting main portion and a connecting extension portion coupled to each other, wherein the connecting main portion is respectively coupled to the second plate of the adjacent second capacitor, and the connecting extension portion is connected to the substrate. The orthographic projection on the bottom substrate at least partially overlaps with the orthographic projection on the base substrate of the first compensation active layer included in one of the two sub-pixel driving circuits adjacent along the first direction, and / or at least partially overlaps with the orthographic projection on the base substrate of the first reset active layer included in the other of the two sub-pixel driving circuits adjacent along the first direction; The orthographic projection of the data line on the base substrate at least partially overlaps with the orthographic projection of the connecting body on the base substrate; And / or, an orthographic projection of the data line on the base substrate at least partially overlaps with an orthographic projection of the connecting extension on the base substrate.

4. The display substrate according to claim 3, wherein: The first compensation active layer includes two first compensation channel portions and first compensation conductor portions respectively coupled to the two first compensation channel portions; the first reset active layer includes two first reset channel portions and first reset conductor portions respectively coupled to the two first reset channel portions; The orthographic projection of the connecting extension on the base substrate at least partially overlaps with the orthographic projection of the first compensation conductor portion included in one of the two sub-pixel driving circuits adjacent along the first direction on the base substrate, and / or at least partially overlaps with the orthographic projection of the first reset conductor portion included in the other of the two sub-pixel driving circuits adjacent along the first direction on the base substrate.

5. The display substrate according to claim 1, wherein The display substrate also includes a plurality of first reference signal connection lines and a plurality of second reference signal connection lines, and the first reference signal connection lines and the second reference signal connection lines are alternately arranged along the first direction; the orthographic projection of at least part of the data lines on the base substrate is located between the orthographic projection of the adjacent first reference signal connection line on the base substrate and the orthographic projection of the second reference signal connection line on the base substrate; the data lines and the first reference signal connection lines are arranged in different layers; and / or the data lines and the second reference signal connection lines are arranged in different layers. The display substrate according to claim 5 , wherein: The display substrate also includes multiple first reference signal lines; the sub-pixel driving circuit also includes a second reset transistor, the first electrode of the second reset transistor is coupled to the corresponding first reference signal line, and the second electrode of the second reset transistor is coupled to the second plate of the first capacitor; the first reference signal connection line is coupled to multiple first reference signal lines respectively.

7. The display substrate according to claim 5, wherein: The display substrate also includes multiple second reference signal lines; the sub-pixel driving circuit also includes a third reset transistor, the first electrode of the third reset transistor is coupled to the corresponding second reference signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor; the second reference signal connection line is respectively coupled to multiple second reference signal lines.

8. The display substrate according to claim 5, wherein: The display substrate further includes a plurality of first initialization signal connection lines and a plurality of second initialization signal connection lines, wherein the first initialization signal connection lines and the second initialization signal connection lines are alternately arranged along the first direction; the orthographic projection of at least some of the data lines on the base substrate is located between the orthographic projection of the first initialization signal connection line and the orthographic projection of the second initialization signal connection line on the base substrate; the data lines and the first initialization signal connection lines are arranged in different layers; and / or the data lines and the second initialization signal connection lines are arranged in different layers.

9. The display substrate according to claim 8, wherein: The display substrate also includes multiple first initialization signal lines; the sub-pixel driving circuit also includes a first reset transistor, the first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and the second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first initialization signal connection line is coupled to multiple first initialization signal lines respectively.

10. The display substrate according to claim 8, wherein The display substrate also includes multiple second initialization signal lines; the sub-pixel driving circuit also includes a fourth reset transistor, the first electrode of the fourth reset transistor is coupled to the corresponding second initialization signal line, and the second electrode of the fourth reset transistor is coupled to the anode of the light-emitting element; the second initialization signal connection line is respectively coupled to multiple second initialization signal lines.

11. The display substrate according to claim 8, wherein The display substrate comprises a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer stacked in sequence in a direction away from the base substrate; The data line is provided in the same layer and material as the third source-drain metal layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line and the second initialization signal connection line are all provided in the same layer and material as the second source-drain metal layer.

12. The display substrate according to claim 11, wherein: The display substrate further comprises a plurality of data line leads; the display substrate comprises a plurality of data lines arranged along the first direction, the plurality of data lines being divided into a first data line group, a second data line group and a third data line group arranged along the first direction; The data lines in the first data line group are coupled to corresponding data line leads, and the data line leads extend from locations where the data lines to which they are coupled are located to a middle area of ​​the display substrate, and then extend from the middle area to a lower frame area of ​​the display substrate; The data lines in the third data line group are coupled to corresponding data line leads, which extend from the location of the coupled data lines to the middle area, and then extend from the middle area to the lower frame area.

13. The display substrate according to claim 8, wherein: The display substrate comprises a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer stacked in sequence in a direction away from the base substrate; The data line is provided in the same layer and material as the second source-drain metal layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line and the second initialization signal connection line are all provided in the same layer and material as the third source-drain metal layer.

14. The display substrate according to claim 8, wherein The display substrate comprises a light shielding layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer which are sequentially stacked in a direction away from the base substrate; The data line is provided in the same layer and material as the light shielding layer, and the first reference signal connection line, the second reference signal connection line, the first initialization signal connection line and the second initialization signal connection line are all provided in the same layer and material as the second source / drain metal layer.

15. The display substrate according to claim 1, wherein The display substrate further includes a plurality of power connection lines, each of which includes at least a portion extending along the first direction, and each of which is coupled to the plurality of power lines.

16. The display substrate according to claim 15, wherein: The power connection line includes a plurality of first power parts and a plurality of second power parts, wherein the first power parts and the second power parts are alternately arranged along the first direction; The first power supply part includes a first sub-part and a second sub-part, the first sub-part is coupled to the second sub-part and the power line respectively, and the adjacent second sub-part and the second power line are connected. The second power supply portion is coupled to the source portion, the width of the second power supply portion along the second direction is greater than the width of the second sub-portion, and the orthographic projection of the second power supply portion on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate.

17. The display substrate according to any one of claims 1 to 16, wherein The sub-pixel also includes a first scan line and a control signal line; the sub-pixel driving circuit also includes a first compensation transistor and a second compensation transistor, the gate of the first compensation transistor is coupled to the corresponding first scan line, the first electrode of the first compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first compensation transistor is coupled to the gate of the driving transistor; the gate of the second compensation transistor is coupled to the corresponding control signal line, the first electrode of the second compensation transistor is coupled to the corresponding power line, and the second electrode of the second compensation transistor is coupled to the first electrode of the driving transistor.

18. The display substrate according to claim 17, wherein: In the same sub-pixel driving circuit, the control signal line to which the gate of the second compensation transistor is coupled is multiplexed as the first scanning line to which the gate of the first compensation transistor is coupled.

19. The display substrate according to any one of claims 1 to 16, wherein The plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein a sub-pixel driving circuit in the red sub-pixel includes a driving transistor having a first channel width-to-length ratio, a sub-pixel driving circuit in the green sub-pixel includes a driving transistor having a second channel width-to-length ratio, and a sub-pixel driving circuit in the blue sub-pixel includes a driving transistor having a third channel width-to-length ratio; The third channel width-to-length ratio is greater than the first channel width-to-length ratio; and / or the third channel width-to-length ratio is greater than the second channel width-to-length ratio.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

21. A method for driving a display substrate, for driving the display substrate according to any one of claims 1 to 19, the method comprising: In the data writing phase, the data writing transistor is turned on to write the data signal transmitted by the data line into the second plate of the first capacitor, and the first capacitor couples the potential jump of its second plate to the first plate it includes.

22. The method for driving a display substrate according to claim 21, wherein: In the following case: the sub-pixel driving circuit further includes a first compensation transistor and a second compensation transistor, and in the same sub-pixel driving circuit, the control signal line coupled to the gate of the second compensation transistor is multiplexed as the first scan line coupled to the gate of the first compensation transistor; The driving method further includes: During the compensation phase, the control signal transmitted by the control signal line is at an effective level, and the control signal controls both the first compensation transistor and the second compensation transistor to be turned on; There is a first time interval t1 between the time when the effective level of the control signal ends and the time when the data writing transistor is controlled to be turned on, and t1 satisfies: t1≤m, where m represents a first threshold.

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