Static-display control method and apparatus for GPU, and device and storage medium

Abstract

The present disclosure relates to a static-display control method and apparatus for a GPU, and a device and a storage medium. The method comprises: in response to entering a static display scenario, copying frame data in a first video memory to a second video memory; reading the frame data from the second video memory, and then displaying the frame data; reducing a clock frequency of the first video memory; and in response to the completion of the clock frequency adjustment of the first video memory, reading the frame data from the first video memory, and then displaying the frame data.

Description

Static display control method, device, equipment and storage medium for GPU

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 16, 2023, with application number 202311532439.4 and application name “Static display control method, device, equipment and storage medium for GPU”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of computer technology, and in particular to a static display control method for a GPU, a static display control device for a GPU, an electronic device, and a storage medium. Background Art

[0003] Static display scenarios using a GPU (Graphics Processing Unit) are typical low-power GPU scenarios. In these scenarios, the display reads and displays frame data from the GPU's video memory (e.g., GDDR (Graphics Double Data Rate) memory) at a preset refresh rate. Video memory power consumption accounts for a significant portion of the GPU's overall power consumption. Therefore, reducing video memory power consumption is crucial for reducing overall GPU power consumption. Summary of the Invention

[0004] The present disclosure provides a static display control technology solution for a GPU.

[0005] According to one aspect of the present disclosure, a static display control method for a GPU is provided, comprising:

[0006] In response to entering a static display scene, copying the frame data in the first video memory to the second video memory;

[0007] Reading the frame data from the second display memory and displaying the frame data;

[0008] reducing the clock frequency of the first video memory;

[0009] In response to the completion of the adjustment of the clock frequency of the first video memory, the frame data is read from the first video memory and displayed.

[0010] In a possible implementation, in response to entering a static display scene, copying the frame data in the first video memory to the second video memory includes:

[0011] In response to entering a static display scene, obtaining the number of displays;

[0012] Determining a second video memory according to the number of the displays;

[0013] The frame data in the first video memory is copied to the second video memory.

[0014] In a possible implementation, determining the second video memory according to the number of displays includes:

[0015] In response to the number of the displays falling within a preset number interval, the second video memory is determined to be a static random access memory in the GPU.

[0016] In a possible implementation, determining the second video memory according to the number of displays includes:

[0017] In response to the number of the displays not falling within a preset number interval, determining that the second video memory is a low power double data rate (LPDDR) memory in the GPU.

[0018] In a possible implementation, copying the frame data in the first video memory to the second video memory includes:

[0019] In response to the data amount of the frame data in the first video memory being less than or equal to the capacity of the static random access memory, all the frame data in the first video memory are copied to the static random access memory.

[0020] In one possible implementation,

[0021] The copying of the frame data in the first video memory to the second video memory includes: in response to the amount of the frame data in the first video memory being greater than the capacity of the static random access memory, copying the first frame data in the first video memory to the static random access memory, wherein the amount of the first frame data is equal to the capacity of the static random access memory;

[0022] The method further includes: copying the second frame data in the first display memory to the system memory.

[0023] In a possible implementation, the method further includes:

[0024] In response to the first frame data in the static random access memory being retrieved, the second frame data in the system memory is copied to the static random access memory.

[0025] In a possible implementation, the static random access memory adopts a ring buffer data structure.

[0026] According to one aspect of the present disclosure, a static display control device for a GPU is provided, comprising:

[0027] A first copy module, configured to copy the frame data in the first video memory to the second video memory in response to entering a static display scene;

[0028] A first display module, configured to read the frame data from the second display memory and display the frame data;

[0029] A reducing module, configured to reduce the clock frequency of the first video memory;

[0030] The second display module is configured to read and display the frame data from the first display memory in response to completion of adjusting the clock frequency of the first display memory.

[0031] In a possible implementation, the first copy module is configured to:

[0032] In response to entering a static display scene, obtaining the number of displays;

[0033] Determining a second video memory according to the number of the displays;

[0034] The frame data in the first video memory is copied to the second video memory.

[0035] In a possible implementation, the first copy module is configured to:

[0036] In response to the number of the displays falling within a preset number interval, the second video memory is determined to be a static random access memory in the GPU.

[0037] In a possible implementation, the first copy module is configured to:

[0038] In response to the number of the displays not falling within a preset number interval, determining that the second video memory is a low power double data rate (LPDDR) memory in the GPU.

[0039] In a possible implementation, the first copy module is configured to:

[0040] In response to the data amount of the frame data in the first video memory being less than or equal to the capacity of the static random access memory, all the frame data in the first video memory are copied to the static random access memory.

[0041] In one possible implementation,

[0042] The first copy module is configured to: in response to the amount of frame data in the first video memory being greater than the capacity of the static random access memory, copy the first frame data in the first video memory to the static random access memory, wherein the amount of the first frame data is equal to the capacity of the static random access memory;

[0043] The device further includes: a second copy module, configured to copy the second frame data in the first display memory to a system memory.

[0044] In a possible implementation, the apparatus further includes:

[0045] The third copy module is configured to copy the second frame data in the system memory to the static random access memory in response to the first frame data in the static random access memory being retrieved.

[0046] In a possible implementation, the static random access memory adopts a ring buffer data structure.

[0047] According to one aspect of the present disclosure, there is provided a static display control device for a GPU, comprising a system management controller, a first video memory, a second video memory, a display engine, and a clock control module;

[0048] a system management controller, configured to copy the frame data in the first video memory to the second video memory in response to the notification message of entering the static display scene;

[0049] A display engine, configured to read the frame data from the second display memory and display the frame data;

[0050] A clock control module, configured to reduce the clock frequency of the first video memory;

[0051] The display engine is further configured to: in response to completion of adjusting the clock frequency of the first video memory, read the frame data from the first video memory and display the frame data.

[0052] In a possible implementation, the second video memory includes a static random access memory.

[0053] In a possible implementation, the static random access memory adopts a ring buffer data structure.

[0054] In a possible implementation, the second video memory includes an LPDDR memory.

[0055] In a possible implementation, the device further includes a direct memory access (DMA) module;

[0056] The system management controller is specifically configured to copy the frame data in the first video memory to the second video memory via the DMA module.

[0057] In a possible implementation, the apparatus further includes:

[0058] The static display control module is configured to send a notification message of entering the static display scene to the system management controller in response to entering the static display scene.

[0059] In a possible implementation, the apparatus further includes:

[0060] The system memory is used to back up the frame data.

[0061] According to one aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0062] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0063] According to one aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0064] In an embodiment of the present disclosure, in response to entering a static display scene, the frame data in the first video memory is copied to the second video memory, the frame data is read from the second video memory and displayed, the clock frequency of the first video memory is reduced, and in response to the completion of the adjustment of the clock frequency of the first video memory, the frame data is read from the first video memory and displayed. Thus, during the process of reading the frame data from the second video memory, the first video memory is in an idle state, thereby reducing the clock frequency of the first video memory to reduce the overall power consumption of the GPU. In an embodiment of the present disclosure, it is not necessary to complete the adjustment of the clock frequency of the first video memory in the VBlank interval, that is, there is sufficient time to complete the adjustment of the clock frequency of the first video memory, thereby reducing the requirements for the GPU chip and eliminating the need for special design of the frequency adjustment process of the first video memory. In addition, the embodiment of the present disclosure copies the frame data in the first video memory to the second video memory in the same GPU, and reads the frame data from the second video memory in the GPU during the process of adjusting the clock frequency of the first video memory, thereby reducing the dependence on external factors of the GPU (such as the bandwidth of the PCIe bus and the system memory bandwidth). That is, it can reduce the dependence on the system hardware configuration, thereby reducing the probability of screen flickering on the display.

[0065] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0066] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0068] FIG1 shows a flowchart of a static display control method for a GPU provided by an embodiment of the present disclosure.

[0069] FIG2 is a schematic diagram showing an application scenario of a single display in the static display control method for a GPU provided by an embodiment of the present disclosure.

[0070] FIG3 is a schematic diagram showing an application scenario of multiple displays in a static display control method for a GPU provided by an embodiment of the present disclosure.

[0071] FIG4 shows a block diagram of a static display control device for a GPU provided by an embodiment of the present disclosure.

[0072] FIG5 shows a block diagram of an electronic device 800 provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0074] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0075] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0076] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0077] A static display scene of a GPU (Graphics Processing Unit) can refer to a scene in which a computer monitor displays a static image. A static image can refer to an image or picture that does not change. A static image can include photos, icons, interface elements, etc.

[0078] The following explanation uses GDDR (Graphics Double Data Rate) memory, the primary video memory in a GPU, as an example. GDDR memory is a high-performance DDR (Double Data Rate) memory specifically designed for high-end graphics cards.

[0079] In a static display scenario using a GPU, the display reads and displays frame data from the GPU's GDDR memory at a preset refresh rate. The maximum time interval for the display to read frame data is called the VBlank (Vertical Blank) interval.

[0080] The power consumption of GDDR memory accounts for a large proportion of the overall power consumption of the GPU. Since static display scenarios have low bandwidth requirements for GDDR memory, the overall power consumption of the GPU can be reduced by reducing the clock frequency of the GDDR memory. However, the GDDR memory requires that its clock frequency must be adjusted when it is in an idle state. That is, the clock frequency of the GDDR memory can only be adjusted when the GDDR memory is in an idle state. Among them, the maximum idle time that can be utilized is the VBlank interval. In the case of static display of multiple displays (that is, multiple displays read frame data from the GDDR memory of the GPU at a corresponding refresh rate and display it), the time point when each display enters the VBlank interval may be inconsistent, resulting in the length of time that multiple displays are idle at the same time may be less than the VBlank interval.

[0081] In the related art, there are mainly two solutions to reduce the clock frequency of the GDDR memory.

[0082] The first solution is to use a GPU with fast GDDR frequency adjustment capabilities. GDDR frequency adjustment refers to adjusting the clock frequency of the GDDR memory, and accordingly, GDDR frequency adjustment capability refers to the ability to adjust the clock frequency of the GDDR memory. In this solution, the clock frequency of the GDDR memory is reduced during the VBlank interval. The VBlank interval may vary depending on the display and refresh rate configuration, typically ranging from 500 to 600 microseconds. In a multi-display scenario, the GDDR memory clock frequency cannot be adjusted until all displays enter the VBlank interval. Some GPUs have special GDDR frequency adjustment designs that enable the GPU to have fast GDDR frequency adjustment capabilities, allowing the GPU to complete the adjustment of the GDDR memory clock frequency within the VBlank interval, thereby meeting the power consumption requirements of the GDDR memory in low-power scenarios.

[0083] The second solution is to use system memory as a frame data buffer. In this solution, frame data is backed up in system memory, and the display is controlled to read and display the frame data from the system memory, leaving the GDDR memory idle. This allows the GDDR memory clock frequency to be reduced while the GDDR memory is idle. After the GDDR memory clock frequency is reduced, the display is controlled to read and display the frame data from the GDDR memory.

[0084] In the first solution, because the VBlank interval is short and fluid, and multiple displays may enter the VBlank interval at different times, the GDDR memory clock frequency cannot be adjusted until all displays enter the VBlank interval. This requires extremely short adjustment times, placing stringent demands on GPU chip design. Consequently, most GPU chips are unable to implement GDDR memory clock frequency adjustment using the first solution.

[0085] In the second solution, the display's ability to retrieve frame data from system memory depends on a number of external factors, including the bandwidth of the PCIe (Peripheral Component Interconnect-express) bus and the bandwidth of the system memory. If the system hardware configuration is low, for example, if the PCIe bus bandwidth and / or the system memory bandwidth cannot meet the bandwidth requirements for static display, the display may experience screen flickering.

[0086] In order to solve technical problems similar to those described above, an embodiment of the present disclosure provides a static display control method for a GPU, which copies frame data in a first video memory to a second video memory in response to entering a static display scene, reads the frame data from the second video memory and displays it, reduces the clock frequency of the first video memory, and in response to the completion of the adjustment of the clock frequency of the first video memory, reads the frame data from the first video memory and displays it, thereby, in the process of reading the frame data from the second video memory, the first video memory is in an idle state, so that the clock frequency of the first video memory can be reduced to reduce the overall power consumption of the GPU. In the embodiment of the present disclosure, there is no need to complete the adjustment of the clock frequency of the first video memory in the VBlank interval, that is, there is sufficient time to complete the adjustment of the clock frequency of the first video memory, thereby reducing the requirements for the GPU chip and eliminating the need for special design of the frequency adjustment process of the first video memory. In addition, the embodiment of the present disclosure copies the frame data in the first video memory to the second video memory in the same GPU, and reads the frame data from the second video memory in the GPU during the process of adjusting the clock frequency of the first video memory, thereby reducing the dependence on external factors of the GPU (such as the bandwidth of the PCIe bus and the system memory bandwidth). That is, it can reduce the dependence on the system hardware configuration, thereby reducing the probability of screen flickering on the display.

[0087] The static display control method for a GPU provided by an embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0088] FIG1 shows a flowchart of a static display control method for a GPU provided by an embodiment of the present disclosure. In one possible implementation, the execution subject of the static display control method for a GPU may be a static display control device for a GPU. For example, the static display control method for a GPU may be executed by a terminal device or a server or other electronic device. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the static display control method for a GPU may be implemented by a processor calling computer-readable instructions stored in a memory. As shown in FIG1 , the static display control method for a GPU includes steps S11 to S14.

[0089] In step S11, in response to entering a static display scene, the frame data in the first video memory is copied to the second video memory;

[0090] In step S12, the frame data is read from the second display memory and displayed;

[0091] In step S13, the clock frequency of the first video memory is reduced;

[0092] In step S14 , in response to the completion of the adjustment of the clock frequency of the first video memory, the frame data is read from the first video memory and displayed.

[0093] In one possible implementation, when not in a static display scene, it can be determined that a static display scene has been entered in response to the duration of displaying a static image reaching a preset duration; when in a static display scene, it can be determined that a static display scene has been exited in response to a change in the displayed image.

[0094] For example, in the case of a dynamic display scene, it can be determined to enter a static display scene in response to the duration of displaying a static image reaching a preset duration; in the case of a static display scene, it can be determined to exit the static display scene and enter a dynamic display scene in response to a change in the displayed image. The dynamic display scene can also be referred to as a normal working display scene, a normal display scene, etc., which are not limited here. In the dynamic display scene, frame data can be read from the first video memory and displayed. For example, in the dynamic display scene, the display engine can read frame data from the first video memory and provide the frame data to the display for display.

[0095] In this implementation, GPU software or GPU hardware can determine the timing of entering and exiting the static display scene (i.e., determining the time point of entering and exiting the static display scene). Entering and exiting the static display scene refers to entering and exiting the static display scene.

[0096] In one possible implementation, the timing of entering and exiting a static display scene can be determined by a static display control module in the GPU software. The static display control module may also be referred to as a GPU idle control logic module, an idle control logic module, a low-power control module, a GPU low-power control logic module, and the like, without limitation herein.

[0097] In one possible implementation, the static display control module may be further configured to, in response to entering a static display scene, send a notification message to a system management controller (SMC) indicating that the static display scene has been entered, and, in response to exiting the static display scene, send a notification message to the SMC indicating that the static display scene has been exited. That is, the static display control module may, in response to entering a static display scene, notify the SMC of the entry into the static display scene, and, in response to exiting the static display scene, notify the SMC of the exit from the static display scene.

[0098] In one possible implementation, a system management controller (SMC) may run firmware code to manage the static display control solution for the GPU. The SMC may also be referred to as a system management unit (SMU), a system management module, or the like, without limitation.

[0099] In one possible implementation, the system management controller may communicate with the GPU software to receive notification messages from the GPU software regarding entering a static display scene and exiting a static display scene. For example, the system management controller may communicate with the static display control module to receive notification messages from the static display control module regarding entering a static display scene and exiting a static display scene.

[0100] In the embodiment of the present disclosure, the first video memory may refer to the main video memory in the GPU. For example, the first video memory may be a GDDR memory, etc., which is not limited here.

[0101] In an embodiment of the present disclosure, in response to entering a static display scene, frame data in the first video memory may be copied to the second video memory in the same GPU, wherein the first video memory and the second video memory are different video memories in the same GPU.

[0102] In one possible implementation, the system management controller may copy frame data in the first video memory to the second video memory in the GPU via a DMA (Direct Memory Access) module in response to entering a static display scene. The DMA module can be used for high-speed data transfer.

[0103] In the disclosed embodiment, the second video memory may be an SRAM (Static Random Access Memory) or an LPDDR (Low Power Double Data Rate) memory in a GPU, etc., which is not limited here.

[0104] In a possible implementation, in response to entering a static display scene, frame data in the first video memory may be copied to at least one second video memory in the GPU.

[0105] As an example of this implementation, in response to entering a static display scene, the frame data in the first video memory may be copied to the SRAM in the GPU. For example, in response to entering a static display scene and the amount of frame data in the first video memory is less than or equal to the capacity of the SRAM, the frame data in the first video memory may be copied to the SRAM in the GPU.

[0106] As another example of this implementation, in response to entering a static display scene, the frame data in the first video memory may be copied to the LPDDR memory in the GPU. For example, in response to entering a static display scene, all frame data in the first video memory may be copied to the LPDDR memory in the GPU.

[0107] As another example of this implementation, in response to entering a static display scene, the frame data in the first video memory can be copied to the SRAM and LPDDR memory in the GPU. For example, in response to entering a static display scene and the amount of frame data in the first video memory is greater than the capacity of the SRAM, a portion of the frame data in the first video memory can be copied to the SRAM, and another portion of the frame data can be copied to the LPDDR, wherein the amount of frame data copied to the SRAM can be equal to the capacity of the SRAM.

[0108] In one possible implementation, in response to entering a static display scene, the frame data in the first video memory may be copied to the second video memory and the system memory. For example, in response to entering a static display scene and the amount of frame data in the first video memory being greater than the capacity of the SRAM, a portion of the frame data in the first video memory may be copied to the SRAM, and another portion of the frame data may be copied to the system memory, wherein the amount of frame data copied to the SRAM is equal to the capacity of the SRAM.

[0109] In one possible implementation, in response to entering a static display scene, copying the frame data in the first video memory to the second video memory includes: in response to entering a static display scene, obtaining the number of displays; determining the second video memory based on the number of displays; and copying the frame data in the first video memory to the second video memory.

[0110] As an example of this implementation, the number of displays may be acquired through a static display control module.

[0111] In this implementation, as the number of displays increases, the amount of frame data in the first video memory will also increase accordingly, and the capacity of different memories in the GPU is different. Therefore, the appropriate second video memory can be determined in the GPU according to the number of displays.

[0112] In this implementation, in response to entering a static display scene, the number of displays is obtained, the second video memory is determined based on the number of displays, and the frame data in the first video memory is copied to the second video memory, thereby helping to balance the overall power consumption of the GPU and the display effect of the display (reducing screen flicker).

[0113] As an example of this implementation, determining the second video memory according to the number of displays includes: in response to the number of displays belonging to a preset number interval, determining that the second video memory is a static random access memory in the GPU.

[0114] The number of displays is a positive integer, and the number of any display that belongs to the preset number interval is smaller than the number of any display that does not belong to the preset data interval.

[0115] In this example, in response to the number of displays falling within a preset number range, the second video memory is determined to be the SRAM in the GPU. Therefore, when the number of displays is small, the SRAM in the GPU can be used as a display cache space, thereby reducing the overall power consumption of the GPU.

[0116] For example, the preset number interval is [1, 1].

[0117] In this example, when the number of displays is 1, the SRAM in the GPU can be determined as the second video memory. When the number of displays is greater than 1, the LPDDR memory in the GPU can be determined as the second video memory. This helps to balance the overall power consumption of the GPU and the display effect of the display.

[0118] The value of the preset number interval can be flexibly set according to at least one of the capacity of the SRAM in the GPU, the frame size of the static image in the static display scene, etc., and is not limited here. For example, the preset number interval can also be [1, 2], etc.

[0119] In one example, copying the frame data in the first video memory to the second video memory includes: in response to the amount of frame data in the first video memory being less than or equal to the capacity of the static random access memory, copying all frame data in the first video memory to the static random access memory.

[0120] In this example, in response to the fact that the amount of frame data in the first video memory is less than or equal to the capacity of the SRAM, the frame data in the first video memory is copied to the SRAM. Therefore, when the number of displays is small, the frame data in the first video memory is backed up from the SRAM within the GPU, which helps to reduce the overall power consumption of the GPU and can reduce the dependence on external factors of the GPU (such as the bandwidth of the PCIe bus and the system memory bandwidth), that is, it can reduce the dependence on the system hardware configuration, thereby reducing the probability of display screen flickering.

[0121] In one example, copying the frame data in the first video memory to the second video memory includes: in response to the data amount of the frame data in the first video memory being greater than the capacity of the static random access memory, copying the first frame data in the first video memory to the static random access memory, wherein the data amount of the first frame data is equal to the capacity of the static random access memory; the method also includes: copying the second frame data in the first video memory to the system memory.

[0122] In this example, the system memory may also be referred to as a CPU memory. The system memory may be a DDR (Double Data Rate) memory, etc., which is not limited here.

[0123] In this example, if the amount of frame data in the first video memory is greater than the capacity of the SRAM, a portion of the frame data in the first video memory can be copied to the SRAM, and another portion of the frame data can be copied to the system memory. The frame data copied from the first video memory to the SRAM can be referred to as first frame data, and the amount of this portion of frame data can be equal to the capacity of the SRAM; the frame data copied from the first video memory to the system memory can be referred to as second frame data.

[0124] In this example, in response to the fact that the amount of frame data in the first video memory is greater than the capacity of the SRAM, a portion of the frame data in the first video memory is copied to the SRAM, and another portion of the frame data is copied to the system memory, wherein the amount of frame data copied to the SRAM is equal to the capacity of the SRAM. Therefore, when the number of displays falls within a preset number range, there is no need to use LPDDR memory, which helps to reduce the overall power consumption of the GPU.

[0125] In one example, after copying a portion of the frame data in the first video memory to the static random access memory and copying another portion of the frame data to the system memory, the method further includes: in response to the first frame data in the static random access memory being retrieved, copying the second frame data in the system memory to the static random access memory.

[0126] In this example, as the first frame of data in the SRAM is retrieved, the second frame of data in the system memory can be copied to the SRAM in sequence.

[0127] In this example, in response to the first frame data in the SRAM being retrieved, the second frame data in the system memory is copied to the SRAM, thereby reducing the probability of screen flickering on the display.

[0128] In one example, the static random access memory adopts a ring buffer data structure.

[0129] The ring buffer may also be called a circular queue, a circular queue, a cyclic buffer, a circular buffer, a ring buffer, etc., which is not limited here.

[0130] In this example, a read pointer and a write pointer can be set for the SRAM. The read pointer can point to the space in the SRAM where the frame data is first stored, and the write pointer can point to the space where the frame data is to be written. If the space pointed to by the write pointer in the SRAM is already occupied, it can be determined that the SRAM is full. The frame data in the system memory must wait until the frame data in the space pointed to by the write pointer is read out before it can be stored in the space pointed to by the write pointer. The head and tail spaces of the SRAM are connected.

[0131] In this example, a ring buffer data structure is adopted through the SRAM, thereby helping to improve the speed and reliability of frame data transmission.

[0132] As an example of this implementation, determining the second video memory according to the number of displays includes: in response to the number of displays not belonging to a preset number interval, determining that the second video memory is an LPDDR memory in the GPU.

[0133] In this example, if the number of displays does not fall within the preset number range, the LPDDR memory can be used as a display buffer space. The number of displays is a positive integer, and the number of displays within the preset number range is smaller than the number of displays not within the preset number range.

[0134] In this example, in response to the fact that the number of displays does not fall within a preset number interval, the second video memory is determined to be the LPDDR memory in the GPU. Therefore, when the number of displays is large, the frame data in the first video memory is backed up by the larger-capacity LPDDR memory in the GPU, thereby reducing dependence on external factors of the GPU (such as the bandwidth of the PCIe bus and the system memory bandwidth), that is, reducing dependence on the system hardware configuration, thereby reducing the probability of display screen flickering.

[0135] As an example of this implementation, the static display control module may obtain the number of displays in response to entering a static display scene. In response to the number of displays being 1, the static display control module may send a notification message to the system management controller indicating that the system has entered a single-display static display scene. In response to the number of displays being greater than 1, the static display control module may send a notification message to the system management controller indicating that the system has entered a multi-display static display scene.

[0136] In this example, the system management controller can determine whether the amount of frame data in the first video memory is less than or equal to the capacity of the SRAM in response to a notification message indicating that a static display scene has been entered on a single display. If the amount of frame data in the first video memory is less than or equal to the capacity of the SRAM, all frame data in the first video memory can be copied to the SRAM. If the amount of frame data in the first video memory is greater than the capacity of the SRAM, a portion of the frame data in the first video memory can be copied to the SRAM, and another portion of the frame data can be copied to the system memory, wherein the amount of frame data copied to the SRAM is equal to the capacity of the SRAM.

[0137] In this example, the system management controller may copy the frame data in the first video memory to the LPDDR memory in response to the notification message of entering the static display scene of the multi-display.

[0138] As an example of this implementation, when the number of displays falls within a preset number range, the electronic device may be configured with only SRAM and not LPDDR, thereby reducing the overall power consumption of the GPU.

[0139] As an example of this implementation, when the number of displays does not fall within a preset number range, the electronic device may be configured with LPDDR, so that frame data corresponding to more displays can be stored in a larger-capacity LPDDR memory.

[0140] In another possible implementation, in response to entering a static display scene and the amount of frame data in the first video memory being less than or equal to the capacity of the SRAM, the frame data in the first video memory may be copied to the SRAM. In this implementation, whether the number of displays falls within the preset number range may not be considered.

[0141] In another possible implementation, in response to entering a static display scene and the amount of frame data in the first video memory exceeding the capacity of the SRAM, the first frame data in the first video memory may be copied to the SRAM, and the second frame data in the first video memory may be copied to the system memory. In this implementation, whether the number of displays falls within the preset range may not be considered.

[0142] In another possible implementation, in response to entering a static display scene, the frame data in the first video memory may be copied to the LPDDR memory. In this implementation, whether the number of displays falls within the preset number range may not be considered.

[0143] In another possible implementation, in response to entering a static display scene, copying the frame data in the first video memory to the second video memory includes: in response to entering a static display scene, obtaining the data amount of the frame data in the first video memory; determining the second video memory based on the data amount of the frame data in the first video memory; and copying the frame data in the first video memory to the second video memory.

[0144] For example, if the amount of frame data in the first video memory is less than or equal to the capacity of the SRAM in the GPU, the SRAM in the GPU may be determined as the second video memory, and the frame data in the first video memory may be copied to the SRAM.

[0145] For another example, if the amount of frame data in the first video memory is greater than the capacity of the SRAM in the GPU, the LPDDR memory in the GPU may be determined as the second video memory, and the frame data in the first video memory may be copied to the LPDDR memory.

[0146] In the embodiment of the present disclosure, after the frame data in the first video memory is copied to the second video memory, the frame data can be read from the second video memory and displayed.

[0147] In one possible implementation, after copying the frame data in the first video memory to the second video memory, the system management controller may configure the display engine to read and display the frame data from the second video memory. For example, if the second video memory is SRAM, the system management controller may configure the display engine to read and display the frame data from the SRAM. For another example, if the second video memory is LPDDR memory, the system management controller may configure the display engine to read and display the frame data from the LPDDR memory.

[0148] In the embodiment of the present disclosure, during the process of reading frame data from the second video memory and displaying the frame data, the first video memory is in an idle state, so the clock frequency of the first video memory can be adjusted.

[0149] In one possible implementation, the system management controller may adjust the clock frequency of the first video memory through the clock control module. For example, the system management controller may reduce the clock frequency of the first video memory through the clock control module. In another example, the system management controller may increase the clock frequency of the first video memory through the clock control module.

[0150] In an embodiment of the present disclosure, after the clock frequency of the first video memory is adjusted, frame data can be read from the first video memory and displayed. In one possible implementation, the system management controller can configure the display engine to read and display frame data from the first video memory in response to the completion of the clock frequency adjustment of the first video memory.

[0151] The static display control method for a GPU provided by the embodiments of the present disclosure can be applied to technical fields such as GPU, GDDR, and low power consumption, and is not limited here.

[0152] The static display control method for a GPU provided by an embodiment of the present disclosure is described below through a specific application scenario.

[0153] Figure 2 illustrates a schematic diagram of a single-display application scenario for the static display control method for a GPU provided by an embodiment of the present disclosure. As shown in Figure 2 , in a single-display application scenario, the static display control method for a GPU can be implemented using GPU software, GPU hardware, and system hardware. The system hardware may also be referred to as CPU hardware.

[0154] Among them, GPU software may include a static display control module, GPU hardware may include an SMC, a clock control module, a DMA module, SRAM, GDDR memory and a display engine, and system hardware may include system memory.

[0155] The static display control module can be used to determine the timing of entering and exiting the static display scene (i.e., determining the time point of entering and exiting the static display scene), and can notify the SMC to enter the static display scene in response to entering the static display scene, and, in response to exiting the static display scene, notify the SMC to exit the static display scene.

[0156] The SMC communicates with the static display control module, receiving notifications from the static display control module regarding entering and exiting static display scenes. The SMC also configures the clock control module to adjust the clock frequency of the GDDR memory. The SMC also configures parameters for the DMA module. The SMC also coordinates the transfer of frame data between system memory and the GPU's SRAM.

[0157] The clock control module can be used to adjust the clock frequency of the GDDR memory.

[0158] The DMA module can be used to copy frame data in the GDDR memory to the SRAM and system memory, and to copy frame data in the system memory to the SRAM.

[0159] SRAM and system memory can be used to back up frame data in GDDR memory for static display.

[0160] GDDR memory can be used to store frame data required for display.

[0161] The display engine can read frame data from the GDDR memory or SRAM and provide the frame data to the display for display.

[0162] The following describes the basic process of static display control in a single-monitor application scenario:

[0163] S1. In a dynamic display scenario, the display may read frame data from the GDDR memory and provide the frame data to the display for display.

[0164] S2. In response to detecting that a static display scene of a single display has been entered, the static display control module may send a notification message of entering a static display scene of a single display to the SMC.

[0165] S3. The SMC can respond to the notification message of entering the static display scene of a single display and determine whether the amount of frame data in the GDDR memory is less than or equal to the capacity of the SRAM (SRAM size). If the amount of frame data in the GDDR memory is less than or equal to the capacity of the SRAM, all frame data in the GDDR memory can be copied to the SRAM. If the amount of frame data in the GDDR memory is greater than the capacity of the SRAM, a portion of the frame data in the GDDR memory can be copied to the SRAM, and the other portion of the frame data can be copied to the system memory, wherein the amount of frame data copied to the SRAM is equal to the capacity of the SRAM.

[0166] S4 and SMC can configure the display engine to read frame data from SRAM and display it. In the case where part of the frame data in the GDDR memory is copied to the system memory, the frame data in the system memory can be copied to the free space of the SRAM in response to the frame data in the SRAM being retrieved.

[0167] S5 and SMC can reduce the clock frequency of GDDR memory through the clock control module.

[0168] S6. In response to the completion of the clock frequency adjustment of the GDDR memory, the SMC may configure the display engine to read the frame data from the GDDR memory and display the frame data.

[0169] Figure 3 illustrates a schematic diagram of a multi-display application scenario in the static display control method for a GPU provided by an embodiment of the present disclosure. Multi-display can refer to two or more displays. As shown in Figure 3 , in a multi-display application scenario, the static display control method for a GPU can be implemented using GPU software and GPU hardware.

[0170] Among them, the GPU software may include a static display control module, and the GPU hardware may include an SMC, a clock control module, a DMA module, an LPDDR memory, a GDDR memory, and a display engine.

[0171] The static display control module can be used to determine the timing of entering and exiting the static display scene (i.e., determining the time point of entering and exiting the static display scene), and can notify the SMC to enter the static display scene in response to entering the static display scene, and, in response to exiting the static display scene, notify the SMC to exit the static display scene.

[0172] The SMC can communicate with the static display control module, receiving notification messages from the static display control module to enter and exit static display scenes. The SMC can also configure the clock control module to adjust the clock frequency of the GDDR memory through the clock control module. The SMC can also configure the parameters of the DMA module.

[0173] The clock control module can be used to adjust the clock frequency of the GDDR memory.

[0174] The DMA module can be used to copy frame data in the GDDR memory to the LPDDR memory.

[0175] The LPDDR memory can be used to back up frame data for static display in the GDDR memory.

[0176] GDDR memory can be used to store frame data required for display.

[0177] The display engine can read frame data from the GDDR memory or the LPDDR memory and provide the frame data to the display for display.

[0178] The following describes the basic process of static display control in multi-monitor application scenarios:

[0179] S1. In a dynamic display scenario, the display may read frame data from the GDDR memory and provide the frame data to the display for display.

[0180] S2. In response to detecting that a static display scene of multiple displays has been entered, the static display control module may send a notification message of entering a static display scene of multiple displays to the SMC.

[0181] S3. The SMC may copy the frame data of each display in the GDDR memory to the LPDDR in response to the notification message of entering the static display scene of multiple displays.

[0182] S4 and SMC can configure the display engine to read frame data from the LPDDR memory and display it.

[0183] S5 and SMC can reduce the clock frequency of GDDR memory through the clock control module.

[0184] S6. In response to the completion of the clock frequency adjustment of the GDDR memory, the SMC may configure the display engine to read the frame data from the GDDR memory and display the frame data.

[0185] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0186] In addition, the present disclosure also provides a static display control device for a GPU, an electronic device, a computer-readable storage medium, and a computer program product, all of which can be used to implement any static display control method for a GPU provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method section and will not be repeated here.

[0187] FIG4 shows a block diagram of a static display control device for a GPU provided by an embodiment of the present disclosure. As shown in FIG4 , the static display control device for a GPU includes:

[0188] A first copy module 41 is configured to copy the frame data in the first video memory to the second video memory in response to entering a static display scene;

[0189] A first display module 42 is configured to read the frame data from the second display memory and display the frame data;

[0190] A reducing module 43, configured to reduce the clock frequency of the first video memory;

[0191] The second display module 44 is configured to read and display the frame data from the first video memory in response to the completion of adjusting the clock frequency of the first video memory.

[0192] In a possible implementation, the first copy module 41 is configured to:

[0193] In response to entering a static display scene, obtaining the number of displays;

[0194] Determining a second video memory according to the number of the displays;

[0195] The frame data in the first video memory is copied to the second video memory.

[0196] In a possible implementation, the first copy module 41 is configured to:

[0197] In response to the number of the displays falling within a preset number interval, the second video memory is determined to be a static random access memory in the GPU.

[0198] In a possible implementation, the first copy module 41 is configured to:

[0199] In response to the number of the displays not falling within a preset number interval, determining that the second video memory is a low power double data rate (LPDDR) memory in the GPU.

[0200] In a possible implementation, the first copy module 41 is configured to:

[0201] In response to the data amount of the frame data in the first video memory being less than or equal to the capacity of the static random access memory, all the frame data in the first video memory are copied to the static random access memory.

[0202] In one possible implementation,

[0203] The first copy module 41 is configured to: in response to the amount of frame data in the first video memory being greater than the capacity of the static random access memory, copy the first frame data in the first video memory to the static random access memory, wherein the amount of the first frame data is equal to the capacity of the static random access memory;

[0204] The device further includes: a second copy module, configured to copy the second frame data in the first display memory to a system memory.

[0205] In a possible implementation, the apparatus further includes:

[0206] The third copy module is configured to copy the second frame data in the system memory to the static random access memory in response to the first frame data in the static random access memory being retrieved.

[0207] In a possible implementation, the static random access memory adopts a ring buffer data structure.

[0208] An embodiment of the present disclosure provides a static display control device for a GPU, comprising a system management controller, a first video memory, a second video memory, a display engine, and a clock control module;

[0209] a system management controller, configured to copy the frame data in the first video memory to the second video memory in response to the notification message of entering the static display scene;

[0210] A display engine, configured to read the frame data from the second display memory and display the frame data;

[0211] A clock control module, configured to reduce the clock frequency of the first video memory;

[0212] The display engine is further configured to: in response to completion of adjusting the clock frequency of the first video memory, read the frame data from the first video memory and display the frame data.

[0213] In a possible implementation, the second video memory includes a static random access memory.

[0214] In a possible implementation, the static random access memory adopts a ring buffer data structure.

[0215] In a possible implementation, the second video memory includes an LPDDR memory.

[0216] In a possible implementation, the device further includes a direct memory access (DMA) module;

[0217] The system management controller is specifically configured to copy the frame data in the first video memory to the second video memory via the DMA module.

[0218] In a possible implementation, the apparatus further includes:

[0219] The static display control module is configured to send a notification message of entering the static display scene to the system management controller in response to entering the static display scene.

[0220] In a possible implementation, the apparatus further includes:

[0221] The system memory is used to back up the frame data.

[0222] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0223] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above method. The computer-readable storage medium may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium.

[0224] The embodiment of the present disclosure further provides a computer program, comprising a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0225] An embodiment of the present disclosure further provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0226] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0227] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0228] 5 shows a block diagram of an electronic device 800 according to an embodiment of the present disclosure. For example, the electronic device 800 may be a computer, a mobile phone, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0229] 5 , electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output interface 812 , a sensor component 814 , and a communication component 816 .

[0230] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0231] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0232] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0233] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0234] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0235] The input / output interface 812 provides an interface between the processing component 802 and peripheral interface modules, such as a keyboard, a click wheel, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0236] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 814 can also detect changes in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a complementary metal oxide semiconductor (CMOS) or charge coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0237] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as wireless network (Wi-Fi), second generation mobile communication technology (2G), third generation mobile communication technology (3G), fourth generation mobile communication technology (4G), long term evolution (LTE) of universal mobile communication technology, fifth generation mobile communication technology (5G), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0238] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0239] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 804 including computer program instructions. The computer program instructions can be executed by the processor 820 of the electronic device 800 to perform the above method.

[0240] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0241] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0242] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0243] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0244] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0245] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0246] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0247] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0248] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0249] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0250] If the technical solutions of the embodiments of the present disclosure involve personal information, the products applying the technical solutions of the embodiments of the present disclosure have clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, the products applying the technical solutions of the embodiments of the present disclosure have obtained the individual's separate consent before processing the sensitive personal information, and at the same time meet the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information. The personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0251] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A static display control method for a GPU, characterized in that: include: In response to entering a static display scene, copying frame data in the first video memory to the second video memory; Reading the frame data from the second video memory and displaying it; reducing the clock frequency of the first video memory; In response to the clock frequency of the first video memory being adjusted, the frame data is read from the first video memory and displayed.

2. The method according to claim 1, characterized in that In response to entering a static display scene, copying the frame data in the first video memory to the second video memory includes: In response to entering a static display scene, obtaining the number of displays; Determining a second video memory according to the number of the displays; The frame data in the first video memory is copied to the second video memory.

3. The method according to claim 2, characterized in that The step of determining the second video memory according to the number of the displays includes: In response to the number of the displays belonging to a preset number interval, determining that the second video memory is a static random access memory in the GPU.

4. The method according to claim 2, characterized in that: The step of determining the second video memory according to the number of the displays includes: In response to the number of the displays not belonging to a preset number interval, determining that the second video memory is a low power double data rate LPDDR memory in the GPU.

5. The method according to claim 3, characterized in that: The step of copying the frame data in the first video memory to the second video memory includes: In response to the data amount of the frame data in the first video memory being less than or equal to the capacity of the static random access memory, all the frame data in the first video memory are copied to the static random access memory.

6. The method according to claim 3, characterized in that The step of copying the frame data in the first video memory to the second video memory includes: In response to the data amount of the frame data in the first video memory being greater than the capacity of the static random access memory, copying the first frame data in the first video memory to the static random access memory, wherein the data amount of the first frame data is equal to the capacity of the static random access memory; The method further includes: copying the second frame data in the first display memory to the system memory.

7. The method according to claim 6, characterized in that The method further comprises: In response to the first frame of data in the static random access memory being retrieved, the second frame of data in the system memory is copied to the static random access memory.

8. The method according to any one of claims 3, 5-7, characterized in that: The static random access memory adopts a data structure of a ring buffer.

9. A static display control device for a GPU, characterized in that: include: A first copy module, configured to copy frame data in the first video memory to the second video memory in response to entering a static display scene; A first display module, used for reading the frame data from the second display memory and displaying the frame data; A reducing module, used for reducing the clock frequency of the first video memory; The second display module is used for reading and displaying the frame data from the first display memory in response to the clock frequency adjustment of the first display memory being completed.

10. A static display control device for a GPU, characterized in that: It includes a system management controller, a first video memory, a second video memory, a display engine and a clock control module; A system management controller, configured to copy the frame data in the first video memory to the second video memory in response to the notification message of entering the static display scene; A display engine, used for reading the frame data from the second display memory and displaying the frame data; A clock control module, used to reduce the clock frequency of the first video memory; The display engine is further configured to: in response to the clock frequency of the first video memory being adjusted, read the frame data from the first video memory and display the frame data.

11. The device according to claim 10, characterized in that The device also includes a direct memory access DMA module; The system management controller is specifically used to copy the frame data in the first video memory to the second video memory through the DMA module.

12. The device according to claim 10, characterized in that The device also includes: The static display control module is used for sending a notification message of entering the static display scene to the system management controller in response to entering the static display scene.

13. An electronic device, characterized in that: include: one or more processors; a memory for storing executable instructions; The one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 8.

14. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

15. A computer program product, characterized in that The invention comprises a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is executed in an electronic device, a processor in the electronic device executes the method according to any one of claims 1 to 8.

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