Layout data inspection system, layout data inspection method, program, and recording medium

Abstract

Provided is a novel inspection system. This layout data inspection system comprises: a reception means for receiving layout data to be inspected; a circuit pattern generation means for generating a circuit pattern from the layout data; a detection model generation means for generating a detection model by means of machine learning by using, as teacher data, a plan view of a circuit pattern that includes a shape abnormality and a cross-sectional view of a circuit pattern that includes a shape abnormality; a detection means for detecting, by using the detection model, a shape abnormality in the circuit pattern generated from the received layout data; and an output means for outputting detection information including position information for the detected shape abnormality.

Description

Layout data inspection system, layout data inspection method, program, and recording medium

[0001] One aspect of the present invention relates to a layout data inspection system, a layout data inspection method, a program, and a recording medium.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In recent years, there has been an increasing demand for higher integration, multi-functionality, and higher performance of electronic circuits. Accordingly, the complexity of circuit design has increased. In particular, there is a demand for more efficient, optimized, and automated layout design, which determines the layout of wiring and circuit elements necessary to achieve a desired circuit operation. Furthermore, in response to demands for higher integration, multi-functionality, and higher performance of integrated circuits, electronic circuits tend to be multi-layered, combining multiple wiring layers. Therefore, the complexity of layout design is likely to increase further. For example, Patent Document 1 discloses a layout design method for reducing the parasitic capacitance and parasitic resistance of wiring to within allowable values. Furthermore, for example, Patent Document 2 discloses a layout design method for suppressing variations in transistor characteristics.

[0004] Furthermore, the use of artificial intelligence (AI) is being considered for various applications. Examples of types of AI include discriminative AI such as image recognition and voice recognition, and generative AI such as text generation and image generation, which are utilized depending on the application. One example of utilizing artificial intelligence has been reported, which is its application to visual inspection in a manufacturing process. Patent Document 3 reports a system that automatically determines anomalies by analyzing the difference between an inspection image and an image generated by a neural network.

[0005] JP 2003-50835 A JP 2009-65056 A International Publication No. 2018-105023

[0006] The layout design of semiconductor devices such as integrated circuits must follow design rules that stipulate the minimum width of wiring, the shortest distance between adjacent wiring, etc. The design rules are determined taking into consideration the processing accuracy of the manufacturing equipment, etc. Generally, a design rule check (DRC) is performed to confirm that the designed layout does not violate the design rules.

[0007] Furthermore, in the process of layout design, unnecessary connection configurations, unnecessary routing configurations, etc. may occur unintentionally. Such unintended configurations may not be detected by DRC. Specifically, if the unintended configuration does not violate the design rules, it will not be detected by DRC. Furthermore, such unintended configurations are likely to cause increases in parasitic capacitance and parasitic resistance. Increases in parasitic capacitance and parasitic resistance can cause deterioration in the operating characteristics of semiconductor devices, increase in power consumption, etc.

[0008] It takes a lot of time for an operator to detect unintended configurations, which reduces the throughput of layout design. In addition, the detection accuracy is likely to vary among multiple operators due to oversights.

[0009] An object of one embodiment of the present invention is to provide an inspection system with high inspection efficiency that supports the layout design of a semiconductor device.An object of one embodiment of the present invention is to provide a novel inspection system that supports the layout design of a semiconductor device.An object of one embodiment of the present invention is to provide an inspection system that supports layout design for realizing a semiconductor device with improved operating characteristics.An object of one embodiment of the present invention is to provide an inspection system that supports layout design for realizing a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide an inspection system that supports layout design for realizing a semiconductor device with improved manufacturing yield.

[0010] The above-mentioned problem does not preclude the existence of other problems. Problems other than the above-mentioned problem will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract other problems other than the above-mentioned problem from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0011] (1) One aspect of the present invention is a layout data inspection system for a circuit including n wiring layers (n is an integer of 2 or more), the system comprising: a receiving means for receiving layout data; a circuit pattern generating means for generating, using the layout data, a first planar circuit pattern that is a planar structure of an i-th wiring layer (i is an integer of 1 or more and n or less); a second planar circuit pattern including planar structures of a p-th wiring layer (p is an integer of 1 or more and n-1 or less) and a p+1-th wiring layer, respectively; and a cross-sectional circuit pattern including cross-sectional structures of the p-th wiring layer and the p+1-th wiring layer, respectively; a detection means for detecting shape abnormalities in each of the first planar circuit pattern, the second planar circuit pattern, and the cross-sectional circuit pattern using a detection model machine-learned using the teacher planar circuit pattern including the teacher shape abnormality and the teacher cross-sectional circuit pattern including the teacher shape abnormality as training data; and an output means for outputting detection information including position information of the detected shape abnormality.

[0012] (2) Another aspect of the present invention is a layout data inspection method for a circuit including n wiring layers, which uses accepted layout data to generate a first planar circuit pattern that is a planar structure of the i-th wiring layer, a second planar circuit pattern that includes planar structures of each of the p-th wiring layer and the p+1-th wiring layer, and a cross-sectional circuit pattern that includes cross-sectional structures of each of the p-th wiring layer and the p+1-th wiring layer, detects shape abnormalities in each of the first planar circuit pattern, the second planar circuit pattern, and the cross-sectional circuit pattern using a detection model that has been machine-learned using the teacher planar circuit pattern including the teacher cross-sectional circuit pattern including the teacher shape abnormality as teacher data, and outputs detection information including position information of the shape abnormality to an output means.

[0013] Furthermore, it is preferable to use, as the training data, either or both of the antenna ratio and information related to design for manufacturing (DFM) technology. By adding either or both of the antenna ratio and information related to design for manufacturing (DFM) technology to the training data, it is possible to realize layout data that can improve the manufacturing yield of semiconductor devices.

[0014] The detection information includes, for example, position information of the detected shape abnormality, the name of the shape abnormality, and a circuit pattern image of the area including the detected shape abnormality.

[0015] Another aspect of the present invention is a program for implementing the layout data inspection system on one or more computers. Another aspect of the present invention is a program for executing the layout data inspection method on one or more computers. Another aspect of the present invention is a computer-readable recording medium on which the program is recorded.

[0016] According to one embodiment of the present invention, an inspection system with high inspection efficiency that supports the layout design of a semiconductor device can be provided. Alternatively, a novel inspection system that supports the layout design of a semiconductor device can be provided. Alternatively, an inspection system that supports the layout design for realizing a semiconductor device with improved operating characteristics can be provided. Alternatively, an inspection system that supports the layout design for realizing a semiconductor device with reduced power consumption can be provided. Alternatively, an inspection system that supports the layout design for realizing a semiconductor device with improved manufacturing yield can be provided.

[0017] The above-described effects do not preclude the existence of other effects. Effects other than the above-described effects will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract other effects other than the above-described effects from the description in this specification, drawings, claims, etc. One embodiment of the present invention does not necessarily have all of these effects (the above-described effects and other effects).

[0018] FIGS. 1A to 1C are diagrams illustrating an example of an inspection system. FIG. 2 is a diagram illustrating an example of an inspection system. FIGS. 3A to 3F are diagrams illustrating an example of a circuit pattern. FIGS. 4A to 4D are diagrams illustrating an example of a circuit pattern. FIGS. 5A to 5C are diagrams illustrating an example of a circuit pattern. FIGS. 6A and 6B are diagrams illustrating an example of the configuration of a neural network. FIG. 6C is a diagram illustrating an example of training data. FIG. 7 is a flowchart illustrating an example of the operation of the inspection system. FIG. 8 is a flowchart illustrating an example of the operation of the inspection system. FIG. 9 is a diagram illustrating an example of displaying inspection results. FIG. 10 is a flowchart illustrating an example of the operation of the inspection system. FIG. 11 is a flowchart illustrating an example of the operation of the inspection system.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor, a diode, etc.) or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit including a semiconductor element, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, or an electronic device equipped with an electronic component are examples of semiconductor devices. Furthermore, for example, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, electronic computers, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments.

[0021] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0022] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0023] In the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated explanations. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for ease of understanding, some components may be omitted in perspective views, plan views, etc. Furthermore, for example, some hidden lines may be omitted from the drawings. Furthermore, for example, hatching patterns may be omitted from the drawings.

[0024] In addition, in the drawings related to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, etc., the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, etc., one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0025] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "A", "b", "_1", "[n]", "[m, n]", etc. may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0026] Embodiment 1 In this embodiment, a configuration example and an operation example of an inspection system 100 that inspects layout data according to one embodiment of the present invention will be described.

[0027] In this specification, information relating to the wiring shape, wiring arrangement, circuit element shape, circuit element arrangement, etc. determined by layout design may be referred to as "layout data."

[0028] The shape and arrangement of each of the wiring and circuit elements generated based on layout data may also be called a "circuit pattern." The shape and arrangement of a plurality of circuit elements and the wiring connecting these circuit elements may also be called a "circuit pattern." Examples of such circuit patterns include photomask patterns, patterns used when directly drawing with an electron beam drawing device, patterns for printed circuit boards (PCBs), and patterns for flexible printed circuits (FPCs).

[0029] Layout data is a representation in vector format (e.g., Graphics Data System II (GDSII) or Drawing Exchange Format (DXF)) of a circuit pattern of an electronic circuit realized by a semiconductor device such as an integrated circuit, and includes information such as the types of elements included in the circuit pattern (points, lines, rectangles, polygons, etc.), vertices, and layers. For example, if the circuit pattern of an electronic circuit is composed of multi-layer wiring, the layout data includes the circuit pattern of each wiring layer and the circuit pattern of a connection layer (a layer including connection electrodes such as vias) provided between the wiring layers.

[0030] The planar structure or its planar view of a circuit pattern may be referred to as a “planar circuit pattern.” In a layout including multiple wiring layers, the cross-sectional structure or its cross-sectional view of a portion including one or more wiring layers may be referred to as a “cross-sectional circuit pattern.”

[0031] <Configuration Example of Inspection System> Fig. 1A shows a configuration example of an inspection system 100 according to one embodiment of the present invention. Fig. 1A shows, as an example, a component 10, an input unit 20, an input unit 30, and a display device 180. Fig. 1A illustrates a keyboard as the input unit 20. Fig. 1A also illustrates a mouse as the input unit 30.

[0032] The component 10 may be a desktop computer, a notebook computer, or the like. The component 10 may also be a large-scale computer such as a workstation, a server computer, or a supercomputer.

[0033] 1B and 1C are block diagrams illustrating an example configuration of an inspection system 100. The component 10 of the inspection system 100 includes a control device 110, an arithmetic device 120, a storage device 130, an auxiliary storage device 140, a communication device 150, and an input / output device 160. Each device is connected via a bus line 101. A display device 180 can also be connected to the component 10 via the bus line 101.

[0034] The input means 20 and the input means 30 are each connected to the input / output device 160. Note that the input means 20 and the input means 30 are not limited to a keyboard and a mouse. Various input means such as a trackball, a pen tablet, a digitizer, a touch panel, and an eye tracker can be used as the input means 20 and the input means 30.

[0035] [Control device 110, arithmetic device 120] The control device 110 has a function of controlling the operations of the devices included in the inspection system 100. The arithmetic device 120 has a function of executing arithmetic processing related to the inspection. For example, a central processing unit (CPU) can be used as the control device 110. For example, a CPU or a GPU (Graphics Processing Unit) can be used as the arithmetic device 120.

[0036] The control device 110 and the arithmetic device 120 can also be realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).

[0037] The calculation results obtained by the arithmetic unit 120 are stored in the storage unit 130 or the auxiliary storage unit 140. The calculation results obtained by the arithmetic unit 120 can be output to the outside via the communication unit 150 or the input / output unit 160. The calculation results obtained by the arithmetic unit 120 can also be displayed on the display unit 180.

[0038] [Storage Device 130] The storage device 130 has a function of storing programs and parameters related to the operation of the inspection system 100, and is preferably at least partially rewritable memory. The storage device 130 can include volatile memory such as RAM (Random Access Memory) and non-volatile memory such as ROM (Read Only Memory).

[0039] The RAM provided in the storage device 130 may be, for example, a dynamic random access memory (DRAM). A part of the RAM is allocated as a memory space as a working space for the inspection system 100. The operating system, application programs, data, etc. stored in the auxiliary storage device 140 are loaded into the RAM for execution.

[0040] The ROM provided in the storage device 130 may be a mask ROM, an OTPROM (One Time Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), etc. Examples of the EPROM include a UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory), which allows stored data to be erased by ultraviolet light irradiation, an EEPROM (Electrically Erasable Programmable Read Only Memory), and a flash memory. The ROM can store BIOS (Basic Input / Output System), firmware, etc., which do not require rewriting.

[0041] [Auxiliary Storage Device 140] The auxiliary storage device 140 is a storage device for storing an operating system, application programs, data, etc. Layout data 147 to be inspected is received by the input / output device 160 and stored in the auxiliary storage device 140. The auxiliary storage device 140 can store one or more pieces of layout data 147.

[0042] It is preferable to use a storage device that employs a nonvolatile storage element such as a flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change RAM), ReRAM (Resistive RAM), or FeRAM (Ferroelectric RAM) as the auxiliary storage device 140. Note that, if necessary, a volatile storage element such as a DRAM or SRAM (Static RAM) can also be used as the auxiliary storage device 140.

[0043] Furthermore, the auxiliary storage device 140 may be a recording media drive such as a hard disk drive (HDD) or a solid state drive (SSD).

[0044] Furthermore, a storage device such as an HDD or SSD that is detachable from the component 10 can also be used as the auxiliary storage device 140. Furthermore, a media drive for a computer-readable recording medium such as a flash memory, a Blu-ray Disc (registered trademark), a DVD, or a USB memory can also be used as the auxiliary storage device 140.

[0045] The application programs stored in the auxiliary storage device 140 include a control program 141, a physical verification program 142, a cross-section generation program 143, and a shape recognition program 144. The data stored in the auxiliary storage device 140 includes, in addition to layout data 147 accepted by the inspection system 100, a DRC database 145, a circuit pattern database 146, a learning database 148, and detection information 155 (see FIG. 1C ).

[0046] The control program 141 is a program for controlling the overall operation of the inspection system 100. The control program 141 is also a program for causing a computer to function as the inspection system 100.

[0047] The physical verification program 142 is a program for generating a plane circuit pattern 151 using the layout data 147. Therefore, the physical verification program 142 can be said to be a program that causes the component 10 to function as a circuit pattern generating means.

[0048] The control device 110 generates a planar circuit pattern 151 from layout data 147 using the arithmetic device 120 in accordance with the physical verification program 142. The planar circuit pattern 151 generated using the physical verification program 142 is stored in a circuit pattern database 146. The planar circuit pattern 151 includes a first planar circuit pattern 151a and a second planar circuit pattern 151b. The physical verification program 142 is a program for realizing DRC in the inspection system 100 based on the verification conditions held in the DRC database 145.

[0049] The cross section generation program 143 is a program for generating a cross section circuit pattern 152 using the layout data 147. Therefore, it can be said that the cross section generation program 143 is a program that causes the component 10 to function as a circuit pattern generation means. The control device 110 generates the cross section circuit pattern 152 from the layout data 147 using the arithmetic device 120 in accordance with the cross section generation program 143. The cross section circuit pattern 152 generated by the cross section generation program 143 is stored in a circuit pattern database 146.

[0050] It is also possible to add a function for generating the cross-sectional circuit pattern 152 to the physical verification program 142. It is also possible to generate one or both of the planar circuit pattern 151 and the cross-sectional circuit pattern 152 using the physical verification program 142.

[0051] It is also possible to add a function for generating a planar circuit pattern 151 to the cross section generation program 143. It is also possible to generate one or both of the planar circuit pattern 151 and the cross section circuit pattern 152 using the cross section generation program 143.

[0052] Furthermore, a program for realizing the function of generating a planar circuit pattern 151 and a cross-sectional circuit pattern 152 using layout data 147 may be provided in the component 10 separately from the physical verification program 142 and the cross-section generation program 143 .

[0053] The shape recognition program 144 has a function of generating a detection model 149 through machine learning using a teacher planar circuit pattern including a shape abnormality, a teacher cross-sectional circuit pattern including a shape abnormality, and a classification name (also referred to as a "mode name") of the shape abnormality as teacher data. Note that a shape abnormality for machine learning included in the teacher planar circuit pattern or the teacher cross-sectional circuit pattern is also referred to as a "teacher shape abnormality."

[0054] Training data used for machine learning is received by the input / output device 160 and stored in the learning database 148. Training data can also be received by the input / output device 160 via the communication device 150 and stored in the learning database 148. A detection model 149 generated by machine learning is stored in the learning database 148. The shape recognition program 144 is a program that causes the component 10 to function as a detection model generation means.

[0055] For example, an object detection model using a classification AI can be used as the detection model 149. In particular, it is preferable to use a neural network model. An example of the configuration of a neural network will be described later.

[0056] The shape recognition program 144 is also a program for detecting a shape abnormality included in one or both of the planar circuit pattern 151 and the cross-sectional circuit pattern 152, using the detection model 149, the planar circuit pattern 151, and the cross-sectional circuit pattern 152. In other words, the shape recognition program 144 is also a program for detecting a shape abnormality included in the layout data 147. Thus, the shape recognition program 144 is a program for causing the component 10 to function as a detection model generating means, and also causing the component 10 to function as a detecting means for detecting a shape abnormality included in the layout data 147.

[0057] If a shape abnormality is detected in one or both of the planar circuit pattern 151 and the cross-sectional circuit pattern 152, the control device 110 stores detection information 155, such as the location information of the location where the shape abnormality was detected (also called the "abnormal location"), a circuit pattern image of the area including the abnormal location, and the name of the corresponding mode, in the auxiliary storage device 140.

[0058] [Communication Device 150] The communication device 150 can communicate via an antenna. For example, the communication device 150 generates a control signal for connecting the inspection system 100 to a computer network in response to a command from the control device 110 and transmits the signal to the computer network. This allows the inspection system 100 to connect to and communicate with computer networks such as the Internet, an intranet, an extranet, a personal area network (PAN), a local area network (LAN), a campus area network (CAN), a metropolitan area network (MAN), a wide area network (WAN), or a global area network (GAN). Furthermore, if multiple communication methods are used, the communication device 150 may have multiple antennas depending on the communication methods.

[0059] The communication device 150 may be provided with, for example, a high-frequency circuit (RF circuit) for transmitting and receiving RF signals. The high-frequency circuit converts between electromagnetic signals and electrical signals in a frequency band defined by the laws of each country and communicates wirelessly with other communication devices using the electromagnetic signals. A practical frequency band is generally between several tens of kilohertz and several tens of gigahertz. The high-frequency circuit connected to the antenna has a high-frequency circuit section compatible with multiple frequency bands, and the high-frequency circuit section may be configured to include an amplifier, a mixer, a filter, a digital signal processor (DSP), an RF transceiver, etc. When wireless communication is performed, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and WCDMA (Wideband Code Division Multiple Access: registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark), can be used as communication protocols or communication technologies.

[0060] [Input / Output Device 160] The input / output device 160 has a function of controlling the input and output of signals between external devices and the inspection system 100. Furthermore, an HDMI (registered trademark) terminal, a USB terminal, a LAN connection terminal, or the like can be used as an external port of the input / output device 160. The input / output device 160 can also have a transmission / reception function for optical communication using infrared light, visible light, ultraviolet light, or the like. The input / output device 160 also functions as an interface for information input means such as a mouse, keyboard, trackball, pen tablet, digitizer, touch panel, and eye tracker.

[0061] Layout data 147 to be inspected is received by the input / output device 160 and stored in the auxiliary storage device 140 .

[0062] Furthermore, a user of the inspection system 100 (such as a layout designer of a semiconductor device) can specify the layout data 147 to be inspected, input parameters, instruct the execution of an application program, instruct the stopping of an application program, and so on, via the input / output device 160.

[0063] [Display Device 180] Various display devices can be used as the display device 180. For example, a liquid crystal display device, a light-emitting display device in which each pixel has a light-emitting element such as an EL (Electro Luminescence) element, an electrophoretic display device, or the like can be used. In addition, display devices such as a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and an FED (Field Emission Display) can be used.

[0064] If a shape abnormality is found in one or both of the planar circuit pattern 151 and the cross-sectional circuit pattern 152, part or all of the detection information 155 is displayed on the display unit 181 of the display device 180. Furthermore, the inspection system 100 can output the detection information 155 to an external device via the communication device 150 or the input / output device 160. Therefore, the communication device 150, the input / output device 160, and the display device 180 each function as an output means.

[0065] Note that the inspection system 100 according to one aspect of the present invention may omit some of the above configurations. For example, if the DRC function is not required, the DRC database 145 may be omitted. Furthermore, the inspection system 100 according to one aspect of the present invention may include additional configurations other than those described above.

[0066] <Modification of Inspection System> Fig. 2 shows a configuration example of an inspection system 100A which is a modification of the inspection system 100. The inspection system 100A shown in Fig. 2 includes an information terminal 40, an information processing device 191, an information processing device 192, an information processing device 193, and a circuit pattern database 146. Furthermore, the information terminal 40, the information processing device 191, the information processing device 192, and the information processing device 193 are connected to each other via a network 90.

[0067] The information terminal 40 preferably has the same functions as the component 10 and the display device 180. In the inspection system 100A, DRC, machine learning, detection of shape abnormalities, generation of cross-sectional structures, and the like can be performed by the information processing devices 191, 192, and 193, thereby reducing the load on the information terminal 40. Therefore, a portable information terminal such as a desktop computer, a notebook computer, or a tablet computer can be used as the information terminal 40. The information terminal 40 can also be called a "client computer" or the like.

[0068] Large-scale computers such as workstations, server computers, and supercomputers can be used as the information processing devices 191, 192, 193, and circuit pattern database 146. It is preferable that the information processing devices 191, 192, and 193 have the function of a parallel computer. In particular, it is preferable that the information processing device 193, which performs learning and inference, has the function of a parallel computer. This makes it possible to perform large-scale calculations required for processing such as AI learning and inference, for example.

[0069] The network 90 may be, for example, an intranet or an extranet. For example, a PAN, LAN, CAN, MAN, WAN, GAN, etc. may be used. Furthermore, the network 90 may be, for example, a global network. Specifically, the Internet, which is the foundation of the World Wide Web (WWW), may be used.

[0070] When wireless communication is performed, the communication protocol or technology that can be used may be, for example, a communication standard such as the fourth generation mobile communication system (4G), the fifth generation mobile communication system (5G), or the sixth generation mobile communication system (6G), or a specification standardized by the IEEE such as Wi-Fi (registered trademark) or Bluetooth (registered trademark).

[0071] Layout data 147 to be inspected is received by an input / output device 160 (not shown in FIG. 2) of the information terminal 40 and is stored in an auxiliary storage device 140 (not shown in FIG. 2) of the information terminal 40 .

[0072] The information processing device 191 stores, for example, a physical verification program 142 and a DRC database 145. The information processing device 191 has a function of acquiring layout data 147 stored in the auxiliary storage device 140 of the information terminal 40 via the network 90.

[0073] The physical verification program 142 possessed by the information processing device 191 is a program for generating a planar circuit pattern 151 by the information processing device 191 using layout data 147 to be inspected. The generated planar circuit pattern 151 is stored in a circuit pattern database 146. The generated planar circuit pattern 151 can be stored in a storage device provided in the information processing device 191, or can be stored in the auxiliary storage device 140 of the information terminal 40.

[0074] Furthermore, the physical verification program 142 possessed by the information processing device 191 is a program for implementing DRC in the information processing device 191. The information processing device 191 has a function of executing DRC on a planar circuit pattern in accordance with the physical verification program 142. The execution results of the DRC are supplied to the information terminal 40 via the network 90.

[0075] The information processing device 192 stores, for example, a cross section generation program 143. The information processing device 192 has a function of acquiring layout data 147 stored in the auxiliary storage device 140 of the information terminal 40 via the network 90.

[0076] The cross section generation program 143 possessed by the information processing device 192 is a program for generating a cross section circuit pattern in the information processing device 192 by using layout data 147 to be inspected. The generated cross section circuit pattern is stored in a circuit pattern database 146. The generated cross section circuit pattern can be stored in a storage device provided in the information processing device 192, or can be stored in the auxiliary storage device 140 of the information terminal 40.

[0077] The information processing device 193 also stores, for example, a shape recognition program 144, a learning database 148, and a detection model 149. The information processing device 193 has a function of acquiring layout data 147 stored in the auxiliary storage device 140 of the information terminal 40 via the network 90.

[0078] The shape recognition program 144 included in the information processing device 193 is a program that generates a detection model 149 by machine learning using a teacher planar circuit pattern 153 including a shape abnormality, a teacher cross-sectional circuit pattern 154 including a shape abnormality, and a mode name of the shape abnormality as teacher data in the information processing device 193. The teacher data used for machine learning and the detection model 149 generated by machine learning are stored in a learning database 148.

[0079] The shape recognition program 144 possessed by the information processing device 193 is also a program for detecting shape abnormalities contained in the planar circuit pattern 151 and the cross-sectional circuit pattern 152 by the information processing device 193. Therefore, the shape recognition program 144 possessed by the information processing device 193 is a program for causing the information processing device 193 to function as a detection model generating means and also as a detecting means for detecting shape abnormalities in the layout data 147. When a shape abnormality is detected, detection information 155 is supplied to the information terminal 40 via the network 90.

[0080] A part or all of the detection information 155 supplied to the information terminal 40 is displayed on the display unit 41 of the information terminal 40. In addition, the information terminal 40 can output the supplied detection information 155 to an external device via the communication device 150 or the input / output device 160.

[0081] As in the inspection system 100A, the information terminal 40, the information processing device 191, the information processing device 192, the information processing device 193, and the circuit pattern database 146 are configured to be connected to each other via a network 90, thereby distributing the load related to information processing.

[0082] A person who provides a service using an inspection system according to an aspect of the present invention can provide the service using a processing method according to an aspect of the present invention via a network 90, for example.

[0083] In addition, when a provider of a service using a processing method according to one aspect of the present invention and a user of the service belong to the same organization (such as a company), it is preferable to use, for example, a local network established within the organization as the network 90. ​​This allows for more secure information exchange than when a global network such as the Internet is used. Furthermore, it is possible to prevent confidential information within the organization from leaking to the outside.

[0084] Furthermore, a user of the inspection system 100 or the inspection system 100A can access the inspection system 100 or the inspection system 100A according to one aspect of the present invention via a network using, for example, dedicated application software or a web browser, etc. This allows the user to enjoy services using the inspection system 100 or the inspection system 100A from a remote location.

[0085] Note that the inspection system 100A according to one aspect of the present invention can omit some of the above configurations, similar to the inspection system 100. Furthermore, similar to the inspection system 100, the inspection system 100A according to one aspect of the present invention can add configurations other than the above configurations.

[0086] <Teacher Data Used in Machine Learning> Next, an example of teacher data used in machine learning will be described. Figures 3A to 3F, 4A to 4D, and 5A to 5C each show a part of a circuit pattern generated using layout data.

[0087] [Bump Mode] Fig. 3A shows a planar circuit pattern in which wiring 901 and wiring 902 are normally arranged. Figs. 3B and 3C show an example of a shape abnormality in which a protrusion is formed in a part of wiring 901 or wiring 902. In the present embodiment and the like, the classification name of the shape abnormality shown in Figs. 3B and 3C is referred to as a bump mode. In Fig. 3B, a protrusion 911 is formed in a part of wiring 901, and a protrusion 921 is formed in another part of wiring 901. In Fig. 3C, a protrusion 912 is formed in a part of wiring 902, and a protrusion 922 is formed in another part of wiring 902.

[0088] When a bump-mode shape abnormality occurs in a circuit pattern, the wiring distance outside the abnormality increases, which may increase the area occupied by the semiconductor device including the circuit pattern. Furthermore, as the wiring distance increases, the parasitic resistance and parasitic capacitance also increase, resulting in increased signal delay.

[0089] [Bented Mode] Fig. 3D shows a planar circuit pattern in which wiring 904 and wiring 905 are normally arranged. Fig. 3E shows an example of a shape abnormality in which bent portions 915 and 925 are formed in wiring 905. In the present embodiment and the like, the classification name of the shape abnormality shown in Fig. 3E is called a bent mode.

[0090] When a shape abnormality due to the Ventet mode occurs in a circuit pattern, the wiring distance including the Ventet mode increases, which may increase the area occupied by a semiconductor device including the circuit pattern. Furthermore, as the wiring distance increases, the parasitic resistance and parasitic capacitance also increase, resulting in a large signal delay.

[0091] [Loop Mode] Fig. 3F shows an example of a shape abnormality in which a loop portion 914 is formed in a wiring 904. In this embodiment and the like, the classification name of the shape abnormality shown in Fig. 3E is called a loop mode.

[0092] When a loop mode shape abnormality occurs in a circuit pattern, the area occupied by the wiring including the loop mode increases, resulting in increased parasitic capacitance. Furthermore, when forming the wiring 904 by wet etching, depending on the size of the ring-shaped portion 914, the etching solution may not easily enter the ring-shaped portion 914, which may result in the wiring not being processed into the intended shape. Furthermore, a rinse process is performed after the wet etching process to remove the etching solution, but the rinse solution may not easily enter the ring-shaped portion 914, which may result in the wiring width of the ring-shaped portion 914 becoming narrower or the wiring being broken.

[0093] [Bridge Mode] Fig. 4A shows a normal planar circuit pattern in which a wiring intersection in the circuit pattern is realized using two wiring layers and one connection layer at a wiring intersection portion. Fig. 4B shows a normal cross-sectional circuit pattern of a portion X1-X2 indicated by a dashed line in Fig. 4A. Figs. 4A and 4B show a configuration in which a wiring 906 extending in the Y direction crosses between wiring 907a and wiring 907b extending in the X direction.

[0094] The wiring 907a, wiring 907b, and wiring 906 shown in Figures 4A and 4B are formed in an i-th wiring layer 991 (i is an integer greater than or equal to 1). In this specification, the i-th wiring layer 991 is referred to as wiring layer 991_i. Furthermore, the wiring 909 shown in Figures 4A and 4B is formed in an i+1-th wiring layer 991. In this specification, the i+1-th wiring layer 991 is referred to as wiring layer 991_i+1. Furthermore, an i-th connection layer 992 is formed between the wiring layer 991_i and the wiring layer 991_i+1. In this specification, the i-th connection layer 992 is referred to as connection layer 992_i.

[0095] The wiring 907a is connected to the wiring 909 via an electrode 908a provided in the connection layer 992_i. Furthermore, the wiring 907b is connected to the wiring 909 via an electrode 908b provided in the connection layer 992_i. Therefore, the wiring 907a and the wiring 907b are connected via the electrode 908a, the electrode 908b, and the wiring 909. With this configuration, it is possible to realize an intersection of the wiring extending in the X direction and the wiring extending in the Y direction.

[0096] 4C and 4D show an example of a shape abnormality in which a wiring that can be formed without interruption in one wiring layer 991 is formed across multiple wiring layers 991. In the present embodiment and the like, the classification name of the shape abnormality shown in FIGS. 4C and 4D is called a bridge mode.

[0097] The bridge mode shown in Figures 4C and 4D can be considered a configuration obtained by removing the wiring 906 from the normal configuration shown in Figures 4A and 4B. Figure 4C shows a planar circuit pattern in the bridge mode. Figure 4D also shows a cross-sectional circuit pattern of the portion X3-X4 indicated by the dashed line in Figure 4C.

[0098] In the bridge mode, the wiring 907a and the wiring 907b are connected to the electrodes 908a and 908b provided in the connection layer 992_i via the wiring 909 provided in the wiring layer 991_i+1. However, since the wiring 906 shown in FIGS. 4A and 4B does not exist, the wiring 907a and the wiring 907b can be formed as one wiring 907.

[0099] When a bridge mode shape abnormality occurs in a circuit pattern, the contact resistance of the intervening electrodes and wiring increases, resulting in increased signal delay. Furthermore, the design freedom of other layers (here, the connection layer 992_i and the wiring layer 991_i+1) decreases. This can increase the area occupied by a semiconductor device including the circuit pattern. Furthermore, an increase in the number of electrodes and wiring between two wirings can reduce the manufacturing yield of the semiconductor device.

[0100] [Across mode] Fig. 5A shows a planar circuit pattern in which wiring 901, wiring 902, and wiring 903 are normally arranged. Fig. 5B shows a planar circuit pattern including a shape abnormality. Fig. 5C shows a cross-sectional circuit pattern of a portion X5-X6 indicated by a dashed line in Fig. 5B.

[0101] 5B and 5C, wiring 902a and wiring 902b are connected via wiring 909 having an overlapping area with wiring 901. In the present embodiment and the like, the classification name of the shape abnormality shown in FIGS. 5B and 5C is called the Across mode.

[0102] 5B and 5C , a wiring 901, a wiring 902a, and a wiring 902b are formed in a wiring layer 991_i. A wiring 909 is formed in a wiring layer 991_i+1. The wiring 902a is connected to the wiring 909 via an electrode 908a provided in a connection layer 992_i. The wiring 902b is connected to the wiring 909 via an electrode 908b provided in the connection layer 992_i. Thus, the wiring 902a and the wiring 902b are connected to each other via the electrode 908a, the electrode 908b, and the wiring 909.

[0103] In the across mode, the wiring 909 has an overlapping area with the wiring 901, which increases parasitic capacitance. Furthermore, the presence of electrodes and wiring between the wiring 902a and the wiring 902b increases contact resistance. Therefore, when a shape abnormality in the across mode occurs in the circuit pattern, signal delay increases compared to the normal circuit pattern shown in FIG. 5A . Furthermore, the area occupied by a semiconductor device including the circuit pattern may increase. Furthermore, an increase in the number of electrodes and wiring between the two wirings may reduce the manufacturing yield of the semiconductor device.

[0104] <Neural Network> In this specification, the term "neural network" refers to a general model that mimics biological neural networks, determines the connection strengths between neurons through learning, and provides problem-solving capabilities. A neural network has an input layer, an intermediate layer (also called a "hidden layer"), and an output layer. In a neural network, determining the connection strengths (also called weight coefficients) between neurons from existing information (also called a data set) is sometimes referred to as "learning" or "machine learning." In other words, a neural network model is created through learning. Learning methods include "supervised learning," "unsupervised learning," and "reinforcement learning." Furthermore, constructing a neural network using the connection strengths obtained through learning and deriving new conclusions from it is sometimes referred to as "inference." A neural network can be implemented using circuits (hardware) or programs (software).

[0105] For example, the detection model 149 can be generated by learning using a neural network and the above-mentioned training data, using a backpropagation method, a stochastic gradient descent method, or the like.

[0106] Furthermore, as a neural network detection model, for example, R-CNN (Regions with Convolutional Neural Networks), YOLO (You Only Look Once), SSD (Single Shot MultiBox Detector), DCN (Deformed Convolutional Networks), DETR (End-to-End Object Detection with Transformers), and HOG (Histogram of Oriented Gradient) can be used.

[0107] FIG. 6A shows an example of the configuration of a neural network NN. The neural network NN can be configured with an input layer IL, an output layer OL, and an intermediate layer HL. The input layer IL, output layer OL, and intermediate layer HL each have one or more neurons (units). The intermediate layer HL may have one layer or two or more layers. A neural network with two or more intermediate layers HL can also be called a DNN (deep neural network), and learning using a deep neural network can also be called deep learning.

[0108] Input data is input to each neuron in the input layer IL, the output signal of a neuron in the previous or next layer is input to each neuron in the hidden layer HL, and the output signal of a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron can be connected to all neurons in the previous or next layer (fully connected), or it can be connected to only some of the neurons.

[0109] An example of a neuron operation is shown in FIG. 6B. Here, a neuron N and an output x output from one of the neurons included in the previous layer are used. １ and the output x from another one of the neurons included in the previous layer. ２ Neuron N has an output x １ and output x ２ is input. Then, in neuron N, the output x １ And weight lol １ The multiplication result (x １ w １ ) and output x ２ And weight lol ２ The multiplication result (x ２ w ２ ) the sum x １ w １ +x ２ w ２ After is calculated, a bias b is added if necessary, and the value a = x １ w １ +x ２ w ２ Then, the value a is transformed by the activation function h, and the neuron N outputs an output signal y.

[0110] In this way, the operation by a neuron includes the operation of adding the product of the output of the neuron in the previous layer and the weight, that is, the sum-of-products operation (the above x １ w １ +x ２ w ２ ). This product-sum operation can be performed on software using a program, or it can be performed by hardware. When the product-sum operation is performed by hardware, a product-sum operation circuit can be used. This product-sum operation circuit can be a digital circuit or an analog circuit. When an analog circuit is used for the product-sum operation circuit, it is possible to reduce the circuit scale of the product-sum operation circuit or the number of memory accesses, thereby improving processing speed and reducing power consumption.

[0111] 6C is a conceptual diagram showing an example of training data 200 used for training the detection model 149. Circuit patterns classified according to the aforementioned shape anomaly modes can be used as the training data 200. For example, a circuit pattern including shape anomalies such as a bump mode, a vented mode, or a loop mode can be used as the training planar circuit pattern 153. Furthermore, a circuit pattern including shape anomalies such as a bridge mode or an across mode can be used as the training cross-sectional circuit pattern 154.

[0112] In addition to the circuit patterns classified by each mode of shape abnormality, information related to antenna ratios, DFM techniques, etc. can also be used as training data 200.

[0113] The antenna ratio refers to the ratio of the area of ​​an electrode exposed to plasma to the area of ​​overlap with the underlying electrode or semiconductor during the semiconductor device manufacturing process. In plasma-based processing, the electrode functions as an antenna to capture charged particles in the plasma, potentially resulting in charge-up damage such as dielectric breakdown. The larger the antenna ratio, the more likely charge-up damage occurs. DFM is a technology that improves manufacturing yield by varying the allowable shape of a circuit pattern depending on differences in the manufacturing process, such as differences in etching methods. By adding either or both of the antenna ratio and information related to DFM technology to the training data 200, layout data that can improve the manufacturing yield of semiconductor devices can be realized.

[0114] In this way, it is possible to use not only the circuit pattern including the shape abnormality described above as the training data 200 but also various other information.

[0115] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0116] Second Embodiment In this embodiment, an example of the operation of the inspection system 100 will be described. Note that the inspection system 100A can also operate in the same manner as the inspection system 100. In this embodiment, it is assumed that the circuit pattern to be inspected is composed of n (n is an integer of 2 or more) wiring layers 991 and n-1 connection layers 992.

[0117] First, a command to execute a control program 141 is input to the component 10 by a user of the inspection system 100. The control device 110 of the component 10 receives the execution command from the user, reads the control program 141 from the auxiliary storage device 140, and stores it in the storage device 130. The control device 110 controls the operation of the entire inspection system 100 in accordance with the control program 141.

[0118] <Operation Example 1> As an operation example of the inspection system 100, an operation (also referred to as "shape abnormality inspection") of searching for shape abnormalities in a circuit pattern generated from layout data 147 using a detection model 149 generated by machine learning will be described. Figures 7 and 8 are flowcharts for explaining an operation example of the inspection system 100.

[0119] In step S311, the layout data 147 to be inspected is received from an external device. Note that the layout data 147 to be inspected may be previously received. For example, the layout data 147 stored in the auxiliary storage device 140 may be used.

[0120] In step S312, a planar circuit pattern 151 and a cross-sectional circuit pattern 152 are generated from the received layout data 147.

[0121] In the operation example shown in this embodiment, the formation of the planar circuit pattern 151 is performed in accordance with the physical verification program 142. The control device 110 reads the physical verification program 142 from the auxiliary storage device 140 in accordance with the control program 141 and stores it in the storage device 130. The control device 110 also generates the planar circuit pattern 151 from the layout data 147 using the arithmetic device 120 in accordance with the physical verification program 142. The generated planar circuit pattern 151 is stored in the circuit pattern database 146, or in both the circuit pattern database 146 and the storage device 130.

[0122] In the operation example shown in this embodiment, the cross-section circuit pattern 152 is formed in accordance with the cross-section generation program 143. The control device 110 reads the cross-section generation program 143 from the auxiliary storage device 140 in accordance with the control program 141 and stores it in the storage device 130. The control device 110 also generates the cross-section circuit pattern 152 from the layout data 147 using the arithmetic device 120 in accordance with the cross-section generation program 143. The generated cross-section circuit pattern 152 is stored in the circuit pattern database 146, or in both the circuit pattern database 146 and the storage device 130.

[0123] Next, in steps S313 to S321, a loop process (also referred to as a "shape abnormality inspection loop") is performed to check the presence or absence of shape abnormalities for the planar circuit pattern 151 of each layer, the planar circuit pattern 151 consisting of multiple layers, and the cross-sectional circuit pattern 152 consisting of multiple layers. The shape abnormality inspection loop is executed during the period when i is equal to or less than n. In this embodiment, confirmation of shape abnormalities in the circuit pattern is performed sequentially from the first layer, which is the lowest layer, to the nth layer. However, the inspection order of each circuit pattern layer is not limited to this. It is also possible to inspect only one arbitrary layer depending on the inspection purpose, etc. Furthermore, it is also possible to inspect only odd-numbered layers or only even-numbered layers from the second layer to the (n-1)th layer depending on the inspection purpose, etc. Furthermore, the inspection order may be from the bottom layer to the top layer, or from the top layer to the bottom layer.

[0124] In step S314, inference is performed using the detection model 149 to search for shape abnormalities in the planar circuit pattern 151, which is the circuit pattern of the i-th wiring layer 991. Here, the planar circuit pattern 151 formed by the circuit pattern of the i-th wiring layer 991 (wiring layer 991_i) is referred to as a first planar circuit pattern 151a.

[0125] Specifically, first, control device 110 reads cross section generation program 143 from auxiliary storage device 140 in accordance with control program 141, and stores it in storage device 130. Next, control device 110 performs inference using detection model 149 in arithmetic device 120 in accordance with cross section generation program 143, and searches for shape abnormalities in first planar circuit pattern 151a.

[0126] In step S314, shape abnormalities of the circuit pattern, such as bump mode, bent mode, and loop mode, are mainly detected. If it is determined in step S315 that "shape abnormality is present," in step S316, the control device 110 uses the arithmetic device 120 to generate detection information 155, such as position information of the abnormality, the circuit pattern of the area including the abnormality, and the name of the corresponding mode. The generated detection information 155 is stored in the auxiliary storage device 140, or in both the auxiliary storage device 140 and the storage device 130.

[0127] If it is not determined in step S315 that "there is a shape abnormality," the process proceeds to step S317 without performing step S316. In step S317, it is determined whether i is less than n. That is, it is determined whether the layer position of the wiring layer 991 of the inspected planar circuit pattern is between the 1st layer and the (n-1)th layer. If i is n, the shape abnormality inspection is terminated.

[0128] If i is less than n, in step S318, inference is performed using the detection model 149 to search for shape abnormalities in the planar circuit pattern 151 configured of the i-th wiring layer 991 (wiring layer 991_i) and the (i+1)-th wiring layer 991 (wiring layer 991_i+1). Here, the planar circuit pattern 151 configured of the circuit pattern of the wiring layer 991_i and the circuit pattern of the wiring layer 991_i+1 is referred to as the second planar circuit pattern 151b. In this embodiment and other cases, when p is an integer greater than or equal to 1 and less than or equal to n-1, the second planar circuit pattern 151b is configured to include the circuit pattern of the p-th wiring layer 991 and the circuit pattern of the p+1-th wiring layer 991.

[0129] Specifically, similarly to step S314, control device 110 reads cross section generation program 143 from auxiliary storage device 140 in accordance with control program 141, and stores it in storage device 130. Next, control device 110 performs inference using detection model 149 in arithmetic device 120 in accordance with cross section generation program 143, and searches for shape abnormalities in second planar circuit pattern 151b.

[0130] In step S318, shape abnormalities in the circuit pattern, such as across mode, are mainly detected. If it is determined in step S319 that "a shape abnormality is present," in step S320, the control device 110 uses the arithmetic device 120 to generate detection information 155, such as position information of the abnormality, the circuit pattern of the area including the abnormality, and the name of the corresponding mode. The generated detection information 155 is stored in the auxiliary storage device 140, or in both the auxiliary storage device 140 and the storage device 130.

[0131] If it is not determined in step S319 that "there is a shape abnormality," the process proceeds to step S321 without performing step S320. In step S321, inference is performed using the detection model 149, as in step S314, to search for a shape abnormality in the cross-sectional circuit pattern 152 configured with the i-th wiring layer 991 (wiring layer 991_i), the i-th connection layer 992 (connection layer 992_i), and the i+1-th wiring layer 991 (wiring layer 991_i+1). In this embodiment and the like, when p is an integer between 1 and n-1, the cross-sectional circuit pattern 152 is configured to include the p-th wiring layer 991 and the p+1-th wiring layer 991.

[0132] In step S321, shape abnormalities of the circuit pattern, such as bridge mode, are mainly detected. If it is determined in step S322 that "a shape abnormality is present," in step S323, the control device 110 uses the arithmetic device 120 to generate detection information 155, such as position information of the abnormality, the circuit pattern of the area including the abnormality, and the name of the corresponding mode. The generated detection information 155 is stored in the auxiliary storage device 140, or in both the auxiliary storage device 140 and the storage device 130.

[0133] If it is not determined in step S322 that "a shape abnormality exists," the process proceeds to step S324 without performing step S323. In step S324, i is incremented by 1. Then, the process proceeds to step S325. At this time, if i exceeds n, the shape abnormality inspection loop ends, and the process proceeds to step S326. If i is equal to or less than n, the process proceeds to step S313, and the shape abnormality inspection loop continues to be executed.

[0134] In step S326, the control device 110 displays inspection results such as the detection information 155 on the display unit 181 of the display device 180. An example of the detection information 155 displayed on the display unit 181 of the display device 180 is shown in Fig. 9. Fig. 9 shows an example in which the display unit 181 displays the inspection date (date), the file name (File Name) of the inspected layout data, the serial number (No.) of the detected shape abnormality, position information of the detected abnormality (Detected Area: D.A.), the layer number (Layer Number: L.N.) in which the shape abnormality was detected, the mode name (Mode), the shape determination result of the planar circuit pattern (Plane), the shape determination result of the cross-sectional circuit pattern (Cross), the relative position (Map) of the shape abnormality with respect to the entire circuit pattern, and the circuit pattern image (Image) of the area including the abnormality. 9, "11 / 8 / 20XX" is displayed as the date, and "FL54" is displayed as the file name. Also, if no shape abnormality is detected, a circle (Good) is displayed, and if a shape abnormality is detected, an x ​​(No Good) is displayed. In FIG. 9, the map shows the relative position of the shape abnormality No. 3 with respect to the entire circuit pattern, and the image shows the planar circuit pattern of the area including the shape abnormality No. 3.

[0135] In this manner, it is possible to find shape abnormalities in a circuit pattern generated using the layout data 147. According to the inspection system 100 of one embodiment of the present invention, unintended configurations contained in the layout data 147 can be easily detected, thereby enabling the layout data 147 to be reliably corrected. Therefore, by using the inspection system 100 of one embodiment of the present invention, it is possible to achieve improvements in the operating characteristics of a semiconductor device, reductions in power consumption, and the like. Furthermore, by using the inspection system 100 of one embodiment of the present invention, it is possible to improve the throughput of layout design and increase the productivity of layout design. While an example of the operation of the inspection system 100 has been described in this embodiment, the inspection system 100A can also operate in the same manner as the inspection system 100.

[0136] In this embodiment, the second planar circuit pattern 151b and the cross-sectional circuit pattern 152 are each described as circuit patterns including two wiring layers, but one aspect of the present invention is also applicable to planar circuit patterns including three or more wiring layers and cross-sectional circuit patterns including three or more wiring layers.

[0137] <Operation Example 2> The shape anomaly inspection shown in Operation Example 1 is preferably performed after execution of DRC. By performing the shape anomaly inspection after execution of DRC, missed detection of shape anomalies is reduced, and productivity of layout design can be improved. Figures 10 and 11 show flowcharts explaining the operation of performing shape anomaly inspection after execution of DRC.

[0138] In step S331, similarly to step S311, the layout data 147 to be inspected is accepted.

[0139] In step S332, DRC is performed on the received layout data 147. In the operation example shown in this embodiment, DRC is performed on a circuit pattern generated in accordance with the layout data 147. The control device 110 reads out the physical verification program 142 from the auxiliary storage device 140 in accordance with the control program 141, and stores it in the storage device 130. The control device 110 also performs DRC on the circuit pattern using the arithmetic device 120 in accordance with the physical verification program 142.

[0140] It is determined whether or not there is a DRC violation in the circuit pattern (step S333), and if there is a violation, in step S334, the control device 110 prompts the user to make corrections, and the user corrects the layout data 147. In step S335, the corrected layout data 147 is saved in the auxiliary storage device 140. Thereafter, the process proceeds to step S332, where DRC is performed again on the corrected layout data 147.

[0141] If it is determined in step S333 that there is no DRC violation in the layout data 147, the process proceeds to step S336. In step S336, the shape abnormality detection described in operation example 1 is performed. The presence or absence of a shape abnormality is determined (step S337), and if a shape abnormality is found, in step S338, the control device 110 prompts the user to make corrections, and the user corrects the layout data 147. In step S339, the corrected layout data 147 is saved in the auxiliary storage device 140. Thereafter, the process proceeds to step S336, and shape abnormality detection is performed on the corrected layout data 147.

[0142] If it is determined in step S337 that there is no shape abnormality, it is determined whether the layout data 147 used in the shape abnormality detection in step S336 is data that has been corrected in the immediately preceding step S338 (step S340). If the layout data 147 used in the shape abnormality detection in step S336 is data that has been corrected in the immediately preceding step S338, the process proceeds to step S332 to confirm that the correction has not caused any DRC violation in the layout data 147.

[0143] If it is determined in step S340 that the layout data 147 used in the shape abnormality detection is not data that has been corrected after an abnormality was detected in the previous shape abnormality detection, the process ends.

[0144] According to the inspection system 100 of one embodiment of the present invention, unintended configurations included in the layout data 147 can be easily detected, thereby enabling the layout data 147 to be reliably corrected. Furthermore, by performing DRC and shape abnormality inspection in cooperation with each other, the layout data 147 can be more reliably corrected. Therefore, by using the inspection system 100 of one embodiment of the present invention, it is possible to achieve improvements in the operating characteristics of a semiconductor device, reductions in power consumption, and the like. Furthermore, by using the inspection system 100 of one embodiment of the present invention, it is possible to improve the throughput of layout design and increase the productivity of layout design.

[0145] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0146] 10: Component, 20: Input means, 30: Input means, 40: Information terminal, 41: Display unit, 90: Network, 100: Inspection system, 101: Bus line, 110: Control device, 120: Arithmetic device, 130: Storage device, 140: Auxiliary storage device, 141: Control program, 142: Physical verification program, 143: Cross section generation program, 144: Shape recognition program, 145: DRC database, 146: Circuit pattern database, 147: Layout data, 148: Learning database, 149: Detection model, 150: Communication device, 151: Planar circuit pattern, 152: Cross section circuit pattern, 153: Teacher planar circuit pattern, 154: Teacher cross section circuit pattern, 155: Detection information, 160 : input / output device, 180: display device, 181: display unit, 191: information processing device, 192: information processing device, 193: information processing device, 200: training data, 901: wiring, 902: wiring, 903: wiring, 904: wiring, 905: wiring, 906: wiring, 907: wiring, 909: wiring, 911: protrusion, 912: protrusion, 914: ring-shaped portion, 915: bending portion, 921: protrusion, 922: protrusion, 925: bent portion, 991: wiring layer, 992: connection layer, 100A: inspection system, 902a: wiring, 902b: wiring, 907a: wiring, 907b: wiring, 908a: electrode, 908b: electrode, 991_i: wiring layer, 992_i: connection layer, HL: intermediate layer, IL: input layer, NN: neural network, OL: output layer

Claims

A layout data inspection system for a circuit including n wiring layers (n is an integer of 2 or more), comprising: A receiving means for receiving layout data; Using the layout data, a first planar circuit pattern which is a planar structure of the wiring layer in an i-th layer (i is an integer of 1 to n); a second planar circuit pattern including planar structures of the p-th wiring layer (p is an integer of 1 to n-1) and the p+1-th wiring layer; a circuit pattern generating means for generating a cross-sectional circuit pattern including a cross-sectional structure of each of the p-th wiring layer and the p+1-th wiring layer; a detection means for detecting shape anomalies in the first planar circuit pattern, the second planar circuit pattern, and the cross-sectional circuit pattern by using a detection model machine-learned using a teacher planar circuit pattern including a teacher shape anomaly and a teacher cross-sectional circuit pattern including a teacher shape anomaly as teacher data; and an output means for outputting detection information including position information of the detected shape abnormality. Layout data inspection system. 　 In claim 1, A layout data inspection system that uses one or both of antenna ratios and information related to manufacturability-aware design technology as the teaching data. 　 In claim 1 or 2, A layout data inspection system, wherein the detection information includes a circuit pattern image of an area including the detected shape abnormality. 　 The layout data inspection system according to claim 1 or 2, A program for execution on one or more computers. 　 A computer-readable recording medium on which the program according to claim 4 is recorded. 　 A method for inspecting layout data of a circuit including n wiring layers (n is an integer of 2 or more), comprising the steps of: Using the received layout data, a first planar circuit pattern which is a planar structure of the wiring layer in an i-th layer (i is an integer of 1 to n); a second planar circuit pattern including planar structures of the p-th wiring layer (p is an integer of 1 to n-1) and the p+1-th wiring layer; a cross-sectional circuit pattern including a cross-sectional structure of each of the p-th wiring layer and the p+1-th wiring layer; A detection model machine-learned using a teacher planar circuit pattern including a teacher shape anomaly and a teacher cross-sectional circuit pattern including a teacher shape anomaly as teacher data is used. Detecting shape abnormalities of the first planar circuit pattern, the second planar circuit pattern, and the cross-sectional circuit pattern, The layout data inspection method further comprises outputting detection information including position information of the shape abnormality to an output means. 　 In claim 6, A layout data inspection method using one or both of antenna ratio and information related to manufacturability-aware design technology as the teacher data. 　 In claim 6 or 7, The layout data inspection method, wherein the detection information includes a circuit pattern image of the area including the detected shape abnormality. 　 The layout data inspection method according to claim 6 or 7, A program intended to be executed on one or more computers. 　 A computer-readable recording medium on which the program according to claim 9 is recorded.

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