Storage array and preparation method therefor, memory, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductor storage, provide a storage array and a preparation method therefor, a memory, and an electronic device, and are used for improving the storage density of a memory and simplifying the preparation process of a memory. The storage array comprises a substrate and multiple storage layers, the multiple storage layers being stacked along a first direction perpendicular to the substrate; the storage layers each comprise multiple memory cells, the memory cells each comprise a controllable thyristor, and the controllable thyristor comprises an active pattern, a gate electrode, a first electrode, and a second electrode. Along the first direction, the gate electrode is located on at least one side of the active pattern and is insulated from the active pattern; the first electrode extends along the first direction; the active pattern surrounds the peripheral side of the first electrode and is electrically connected to the first electrode; the second electrode and the active pattern are disposed on the same layer, and the second electrode is connected to the active pattern; and the active pattern is located between the first electrode and the second electrode. The described storage array is applied in a memory to improve the performance of the memory.

Description

Storage array and preparation method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 20, 2023, with application number 202311554587.6 and application name “Memory Array and Preparation Method thereof, Memory, Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor storage technology, and in particular to a storage array and a preparation method thereof, a memory, and an electronic device. Background Art

[0003] Memory is a device used to store information, typically digitizing the information and then storing it in electrical, magnetic, or optical media. Based on volatility, memory can be divided into volatile memory and non-volatile memory. Volatile memory is typically used as internal memory or cache, while non-volatile memory is typically used as external storage. Volatile memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), loses its stored information when the current or voltage is interrupted.

[0004] As memory density increases and overall size continues to shrink, the structure of memory cells within them is becoming increasingly diverse. Taking DRAM memory as an example, its memory cells can be either 1T1C or 2T0C, where T represents a transistor and C represents a capacitor. In 1T1C cells, the capacitor's size is difficult to reduce, hindering further memory scaling. In 2T0C cells, the numerous interfaces and relatively complex cell structure complicate the memory manufacturing process, making industrial applications difficult.

[0005] Based on this, how to provide a memory with high storage density and simple preparation process has become one of the technical problems that need to be solved urgently in this field.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a memory array and a method for manufacturing the same, a memory, and an electronic device, which are used to improve the storage density of the memory and simplify the memory manufacturing process.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, a memory array is provided, comprising a substrate and multiple memory layers. The multiple memory layers are stacked along a first direction perpendicular to the substrate. The memory layers include multiple memory cells, each including a controlled thyristor (SCR), each including an active pattern, a gate, a first electrode, and a second electrode.

[0010] Among them, along the first direction, the gate is located on at least one side of the active pattern and is insulated from the active pattern; the first pole extends along the first direction; the active pattern is arranged around the first pole and is electrically connected to the first pole; the second pole is arranged in the same layer as the active pattern and is connected to the active pattern; the active pattern is located between the first pole and the second pole; in the multiple storage layers, the first poles of the multiple storage cells arranged along the first direction are connected to form a bit line; in the storage layer, the second poles of the multiple storage cells are connected to form a common electrode layer.

[0011] In the storage array provided in the embodiment of the present application, multiple storage layers are stacked along a first direction perpendicular to the substrate, and each storage layer includes multiple storage cells, so that the multiple storage cells can not only be arranged along a direction parallel to the substrate, but also can be stacked along the first direction, so that the number of storage cells in the storage array provided in the embodiment of the present application can be large, and the storage density of the storage array can be high.

[0012] The storage unit provided in the embodiment of the present application includes a controllable thyristor, which has two states of on and off, and can be used to represent "0" or "1" to achieve information storage. There are no hot carriers in the controllable thyristor, so the reliability of the controllable thyristor can be higher, and the working stability of the storage unit using the controllable thyristor can also be higher. At the same time, the subthreshold swing of the controllable thyristor is small, so that the read and write speed of the storage unit provided in the embodiment of the present application can be faster. The operating voltage of the controllable thyristor is small, so that the power consumption of the storage unit provided in the embodiment of the present application can be small.

[0013] Compared to memory cells with a 1T1C structure provided by related art, the memory cells provided by embodiments of the present application do not require capacitors, thereby avoiding the problem of difficulty in increasing storage density due to the large space occupied by capacitors, thereby enabling a higher storage density for the memory array. Furthermore, compared to memory cells with a 2T0C structure provided by related art, the memory cells provided by embodiments of the present application utilize a single controlled thyristor structure, which can reduce the number of interfaces in the memory cell, simplify the structure of the memory array, and reduce costs.

[0014] Furthermore, in the controllable thyristor provided in the embodiments of the present application, the gate is located on at least one side of the active pattern, the active pattern is arranged around the first electrode, and the second electrode is provided on the same layer as the active pattern. This structural design can be implemented using existing 3D NAND fabrication processes, thereby simplifying the fabrication process of the memory array, reducing fabrication risks, and facilitating industrial application.

[0015] In some embodiments, the active pattern includes a first doped region, a second doped region, and an intrinsic region, the intrinsic region being located between the first doped region and the second doped region; the intrinsic region includes a first region and a second region, the first region being closer to the second doped region than the second region; the gate includes a first gate and a second gate; along the first direction, the active pattern is located between the first gate and the second gate; the projection of the first gate on the substrate at least partially overlaps with the projection of the first region on the substrate; and the projection of the intrinsic region on the substrate is located within the projection of the second gate on the substrate.

[0016] In the embodiment of the present application, by adjusting the voltages on the first gate, the second gate, the first pole, and the second pole, a PNPN junction (or NPNP junction) can be formed in the active pattern to generate a larger current, or an NNPP junction can be formed to generate a smaller current (or even no current), thereby realizing the opening and closing of the controllable thyristor.

[0017] In some embodiments, the projection of the active pattern on the substrate is annular, and the projection of the second gate on the substrate is annular; or, the projection of the active pattern on the substrate is semicircular, and the projection of the second gate on the substrate is semicircular.

[0018] In this way, the shape of the projection of the second gate on the substrate is the same as the shape of the projection of the active pattern on the substrate, so that the overlapping area between the projection of the second gate on the substrate and the projection of the active pattern on the substrate can be larger, and the gate has a stronger control ability over the controlled thyristor, which is beneficial to improving the storage performance of the controlled thyristor and improving the yield of the storage array.

[0019] In some embodiments, in the same memory layer, the second gates of multiple memory cells are connected to form a common gate layer.

[0020] In this way, the second gates in the same storage layer can share the same lead terminal, so that fewer lead terminals can be provided in the storage array, which is beneficial to simplifying the structure of the storage array, further reducing the size of the storage array, and reducing the size of the memory using the storage array.

[0021] In some embodiments, at least two adjacent memory cells in the first direction share the same second gate, which can reduce the number of second gates in the memory array, lower the cost of the memory array, and simplify the structure of the memory array.

[0022] In some embodiments, the active pattern includes a first doping region, a second doping region, a third doping region and an intrinsic region; the intrinsic region is located between the first doping region and the second doping region, and the third doping region is located between the first doping region and the intrinsic region; the doping element type of the third doping region is the same as the doping element type of the second doping region, and the doping element type of the third doping region is different from the doping element type of the first doping region; the gate includes a first gate, and the projection of the first gate on the substrate at least partially overlaps with the projection of the intrinsic region on the substrate.

[0023] In the embodiment of the present application, by adjusting the voltage on the first gate, the first pole, and the second pole, a PNPN junction (or NPNP junction) can be formed in the active pattern to generate a larger current, or an NNPP junction can be formed to generate a smaller current (or even no current), thereby realizing the opening and closing of the controllable thyristor.

[0024] In some embodiments, the projection of the active pattern on the substrate is in the shape of a circular ring, and the projection of the first gate on the substrate is in the shape of a circular ring; or, the projection of the active pattern on the substrate is in the shape of a semicircular ring, and the projection of the first gate on the substrate is in the shape of a semicircular ring; or, the projection of the first gate on the substrate is in the shape of a rectangle.

[0025] When the shapes of the projection of the active pattern on the substrate and the projection of the first gate on the substrate are both circular or semicircular, the shape of the projection of the first gate on the substrate is the same as the shape of the projection of the active pattern on the substrate, so that the overlapping area between the projection of the first gate on the substrate and the projection of the active pattern on the substrate can be larger, and the first gate has a stronger control ability over the controlled thyristor, which is beneficial to improving the performance of the controlled thyristor and the performance of the storage array.

[0026] When the projection of the first gate on the substrate is rectangular, the area of ​​the projection of the first gate on the substrate can be smaller, which is beneficial to reducing the area occupied by the first gate and reducing the cost of the memory array.

[0027] In some embodiments, multiple memory cells located in the same memory layer are arranged into multiple rows along the second direction and into multiple columns along the third direction; wherein the second direction and the third direction are both parallel to the substrate, and the second direction and the third direction are perpendicular to each other.

[0028] Two adjacent storage units in the second direction are symmetrically arranged with respect to a second reference plane; the second reference plane is perpendicular to the substrate and parallel to the third direction; and / or two adjacent storage units in the third direction are symmetrically arranged with respect to a third reference plane; the third reference plane is perpendicular to the substrate and parallel to the second direction.

[0029] By setting it in this way, the structure of the storage array can be made regular and orderly, which is convenient for preparation. At the same time, the stress balance of the storage array can be adjusted to ensure the structural stability of the storage array.

[0030] In some embodiments, the gate includes a first gate, and the memory array further includes a first connection structure, which is arranged in the same layer as the first gate and connects two adjacent first gates of multiple memory cells in the same row.

[0031] In some embodiments, the shape of the projection of the first connection structure on the substrate is the same as the shape of the projection of the first gate on the substrate. This allows the first word line formed by the first connection structure and the first gate to have a regular shape, thereby improving the regularity of the memory array structure and enhancing the structural stability of the memory array.

[0032] In some embodiments, the gate includes a first gate, the first gates of the plurality of memory cells in the same row are directly connected, and two adjacent active patterns of the plurality of memory cells in the same row are directly connected.

[0033] Thus, in the second direction, there is no gap between two adjacent memory cells. In the second direction, the number of memory cells that can be set per unit length can be large, so that the number of memory cells in a single memory layer can be large, which is conducive to increasing the number of memory cells in the memory array.

[0034] In some embodiments, two adjacent memory cells in the first direction are symmetrical about a first reference plane parallel to the substrate. This arrangement can provide a regular and orderly structure for the memory array, facilitate fabrication, and regulate stress balance in the memory array, ensuring structural stability.

[0035] In some embodiments, the projection of the active pattern on the substrate is in the shape of a semicircle; the projection of the first pole on the substrate is in the shape of a circle; and in the same storage layer, there are two adjacent storage cells sharing the same first pole.

[0036] This reduces the projected area of ​​the active pattern on the substrate, and thus the projected area of ​​the memory cells on the substrate. This allows for a greater number of memory cells per unit area of ​​the memory array, thereby improving the storage density of the memory array. Furthermore, since two memory cells share the same first electrode, the number of first electrodes in the memory array can be reduced, simplifying the overall structure of the memory array and reducing costs.

[0037] In some embodiments, the projection of the active pattern on the substrate is in the shape of a semicircle, and the projection of the first pole on the substrate is in the shape of a semicircle; or, the projection of the active pattern on the substrate is in the shape of a circular ring, and the projection of the first pole on the substrate is in the shape of a circle; in the same storage layer, one first pole is connected to one active pattern.

[0038] In some embodiments, the common electrode layers in the plurality of storage layers are connected.

[0039] At this time, the common electrode layers in multiple storage layers can share the same one or more lead terminals to receive electrical signals. Compared with the solution in which the common electrode layers in multiple storage layers are respectively connected to one or more lead terminals, the number of lead terminals in the storage array can be reduced, which is beneficial to simplifying the structure of the storage array, further reducing the size of the storage array, and further beneficial to reducing the size of the memory using the storage array.

[0040] In a second aspect, a method for preparing a memory array is provided, which may include forming a plurality of memory layers on a substrate, wherein the plurality of memory layers are stacked along a first direction perpendicular to the substrate; the memory layers include a plurality of memory cells, and the memory cells include controllable thyristors, and the controllable thyristors include an active pattern, a gate, a first pole, and a second pole.

[0041] Among them, along the first direction, the gate is located on at least one side of the active pattern and is insulated from the active pattern; the first pole extends along the first direction; the active pattern is arranged around the first pole and is electrically connected to the first pole; the second pole is arranged in the same layer as the active pattern and is connected to the active pattern; the active pattern is located between the first pole and the second pole; in the multiple storage layers, the first poles of the multiple storage cells arranged along the first direction are connected to form a bit line; in the storage layer, the second poles of the multiple storage cells are connected to form a common electrode layer.

[0042] In some embodiments, forming a plurality of storage layers on the substrate includes:

[0043] A plurality of stacked film layers are sequentially formed on a substrate, wherein the stacked film layers include a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially away from the substrate.

[0044] The semiconductor layer is etched to form a semiconductor pattern.

[0045] The semiconductor pattern is doped to form a second doping region.

[0046] A second electrode is formed, wherein the second electrode is disposed in the same layer as the semiconductor pattern and is connected to the second doped region.

[0047] A through hole is formed through the plurality of stacked film layers.

[0048] The first dielectric layer is removed through the through hole to form a first gate; the first gate is insulated from the semiconductor pattern.

[0049] The second dielectric layer is removed through the through hole to form a second gate; the second gate is insulated from the semiconductor pattern.

[0050] The semiconductor pattern is doped through the through hole to form a first doped region; there is a distance between the first doped region and the second doped region, and the undoped portion of the semiconductor pattern serves as an intrinsic region; the intrinsic region, the first doped region, and the second doped region form the active pattern; the intrinsic region includes a first area and a second area, and the first area is closer to the second doped region than the second area; the projection of the first gate on the substrate at least partially overlaps with the projection of the first area on the substrate; the projection of the intrinsic region on the substrate is located inside the projection of the second gate on the substrate.

[0051] A first electrode is formed in the through hole; the first electrode is connected to the first doping region.

[0052] In some embodiments, forming a plurality of storage layers on the substrate includes:

[0053] A plurality of stacked film layers are sequentially formed on a substrate, wherein the stacked film layers include a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially away from the substrate.

[0054] The semiconductor layer is etched to form a semiconductor pattern.

[0055] The semiconductor pattern is doped to form a second doping region.

[0056] A second electrode is formed, wherein the second electrode is disposed in the same layer as the semiconductor pattern and is connected to the second doped region.

[0057] A through hole is formed through the stacked film layers.

[0058] The first dielectric layer is removed through the through hole to form a first gate; the first gate is insulated from the semiconductor pattern.

[0059] The semiconductor pattern is doped through the through hole to form a third doping region and a first doping region; the undoped portion of the semiconductor pattern serves as an intrinsic region; the first doping region, the second doping region, the third doping region and the intrinsic region form the active pattern; wherein the third doping region is located between the first doping region and the intrinsic region; the doping element type of the third doping region is the same as the doping element type of the second doping region, and the doping element type of the third doping region is different from the doping element type of the first doping region; the projection of the first gate on the substrate at least partially overlaps with the projection of the intrinsic region on the substrate.

[0060] A first electrode is formed in the through hole; the first electrode is connected to the first doping region.

[0061] In some embodiments, etching the semiconductor layer to form a semiconductor pattern includes etching the semiconductor layer to form an initial semiconductor pattern, wherein the initial semiconductor pattern has a circular projection on the substrate. Etching the initial semiconductor pattern to form a trench and two semiconductor patterns located on either side of the trench, wherein the projections of the two semiconductor patterns on the substrate are both semicircular. Before doping the semiconductor pattern to form the second doped region, the preparation method further includes forming a filling layer in the trench. Forming a through hole through the multiple stacked film layers includes etching the filling layer to form a through hole through the multiple stacked film layers.

[0062] In some embodiments, forming the first electrode in the through hole includes depositing a conductive material in the through hole to form an initial electrode, etching the initial electrode to form two first electrodes; the two first electrodes are respectively connected to the two first doped regions in a direction parallel to the substrate.

[0063] In some embodiments, the stacked film layers further include another semiconductor layer located on a side of the second dielectric layer away from the substrate.

[0064] In a third aspect, a memory is provided, which may include a controller and a memory array as described in any one of the above embodiments. The controller is electrically connected to the memory array and is used to control the reading and writing of the memory array.

[0065] In a fourth aspect, an electronic device is provided. The electronic device may include the memory and the circuit board as described in the above embodiment, wherein the memory is located on the circuit board and is electrically connected to the circuit board.

[0066] Among them, the technical effects brought about by any design method in the second aspect and the fourth aspect can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0068] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0069] FIG2 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0070] FIG3 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0071] FIG4 is a schematic diagram of a three-dimensional structure of a storage array provided in an embodiment of the present application;

[0072] FIG5 is a schematic top view of a storage array provided in an embodiment of the present application;

[0073] FIG6 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0074] FIG7 is a schematic top view of another storage array provided in an embodiment of the present application;

[0075] FIG8 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0076] FIG9 is a schematic top view of another storage array provided in an embodiment of the present application;

[0077] FIG10 is a schematic structural diagram of another storage array provided in an embodiment of the present application;

[0078] FIG11 is a schematic diagram of the three-dimensional structure of another storage array provided in an embodiment of the present application;

[0079] FIG12 is a schematic structural diagram of another storage array provided in an embodiment of the present application;

[0080] FIG13 is an equivalent circuit diagram of a memory array provided in an embodiment of the present application;

[0081] FIG14 is an equivalent circuit diagram of another memory array provided in an embodiment of the present application;

[0082] FIG15 is a schematic diagram of a three-dimensional structure of another storage array provided in an embodiment of the present application;

[0083] FIG16 is a schematic diagram of a three-dimensional structure of another storage array provided in an embodiment of the present application;

[0084] FIG17 is a schematic top view of another storage array provided in an embodiment of the present application;

[0085] FIG18 is a schematic structural diagram of another storage array provided in an embodiment of the present application;

[0086] FIG19 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0087] FIG20 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0088] FIG21 is a flow chart of a process for preparing a storage array according to an embodiment of the present application;

[0089] 22 to 24 are structural diagrams of the storage array corresponding to step S100 and step S200 in the flowchart provided in FIG. 21 ;

[0090] 25 and 26 are structural diagrams of the storage array corresponding to step S210 and step S220 provided in an embodiment of the present application;

[0091] FIG27 is a schematic cross-sectional view taken along the line AA′ of FIG26 ;

[0092] FIG28 is a structural diagram of a storage array corresponding to step S230 provided in an embodiment of the present application;

[0093] 29A to 31 are structural diagrams of the storage array corresponding to steps S300 to S500 in the flowchart provided in FIG. 21 ;

[0094] 32 to 35 are structural diagrams of the storage array corresponding to steps S610 to S640 provided in an embodiment of the present application;

[0095] 36 to 39 are structural diagrams of the storage array corresponding to steps S710 to S740 provided in an embodiment of the present application;

[0096] 40 and 41 are structural diagrams of the storage array corresponding to step S800 and step S900 in the flowchart provided in FIG. 21 , respectively;

[0097] FIG42 is a structural diagram of a storage array corresponding to step S920 provided in an embodiment of the present application;

[0098] FIG43 is a flow chart of another process for preparing a memory array according to an embodiment of the present application;

[0099] 44 and 45 are structural diagrams of the storage array corresponding to step S700 ′ and step S800 ′ in the flowchart provided in FIG. 43 , respectively. DETAILED DESCRIPTION

[0100] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0101] In the following embodiments of the present application, the terms "first," "second," etc. are used for convenience of description only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0102] In the embodiments of the present application, “upper”, “lower”, “left” and “right” are not limited to being defined relative to the orientations of the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative description and clarification, and may change accordingly according to changes in the orientations of the components in the drawings.

[0103] In the embodiments of the present application, unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0104] When describing some embodiments, the term "coupled" and its derivatives may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0105] In the embodiments of the present application, exemplary embodiments are described with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams as idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0106] An embodiment of the present application provides an electronic device. FIG1 is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 can be a terminal device such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0107] As shown in Figure 1, the electronic device 100 may include a bus 110 and a system on chip (SOC) 120 connected to the bus 110. The SOC 120 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 120 may include an application processor (AP) 121 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first random access memory (RAM) 123 for caching high-speed data. The first RAM 123 may be a static random access memory (SRAM) or an embedded flash memory (EFlash). The AP 121, GPU 122, and first RAM 123 may be integrated into a single die or may be separately provided in multiple dies.

[0108] As shown in FIG1 , the electronic device 100 may further include a second RAM 130 connected to the SOC 120 via the bus 110. The second RAM 130 may be a dynamic random access memory (DRAM). The second RAM 130 may be used to store volatile data, such as temporary data generated by the SOC 120. The storage capacity of the second RAM 130 is generally greater than that of the first RAM 123, but the read speed is generally slower than that of the first RAM 123.

[0109] In addition, the electronic device 100 may further include a communication chip 140 and a power management chip 150 connected to the SOC 120 via the bus 110. The communication chip 140 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 150 may be used to power other chips. In one embodiment, the SOC 120 and the second RAM 130 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve faster inter-chip data transmission rates.

[0110] FIG2 is a circuit block diagram of a memory 200 that can be used in an electronic device according to an embodiment of the present application. In one embodiment, the memory 200 can be the first RAM 123 shown in FIG1 , or the second RAM 130. The application scenario of the memory 200 of the present application is not limited. In one possible embodiment, the memory 200 can also be a RAM provided outside the SOC 120. The location of the memory 200 in the electronic device and its positional relationship with the SOC 120 are not limited in the present application.

[0111] As shown in FIG. 2 , the memory 200 includes a memory array 300 and a controller 210 for accessing the memory array 300 , wherein the controller 210 is used to control read and write operations of the memory array 300 .

[0112] The memory array 300 and the controller 210 have various possible packaging structures. For example, the memory array 300 and the controller 210 may be two independent chips, each integrated on a substrate. For example, the memory array 300 and the controller 210 may be electrically connected via metal traces arranged on the substrate. In this structure, since the memory array 300 and the controller 210 are two independent chips, the memory array 300 may be referred to as a stand-alone memory.

[0113] Alternatively, the memory array 300 and the controller 210 are stacked. For example, the memory array 300 and the controller 210 may be connected to each other through a through silicon via (TSV) or a redistribution layer (RDL).

[0114] Alternatively, the memory array 300 and the controller 210 are integrated into the same chip, and the chip is integrated on a substrate. Therefore, the memory array 300 can be called an embedded memory.

[0115] In some examples, as shown in FIG3 , the memory array 300 may include a plurality of memory cells 310 , each of which may be used to store 1 bit (bit) or multiple bits of data. The memory array 300 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 310 is electrically connected to a corresponding word line and bit line. Different memory cells 310 may be electrically connected via word lines and bit lines. One or more of the above-mentioned word lines and bit lines are used to select a memory cell 310 to be read or written in the memory array by receiving a control level output by a control circuit, thereby implementing data read and write operations.

[0116] The controller 210 in the memory may include one or more circuit structures of the decoder 211 , the driver 212 , the timing controller 213 , the buffer 214 , or the input / output driver 215 shown in FIG. 3 .

[0117] In the memory 200 structure shown in Figure 3, the decoder 211 is used to decode the received address to determine the storage unit 310 that needs to be accessed. The driver 212 is used to control the level of the signal line according to the decoding result generated by the decoder 211, thereby achieving access to the specified storage unit 310. The buffer 214 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO) method. The timing controller 213 is used to control the timing of the buffer 214 and control the driver 212 to drive the signal lines in the storage array 300. The input and output driver 215 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0118] The memory array 300 , decoder 211 , driver 212 , timing controller 213 , buffer 214 and input / output driver 215 may be integrated into one chip or may be integrated into multiple chips.

[0119] The memory 200 involved in the embodiment of the present application may be a dynamic random access memory (DRAM). In a traditional DRAM, a memory cell is composed of a transistor and a capacitor, and the memory cell has a 1T1C structure.

[0120] With the continuous development of integrated circuits, the size of transistors in memory cells continues to shrink. This has also brought about the inevitable short-channel effect, such as increased transistor leakage current and reduced mobility. When the transistor is in the off state, a certain amount of leakage exists between the source and drain. At the same time, the projected area of ​​the capacitor is also getting smaller and smaller as the transistor shrinks. To ensure the stable operation of the memory cell, the capacitor needs to be made taller. However, the continuous increase in capacitor height and the continuous shrinking of projected area also pose a great challenge to the etching process.

[0121] While three-dimensional (3D) DRAM based on a 1T1C structure can increase storage density through vertical stacking, the capacitors in the memory cells remain difficult to reduce, resulting in a relatively large overall structure. Furthermore, the number of stacked layers is affected by the depth of the etching process, making it difficult to increase storage density. 3D DRAM based on a 2T0C structure eliminates the need for capacitors, allowing for higher storage density. However, due to the numerous interfaces in the memory cells and the relatively complex structure, its fabrication process is complex and risky, making it difficult to commercialize.

[0122] To address the above issues, an embodiment of the present application provides a storage array 300. FIG4 shows a schematic diagram of the three-dimensional structure of a storage array 300 provided in an embodiment of the present application, FIG5 shows a top view of a storage array 300 provided in an embodiment of the present application, and FIG6 shows a schematic diagram of the structure of a storage array 300 provided in an embodiment of the present application.

[0123] As shown in Figures 4 to 6, the memory array 300 includes a substrate 10 and multiple memory layers 20. The multiple memory layers 20 are stacked along a first direction Z perpendicular to the substrate 10. The memory layers 20 include multiple memory cells 310. The memory cells 310 include controllable thyristors T. The controllable thyristors T include an active pattern 21, a gate 22, a first electrode 23, and a second electrode 24.

[0124] In the embodiment of the present application, there is no limitation on the number of storage layers 20 or the number of storage units 310 in a single storage layer 20, and the number can be designed according to storage requirements.

[0125] As shown in Figure 5, multiple memory cells 310 located in the same memory layer 20 are arranged into multiple rows along the second direction X and into multiple columns along the third direction Y. The second direction X and the third direction Y are both parallel to the substrate 10 and perpendicular to each other.

[0126] In some examples, the material of the active pattern 21 includes one or a combination of semiconductor materials such as Si (silicon), poly-Si (polycrystalline silicon), amorphous-Si (amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multi-compound, ZnO (zinc oxide), In-Ti-O (ITO, indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), etc.

[0127] The gate 22 is located on at least one side of the active pattern 21 along the first direction Z and is insulated from the active pattern 21. It is understood that in the thyristor T, when the structure of the gate 22 is different, the structure of the active pattern 21 of the thyristor is also different accordingly.

[0128] Exemplarily, the material of the gate 22 is a conductive material. For example, the material of the gate 22 can be at least one of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (rubidium), and Ag (silver).

[0129] As shown in Figures 5 and 6, the first electrode 23 extends along the first direction Z. The active pattern 21 is disposed around the first electrode 23 and is electrically connected to the first electrode 23. In the plurality of memory layers 20, the first electrodes 23 of the plurality of memory cells 310 arranged along the first direction Z are connected to form a bit line BL.

[0130] It can be understood that "the active pattern 21 is arranged around the circumference of the first pole 23", which can not only be as shown in Figure 5, where the active pattern 21 is arranged around the first pole 23 in a circle in a direction parallel to the substrate 10, but also can be as shown in Figure 7, where the active pattern 21 is arranged around the first pole 23 half a circle.

[0131] In some examples, as shown in FIG5 , the projection of the active pattern 21 on the substrate 10 can be annular, and the projection of the first electrode 23 on the substrate 10 can be circular. In the same storage layer 20, one storage cell corresponds to one first electrode 23, that is, one first electrode 23 is connected to one active pattern 21. In this case, the structures of both the active pattern 21 and the first electrode 23 are relatively simple, which helps simplify the manufacturing process, reduce the process difficulty, and improve the manufacturing efficiency.

[0132] In other examples, as shown in Figures 7 and 8 , the projection of the active pattern 21 on the substrate 10 is semicircular, and the projection of the first pole 23 on the substrate 10 is circular. In the same storage layer 20, two adjacent storage cells 310 share the same first pole 23, meaning that at least one first pole 23 connects the two active patterns 21. Figures 7 and 8 illustrate an example where two adjacent storage cells 310 in the second direction Y share the same first pole 23.

[0133] In this way, the projected area of ​​the active pattern 21 on the substrate 10 is smaller, the projected area of ​​the storage unit 310 on the substrate 10 can be smaller, and the number of storage units 310 per unit area of ​​the storage array 300 can be larger, which is beneficial to improving the storage density of the storage array 300.

[0134] At the same time, the two memory cells 310 share the same first pole 23, which can also reduce the number of first poles 23 in the memory array 300, simplify the overall structure of the memory array 300, and reduce costs. It is understood that when the number of first poles 23 in the memory array 300 is small, the structure of the controller of the memory 200 using the memory array 300 can also be simpler, thereby simplifying the structure of the memory 200.

[0135] In some other examples, as shown in Figures 9 and 10, the projection of the active pattern 21 on the substrate 10 is semicircular, and the projection of the first pole 23 on the substrate 10 is also semicircular. In the same storage layer 20, one storage unit 310 corresponds to one first pole 23, that is, one first pole 23 is connected to one active pattern 21.

[0136] Through such an arrangement, the projected areas of the active pattern 21 and the first pole 23 on the substrate 10 are both smaller, the projected area of ​​the storage unit 310 on the substrate 10 can be smaller, and the number of storage units 310 per unit area of ​​the storage array 300 can be larger, which is beneficial to improving the storage density of the storage array 300.

[0137] As shown in FIG4 , the second electrode 24 is provided in the same layer as the active pattern 21 and is connected to the active pattern 21. The active pattern 21 is located between the first electrode 23 and the second electrode 24. In the storage layer 20, the second electrodes 24 in multiple memory cells 310 are connected to form a common electrode layer 25.

[0138] The material of the first electrode 23 and the material of the second electrode 24 may be the same or different. For example, the material of the first electrode 23 and the second electrode 24 may include at least one of TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, and Ag.

[0139] In some examples, as shown in Figure 6, the common electrode layers 25 in the multiple storage layers 20 are connected. For example, the common electrode layers 25 in the multiple storage layers 20 can be connected in series or in parallel.

[0140] At this time, referring to Figure 4, the common electrode layers 25 in multiple storage layers 20 can share the same one or more lead terminals 320 to receive electrical signals. Compared with the solution in which the common electrode layers 25 in multiple storage layers 20 are respectively connected to one or more lead terminals, the number of lead terminals in the storage array 300 can be reduced, which is beneficial to simplifying the structure of the storage array 300, further reducing the size of the storage array 300, and further beneficial to reducing the size of the memory 200 using the storage array 300.

[0141] When the common electrode layers 25 in the plurality of storage layers 20 are connected in parallel, the total resistance of the plurality of common electrode layers 25 can be reduced, thereby reducing the power consumption of the storage array 300 , thereby facilitating improved performance of the storage array 300 .

[0142] In other examples, as shown in FIG11 , the common electrode layers 25 in the multiple storage layers 20 can form a single integral structure. This eliminates the need for a connecting structure to connect two adjacent common electrode layers 25, thereby further simplifying the structure of the memory array 300. This arrangement can also increase the cross-sectional area of ​​the common electrode layers 25 in the multiple storage layers 20, thereby lowering the total resistance of the common electrode layers 25 in the multiple storage layers 20, further reducing power consumption and improving the performance of the memory array 300.

[0143] In some examples, referring to Figures 6, 8, and 10, the memory array 300 further includes a gate dielectric layer 26, which is located between the gate 22 and the active pattern 21 to insulate the active pattern 21 from the gate 22. The gate dielectric layer 26 is also located between the gate 22 and the first electrode 23 and the second electrode 24 to insulate the gate 22 from the first electrode 23 and from the second electrode 24.

[0144] In one possible implementation, the gate dielectric layer 26 may be made of a high-k dielectric material, such as SiO2 (silicon dioxide), Al2O3 (silicon dioxide), HfO2 (hafnium dioxide), ZrO2 (zirconium dioxide), TiO2 (titanium dioxide), Y2O3 (yttrium dioxide), Si3N4 (silicon nitride), etc. A high-k dielectric material refers to a material having a dielectric constant greater than 3.

[0145] In the storage array 300 provided in the embodiment of the present application, multiple storage layers 20 are stacked along a first direction Z perpendicular to the substrate 10, and each storage layer 20 includes multiple storage cells 310, so that the multiple storage cells 310 can not only be arranged along a direction parallel to the substrate 10, but also can be stacked along the first direction Z, so that the number of storage cells 310 in the storage array 300 provided in the embodiment of the present application can be large, and the storage density of the storage array 300 can be high.

[0146] The storage unit 310 provided in the embodiment of the present application includes a controllable thyristor T, which has two states of on and off, and can be used to represent "0" or "1" to achieve information storage. There are no hot carriers in the controllable thyristor T, so that the reliability of the controllable thyristor T can be higher, and the working stability of the storage unit 310 using the controllable thyristor T can also be higher. At the same time, the sub-threshold swing (SS) of the controllable thyristor T is small, so that the read and write speed of the storage unit 310 provided in the embodiment of the present application can be faster. The operating voltage of the controllable thyristor T is small, so that the power consumption of the storage unit 310 provided in the embodiment of the present application can be small.

[0147] Compared to memory cells with a 1T1C structure provided in related art, the memory cell 310 provided in the embodiment of the present application does not require a capacitor, thereby avoiding the problem of difficulty in increasing storage density due to the large space occupied by capacitors, thereby enabling a higher storage density for the memory array 300. Furthermore, compared to memory cells with a 2T0C structure provided in related art, the memory cell 310 provided in the embodiment of the present application utilizes a single controlled thyristor T, which reduces the number of interfaces in the memory cell 310, simplifies the structure of the memory array 300, and reduces costs.

[0148] In addition, in the controllable thyristor T provided in the embodiment of the present application, the gate 22 is located on at least one side of the active pattern 21. The active pattern 21 is arranged around the first electrode 23, and the second electrode 24 is provided on the same layer as the active pattern 21. This structural design can be implemented using existing 3D NAND manufacturing processes, thereby making the manufacturing process of the memory array 300 relatively simple, with low manufacturing risks, and facilitating industrial application.

[0149] In order to make the structure of the memory array 300 regular and orderly for easy preparation, and to adjust the stress balance of the memory array 300 and ensure the structural stability of the memory array 300, the memory array 300 may have a symmetrical structure.

[0150] At this time, in some examples, as shown in FIG12 , two adjacent memory cells 310 in the first direction Z may be symmetrical about the first reference plane Q1 , wherein the first reference plane Q1 is parallel to the substrate 10 .

[0151] 9 , two adjacent memory cells 310 in the second direction X may be symmetrically arranged about the second reference plane Q2 , wherein the second reference plane Q2 is perpendicular to the substrate 10 and parallel to the third direction Y.

[0152] Alternatively, in some examples, referring to FIG9 , two adjacent memory cells 310 in the third direction Y may be symmetrically arranged about a third reference plane Q3 , wherein the third reference plane Q3 is perpendicular to the substrate 10 and parallel to the second direction X.

[0153] It is understood that, in the memory array 300, when two adjacent memory cells 310 in the first direction Z are symmetrical about the first reference plane Q1, two adjacent memory cells 310 in the second direction X can be symmetrically arranged about the second reference plane Q2. Alternatively, when two adjacent memory cells 310 in the memory array 300 are symmetrical about the first reference plane Q1, two adjacent memory cells 310 in the third direction Y can be symmetrically arranged about the third reference plane Q3. Alternatively, when two adjacent memory cells 310 in the memory array 300 are symmetrical about the first reference plane Q1, two adjacent memory cells 310 in the second direction X can be symmetrically arranged about the second reference plane Q2, and two adjacent memory cells 310 in the third direction Y can be symmetrically arranged about the third reference plane Q3.

[0154] The structure of the controlled thyristor T is briefly described above. A possible structure of the controlled thyristor T is described in detail below with reference to FIG. 12 .

[0155] As shown in FIG12 , in some embodiments, the active pattern 21 includes a first doped region 21 a, a second doped region 21 b, and an intrinsic region 21 c. The intrinsic region 21 c is located between the first doped region 21 a and the second doped region 21 b. The intrinsic region 21 c includes a first region M1 and a second region M2. The first region M1 is closer to the second doped region 21 b than the second region M2.

[0156] In some examples, the first doping region 21a may be doped with a pentavalent element to serve as an N-type doping region, and the second doping region 21b may be doped with a trivalent element to serve as a P-type doping region. Of course, in other examples, the first doping region 21a may also be doped with a trivalent element to serve as a P-type doping region, and the second doping region 21b may be doped with a pentavalent element to serve as an N-type doping region.

[0157] The pentavalent element may be, for example, phosphorus, arsenic, antimony, etc. The trivalent element may be, for example, boron, indium, gallium, etc.

[0158] The gate 22 includes a first gate 221 and a second gate 222. Along the first direction Z, the active pattern 21 is located between the first gate 221 and the second gate 222. The projection of the first gate 221 on the substrate 10 at least partially overlaps with the projection of the first region M1 on the substrate 10. The projection of the intrinsic region 21c on the substrate 10 is located within the projection of the second gate 222 on the substrate 10. It will be understood that the first gate 221 and the second gate 222 are both insulated from the first electrode 23 and the second electrode 24. The first gate 221 and the second gate 222 are both insulated from the active pattern 21.

[0159] “The projection of the first gate 221 on the substrate 10 at least partially overlaps with the projection of the first region M1 on the substrate 10” includes both a situation where the projection of the first gate 221 on the substrate 10 partially overlaps with the projection of the first region M1 on the substrate 10 and a situation where the projection of the first gate 221 on the substrate 10 completely overlaps with the projection of the first region M1 on the substrate 10.

[0160] In which, when the projection of the intrinsic region 21c on the substrate 10 is located inside the projection of the second gate 222 on the substrate 10, the boundary of the projection of the intrinsic region 21c on the substrate 10 can completely overlap with the boundary of the projection of the second gate 222 on the substrate 10, or can partially overlap with the boundary of the projection of the second gate 222 on the substrate 10. Of course, there can also be a gap between the boundary of the projection of the intrinsic region 21c on the substrate 10 and the boundary of the projection of the second gate 222 on the substrate 10.

[0161] In some examples, the materials of the first gate 221 and the second gate 222 can be the same. In other examples, the materials of the first gate 221 and the second gate 222 can be different. In the embodiment of the present application, there is no limitation on the thickness of the first gate 221 and the second gate 222. The thickness can be designed according to actual needs.

[0162] 12 , the reading process and the writing process of the controllable thyristor T are described. In the following examples, the first doping region 21 a is a P-type doping region and the second doping region 21 b is an N-type doping region.

[0163] The writing process of the controlled thyristor T can be divided into a "1" writing phase and a "0" writing phase. During the "1" writing phase, a voltage is applied to the first gate 221 and the second gate 222, so that the voltage difference between the first gate 221 and the second gate 222 is 2V. When a negative voltage is applied to the first gate 221, a P-type channel is generated in the first region M1 of the active pattern 21 located on one side of the first gate 221, and an N-type channel is generated in the second region M2. When a negative voltage is also applied to the second electrode 24, a PNPN junction is formed between the first electrode 23 and the second electrode 24, generating a large current in the first electrode 23 and the second electrode 24.

[0164] During the "0" writing phase, voltages are applied to the first gate 221 and the second gate 222, so that the voltage difference between the first gate 221 and the second gate 222 is 2 V. When a negative voltage is applied to the first gate 221 and a 0 V voltage is applied to the second electrode 24, a PPNN junction is formed between the first electrode 23 and the second electrode 24, generating a small current or even no current at the first electrode 23 and the second electrode 24.

[0165] The reading process of the thyristor T can be divided into a "1" reading phase and a "0" reading phase. It is understood that during the "0" reading phase and the "1" reading phase, the electrical signals applied to the first gate 221, the second gate 222, and the second electrode 24 of the thyristor T are completely consistent, but the magnitude of the current signal flowing through the first electrode 23 is different.

[0166] For example, in the reading "1" stage, negative voltages are applied to both the first gate 221 and the second pole 24. At this time, the value of the current signal flowing through the first pole 23 is larger. In the reading "0" stage, negative voltages are applied to both the first gate 221 and the second pole 24, and the value of the current signal flowing through the first pole 23 is smaller and close to 0.

[0167] It can be understood that the above process is explained using the example of a voltage difference of 2V between the first gate 221 and the second gate 222. In different situations, the voltage difference between the first gate 221 and the second gate 222 can also be other values. In the embodiment of the present application, there is no restriction on the voltage value applied to the first gate 221 and the second gate 222, nor on the voltage difference between the two.

[0168] As shown in FIG11 , in the same storage layer 20, the first gate electrodes 221 of multiple memory cells 310 located in the same row are connected to form a first word line WL1. In the same storage layer 20, as shown in FIG5 , one first electrode 23 can correspond to one memory cell 310. Alternatively, in the same storage layer 20, as shown in FIG7 , one first electrode 23 can correspond to two memory cells 310.

[0169] Figures 13 and 14 show equivalent circuit diagrams of multiple memory cells 310 in the same memory layer 20. In the equivalent circuit diagram shown in Figure 13, one bit line BL connects one memory cell 310 in the same memory layer 20. In the equivalent circuit diagram shown in Figure 14, one bit line BL connects two memory cells 310 in the same memory layer 20. It should be understood that the number of memory cells 310 in Figures 13 and 14 does not limit the number of memory cells 310 in the memory layer 20. By selecting the bit line BL and the first word line WL1, read and write operations can be performed on any memory cell 310 in the memory array 300.

[0170] For example, when a "1" operation is performed on the memory cell 310, a first voltage signal may be applied to the first word line WL1 and the bit line BL connected to the memory cell 310. When a "0" operation is performed on the memory cell, a first voltage signal may be transmitted to the first word line WL1 connected to the memory cell, and a second voltage signal may be transmitted to the bit line BL connected to the memory cell 310. When a memory cell 310 is read, a third voltage signal may be transmitted to the first word line WL1 connected to the memory cell 310, and the first voltage signal may be transmitted to the bit line BL connected to the memory cell 310.

[0171] The voltage value of the second voltage signal is 0V, the voltage value of the third voltage signal is half of the voltage value of the first voltage signal, and both the first voltage signal and the second voltage signal are negative.

[0172] Some possible structures of the first gate 221 and the active pattern 21 are described below with reference to FIG. 9 , FIG. 11 and FIG. 15 .

[0173] In some examples, as shown in FIG9 , the projection of the active pattern 21 on the substrate 10 is in the shape of a semicircle, and the projection of the first gate 221 on the substrate 10 is in the shape of a semicircle. In other examples, as shown in FIG11 , the projection of the active pattern 21 on the substrate 10 is in the shape of a circular ring, and the projection of the first gate 221 on the substrate 10 is in the shape of a circular ring.

[0174] It is understandable that when the projection of the active pattern 21 on the substrate 10 is semicircular or annular, the first doped region 21a, the second doped region 21b and the intrinsic region 21c in the active pattern 21 are also semicircular or annular.

[0175] In this way, the shape of the projection of the first gate 221 on the substrate 10 is the same as the shape of the projection of the active pattern 21 on the substrate 10, so that the overlapping area between the projection of the first gate 221 on the substrate 10 and the projection of the active pattern 21 on the substrate 10 can be larger, and the first gate 221 has a stronger control ability over the controlled thyristor T, which is beneficial to improving the performance of the controlled thyristor T and improving the performance of the memory array 300.

[0176] At the same time, the shape of the first gate 221 on the substrate 10 is circular or semi-circular, and the shape of the active pattern 21 on the substrate 10 is circular or semi-circular, which can also make the preparation process of the first gate 221 and the active pattern 21 relatively simple, thereby helping to improve the preparation efficiency of the storage array 300.

[0177] In some other examples, as shown in FIG15 , the projection of the first gate 221 on the substrate 10 may be rectangular. In this case, the projection of the first gate 221 on the substrate 10 may be smaller, thereby reducing the area occupied by the first gate 221 and lowering the cost of the memory array 300.

[0178] In the same storage layer 20, the first gates 221 of the memory cells 310 in the same row are connected to form a first word line WL1. In some embodiments, the first gates 221 of the memory cells 310 in the same row may be indirectly connected.

[0179] 9, 11, and 15, the memory array 300 further includes a first connection structure 30. The first connection structure 30 is disposed in the same layer as the first gate 221 and connects two adjacent first gates 221 in the plurality of memory cells 310 located in the same row. The first word line WL1 includes the first gate 221 and the first connection structure 30.

[0180] For example, the material of the first connection structure 30 can be the same as that of the first gate 221. In this case, the first connection structure 30 and the first gate 221 can be manufactured simultaneously, thereby simplifying the manufacturing process of the memory array 300 and reducing the cost of the memory array 300.

[0181] Exemplarily, the shape of the projection of the first connection structure 30 on the substrate 10 is the same as the shape of the projection of the first gate 221 on the substrate 10 .

[0182] For example, as shown in FIG9 , the projection of the first gate 221 on the substrate 10 is semicircular, and the projection of the first connection structure 30 on the substrate 10 is also semicircular. As shown in FIG11 , the projection of the first gate 221 on the substrate 10 is circular, and the projection of the first connection structure 30 on the substrate 10 is also circular. As shown in FIG15 , the projection of the first gate 221 on the substrate 10 is rectangular, and the projection of the first connection structure 30 on the substrate 10 is also rectangular.

[0183] It can be understood that when the shape of the projection of the first connection structure 30 on the substrate 10 is the same as the shape of the projection of the first gate 221 on the substrate 10, the size of the projection of the first connection structure 30 on the substrate 10 can be the same as or different from the size of the projection of the first gate 221 on the substrate 10.

[0184] In the embodiment of the present application, the shape of the projection of the first connection structure 30 on the substrate 10 is the same as the shape of the projection of the first gate 221 on the substrate 10, so that the shape of the first word line WL1 formed by the first connection structure 30 and the first gate 221 is regular, which is beneficial to improving the regularity of the structure of the memory array 300 and improving the structural stability of the memory array 300.

[0185] In some other embodiments, as shown in FIG. 16 , the first gates 221 of the memory cells 310 in the same row are directly connected, and two adjacent active patterns 21 of the memory cells 310 in the same row are directly connected.

[0186] 16 , when two adjacent active patterns 21 in a plurality of memory cells 310 located in the same row are directly connected, the second doped regions 21 b of the active patterns 21 may be directly connected.

[0187] Thus, there is no gap between two adjacent memory cells 310 in the second direction X. In the second direction X, a greater number of memory cells 310 can be arranged per unit length, thereby increasing the number of memory cells 310 in a single memory layer 20, thereby facilitating an increase in the number of memory cells in the memory array 300.

[0188] In some embodiments, as shown in FIG17 , the projection of the active pattern 21 on the substrate 10 is in the shape of a ring, and the projection of the second gate 222 on the substrate 10 is in the shape of a ring. In other examples, the projection of the active pattern 21 on the substrate 10 is in the shape of a semicircle, and the projection of the second gate 222 on the substrate 10 is in the shape of a semicircle.

[0189] In this way, the shape of the projection of the second gate 222 on the substrate 10 is the same as the shape of the projection of the active pattern 21 on the substrate 10, so that the overlapping area between the projection of the second gate 222 on the substrate 10 and the projection of the active pattern 21 on the substrate 10 can be larger, and the gate 22 has a stronger control ability over the controlled thyristor T, which is beneficial to improving the storage performance of the controlled thyristor T and improving the yield of the storage array 300.

[0190] At the same time, the shape of the second gate 222 on the substrate 10 is annular or semi-annular, which can also simplify the preparation process of the second gate 222 , thereby improving the preparation efficiency of the memory array 300 .

[0191] In some embodiments, as shown in FIG. 17 , the second gates 222 of a plurality of memory cells 310 in the same row are connected to form a second word line WL2 .

[0192] In some examples, the second gates 222 of a plurality of memory cells 310 in the same row may be indirectly connected.

[0193] 17 , the memory array 300 further includes a second connection structure 40. The second connection structure 40 is disposed in the same layer as the second gate 222 and connects two adjacent second gates 222 in the plurality of memory cells 310 located in the same row. The second word line WL2 includes the second gate 222 and the second connection structure 40.

[0194] For example, the material of the second connection structure 40 can be the same as that of the second gate 222. In this case, the second connection structure 40 and the second gate 222 can be manufactured simultaneously, which is beneficial to simplify the manufacturing process and reduce costs.

[0195] Exemplarily, the shape of the projection of the second connection structure 40 on the substrate 10 is the same as the shape of the projection of the second gate 222 on the substrate 10 .

[0196] For example, the projection of the second gate 222 on the substrate 10 is semicircular, and the projection of the second connection structure 40 on the substrate 10 is also semicircular. The projection of the second gate 222 on the substrate 10 is circular, and the projection of the second connection structure 40 on the substrate 10 is also circular.

[0197] It can be understood that when the shape of the projection of the second connection structure 40 on the substrate 10 is the same as the shape of the projection of the second gate 222 on the substrate 10, the size of the projection of the second connection structure 40 on the substrate 10 can be the same as or different from the size of the projection of the second gate 222 on the substrate 10.

[0198] The shape of the projection of the second connection structure 40 on the substrate 10 is the same as the shape of the projection of the second gate 222 on the substrate 10, so that the shape of the second word line WL2 formed by the second connection structure 40 and the second gate 222 is regular, which is beneficial to improving the regularity of the structure of the memory array 300 and improving the structural stability of the memory array 300.

[0199] In some other examples, the second gates 222 of the memory cells 310 in the same row may be directly connected, and two adjacent active patterns 21 of the memory cells 310 in the same row may be directly connected.

[0200] Thus, there is no gap between two adjacent memory cells 310 in the second direction X. In the second direction X, a greater number of memory cells 310 can be arranged per unit length, thereby increasing the number of memory cells 310 in a single memory layer 20, thereby facilitating an increase in the number of memory cells in the memory array 300.

[0201] In some embodiments, referring to FIG. 16 , in the same memory layer 20 , the second gates 222 of a plurality of memory cells 310 are connected to form a common gate layer 27 .

[0202] In this way, the second gate 222 in the same storage layer 20 can share the same lead terminal, so that the number of lead terminals provided in the storage array 300 can be fewer, which is conducive to simplifying the structure of the storage array 300, further reducing the size of the storage array 300, and reducing the size of the memory 200 using the storage array 300.

[0203] In some embodiments, as shown in FIG18 , at least two adjacent memory cells 310 share the same second gate 222 in the first direction Z. This can reduce the number of second gates 222 in the memory array 300, lower the cost of the memory array 300, and simplify the structure of the memory array 300.

[0204] Figures 19 and 20 respectively illustrate the structures of two memory arrays 300 provided in embodiments of the present application. Compared to the memory array 300 shown in Figure 19 , the memory array 300 shown in Figure 20 has two adjacent memory cells 310 in a first direction Z that are symmetrical about a first reference plane Q1. The first reference plane Q1 is parallel to the substrate 10.

[0205] As shown in Figures 19 and 20, in some embodiments, the active pattern 21 includes a first doping region 21a, a second doping region 21b, a third doping region 21d, and an intrinsic region 21c. The intrinsic region 21c is located between the first doping region 21a and the second doping region 21b, and the third doping region 21d is located between the first doping region 21a and the intrinsic region 21c. The doping element type of the third doping region 21d is the same as the doping element type of the second doping region 21b, and the doping element type of the third doping region 21d is different from the doping element type of the first doping region 21a. The gate 22 includes a first gate 221, the projection of the first gate 221 on the substrate 10 at least partially overlapping with the projection of the intrinsic region 21c on the substrate 10.

[0206] Here, “the projection of the first gate 221 on the substrate 10 at least partially overlaps with the projection of the intrinsic region 21c on the substrate 10” includes both the situation where the projection of the first gate 221 on the substrate 10 partially overlaps with the projection of the intrinsic region 21c on the substrate 10 and the situation where the projection of the first gate 221 on the substrate 10 completely overlaps with the projection of the intrinsic region 21c on the substrate 10.

[0207] In some examples, the first doping region 21a may be doped with a pentavalent element to serve as an N-type doping region, and the second doping region 21b and the third doping region 21d may be doped with a trivalent element to serve as a P-type doping region. Of course, in other examples, the first doping region 21a may be doped with a trivalent element to serve as a P-type doping region, and the second doping region 21b and the third doping region 21d may be doped with a pentavalent element to serve as an N-type doping region.

[0208] The structure of the active pattern 21 and the structure of the first gate 221 may refer to the description in the above embodiment, and will not be repeated here.

[0209] In the controlled thyristor T provided in the embodiment of the present application, a NINP junction or a PIPN junction exists in the active pattern 21, and thus a first gate 221 is formed on one side of the active pattern 21, so that an NPNP junction or a PNPN junction can be formed between the first electrode 23 and the second electrode 24 of the controlled thyristor T, without providing a second gate.

[0210] The working process of the controlled thyristor T provided in the embodiment of the present application is similar to the working process of the controlled thyristor T with the first gate 221 and the second gate 222 provided in the above embodiment, and will not be repeated here.

[0211] As shown in FIG. 21 , an embodiment of the present application provides a method for preparing a memory array 300 , which includes step S1000 .

[0212] S1000: Form a plurality of memory layers 20 on a substrate 10. The plurality of memory layers 20 are stacked along a first direction Z perpendicular to the substrate 10. The memory layers 20 include a plurality of memory cells 310. The memory cells 310 include a controlled thyristor T. The controlled thyristor T includes an active pattern 21, a gate 22, a first electrode 23, and a second electrode 24.

[0213] The gate 22 is located on at least one side of the active pattern 21 along the first direction Z and is insulated from the active pattern 21. The first electrode 23 extends along the first direction Z. The active pattern 21 is disposed around the first electrode 23 and is electrically connected to the first electrode 23. The second electrode 24 is disposed in the same layer as the active pattern 21 and is connected to the active pattern 21. The active pattern 21 is located between the first electrode 23 and the second electrode 24. In the plurality of storage layers 20, the first electrodes 23 of the plurality of memory cells 310 arranged along the first direction Z are connected to form a bit line BL. In the storage layer 20, the second electrodes 24 of the plurality of memory cells 310 are connected to form a common electrode layer 25.

[0214] The beneficial effects that can be achieved by the method for preparing the memory array 300 provided in the embodiment of the present application are the same as the beneficial effects that can be achieved by the memory array 300 provided in the above embodiment, and will not be repeated here.

[0215] As shown in FIG. 21 , in some embodiments, the above-mentioned step S1000 may include steps S100 to S900 .

[0216] S100, as shown in FIG22, a plurality of stacked film layers 301 are sequentially formed on a substrate 10, wherein the stacked film layers 301 include a first dielectric layer 11, a semiconductor layer 13, and a second dielectric layer 12, which are sequentially away from the substrate 10. The first dielectric layer 11 and the second dielectric layer 12 are made of different materials.

[0217] Exemplarily, the materials of the first dielectric layer 11 and the second dielectric layer 12 may include silicon, germanium, silicon germanium, silicon oxide, silicon nitride, aluminum oxide, hafnium dioxide, etc.

[0218] For example, multiple stacked film layers 301 can be sequentially formed on the substrate 10 using an epitaxial growth process or a deposition process. In the present embodiment, there is no limit on the number of stacked film layers 301 on the substrate 10 and the number can be designed based on storage requirements. FIG. 22 illustrates an example of forming three stacked film layers 301 on the substrate.

[0219] In the embodiment of the present application, there is no restriction on the thickness of the first dielectric layer 11 , the second dielectric layer 12 and the semiconductor layer 13 , and they can be designed according to actual needs.

[0220] In the case where the gate 22 includes a first gate 221 and a second gate 22, the first dielectric layer 11 can serve as a sacrificial layer for the first gate 221, and the second dielectric layer 12 can serve as a sacrificial layer for the second gate 222. The semiconductor layer 13 is used to form the active pattern 21. Based on this, by adjusting the arrangement order and number of the first dielectric layer 11, the second dielectric layer 12, and the semiconductor layer 13 in the stacked film layer 301, the structure of the memory cell 310 in the memory layer 20 can be adjusted, thereby realizing a memory array 300 with different structures.

[0221] For example, when the stacked film layer 301 includes a first dielectric layer 11, a semiconductor layer 13, and a second dielectric layer 12 sequentially away from the substrate 10, the structure of the memory array 300 obtained by the preparation method provided in the embodiment of the application may be as shown in FIG. 6 .

[0222] For another example, as shown in FIG23 , the stacked film layer 301 further includes another semiconductor layer 13 located on the side of the second dielectric layer 12 away from the substrate 10. In this case, the stacked film layer 301 may include, in order, a first dielectric layer 11, a semiconductor layer 13, a second dielectric layer 12, and a semiconductor layer 13 away from the substrate 10. The structure of the memory array 300 obtained using the fabrication method provided in the embodiment of the present application may be as shown in FIG18 .

[0223] Of course, the structure of the stacked film layer 301 provided in the embodiment of the present application is not limited to the above example.

[0224] S200 , as shown in FIG. 24 , the semiconductor layer 13 is etched to form a semiconductor pattern 131 .

[0225] For example, a dry etching process or a wet etching process may be used to etch the semiconductor layer 13 to form the semiconductor pattern 131 .

[0226] In some examples, as shown in FIG24 , during the etching of the semiconductor layer 13, the first dielectric layer 11 and the second dielectric layer 12 may also be etched. Of course, in other examples, during the etching of the semiconductor layer 13, the first dielectric layer 11 and the second dielectric layer 12 may be retained, thereby forming a cavity that can be used to accommodate the second electrode of the controllable thyristor T.

[0227] In some embodiments, the projection of the semiconductor pattern 131 on the substrate 10 may be circular. In this case, the semiconductor pattern 131 may be obtained by directly etching the semiconductor layer 13 .

[0228] In some other embodiments, the projection of the semiconductor pattern 131 on the substrate 10 may be semicircular. Referring to Figures 25, 26, and 27, step S200 may include step S210 and step S220.

[0229] S210 , as shown in FIG. 25 , the semiconductor layer 13 is etched to form an initial semiconductor pattern 132 . The projection of the initial semiconductor pattern 132 on the substrate 10 is circular.

[0230] For example, the semiconductor layer 13 may be etched using a dry etching process or a wet etching process.

[0231] Here, “the projection of the initial semiconductor pattern 132 on the substrate 10 is circular” means that the projection of the initial semiconductor pattern 132 on the substrate 10 is circular as a whole, but is not limited to a standard circle. For example, the boundary of the projection of the initial semiconductor pattern 132 on the substrate 10 is allowed to be non-smooth (for example, it may have jagged edges, etc.).

[0232] In the embodiment of the present application, there is no restriction on the size of the projection of the initial semiconductor pattern 132 on the substrate 10, and it can be designed according to actual needs. Similarly, in the embodiment of the present application, there is no restriction on the spacing between the projections of two adjacent initial semiconductor patterns 132 on the substrate 10, and it can be designed according to actual needs.

[0233] S220 , as shown in FIG. 26 and FIG. 27 , the initial semiconductor pattern 132 is etched to form a trench W and two semiconductor patterns 131 located on both sides of the trench W. The projections of the two semiconductor patterns 131 on the substrate 10 are both semicircular.

[0234] 26 , the trench W may extend along the second direction X. In other examples, the trench W may further extend along the third direction Y.

[0235] In the embodiment of the present application, there is no restriction on the length, width and depth of the groove W, and it can be designed according to the number of stacked film layers 301 on the substrate 10, the thickness of the stacked film layers 301, and the size of the projection of the stacked film layers 301 on the substrate 10.

[0236] The projection of the semiconductor pattern 131 on the substrate 10 is semicircular, so that the size of the semiconductor pattern 131 on the substrate 10 can be smaller, and the size of the active pattern 21 formed using the semiconductor pattern 131 can also be smaller, which is beneficial to reducing the size of the projection of the controlled thyristor T on the substrate 10, reducing the area of ​​the projection of the memory cell 310 on the substrate 10, increasing the number of memory cells 310 per unit area of ​​the memory array 300, and improving the storage density of the memory array 300.

[0237] Based on this, in some examples, before step S300, as shown in FIG28, the preparation method may further include step S230.

[0238] S230 , forming a filling layer 14 in the trench W. The filling layer 14 is used to insulate the semiconductor patterns 131 on both sides of the trench W.

[0239] For example, the material of the filling layer 14 can be different from the material of the first dielectric layer 11 and the material of the second dielectric layer 12, thereby avoiding the situation where the filling layer 14 is also removed during the subsequent removal of the first dielectric layer 11 and the second dielectric layer 12, resulting in a short circuit between multiple semiconductor patterns 131 on both sides of the same trench.

[0240] S300 , as shown in FIG. 29A and FIG. 29B , doping is performed on the semiconductor pattern 131 to form a second doping region 21 b .

[0241] For example, the semiconductor pattern 131 can be doped using an ion implantation process to form the second doped region 21 b. The present embodiment does not limit the type of doping element in the second doped region 21 b; it can be a trivalent element or a pentavalent element. That is, the second doped region 21 b can be a P-type doped region or an N-type doped region.

[0242] S400: As shown in FIG30A and FIG30B , a second electrode 24 is formed. The second electrode 24 is provided in the same layer as the semiconductor pattern 131 and is connected to the second doped region 21b. FIG30A and FIG30B illustrate an example in which the common electrode layer 25 formed by the second electrode 24 is connected to form an integral structure.

[0243] In some examples, the second electrode 24 may be formed by a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, or a sputtering process.

[0244] The material of the second electrode 24 may include at least one of TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, and Ag.

[0245] S500 , as shown in FIG31 , forming a through hole 101 penetrating the plurality of stacked film layers 301 .

[0246] In some examples, the trench W and the filling layer 14 may not be formed. In this case, the stacked film layers 301 may be etched using a dry etching process or a wet etching process to form a through hole 101 penetrating the plurality of stacked film layers 301 .

[0247] In other examples, a trench W and a filling layer 14 may be formed. In this case, step S500 may include: etching the filling layer 14 to form a through hole 101 penetrating the plurality of stacked film layers 301 .

[0248] The embodiment of the present application does not limit the opening shape of the through hole 101. For example, the opening shape of the through hole 101 can be circular or rectangular. It is understood that the number of the through holes 101 is the same as the number of the storage units 310 in the storage layer 20.

[0249] S600 , removing the first dielectric layer 11 through the through hole 101 to form a first gate 221 , wherein the first gate 221 is insulated from the semiconductor pattern 131 .

[0250] Exemplarily, the material of the first gate 221 may include at least one of TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, and Ag.

[0251] In some examples, as shown in Figures 32 to 35, the above step S600 may include steps S610 to S640.

[0252] S610 , as shown in FIG32 , based on the through hole 101 , the first dielectric layer 11 is removed to form a first accommodation cavity L1 .

[0253] Illustratively, a wet etching process may be used to remove the first dielectric layer 11 .

[0254] S620 , as shown in FIG33 , a first insulating layer 15 and a first gate 221 are formed in the first receiving cavity L1 .

[0255] For example, an atomic layer deposition process may be used to sequentially form the first insulating layer 15 and the first gate 221 in the first receiving cavity L1 .

[0256] 33 , the first insulating layer 15 is further located between the first gate 221 and the second electrode 24 to insulate the first gate 221 from the second electrode 24 .

[0257] The first insulating layer 15 may be made of a high dielectric constant material, such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, etc. In the embodiment of the present application, there is no limitation on the thickness of the first insulating layer 15 as long as it can insulate the first gate 221 from the semiconductor pattern 131.

[0258] S630 , as shown in FIG34 , the first gate 221 is etched back using an etch-back process to remove a portion of the first gate 221 close to the through hole 101 , thereby forming a second accommodation cavity L2 .

[0259] S640 , as shown in FIG. 35 , forming a second insulating layer 16 in the second receiving cavity L2 .

[0260] Exemplarily, the material of the second insulating layer 16 is the same as that of the first insulating layer 15. The first insulating layer 15 and the second insulating layer 16 form a gate dielectric layer 26. For simplicity, only the gate dielectric layer 26 is shown in the subsequent figures.

[0261] S700 , as shown in FIG36 to FIG39 , the second dielectric layer 12 is removed through the through hole 101 to form a second gate 222 . The second gate 222 is insulated from the semiconductor pattern 131 .

[0262] The material of the second gate 222 may be the same as or different from that of the first gate 221. For example, the gate dielectric layer 26 may be located between the second gate 222 and the semiconductor pattern 131 to insulate the second gate 222 from the semiconductor pattern 131.

[0263] In some examples, as shown in FIG. 36 to FIG. 39 , step S700 includes steps S710 to S740 .

[0264] S710 , as shown in FIG36 , based on the through hole 101 , the second dielectric layer 12 is removed to form a third accommodation cavity L3 .

[0265] For example, a wet etching process may be used to remove the second dielectric layer 12 .

[0266] S720 , as shown in FIG37 , in the third receiving cavity L3 , a third insulating layer 17 and a second gate 222 are formed.

[0267] For example, an atomic layer deposition process may be used to sequentially form the third insulating layer 17 and the second gate 222 in the third receiving cavity L3 .

[0268] 37 , the third insulating layer 17 is further located between the second gate 222 and the second electrode 24 to insulate the second gate 222 from the second electrode 24 .

[0269] The third insulating layer 17 may be made of a high dielectric constant material, such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, etc. In the embodiment of the present application, there is no limitation on the thickness of the third insulating layer 17 as long as it can insulate the second gate 222 from the semiconductor pattern 131.

[0270] S730 , as shown in FIG38 , the second gate 222 is etched back using an etch-back process to remove a portion of the second gate 222 close to the through hole 101 , thereby forming a fourth accommodation cavity L4 .

[0271] S740 , as shown in FIG. 39 , forming a fourth insulating layer 18 in the fourth receiving cavity L4 .

[0272] Exemplarily, the material of the fourth insulating layer 18 is the same as that of the third insulating layer 17 . The third insulating layer 17 and the fourth insulating layer 18 form a gate dielectric layer 26 .

[0273] It is understandable that, in the embodiment of the present application, as shown in FIG. 36 to FIG. 39 , the first gate 221 may be formed first and then the second gate 222 may be formed, or the second gate 222 may be formed first and then the first gate 221 may be formed.

[0274] S800. As shown in FIG40 , the semiconductor pattern 131 is doped through the through hole 101 to form a first doped region 21a. A gap exists between the first doped region 21a and the second doped region 21b. The undoped portion of the semiconductor pattern 131 serves as the intrinsic region 21c. The intrinsic region 21c, the first doped region 21a, and the second doped region 21b form the active pattern 21. The intrinsic region 21c includes a first region M1 and a second region M2, with the first region M1 being closer to the second doped region 21b than the second region M2. The projection of the first gate 221 on the substrate 10 at least partially overlaps with the projection of the first region M1 on the substrate 10. The projection of the intrinsic region 21c on the substrate 10 is located within the projection of the second gate 222 on the substrate 10.

[0275] For example, the semiconductor pattern 131 can be doped using an ion implantation process to form the first doping region 21a. It is understood that the doping element type of the first doping region 21a is different from the doping element type of the second doping region 21b. That is, when a trivalent element is doped into the first doping region 21a, a pentavalent element is doped into the second doping region 21b. Similarly, when a pentavalent element is doped into the first doping region 21a, a trivalent element is doped into the second doping region 21b.

[0276] S900: As shown in FIG41 , a first electrode 23 is formed in the through hole 101. The first electrode 23 is connected to the first doping region 21a.

[0277] For example, a deposition process and an etching process may be used to form the first electrode 23 in the through hole 101 .

[0278] When the projection of the active pattern 21 on the substrate 10 is in the shape of a semicircle, step S900 may include step S910 and step S920.

[0279] S910 , referring to FIG. 41 , a conductive material is deposited in the through hole 101 to form an initial electrode 231 .

[0280] S920 , as shown in FIG42 , etching the initial electrode 231 to form two first electrodes 23 , the two first electrodes 23 being respectively connected to the two first doping regions 21 a .

[0281] For example, the initial electrode 231 may be etched using a dry etching process or a wet etching process.

[0282] In other embodiments, as shown in FIG. 43 , step S1000 may include steps S100 ′ to S800 ′.

[0283] Among them, step S100 ′ to step S600 ′ are the same as step S100 to step S600 in the preparation method provided in the above embodiment, and reference may be made to the above content, which will not be repeated here.

[0284] S700'. As shown in FIG44 , the semiconductor pattern 131 is doped through the through hole 101 to form a third doped region 21d and a first doped region 21a. The undoped portion of the semiconductor pattern 131 serves as the intrinsic region 21c. The first doped region 21a, the second doped region 21b, the third doped region 21d, and the intrinsic region 21c form the active pattern 21. The third doped region 21d is located between the first doped region 21a and the intrinsic region 21c. The doping element type of the third doped region 21d is the same as the doping element type of the second doped region 21b, and the doping element type of the third doped region 21d is different from the doping element type of the first doped region 21a. The projection of the first gate 221 on the substrate 10 at least partially overlaps with the projection of the intrinsic region 21c on the substrate 10.

[0285] In some examples, the first doping region 21a is doped with a trivalent element to serve as a P-type doping region, and the second doping region 21b and the third doping region 21d are doped with a pentavalent element to serve as an N-type doping region. In other examples, the first doping region 21a is doped with a pentavalent element to serve as an N-type doping region, and the second doping region 21b and the third doping region 21d are doped with a trivalent element to serve as a P-type doping region.

[0286] Taking the first doping region 21a as an N-type doping region and the third doping region 21d as a P-type doping region as an example, the above step S700' can be: first, the semiconductor pattern 131 is doped through the through hole 101 to form an N-type doping region, and then the portion of the N-type doping region near the through hole 101 is doped by utilizing the charge compensation effect to form a P-type doping region.

[0287] Alternatively, when the first doping region 21a is an N-type doping region and the third doping region 21d is a P-type doping region, the above step S700' can also be: first, the semiconductor pattern 131 is doped through the through hole 101 to form an N-type doping region, and then the semiconductor pattern 131 is etched to remove the portion of the N-type doping region near the through hole 101, and then an epitaxial growth process is used to form a P-type doping region.

[0288] S800', as shown in FIG45, a first electrode 23 is formed in the through hole 101. The first electrode 23 is connected to the first doping region 21a.

[0289] Illustratively, a dry etching process may be used to etch the initial electrode 231 to form the two first electrodes 23 .

[0290] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0291] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: substrate; A plurality of storage layers are stacked along a first direction perpendicular to the substrate; the storage layers include a plurality of storage units, the storage units include controllable thyristors, and the controllable thyristors include an active pattern, a gate, a first pole, and a second pole; Among them, along the first direction, the gate is located on at least one side of the active pattern and is insulated from the active pattern; the first pole extends along the first direction; the active pattern is arranged around the first pole and is electrically connected to the first pole; the second pole is arranged in the same layer as the active pattern and is connected to the active pattern; the active pattern is located between the first pole and the second pole; in the multiple storage layers, the first poles of the multiple storage cells arranged along the first direction are connected to form a bit line; in the storage layer, the second poles of the multiple storage cells are connected to form a common electrode layer.

2. The storage array according to claim 1, characterized in that: The active pattern includes a first doping region, a second doping region and an intrinsic region, wherein the intrinsic region is located between the first doping region and the second doping region; the intrinsic region includes a first region and a second region, wherein the first region is closer to the second doping region than the second region; The gate includes a first gate and a second gate; along the first direction, the active pattern is located between the first gate and the second gate; the projection of the first gate on the substrate at least partially overlaps with the projection of the first region on the substrate; the projection of the intrinsic region on the substrate is located inside the projection of the second gate on the substrate.

3. The storage array according to claim 2, characterized in that: The projection of the active pattern on the substrate is in a circular ring shape, and the projection of the second gate on the substrate is in a circular ring shape; or, the projection of the active pattern on the substrate is in a semicircular ring shape, and the projection of the second gate on the substrate is in a semicircular ring shape.

4. The storage array according to claim 2 or 3, characterized in that: In the same storage layer, the second gates of a plurality of storage cells are connected to form a common gate layer.

5. The storage array according to any one of claims 2 to 4, characterized in that: In the first direction, there are at least two adjacent memory cells sharing the same second gate.

6. The storage array according to claim 1, characterized in that: The active pattern comprises a first doping region, a second doping region, a third doping region and an intrinsic region; the intrinsic region is located between the first doping region and the second doping region, and the third doping region is located between the first doping region and the intrinsic region; the doping element type of the third doping region is the same as the doping element type of the second doping region, and the doping element type of the third doping region is different from the doping element type of the first doping region; The gate includes a first gate, a projection of the first gate on the substrate at least partially overlapping with a projection of the intrinsic region on the substrate.

7. The storage array according to any one of claims 2 to 6, characterized in that: The projection of the active pattern on the substrate is in a circular ring shape, and the projection of the first gate on the substrate is in a circular ring shape; or, The projection of the active pattern on the substrate is in a semicircular shape, and the projection of the first gate on the substrate is in a semicircular shape; or, The projection of the first gate on the substrate is rectangular.

8. The storage array according to any one of claims 1 to 7, characterized in that: A plurality of storage cells in the same storage layer are arranged into a plurality of rows along a second direction and into a plurality of columns along a third direction; wherein the second direction and the third direction are both parallel to the substrate, and the second direction and the third direction are perpendicular to each other; Two adjacent storage units in the second direction are symmetrically arranged with respect to a second reference plane; the second reference plane is perpendicular to the substrate and parallel to the third direction; and / or, Two adjacent storage units in the third direction are symmetrically arranged with respect to a third reference plane; the third reference plane is perpendicular to the substrate and parallel to the second direction.

9. The storage array according to claim 8, characterized in that: The gate includes a first gate, and the storage array further includes: The first connection structure is arranged in the same layer as the first gate and connects two adjacent first gates of a plurality of storage cells in the same row.

10. The storage array according to claim 9, characterized in that: A shape of a projection of the first connection structure on the substrate is the same as a shape of a projection of the first gate on the substrate.

11. The storage array according to claim 8, characterized in that: The gate includes a first gate, the first gates in a plurality of memory cells in the same row are directly connected, and two adjacent active patterns in a plurality of memory cells in the same row are directly connected.

12. The storage array according to any one of claims 1 to 11, characterized in that: Two adjacent memory cells in the first direction are symmetrical with respect to a first reference plane; the first reference plane is parallel to the substrate.

13. The storage array according to any one of claims 1 to 12, characterized in that: The projection of the active pattern on the substrate is in the shape of a semicircle; the projection of the first pole on the substrate is in the shape of a circle; in the same storage layer, there are two adjacent storage units that share the same first pole.

14. The storage array according to any one of claims 1 to 12, characterized in that: The projection of the active pattern on the substrate is in a semicircular shape, and the projection of the first pole on the substrate is in a semicircular shape; or, the projection of the active pattern on the substrate is in a circular shape, and the projection of the first pole on the substrate is in a circular shape; In the same storage layer, one first electrode is connected to one active pattern.

15. The storage array according to any one of claims 1 to 14, characterized in that: The common electrode layers in the plurality of storage layers are connected.

16. A method for preparing a storage array, characterized in that: include: A plurality of storage layers are formed on a substrate, wherein the plurality of storage layers are stacked along a first direction perpendicular to the substrate; the storage layers include a plurality of storage cells, wherein the storage cells include a controllable thyristor, and the controllable thyristor includes an active pattern, a gate, a first electrode, and a second electrode; Among them, along the first direction, the gate is located on at least one side of the active pattern and is insulated from the active pattern; the first pole extends along the first direction; the active pattern is arranged around the first pole and is electrically connected to the first pole; the second pole is arranged in the same layer as the active pattern and is connected to the active pattern; the active pattern is located between the first pole and the second pole; in the multiple storage layers, the first poles of the multiple storage cells arranged along the first direction are connected to form a bit line; in the storage layer, the second poles of the multiple storage cells are connected to form a common electrode layer.

17. The preparation method according to claim 16, characterized in that: The forming of a plurality of storage layers on a substrate comprises: Forming a plurality of stacked film layers on a substrate in sequence, wherein the stacked film layers include a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially away from the substrate; Etching the semiconductor layer to form a semiconductor pattern; doping the semiconductor pattern to form a second doping region; forming a second electrode, wherein the second electrode is disposed in the same layer as the semiconductor pattern and connected to the second doped region; forming a through hole penetrating the plurality of stacked film layers; The first dielectric layer is removed through the through hole to form a first gate; the first gate is insulated from the semiconductor pattern; The second dielectric layer is removed through the through hole to form a second gate; the second gate is insulated from the semiconductor pattern; The semiconductor pattern is doped through the through hole to form a first doping region; there is a distance between the first doping region and the second doping region, and the undoped portion of the semiconductor pattern is used as an intrinsic region; the intrinsic region, the first doping region and the second doping region form the active pattern; the intrinsic region includes a first area and a second area, and the first area is closer to the second doping region than the second area; the projection of the first gate on the substrate at least partially overlaps with the projection of the first area on the substrate; the projection of the intrinsic region on the substrate is located inside the projection of the second gate on the substrate; A first electrode is formed in the through hole; the first electrode is connected to the first doping region.

18. The preparation method according to claim 16, characterized in that: The forming of a plurality of storage layers on a substrate comprises: Forming a plurality of stacked film layers on a substrate in sequence, wherein the stacked film layers include a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially away from the substrate; Etching the semiconductor layer to form a semiconductor pattern; doping the semiconductor pattern to form a second doping region; forming a second electrode, wherein the second electrode is disposed in the same layer as the semiconductor pattern and connected to the second doped region; forming a through hole penetrating the stacked film layers; The first dielectric layer is removed through the through hole to form a first gate; the first gate is insulated from the semiconductor pattern; The semiconductor pattern is doped through the through hole to form a third doping region and a first doping region; the undoped portion of the semiconductor pattern is used as an intrinsic region; the first doping region, the second doping region, the third doping region and the intrinsic region form the active pattern; wherein the third doping region is located between the first doping region and the intrinsic region; the doping element type of the third doping region is the same as the doping element type of the second doping region, and the doping element type of the third doping region is the same as the doping element type of the first doping region The element types are different; the projection of the first gate on the substrate at least partially overlaps with the projection of the intrinsic region on the substrate; A first electrode is formed in the through hole; the first electrode is connected to the first doping region.

19. The preparation method according to claim 17 or 18, characterized in that: The etching of the semiconductor layer to form a semiconductor pattern comprises: Etching the semiconductor layer to form an initial semiconductor pattern, wherein the projection of the initial semiconductor pattern on the substrate is circular; Etching the initial semiconductor pattern to form a groove and two semiconductor patterns respectively located on both sides of the groove, wherein the projections of the two semiconductor patterns on the substrate are both semicircular; Before doping the semiconductor pattern to form the second doping region, the preparation method further includes: forming a filling layer in the trench; The forming of through holes penetrating the plurality of stacked film layers comprises: etching the filling layer to form through holes penetrating the plurality of stacked film layers.

20. The preparation method according to claim 19, characterized in that: The forming of the first electrode in the through hole comprises: Depositing a conductive material in the through hole to form an initial electrode; The initial electrode is etched to form two first electrodes; in a direction parallel to the substrate, the two first electrodes are respectively connected to the two first doped regions.

21. The preparation method according to any one of claims 17 to 20, characterized in that: The stacked film layer further includes another semiconductor layer located on a side of the second dielectric layer away from the substrate.

22. A memory, characterized in that: include: The storage array according to any one of claims 1 to 15; A controller is electrically connected to the storage array, and is used to control the reading and writing of the storage array.

23. An electronic device, characterized in that: include: The memory as claimed in claim 22; A circuit board, wherein the memory is located on the circuit board and is electrically connected to the circuit board.

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