Driving substrate, display panel, and display device

Abstract

A driving substrate, a display panel, and a display device, relating to the technical field of display. A peripheral area of the driving substrate comprises a plurality of shift registers. Each shift register comprises a driving transistor and a first storage capacitor, a gate of the driving transistor is electrically connected to a first electrode of the first storage capacitor, and a drain of the driving transistor is electrically connected to a second electrode of the first storage capacitor. The driving substrate comprises: a substrate (1), a first conductive layer (2), a second conductive layer (4), and a third conductive layer (6). The first conductive layer (1) comprises gates of the driving transistors and first electrodes of the first storage capacitors; the second conductive layer (4) comprises sources of the driving transistors, drains of the driving transistors, and second electrodes of the first storage capacitors; and the third conductive layer (6) is located on the side of the second conductive layer (4) distant from the first conductive layer (2), and the orthographic projection of at least one of the first storage capacitors and the driving transistors on the substrate (1) overlaps the orthographic projection of the third conductive layer (6) on the substrate. The driving substrate is suitable for manufacturing of a narrow-bezel display device.

Description

Driving substrate, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 21, 2023, with application number 202311560749.7 and titled “A driving substrate, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a driving substrate, a display panel, and a display device. Background Art

[0004] As living standards gradually improve, people have higher and higher requirements for the appearance design of display products. Among the display products on the market now, especially wearable display and touch display products, most of them have special-shaped designs, that is, the four corners are rounded or purely round, and they pursue extremely narrow bezels.

[0005] However, current display products typically integrate gate drivers directly onto the driver substrate's bezel through circuit design, resulting in narrow-bezel products, known as GOA (Gate On Array) driver substrates. For these products, compressing the bezel size is extremely difficult.

[0006] Summary of the Invention

[0007] The embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a drive substrate, the drive substrate comprising a display area and a peripheral area located on one side of the display area, the peripheral area comprising a plurality of shift register units arranged in cascade; the shift register unit comprising a drive transistor and a first storage capacitor, the gate of the drive transistor being electrically connected to a first electrode of the first storage capacitor, and the drain of the drive transistor being electrically connected to a second electrode of the first storage capacitor; the drive substrate further comprising:

[0009] substrate;

[0010] a first conductive layer, located on the substrate, comprising a gate of the driving transistor and a first electrode of the first storage capacitor;

[0011] a second conductive layer, located on a side of the first conductive layer away from the substrate, comprising a source electrode of the driving transistor, a drain electrode of the driving transistor, and a second electrode of the first storage capacitor;

[0012] The third conductive layer is located on a side of the second conductive layer away from the first conductive layer, and the orthographic projection of at least one of the first storage capacitor and the driving transistor on the substrate overlaps with the orthographic projection of the third conductive layer on the substrate.

[0013] In the driving substrate provided in at least one embodiment of the present application, the third conductive layer includes the common electrode and the conductive structure; or the third conductive layer includes the pixel electrode and the conductive structure;

[0014] Wherein, the conductive structure is electrically connected to the gate of the driving transistor.

[0015] In the driving substrate provided in at least one embodiment of the present application, the shift register unit further includes a second storage capacitor, and the second storage capacitor is connected in parallel with the first storage capacitor;

[0016] The second electrode of the first storage capacitor and the first electrode of the second storage capacitor are shared, and the conductive structure serves as the second electrode of the second storage capacitor.

[0017] In the driving substrate provided in at least one embodiment of the present application, the conductive structure includes a first conductive pattern, and an orthographic projection of the first conductive pattern on the substrate overlaps with an orthographic projection of the first storage capacitor on the substrate.

[0018] In the driving substrate provided in at least one embodiment of the present application, the conductive structure further includes a second conductive pattern, and the first conductive pattern and the second conductive pattern are connected;

[0019] The second conductive pattern covers at least a portion of the surface of the drain of the driving transistor away from the side of the substrate, the orthographic projection of the second conductive pattern on the substrate overlaps with the orthographic projection of the drain of the driving transistor on the substrate, and there is a gap between the orthographic projection of the second conductive pattern on the substrate and the orthographic projection of the source of the driving transistor on the substrate.

[0020] In the driving substrate provided in at least one embodiment of the present application, the minimum distance between the orthographic projection of the second conductive pattern on the substrate and the orthographic projection of the source of the driving transistor on the substrate is approximately equal to the minimum distance between the orthographic projection of the drain of the driving transistor on the substrate and the orthographic projection of the source of the driving transistor on the substrate.

[0021] In the driving substrate provided in at least one embodiment of the present application, the second conductive pattern at least further covers a side surface of the drain electrode of the driving transistor that is close to the source electrode;

[0022] The minimum distance between the orthographic projection of the second conductive pattern on the substrate and the orthographic projection of the source of the driving transistor on the substrate is smaller than the minimum distance between the orthographic projection of the drain of the driving transistor on the substrate and the orthographic projection of the source of the driving transistor on the substrate.

[0023] In the driving substrate provided in at least one embodiment of the present application, the first conductive layer includes a gate layer, and the second conductive layer includes a source-drain conductive layer;

[0024] Wherein, the thickness of the source-drain conductive layer along the direction perpendicular to the substrate is 800-1200 nm.

[0025] In the driving substrate provided in at least one embodiment of the present application, a boundary line between the peripheral area and the display area comprises an arc line, and a resolution of the driving substrate is less than or equal to 200;

[0026] The orthographic projection shape of the shift register unit on the substrate includes a figure formed by splicing a first rectangle and a second rectangle, and the outer contour of the figure formed by splicing the first rectangle and the second rectangle close to the display area includes a stepped shape.

[0027] In the driving substrate provided in at least one embodiment of the present application, the absolute value of the difference between the minimum distance between the first rectangle and the boundary line and the minimum distance between the second rectangle and the boundary line in part of the shift register is approximately equal to the absolute value of the difference between the minimum distance between the first rectangle and the boundary line and the minimum distance between the second rectangle and the boundary line in another part of the shift register.

[0028] In the driving substrate provided by at least one embodiment of the present application, the first rectangle and the second rectangle are arranged sequentially along a direction in which the curvature of the arc increases;

[0029] In a direction along which the curvature of the arc increases, the absolute value of the difference between the minimum distance between the first rectangle of the shift register unit and the boundary line and the minimum distance between the second rectangle and the boundary line gradually increases.

[0030] In at least one embodiment of the present application, in the driving substrate provided, the peripheral area includes a first peripheral sub-area, a second peripheral sub-area, and a third peripheral sub-area, the curvatures of a boundary line between the first peripheral sub-area and the display area, the boundary line between the second peripheral sub-area and the display area, and the boundary line between the third peripheral sub-area and the display area increase in sequence, and the resolution of the driving substrate is greater than or equal to 200;

[0031] The positive projection shape of the shift register unit on the substrate includes a third rectangle; the outer contour of multiple third rectangles connected together close to the display area is in a stepped shape, and the sizes of the third rectangles in the first peripheral sub-area, the second peripheral sub-area and the third peripheral sub-area are different.

[0032] In the driving substrate provided in at least one embodiment of the present application, the size of the third rectangle in the first peripheral sub-area along the first direction is greater than the size of the third rectangle in the second peripheral sub-area along the first direction, and the size of the third rectangle in the second peripheral sub-area along the first direction is greater than the size of the third rectangle in the third peripheral sub-area along the first direction; wherein, the first direction is perpendicular to the extension direction of the gate line in the driving substrate.

[0033] In the driving substrate provided in at least one embodiment of the present application, the sum of the size of the third rectangle in the first peripheral sub-area along the first direction and the size of the third rectangle in the third peripheral sub-area along the first direction is approximately equal to twice the size of the third rectangle in the second peripheral sub-area along the first direction.

[0034] In the driving substrate provided by at least one embodiment of the present application, the number of the shift register units in the first peripheral sub-area is equal to the number of the shift register units in the third peripheral sub-area.

[0035] In the driving substrate provided in at least one embodiment of the present application, the size of the third rectangle in the first peripheral sub-area along the second direction is smaller than the size of the third rectangle in the second peripheral sub-area along the second direction, and the size of the third rectangle in the second peripheral sub-area along the second direction is smaller than the size of the third rectangle in the third peripheral sub-area along the second direction; wherein the second direction is consistent with the extension direction of the gate line in the driving substrate.

[0036] In the driving substrate provided in at least one embodiment of the present application, the driving substrate includes an adhesive layer located on the substrate, and a partial area of ​​the adhesive layer is located on a side of the shift register unit away from the display area;

[0037] Wherein, the minimum distance between the side of the adhesive layer away from the display area and the shift register unit is greater than or equal to 200 μm.

[0038] In a second aspect, an embodiment of the present application provides a display panel comprising a driving substrate as described in any one of the first aspects.

[0039] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel as described in the second aspect, wherein the display panel is a special-shaped display panel.

[0040] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] FIG1 is a schematic top view of a display panel in the related art provided by an embodiment of the present application;

[0043] FIG2 is a partial enlarged view of the dotted box area in FIG1 ;

[0044] FIG3 is a simplified circuit diagram of a shift register provided in an embodiment of the present application;

[0045] FIG4 is a schematic top view of a partial region of a shift register in the related art provided by an embodiment of the present application;

[0046] FIG5 is a schematic diagram of the cross-sectional structure along the A1A2 direction of FIG4;

[0047] FIG6 is a simplified circuit diagram of a storage capacitor provided in an embodiment of the present application;

[0048] 7A is a schematic top view of a partial region of a first shift register provided in an embodiment of the present application;

[0049] FIG7B is a schematic top view of the conductive structure included in the third conductive layer in FIG7A ;

[0050] FIG8 is a schematic diagram of the cross-sectional structure of FIG7A along the direction A3A4;

[0051] FIG9 is a schematic top view of a partial region of a second shift register provided in an embodiment of the present application;

[0052] FIG10 is a schematic top view of the conductive structure included in the third conductive layer in FIG9 ;

[0053] FIG11 is a schematic diagram of the cross-sectional structure along the A5A6 direction of FIG9;

[0054] FIG12 is a schematic top view of a partial region of a third shift register provided in an embodiment of the present application;

[0055] FIG13 is a schematic diagram of the cross-sectional structure of FIG12 along the direction A7A8;

[0056] FIG14 is a schematic top view of the structure of the overlap between the conductive structure included in the third conductive layer and the second conductive layer in FIG12;

[0057] FIG15 is a schematic diagram illustrating an arrangement of shift register units in a peripheral area of ​​a driving substrate according to an embodiment of the present application;

[0058] FIG16 is a schematic diagram showing an arrangement of shift register units in a peripheral area of ​​a driving substrate in a related art according to an embodiment of the present application;

[0059] FIG17 is a schematic diagram illustrating an arrangement of shift register units in a peripheral area of ​​another driving substrate provided by an embodiment of the present application;

[0060] FIG18 is a schematic diagram showing the positional relationship between a shift register unit and an adhesive layer in a peripheral region of a driving substrate provided by an embodiment of the present application. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0062] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0063] In the embodiments of the present application, words such as "first" and "second" are used to indicate parts of identical or similar items with substantially the same functions and effects only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0064] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0065] In this specification, the terms "electrically connected" and "coupled" include components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0066] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0067] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0068] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0069] In the embodiments of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. In the embodiments of the present application, one of the source and drain of the transistor can also be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0070] As living standards gradually improve, people have higher and higher requirements for the appearance design of display products. Display products on the market now, especially smart wearable and touch products, are mostly of special-shaped design, that is, the four corners are rounded or purely round, and they pursue extremely narrow bezels.

[0071] The driver substrate of an LCD is typically formed by an array of transistors (e.g., thin-film transistors (TFTs)). Scan signals are input horizontally (e.g., in the direction of the gate lines), turning on the TFT gates row by row. Data signals are input vertically (e.g., in the direction of the data lines), charging the pixel electrodes through the TFT sources. The gate and source electrodes of the transistors are typically driven by a Gate & Data integrated driver chip (IC), which is bonded to the driver substrate's frame using a bonding technique, resulting in a larger frame.

[0072] With the development of technology, the gate drive is directly integrated into the border of the driver substrate through circuit design, forming a narrow-border product, namely the GOA (Gate On Array) driver substrate. GOA, also known as a shift register circuit, is composed of multiple GOA unit circuits in cascade. When the GOA unit in this row outputs, the gate of the previous row will be closed and the gate of the next row will be opened, achieving the effect of opening the gate row by row. Although the GOA design can achieve a narrow border to a certain extent, there is still a great demand to increase the screen-to-body ratio and further reduce the border. Therefore, it is also necessary to optimize the GOA design and further compress the space of the GOA unit.

[0073] Figure 1 shows a schematic diagram of the top structure of a display panel in the related art; Figure 2 shows a partial enlarged view of the dotted box area in Figure 1. For GOA-type display products, in order to reduce the frame size of the display panel, the space occupied by the GOA unit must be reduced. Figure 3 illustrates a partial structure of the circuit diagram of the GOA unit (shift register). For different types of GOA circuits, they all include a driving transistor DTFT and a storage capacitor Cst; wherein, in most GOA circuits, one end of the storage capacitor Cst is electrically connected to the gate G of the driving transistor DTFT, and the other end of the storage capacitor Cst is electrically connected to the drain D of the driving transistor DTFT; of course, the GOA circuit may also include other switching transistors and capacitors, which can be specifically determined according to different circuit designs.

[0074] It should be noted that FIG4 schematically shows a top view of the circuit diagram shown in FIG3 , and FIG5 is a schematic diagram of the cross-sectional structure along the A1A2 direction in FIG4 . Among them, the source-drain conductive layer 4 (SD) includes the source S and the drain D of the driving transistor DTFT, and the gate G (located in the gate layer 2) of the driving transistor DTFT extends from the area marked DTFT to the area marked Cst, and the area where the gate G and the source-drain conductive layer SD overlap forms a storage capacitor Cst. In practical applications, in order to increase the potential holding capability of the storage capacitor, the capacitance of the capacitor will be increased. In related technologies, this is usually achieved by increasing the facing area of ​​the gate G and the source-drain conductive layer SD at the position of the storage capacitor Cst. However, for display products with narrow bezels, this approach seriously sacrifices design space, resulting in the inability to achieve a narrow bezel.

[0075] Based on this, an embodiment of the present application provides a driving substrate, a display panel and a display device, wherein the driving substrate includes a display area and a peripheral area located on one side of the display area, the peripheral area includes a plurality of shift register units arranged in cascade; the shift register unit includes a driving transistor and a first storage capacitor, the gate of the driving transistor is electrically connected to the first electrode of the first storage capacitor, and the drain of the driving transistor is electrically connected to the second electrode of the first storage capacitor; the driving substrate also includes: a substrate, a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer is located on the substrate, the first conductive layer includes the gate of the driving transistor and the first electrode of the first storage capacitor; the second conductive layer is located on the side of the first conductive layer away from the substrate, the second conductive layer includes the source of the driving transistor, the drain of the driving transistor and the second electrode of the first storage capacitor; the third conductive layer is located on the side of the second conductive layer away from the first conductive layer, and the orthographic projection of at least one of the first storage capacitor and the driving transistor on the substrate overlaps with the orthographic projection of the third conductive layer on the substrate.

[0076] In the driving substrate provided in the embodiments of the present application, by setting the third conductive layer to overlap with at least one of the driving transistor and the first storage capacitor in the shift register unit, a parallel capacitor is formed between the third conductive layer and the gate of the driving transistor or the third conductive layer and one electrode of the first storage capacitor, that is, a parallel capacitor is added to the shift register. While ensuring that the capacitance in the shift register remains unchanged, the size of the first storage capacitor can be reduced, the planar size of the shift register can be reduced, and the frame size of the driving substrate can be reduced, thereby reducing the frame size of the driving substrate, which is conducive to the preparation of a narrow-frame display panel and a narrow-frame display device.

[0077] The drive substrate, display panel, and display device provided in the embodiments of the present application will be specifically introduced and described below with reference to the accompanying drawings.

[0078] An embodiment of the present application provides a driving substrate as shown in Figures 1, 2, 6, and 7A. The driving substrate includes a display area AA and a peripheral area BB located on one side of the display area AA. The peripheral area BB includes a plurality of shift register units GOA arranged in cascade. The shift register unit GOA includes a driving transistor DTFT and a first storage capacitor C1. The gate G of the driving transistor DTFT is electrically connected to the first electrode of the first storage capacitor C1, and the drain D of the driving transistor DTFT is electrically connected to the second electrode of the first storage capacitor C1.

[0079] As shown in FIG7A and FIG8 , the driving substrate further includes:

[0080] Substrate 1;

[0081] A first conductive layer 2 (eg, a gate layer Gate), located on the substrate 1, includes a gate G of the driving transistor DTFT and a first electrode of the first storage capacitor C1;

[0082] The second conductive layer 4 (e.g., source-drain conductive layer SD) is located on a side of the first conductive layer 2 away from the substrate 1 and includes a source electrode S of the driving transistor DTFT, a drain electrode D of the driving transistor DTFT, and a second electrode of the first storage capacitor C1;

[0083] The third conductive layer 6 (for example, an ITO layer) is located on a side of the second conductive layer 4 away from the first conductive layer 2 , and the orthographic projection of at least one of the first storage capacitor C1 and the driving transistor DTFT on the substrate 1 overlaps with the orthographic projection of the third conductive layer 6 on the substrate 1 .

[0084] In an exemplary embodiment, the above-mentioned driving substrate can be applied to a liquid crystal display (LCD) panel, such as a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, and an advanced super-dimensional switch (ADS) type liquid crystal display panel.

[0085] The planar shape of the display area AA is not limited here. For example, the planar shape of the display area AA can be an arc, a polygon, or a shape formed by combining an arc and a polygon.

[0086] For example, the planar shape of the display area AA may be a rectangle, a rounded rectangle, a square, a rounded square, a circle, an ellipse, a semicircle, a semi-ellipse, or the like.

[0087] The shape of the peripheral area BB can be determined based on the planar shape of the display area AA. For example, the planar shape of the peripheral area BB is annular, the inner contour of the annular shape overlaps the outer contour of the planar shape of the display area AA, and the outer contour of the annular shape is the same as or similar to the inner contour of the annular shape.

[0088] In addition, in some embodiments, the peripheral area BB is arranged around the display area AA; in other embodiments, the peripheral area BB can also be arranged inside the display area AA, for example, the peripheral area BB inside the display area AA is used to set camera-related circuits.

[0089] In an exemplary embodiment, the above-mentioned shift register unit GOA may include a driving transistor DTFT, multiple switching transistors and at least one capacitor (such as a storage capacitor). Depending on the different driving requirements of the GOA circuit for the product applied to the driving substrate, the structural design of the circuit in the shift register unit GOA is different, which is not specifically limited here.

[0090] The specific material of the substrate 1 of the driving substrate is not limited here. For example, the substrate can be any one of silicon, glass, quartz, PET, plastic and the like.

[0091] A first insulating layer 3 is provided between the first conductive layer 2 and the second conductive layer 4 , and a second insulating layer 5 is further provided between the second conductive layer 4 and the third conductive layer 6 .

[0092] The specific material of the first conductive layer 2 is not limited here.

[0093] For example, the material of the first conductive layer 2 may include aluminum (Al), and for example, a stacked structure of Mo / Al / Mo may be formed by sputtering, wherein the material on the side close to the substrate 1 is Mo, and the thickness is about 1 / 2.5mm. It is mainly used to improve the adhesion between film layers. The middle layer material of the laminated structure is Al, which is the material of the electrical signal transmission channel. The material on the side away from the substrate 1 is Mo, with a thickness of about It can be used to protect the middle layer and prevent the surface of the middle layer with low resistivity from being exposed and oxidized.

[0094] For example, the material of the first conductive layer 2 may include copper (Cu), and for example, a stacked structure of MoNb / Cu / MoNb may be formed by sputtering, wherein the material on the side close to the substrate 1 is MoNb with a thickness of approximately It is mainly used to improve the adhesion between film layers. The middle layer material of the laminated structure is Cu, which is the material of the electrical signal transmission channel. The material on the side away from the substrate 1 is MoNb, with a thickness of about It can be used to protect the middle layer and prevent the surface of the middle layer with low resistivity from being exposed and oxidized. Since the thickness of a single sputtering generally does not exceed 1μm, multiple sputterings are required to form the gate line GL with a thickness exceeding 1μm. In addition, it can also be formed by electroplating. Specifically, a seed layer can be formed using MoNiTi to increase the nucleation density of metal grains in the subsequent electroplating process, and then copper with low resistivity is produced by electroplating, and then an anti-oxidation layer is produced. The material can be MoNiTi.

[0095] In an exemplary embodiment, the material of the second conductive layer 4 may include Cu as described above, and may be formed into a stacked structure such as MoNb / Cu / MoNb by sputtering, for example.

[0096] In an exemplary embodiment, the material of the second conductive layer 4 may be the same as that of the first conductive layer 2 .

[0097] In an exemplary embodiment, the material of the third conductive layer 6 may be a light-transmitting conductive material, such as indium zinc oxide (IZO) or indium tin oxide (ITO).

[0098] The first conductive layer 2 (e.g., gate layer Gate) including the gate G of the driving transistor DTFT and the first electrode of the first storage capacitor C1 means that the gate G of the driving transistor DTFT and the first electrode of the first storage capacitor C1 are arranged in the same layer and are both located in the first conductive layer 2. In some embodiments, the gate G of the driving transistor DTFT and the first electrode of the first storage capacitor C1 are connected together and form an integrated structure.

[0099] The second conductive layer 4 includes the source electrode S of the driving transistor DTFT, the drain electrode D of the driving transistor DTFT, and the second electrode of the first storage capacitor C1, which means that the source electrode S of the driving transistor DTFT, the drain electrode D of the driving transistor DTFT, and the second electrode of the first storage capacitor C1 are arranged in the same layer and are located in the second conductive layer 4. In some embodiments, the drain electrode D of the driving transistor DTFT and the second electrode of the first storage capacitor C1 are electrically connected. For example, the drain electrode D of the driving transistor DTFT and the second electrode of the first storage capacitor C1 are an integrated structure.

[0100] In addition, the orthographic projection of at least one of the first storage capacitor C1 and the driving transistor DTFT on the substrate 1 overlaps with the orthographic projection of the third conductive layer 6 on the substrate 1, including but not limited to the following situations:

[0101] First, the orthographic projection of the first storage capacitor C1 on the substrate 1 overlaps with the orthographic projection of the third conductive layer 6 on the substrate 1;

[0102] Second, the orthographic projection of the driving transistor DTFT on the substrate 1 overlaps with the orthographic projection of the third conductive layer 6 on the substrate 1;

[0103] Third, the orthographic projections of the first storage capacitor C1 and the driving transistor DTFT on the substrate 1 overlap with the orthographic projections of the third conductive layer 6 on the substrate 1 .

[0104] It should be noted that "there is overlap" means: at least partial overlap, that is, it includes two situations: partial overlap and complete overlap. The meaning of similar descriptions in the following text is the same as here and will not be repeated here.

[0105] In the driving substrate provided in the embodiment of the present application, the third conductive layer 6 is arranged to overlap with at least one of the driving transistor DTFT and the first storage capacitor C1 in the shift register unit GOA, so that a parallel capacitor (for example, the second storage capacitor C2 shown in Figure 6) is formed between the third conductive layer 6 and the gate G of the driving transistor DTFT or the third conductive layer 6 and one electrode of the first storage capacitor C1, that is, a parallel capacitor is added to the shift register GOA. While ensuring that the capacitance in the shift register remains unchanged, the size of the first storage capacitor C1 can be reduced, and the planar size of the shift register GOA can be reduced, thereby reducing the frame size of the driving substrate, which is conducive to the preparation of a narrow-frame display panel and a narrow-frame display device.

[0106] In the driving substrate provided in at least one embodiment of the present application, the third conductive layer 6 includes a common electrode (e.g., a Com electrode) and a conductive structure 61; or, the third conductive layer 6 includes a pixel electrode (e.g., a Pixel electrode) and a conductive structure 61; wherein the conductive structure 61 is electrically connected to the gate G of the driving transistor DTFT.

[0107] In an exemplary embodiment, the third conductive layer 6 may be a common electrode layer. In this case, a common electrode and a conductive structure 61 are provided in the third conductive layer 6 , and the common electrode and the conductive structure 61 are disconnected.

[0108] In an exemplary embodiment, the third conductive layer 6 may be a pixel electrode layer. In this case, the pixel electrode and the conductive structure 61 are provided in the third conductive layer 6 , and the pixel electrode and the conductive structure 61 are disconnected.

[0109] In some embodiments, multiple slit structures (Slit) may be provided in the third conductive layer 6 to improve the light transmittance of the display panel fabricated from the drive substrate. The arrangement of the multiple slit structures provided in the third conductive layer 6 is not limited herein and may be specifically configured as appropriate. In the drawings provided in the embodiments of this application, the slit structures are not depicted in the third conductive layer 6 to avoid ambiguity.

[0110] In an exemplary embodiment, as shown in conjunction with Figures 7A and 8, Figures 9 and 11, or Figures 12 and 13, the conductive structure 61 is electrically connected to the gate G of the driving transistor DTFT. Figure 8 is a schematic cross-sectional view taken along lines A3A4 in Figure 7A, Figure 11 is a schematic cross-sectional view taken along lines A5A6 in Figure 9, and Figure 13 is a schematic cross-sectional view taken along lines A7A8 in Figure 12. Specifically, the conductive structure 61 is electrically connected to the gate G of the driving transistor DTFT via a first via Via1.

[0111] In the driving substrate provided in at least one embodiment of the present application, as shown in FIG6 , the shift register unit further includes a second storage capacitor C2 , and the second storage capacitor C2 is connected in parallel with the first storage capacitor C1 ;

[0112] As shown in FIG8 , FIG11 and FIG13 , the second electrode of the first storage capacitor C1 and the first electrode of the second storage capacitor C2 are shared, and the conductive structure 61 serves as the second electrode of the second storage capacitor C2 .

[0113] Specifically, as shown in Figures 8, 11 and 13, a first storage capacitor C1 is formed at the overlapping position of the first conductive layer 2 and the second conductive layer 4, and a second storage capacitor C2 is formed at the overlapping position of the second conductive layer 4 and the third conductive layer 6 (conductive structure 61). The first storage capacitor C1 and the second storage capacitor C2 share a partial area of ​​the second conductive layer 4 (the second electrode of the first storage capacitor C1 and the first electrode of the second storage capacitor C2 are shared).

[0114] In the driving substrate provided in the embodiment of the present application, by adding a parallel capacitor in the shift register GOA (that is, superimposing a capacitor in a direction perpendicular to the substrate 1, without increasing the planar size of the shift register and increasing the capacitance of the capacitor), while ensuring that the capacitance in the shift register remains unchanged, the planar size of the shift register GOA can be reduced, thereby reducing the frame size of the driving substrate, which is conducive to the preparation of narrow-frame display panels and narrow-frame display devices.

[0115] In the driving substrate provided in at least one embodiment of the present application, as shown in Figures 7A, 7B and 8, the conductive structure 61 includes a first conductive pattern 61A, and the orthographic projection of the first conductive pattern 61A on the substrate 1 overlaps with the orthographic projection of the first storage capacitor C1 on the substrate 1.

[0116] In Figures 7A, 7B, and 8, the first conductive pattern 61A can serve as the second electrode of the second storage capacitor C2 and form the second storage capacitor C2 with the second electrode of the first storage capacitor C1 (the second electrode of the first storage capacitor C1 and the first electrode of the second storage capacitor C2 are shared). It should be noted that in the top view provided in the embodiment of the present application, in order to clearly illustrate the structure of the drive substrate, the insulating layer between two adjacent conductive layers is not drawn. The arrangement of the insulating layer can refer to the schematic diagram in the cross-sectional structure diagram.

[0117] In the driving substrate provided in at least one embodiment of the present application, as shown in FIG9 , FIG10 and FIG11 , or as shown in FIG12 , FIG13 and FIG14 , the conductive structure 61 further includes a second conductive pattern 61B, and the first conductive pattern 61A and the second conductive pattern 61B are connected;

[0118] In combination with Figures 9 and 10, or as shown in Figure 14, the second conductive pattern 61B covers at least a portion of the surface of the drain D of the driving transistor DTFT away from the substrate 1, and the orthographic projection of the second conductive pattern 61B on the substrate 1 overlaps with the orthographic projection of the drain D of the driving transistor DTFT on the substrate 1, and as shown in Figures 11 and 13, there is a gap between the orthographic projection of the second conductive pattern 61B on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate 1.

[0119] The second conductive pattern 61B covers at least a portion of the surface of the drain electrode D of the driving transistor DTFT away from the substrate 1 , including but not limited to the following situations:

[0120] The first and second conductive patterns 61B cover a portion of the surface of the drain electrode D of the driving transistor DTFT away from the substrate 1. In this case, the area of ​​the region where the second conductive pattern 61B overlaps with the drain electrode D of the driving transistor DTFT may be smaller than the area of ​​the drain electrode D of the driving transistor DTFT. This can also be understood as the orthographic projection of the second conductive pattern 61B on the substrate 1 partially overlapping with the orthographic projection of the drain electrode D of the driving transistor DTFT on the substrate 1.

[0121] Second, as shown in conjunction with FIG9 and FIG11 , the second conductive pattern 61B covers the entire area of ​​the surface of the drain electrode D of the driving transistor DTFT away from the substrate 1. In this case, the area of ​​the region where the second conductive pattern 61B overlaps with the drain electrode D of the driving transistor DTFT may be substantially equal to the area of ​​the drain electrode D of the driving transistor DTFT. This can also be understood as the orthographic projection of the second conductive pattern 61B on the substrate 1 completely overlapping the orthographic projection of the drain electrode D of the driving transistor DTFT on the substrate 1.

[0122] Third, as shown in FIG. 13 and FIG. 14 , the second conductive pattern 61B covers the entire surface area of ​​the drain D of the driving transistor DTFT away from the substrate 1 , and the second conductive pattern 61B also extends to the area outside the drain D of the driving transistor DTFT.

[0123] In an exemplary embodiment, to avoid increasing the load on a signal line (e.g., a clock signal line CLK) electrically connected to the shift register, the orthographic projection of the second conductive pattern 61B on the substrate 1 may be configured to not overlap with the orthographic projection of the channel region of the drive transistor DTFT on the substrate 1, and the orthographic projection of the second conductive pattern 61B on the substrate 1 may not overlap with the orthographic projection of the source electrode S of the drive transistor DTFT on the substrate 1. The channel region of the drive transistor DTFT refers to the active portion 7 of the transistor (disposed on the semiconductor layer ACT), which is the region of the transistor between the source electrode S and the drain electrode D through which current flows.

[0124] In the driving substrate provided in at least one embodiment of the present application, as shown in Figure 11, the minimum distance d2 between the orthographic projection of the second conductive pattern 61B on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate 1 is approximately equal to the minimum distance d1 between the orthographic projection of the drain D of the driving transistor DTFT on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate.

[0125] As shown in Figures 9 and 11, when the minimum distance d2 between the orthographic projection of the second conductive pattern 61B on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate 1 is approximately equal to the minimum distance d1 between the orthographic projection of the drain D of the driving transistor DTFT on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate, the second conductive pattern 61B covers the entire area of ​​the surface of the drain D of the driving transistor DTFT away from the substrate 1, and the edge of the second conductive pattern 61B is flush with the edge of the drain D of the driving transistor DTFT.

[0126] In this way, the first conductive pattern 61A and the second conductive pattern 61B jointly serve as the second electrode of the second storage capacitor C2, and the second electrode of the first storage capacitor C1 extends from the position marked Cst in Figure 9 to the drain D of the driving transistor DTFT (the second electrode of the first storage capacitor C1 and the first electrode of the second storage capacitor C2 are shared), which greatly increases the facing area between the two electrodes of the second storage capacitor C2, thereby increasing the capacitance of the second storage capacitor C2, and increasing the capacitance of the storage capacitor Cst (including the first storage capacitor C1 and the second storage capacitor C2 in parallel). When the capacitance requirement of the shift register unit GOA in the driving substrate remains unchanged, the size of the capacitor at the position marked Cst in Figure 9 can be reduced, thereby reducing the planar size of the shift register unit GOA, which is conducive to the preparation of narrow-border display panels.

[0127] In the driving substrate provided in at least one embodiment of the present application, in combination with Figures 12, 13 and 14, the second conductive pattern 61B also covers at least the side surface of the drain D of the driving transistor DTFT close to the source S (for example, the position marked by the dotted circle in Figure 13); the minimum distance d3 between the orthographic projection of the second conductive pattern 61B on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate 1 is smaller than the minimum distance d1 between the orthographic projection of the drain D of the driving transistor DTFT on the substrate 1 and the orthographic projection of the source S of the driving transistor DTFT on the substrate 1.

[0128] 13 and 14 , the second conductive pattern 61B covers the side surface of the drain D of the driving transistor DTFT close to the source S, and also covers the side surface of the drain D of the driving transistor DTFT away from the source S.

[0129] As shown in the area marked with a dotted circle in Figure 13, when the second conductive pattern 61B covers the side of the drain D of the driving transistor DTFT, a capacitor structure is formed between the second conductive pattern 61B and the drain D in the horizontal direction, which can further increase the capacitance of the second storage capacitor C2, thereby further increasing the capacitance of the storage capacitor Cst (including the first storage capacitor C1 and the second storage capacitor C2 in parallel). When the capacitance requirement of the shift register unit GOA in the driving substrate remains unchanged, the size of the capacitor at the position marked Cst in Figure 9 can be reduced, thereby reducing the planar size of the shift register unit GOA, which is beneficial to the preparation of a narrow-border display panel.

[0130] In the driving substrate provided in at least one embodiment of the present application, as shown in FIG. 7A to FIG. 14 , the first conductive layer 2 includes a gate layer Gate, and the second conductive layer 4 includes a source-drain conductive layer SD;

[0131] The thickness of the source-drain conductive layer SD along the direction perpendicular to the substrate 1 is 800 nm to 1200 nm.

[0132] In the related art, the thickness of the source-drain conductive layer SD along the direction perpendicular to the substrate 1 is 300nm~600nm. For example, when the source-drain conductive layer SD adopts the aluminum (Al) process, its thickness range is 300nm~400nm; for example, when the source-drain conductive layer SD adopts the copper (Cu) process, its thickness range is 300nm~600nm.

[0133] In an embodiment of the present application, when the source / drain conductive layer SD adopts an aluminum (Al) process, its thickness can be set to a range of 800 nm to 1000 nm; for example, 850 nm, 880 nm, 900 nm, 950 nm, and 980 nm.

[0134] When the source / drain conductive layer SD adopts a copper (Cu) process, its thickness ranges from 800 nm to 1200 nm; for example, 850 nm, 880 nm, 900 nm, 950 nm, 980 nm, 1050 nm, 1100 nm, 1150 nm, and 1180 nm.

[0135] In the embodiment of the present application, as shown in the area marked with a dotted circle in FIG13 , when the second conductive pattern 61B covers the side surface of the drain electrode D of the driving transistor DTFT, a capacitor structure is formed in the lateral direction between the second conductive pattern 61B and the drain electrode D. By increasing the thickness of the second conductive layer 4, the capacitance of the capacitor structure formed in the lateral direction between the second conductive pattern 61B and the drain electrode D can be increased, and the capacitance of the second storage capacitor C2 can be further increased, thereby further increasing the capacitance of the storage capacitor Cst (including the first storage capacitor C1 and the second storage capacitor C2 connected in parallel). When the capacitance requirement of the shift register unit GOA in the driving substrate remains unchanged, the size of the capacitor at the position marked with Cst in FIG9 can be reduced, thereby reducing the planar size of the shift register unit GOA, which is conducive to the preparation of a narrow-frame display panel.

[0136] In the driving substrate provided in at least one embodiment of the present application, as shown in FIG15 , the boundary line between the peripheral area BB and the display area AA includes an arc line, and the resolution of the driving substrate is less than or equal to 200;

[0137] The orthographic projection shape of the shift register unit GOA on the substrate 1 includes a figure formed by splicing the first rectangle J1 and the second rectangle J2. The outer contour of the side of the figure formed by splicing the first rectangle J1 and the second rectangle J2 close to the display area AA includes a stepped shape.

[0138] In an exemplary embodiment, as shown in FIG. 15 , the outer contour of the side of the figure formed by splicing the first rectangle J1 and the second rectangle J2 away from the display area AA includes a stepped shape.

[0139] In an embodiment of the present application, by setting the shape of the outer contour of the side of the figure formed by splicing the first rectangle J1 and the second rectangle J2 close to the display area AA to include a stepped shape, the shift register unit GOA can be arranged closer to the display area AA as a whole, and the space between the display area AA and the shift register unit GOA in the prior art is utilized as much as possible, so that the improved driving substrate can have a smaller frame size.

[0140] In the driving substrate provided in at least one embodiment of the present application, the absolute value of the difference between the minimum distance between the first rectangle J1 and the boundary line between the peripheral area BB and the display area AA in part of the shift register GOA and the minimum distance between the second rectangle J2 and the boundary line between the peripheral area BB and the display area AA (for example, the offset distance between the first rectangle J1 and the second rectangle J2 in the horizontal direction in one shift register in Figure 15) is approximately equal to the absolute value of the difference between the minimum distance between the first rectangle J1 and the boundary line between the peripheral area BB and the display area AA and the minimum distance between the second rectangle J2 and the boundary line between the peripheral area BB and the display area AA in another part of the shift register GOA (for example, the offset distance between the first rectangle J1 and the second rectangle J2 in the horizontal direction in another shift register in Figure 15).

[0141] In an exemplary embodiment, in a local area, the offset distances of the first rectangle J1 and the second rectangle J2 in the horizontal direction in all the shift registers in the area may be set to be substantially equal.

[0142] In an exemplary embodiment, the absolute value of the difference between the minimum distance between the first rectangle J1 and the boundary line between the peripheral area BB and the display area AA in any one shift register GOA and the minimum distance between the second rectangle J2 and the boundary line between the peripheral area BB and the display area AA can be set to be approximately equal to the absolute value of the difference between the minimum distance between the first rectangle J1 and the boundary line between the peripheral area BB and the display area AA and the minimum distance between the second rectangle J2 and the boundary line between the peripheral area BB and the display area AA in any other shift register GOA.

[0143] In the driving substrate provided by at least one embodiment of the present application, as shown in FIG15 , the first rectangle J1 and the second rectangle J2 are sequentially arranged in a direction of increasing curvature ρ along an arc line (a boundary line between the peripheral area BB and the display area AA includes an arc);

[0144] As the curvature ρ of the arc increases, the absolute value of the difference between the minimum distance between the first rectangle J1 and the boundary line of the shift register unit GOA and the minimum distance between the second rectangle J2 and the boundary line gradually increases.

[0145] In an exemplary embodiment, in a local area of ​​the boundary line between the peripheral area BB and the display area AA, the curvature ρ of the arc increases. When the curvature ρ increases, the offset distance between the first rectangle J1 and the second rectangle J2 in the same shift register unit GOA in the horizontal direction can be increased, thereby further effectively utilizing the space in the peripheral area BB, and the shift register unit GOA as a whole can be arranged closer to the display area AA, so that the improved driving substrate can have a smaller frame size.

[0146] In the driving substrate provided in at least one embodiment of the present application, as shown in Figure 17, the peripheral area BB includes a first peripheral sub-area ①, a second peripheral sub-area ② and a third peripheral sub-area ③, and the curvatures of the boundary line between the first peripheral sub-area ① and the display area AA, the boundary line between the second peripheral sub-area ② and the display area AA, and the boundary line between the third peripheral sub-area ③ and the display area AA increase successively, and the resolution of the driving substrate is greater than or equal to 200; wherein, Figure 16 is a schematic diagram of the top view structure of the local area of ​​the driving substrate shown in Figure 17 before improvement; the orthographic projection shape of the shift register unit GOA on the substrate 1 includes a third rectangle J3; the shape of the outer contour of the multiple connected third rectangles J3 close to the display area AA side is stepped, and the sizes of the third rectangles J3 in the first peripheral sub-area ①, the second peripheral sub-area ② and the third peripheral sub-area ③ are different.

[0147] In an exemplary embodiment, the outer contour of the plurality of connected third rectangles J3 on the side away from the display area AA is in a stepped shape.

[0148] Among them, the different sizes of the third rectangle J3 in the first peripheral sub-area ①, the second peripheral sub-area ② and the third peripheral sub-area ③ include but are not limited to: different lengths of the third rectangle J3, different heights of the third rectangle J3, or different areas of the third rectangle J3.

[0149] It should be noted that although the sizes of the third rectangle J3 in the first peripheral sub-area ①, the second peripheral sub-area ② and the third peripheral sub-area ③ are different, the circuit structures of all shift register units in the first peripheral sub-area ①, the second peripheral sub-area ② and the third peripheral sub-area ③ are the same.

[0150] In an exemplary embodiment, by setting the orthographic projection shape of the shift register unit GOA on the substrate 1 to include a third rectangle J3, the curvatures of the boundary line between the first peripheral sub-area ① and the display area AA, the boundary line between the second peripheral sub-area ② and the display area AA, and the boundary line between the third peripheral sub-area ③ and the display area AA increase successively, and the sizes of the third rectangle J3 in the first peripheral sub-area ①, the second peripheral sub-area ②, and the third peripheral sub-area ③ are set to be different, so that the space in the peripheral area BB can be further effectively utilized, and the shift register unit GOA can be arranged closer to the display area AA as a whole, so that the improved driving substrate can have a smaller frame size.

[0151] In the driving substrate provided in at least one embodiment of the present application, as shown in Figure 17, the size h1 of the third rectangle J3 in the first peripheral sub-area ① along the first direction (for example, the OA direction) is greater than the size h0 of the third rectangle J3 in the second peripheral sub-area ② along the first direction, and the size h0 of the third rectangle J3 in the second peripheral sub-area ② along the first direction is greater than the size h2 of the third rectangle J3 in the third peripheral sub-area ③ along the first direction; wherein, the first direction (for example, the OA direction) is perpendicular to the extension direction of the gate line GL in the driving substrate.

[0152] In an embodiment of the present application, when the curvature of the boundary line between the peripheral area BB and the display area AA is greater, the design space in the extension direction parallel to the gate line is more sufficient, and the design space in the extension direction perpendicular to the gate line is smaller. By setting the size h1 of the third rectangle J3 in the first peripheral sub-area ① along the first direction (for example, the OA direction) to be larger than the size h0 of the third rectangle J3 in the second peripheral sub-area ② along the first direction, and the size h0 of the third rectangle J3 in the second peripheral sub-area ② along the first direction to be larger than the size h2 of the third rectangle J3 in the third peripheral sub-area ③ along the first direction, the height of the third rectangle J3 in the third peripheral sub-area ③ can be reduced, and the height of the third rectangle J3 in the first peripheral sub-area ① can be increased, thereby improving the space utilization in the peripheral area BB, so that the improved driving substrate can have a smaller frame size.

[0153] In the driving substrate provided in at least one embodiment of the present application, as shown in Figure 17, the sum of the dimension h1 of the third rectangle J3 in the first peripheral sub-area ① along the first direction and the dimension h2 of the third rectangle J3 in the third peripheral sub-area ③ along the first direction is approximately equal to twice the dimension h0 of the third rectangle J3 in the second peripheral sub-area ② along the first direction, that is, h1+h2=2h0.

[0154] In an exemplary embodiment, the absolute value of the difference of h1 - h0 is substantially equal to the absolute value of the difference of h2 - h0.

[0155] In the driving substrate provided in at least one embodiment of the present application, the number of shift register units GOA in the first peripheral sub-area ① is equal to the number of shift register units GOA in the third peripheral sub-area ③.

[0156] In an embodiment of the present application, when the curvature of the boundary line between the peripheral area BB and the display area AA is greater, the design space in the extension direction parallel to the gate line is more sufficient, and the design space in the extension direction perpendicular to the gate line is smaller, by reducing the size h2 of the third rectangle J3 in the third peripheral sub-area ③ with a larger curvature along the first direction, and increasing the size h1 of the third rectangle J3 in the first peripheral sub-area ① with a smaller curvature along the first direction, and making h1+h2=2h0; when the number of shift register units GOA in the first peripheral sub-area ① is equal to the number of shift register units GOA in the third peripheral sub-area ③, the space perpendicular to the extension direction of the gate line (vertical direction) saved by the third rectangle J3 in the third peripheral sub-area ③ with a larger curvature is roughly the same as the space perpendicular to the extension direction of the gate line (vertical direction) increased by the third rectangle J3 in the first peripheral sub-area ① with a smaller curvature, thereby improving the utilization of space, making the space utilization of different areas in the peripheral area BB more reasonable, and facilitating the preparation of display panels with narrow bezels.

[0157] In some embodiments, the sum of the longitudinal heights of the GOA units on the left (or right) side cannot exceed the height range of the display area AA, that is, the GOA units are arranged on the left and right sides of the display area AA and cannot enter the upper and lower side areas of the display area AA.

[0158] In the driving substrate provided in at least one embodiment of the present application, as shown in Figure 17, the dimension y1 of the third rectangle J3 in the first peripheral sub-area ① along the second direction is smaller than the dimension y0 of the third rectangle J3 in the second peripheral sub-area ② along the second direction, and the dimension y0 of the third rectangle J3 in the second peripheral sub-area ② along the second direction is smaller than the dimension y2 of the third rectangle J3 in the third peripheral sub-area ③ along the second direction; wherein the second direction is consistent with the extension direction of the gate line in the driving substrate.

[0159] In an embodiment of the present application, when the curvature of the boundary line between the peripheral area BB and the display area AA is greater, the design space along the extension direction perpendicular to the gate line is smaller, and the design space in the extension direction parallel to the gate line (or the second direction) is more sufficient. Therefore, by increasing the size y2 of the third rectangle J3 in the third peripheral sub-area ③ along the second direction and reducing the size y1 of the third rectangle J3 in the first peripheral sub-area ① along the second direction, the design space in the extension direction parallel to the gate line in the peripheral area BB can be more reasonably utilized, which is conducive to improving the preparation of display panels with narrow bezels.

[0160] In the driving substrate provided in at least one embodiment of the present application, as shown in FIG18 , the driving substrate includes an adhesive layer 9 located on a substrate 1 , and a portion of the adhesive layer 9 is located on a side of the shift register unit GOA away from the display area AA;

[0161] The minimum distance D between the side of the adhesive layer 9 (eg, sealant) away from the display area AA and the shift register unit GOA is greater than or equal to 200 μm.

[0162] In an exemplary embodiment, the orthographic projection of the shift register unit GOA on the substrate 1 may partially overlap with the orthographic projection of the adhesive layer 9 on the substrate 1 .

[0163] Illustratively, the minimum distance D between the side of the adhesive layer 9 (eg seal) away from the display area AA and the shift register unit GOA may be 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 μm or 400 μm.

[0164] Exemplarily, as shown in FIG18 , the common electrode line Vcom line is disposed between the shift register unit GOA and the display area AA.

[0165] In an embodiment of the present application, by setting the minimum distance D between the side of the adhesive layer 9 (for example, sealant) away from the display area AA and the shift register unit GOA to be greater than or equal to 200 μm, when the display panel is prepared using a driving substrate, the adhesive layer 9 can be fully irradiated with ultraviolet light, avoiding excessive blocking of light by the GOA unit, thereby facilitating the curing of the adhesive layer 9 and improving the reliability of the display panel.

[0166] An embodiment of the present application provides a display panel, comprising any one of the driving substrates described above.

[0167] Exemplarily, the display panel may further include a color filter substrate, and a liquid crystal layer may be provided between the color filter substrate and the driving substrate.

[0168] The display panel may be an LCD (Liquid Crystal Display) display panel, for example, a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, and an advanced super-dimensional switch (ADS) type LCD panel.

[0169] An embodiment of the present application provides a display device, including the display panel as described above, wherein the display panel is a special-shaped display panel.

[0170] For example, the shape of the special-shaped display panel may be circular, elliptical, or have rounded corners or an arc shape.

[0171] The display device may be an LCD (Liquid Crystal Display) display device, for example, a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, and an advanced super-dimensional switching (ADS) type LCD device.

[0172] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0173] In the display device provided in the embodiment of the present application, by adding a parallel capacitor in the shift register GOA (that is, superimposing a capacitor in a direction perpendicular to the substrate 1, without increasing the planar size of the shift register and increasing the capacitance of the capacitor), while ensuring that the capacitance in the shift register remains unchanged, the planar size of the shift register GOA can be reduced, thereby reducing the border size of the driving substrate, which is conducive to the preparation of a narrow-border display panel and a narrow-border display device.

[0174] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A driving substrate, wherein: The driving substrate includes a display area and a peripheral area located on one side of the display area, the peripheral area includes a plurality of shift register units arranged in cascade; the shift register unit includes a driving transistor and a first storage capacitor, the gate of the driving transistor is electrically connected to the first electrode of the first storage capacitor, and the drain of the driving transistor is electrically connected to the second electrode of the first storage capacitor; the driving substrate also includes: substrate; A first conductive layer, located on the substrate, including a gate of the driving transistor and a first electrode of the first storage capacitor; a second conductive layer, located on a side of the first conductive layer away from the substrate, comprising a source electrode of the driving transistor, a drain electrode of the driving transistor and a second electrode of the first storage capacitor; The third conductive layer is located on a side of the second conductive layer away from the first conductive layer, and the orthographic projection of at least one of the first storage capacitor and the driving transistor on the substrate overlaps with the orthographic projection of the third conductive layer on the substrate.

2. The driving substrate according to claim 1, wherein: The third conductive layer includes the common electrode and the conductive structure; or the third conductive layer includes the pixel electrode and the conductive structure; Wherein, the conductive structure is electrically connected to the gate of the driving transistor.

3. The driving substrate according to claim 2, wherein: The shift register unit further includes a second storage capacitor, wherein the second storage capacitor is connected in parallel with the first storage capacitor; The second electrode of the first storage capacitor and the first electrode of the second storage capacitor are shared, and the conductive structure serves as the second electrode of the second storage capacitor.

4. The driving substrate according to claim 3, wherein: The conductive structure includes a first conductive pattern, and an orthographic projection of the first conductive pattern on the substrate overlaps with an orthographic projection of the first storage capacitor on the substrate.

5. The driving substrate according to claim 4, wherein: The conductive structure further includes a second conductive pattern, wherein the first conductive pattern is connected to the second conductive pattern; The second conductive pattern covers at least a portion of a surface of the side of the drain of the driving transistor away from the substrate, an orthographic projection of the second conductive pattern on the substrate overlaps with an orthographic projection of the drain of the driving transistor on the substrate, and the second conductive pattern is disposed on the substrate. There is a gap between the orthographic projection of the source of the driving transistor on the substrate and the orthographic projection of the source of the driving transistor on the substrate.

6. The driving substrate according to claim 5, wherein: The minimum distance between the orthographic projection of the second conductive pattern on the substrate and the orthographic projection of the source of the driving transistor on the substrate is substantially equal to the minimum distance between the orthographic projection of the drain of the driving transistor on the substrate and the orthographic projection of the source of the driving transistor on the substrate.

7. The driving substrate according to claim 5, wherein: The second conductive pattern at least covers the side surface of the drain electrode of the driving transistor close to the source electrode; The minimum distance between the orthographic projection of the second conductive pattern on the substrate and the orthographic projection of the source of the driving transistor on the substrate is smaller than the minimum distance between the orthographic projection of the drain of the driving transistor on the substrate and the orthographic projection of the source of the driving transistor on the substrate.

8. The drive substrate according to any one of claims 2 to 7, wherein: The first conductive layer includes a gate layer, and the second conductive layer includes a source-drain conductive layer; Wherein, the thickness of the source-drain conductive layer along the direction perpendicular to the substrate is 800-1200 nm.

9. The drive substrate according to any one of claims 2 to 7, wherein: The boundary line between the peripheral area and the display area includes an arc line, and the resolution of the driving substrate is less than or equal to 200; The orthographic projection shape of the shift register unit on the substrate includes a figure formed by splicing a first rectangle and a second rectangle, and the shape of the outer contour of a side of the figure formed by splicing the first rectangle and the second rectangle close to the display area includes a stepped shape.

10. The driving substrate according to claim 9, wherein: The absolute value of the difference between the minimum distance between the first rectangle and the boundary line and the minimum distance between the second rectangle and the boundary line in some of the shift registers is approximately equal to the absolute value of the difference between the minimum distance between the first rectangle and the boundary line and the minimum distance between the second rectangle and the boundary line in another part of the shift register.

11. The driving substrate according to claim 9, wherein: The first rectangle and the second rectangle are arranged in sequence along a direction in which the curvature of the arc increases; In the direction of increasing curvature along the arc, the minimum distance between the first rectangle of the shift register unit and the boundary line is greater than the minimum distance between the second rectangle and the boundary line. The absolute value of the difference between small distances gradually increases.

12. The drive substrate according to any one of claims 2 to 7, wherein: The peripheral area includes a first peripheral sub-area, a second peripheral sub-area and a third peripheral sub-area, the curvatures of a boundary line between the first peripheral sub-area and the display area, a boundary line between the second peripheral sub-area and the display area and a boundary line between the third peripheral sub-area and the display area increase in sequence, and the resolution of the driving substrate is greater than or equal to 200; The positive projection shape of the shift register unit on the substrate includes a third rectangle; the outer contour of multiple third rectangles connected together close to the display area is in a stepped shape, and the sizes of the third rectangles in the first peripheral sub-area, the second peripheral sub-area and the third peripheral sub-area are different.

13. The driving substrate according to claim 12, wherein: The size of the third rectangle in the first peripheral sub-area along the first direction is greater than the size of the third rectangle in the second peripheral sub-area along the first direction, and the size of the third rectangle in the second peripheral sub-area along the first direction is greater than the size of the third rectangle in the third peripheral sub-area along the first direction; wherein the first direction is perpendicular to the extension direction of the gate line in the driving substrate.

14. The driving substrate according to claim 13, wherein: The sum of the size of the third rectangle in the first peripheral sub-region along the first direction and the size of the third rectangle in the third peripheral sub-region along the first direction is substantially equal to twice the size of the third rectangle in the second peripheral sub-region along the first direction.

15. The driving substrate according to claim 14, wherein: The number of the shift register units in the first peripheral sub-area is equal to the number of the shift register units in the third peripheral sub-area.

16. The driving substrate according to claim 13, wherein: The size of the third rectangle in the first peripheral sub-area along the second direction is smaller than the size of the third rectangle in the second peripheral sub-area along the second direction, and the size of the third rectangle in the second peripheral sub-area along the second direction is smaller than the size of the third rectangle in the third peripheral sub-area along the second direction; wherein the second direction is consistent with the extension direction of the gate line in the driving substrate.

17. The drive substrate according to any one of claims 1 to 7, 10 to 11, and 13 to 16, wherein: The driving substrate comprises a bonding layer located on the substrate, and a partial area of ​​the bonding layer is located on a side of the shift register unit away from the display area; Wherein, the minimum distance between the side of the adhesive layer away from the display area and the shift register unit is greater than or equal to 200 μm.

18. A display panel, wherein: The invention comprises the drive substrate according to any one of claims 1 to 17.

19. A display device, wherein: It comprises the display panel as claimed in claim 18, wherein the display panel is a special-shaped display panel.

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