Light-emitting device, display device comprising same, and method for manufacturing display device

Abstract

A light-emitting device according to an embodiment includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a light-emitting layer disposed on the second semiconductor layer; a third semiconductor layer disposed on the light-emitting layer; a device electrode layer disposed on the third semiconductor layer; a connection electrode disposed on the device electrode layer; a first insulating layer surrounding the lateral sides of the first semiconductor layer and the second semiconductor layer; a contact electrode surrounding the lateral sides of the first semiconductor layer and the second semiconductor layer; and a second insulating layer surrounding the lateral sides of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, the device electrode layer, and the connection electrode, wherein the contact electrode is in contact with the lateral sides of the second semiconductor layer.

Description

Light-emitting element, display device including same, and method for manufacturing display device

[0001] The present invention relates to a light-emitting element, a display device including the same, and a method for manufacturing the display device.

[0002] The importance of display devices is increasing with the development of multimedia. In response, various types of display devices are being used, such as organic light-emitting diode displays (OLED displays) and liquid crystal displays (LCDs).

[0003] A display device that displays an image includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among these, the light-emitting display panel may include a light-emitting element. For example, in the case of a light-emitting diode (LED), there are organic light-emitting diodes (OLEDs) that use organic materials as light-emitting materials, and inorganic light-emitting diodes that use inorganic materials as light-emitting materials.

[0004] The problem to be solved by the present invention is to provide a light-emitting element capable of making side contact with a first semiconductor layer, a display device including the same, and a method for manufacturing the display device.

[0005] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a light-emitting device includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, a light-emitting layer disposed on the second semiconductor layer, a third semiconductor layer disposed on the light-emitting layer, a device electrode layer disposed on the third semiconductor layer, a connection electrode disposed on the device electrode layer, a first insulating film surrounding side surfaces of the first semiconductor layer and the second semiconductor layer, a contact electrode surrounding side surfaces of the first insulating film and the second semiconductor layer, and a second insulating film surrounding side surfaces of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, the device electrode layer, and the connection electrode, wherein the contact electrode can contact a side surface of the second semiconductor layer.

[0007] The first insulating film may surround the entire side surface of the first semiconductor layer and may surround a portion of the side surface of the second semiconductor layer.

[0008] The above contact electrode may be in non-contact with the first semiconductor layer.

[0009] The second insulating film may surround a side of the contact electrode, but may not be in contact with the first insulating film.

[0010] The contact electrode and the second semiconductor layer include a contact area in which they are in contact with each other, and the contact area can be arranged in an area of ​​1 to 90% of the length of the second semiconductor layer from the interface between the first semiconductor layer and the second semiconductor layer.

[0011] The above contact area may range from 1 to 90% of the total area of ​​the side surface of the second semiconductor layer.

[0012] The side of the first insulating film, the side of the contact electrode, and the side of the second insulating film can be aligned with each other.

[0013] The above first insulating film may be in non-contact with the second semiconductor layer.

[0014] The second insulating film is not in contact with the side surface of the contact electrode and can be aligned with the side surface of the contact electrode.

[0015] It further includes a reflective layer surrounding a side surface of the second insulating film, and a side surface of the reflective layer can be mutually aligned with a side surface of the contact electrode.

[0016] The first semiconductor layer may include an undoped semiconductor, the second semiconductor layer may include an n-type semiconductor, and the third semiconductor layer may include a p-type semiconductor.

[0017] In addition, a display device according to one embodiment includes a substrate, a pixel electrode disposed on the substrate, a light-emitting element disposed on the pixel electrode, a first organic layer disposed on the pixel electrode and between the light-emitting elements, and a common electrode disposed on the first organic layer and the light-emitting elements, wherein each of the light-emitting elements includes a connection electrode disposed on the pixel electrode, an element electrode layer disposed on the connection electrode, a third semiconductor layer disposed on the element electrode c layer, an emission layer disposed on the third semiconductor layer, a second semiconductor layer disposed on the emission layer, a first semiconductor layer disposed on the second semiconductor layer, a first insulating film surrounding side surfaces of the first semiconductor layer and the second semiconductor layer, a contact electrode surrounding side surfaces of the first insulating film and the second semiconductor layer, and a second insulating film surrounding side surfaces of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, the element electrode layer, and the connection electrode, wherein the contact electrode is disposed on a side surface of the second semiconductor layer, and the common electrode may be connected to the contact electrode.

[0018] The above connecting electrode is connected to the pixel electrode, and the second semiconductor layer can be electrically connected to the common electrode through the connecting electrode.

[0019] The upper surface of the first organic layer can be mutually aligned with the upper surface of the first insulating film and the upper surface of the contact electrode.

[0020] The common electrode may be disposed on the first semiconductor layer, the first insulating film, the contact electrode, and the first organic layer.

[0021] It further includes a third insulating film disposed between the first semiconductor layer and the common electrode, wherein the common electrode can be in non-contact with the first semiconductor layer.

[0022] The third insulating film may be in contact with the first semiconductor layer and may not be in contact with the first insulating film.

[0023] The common electrode can be in contact with the side surface of the first insulating film and the side surface of the contact electrode.

[0024] The light emitting element further includes a reflective layer surrounding a side surface of the second insulating film, and the first organic layer can cover the reflective layer.

[0025] It further includes a second organic layer disposed on the first organic layer, and the common electrode can be disposed between the first organic layer and the second organic layer.

[0026] The common electrode surrounds and contacts a side of the contact electrode, and the second organic layer can cover a portion of the common electrode.

[0027] In addition, a method for manufacturing a display device according to one embodiment includes a step of forming a pixel electrode on a substrate, a step of forming light-emitting elements on a base substrate, a step of combining the light-emitting elements formed on the base substrate onto the pixel electrode, a step of forming an organic layer between the light-emitting elements on the pixel electrode, and a step of forming a common electrode on the organic layer and the light-emitting elements, wherein the step of forming the light-emitting elements on the base substrate may include a step of forming a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a third semiconductor layer, and a device electrode layer on the base substrate, a step of forming a first insulating film surrounding side surfaces of the first semiconductor layer and the second semiconductor layer, a step of forming a contact electrode surrounding side surfaces of the first insulating film and the second semiconductor layer, a step of forming a second insulating film surrounding side surfaces of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, and the device electrode layer, and a step of forming a connection electrode on the device electrode layer.

[0028] The first insulating film, the second insulating film, and the contact electrode can be formed by simultaneously etching the first insulating material layer, the contact electrode material layer, and the second insulating material layer.

[0029] The step of combining the light-emitting elements formed on the base substrate onto the pixel electrode may include the step of adhering a support film onto the connection electrodes of the light-emitting elements, the step of separating the base substrate from the light-emitting elements, the step of adhering a transfer film to one surface of the light-emitting elements facing the support film, the step of separating the support film from the light-emitting elements, the step of combining the connection electrodes of the light-emitting elements onto the pixel electrode, and the step of removing the transfer film from the light-emitting elements.

[0030] After the step of separating the support film from the light-emitting elements, the transfer film can be stretched to increase the spacing between the light-emitting elements.

[0031] The step of connecting the connection electrodes of the light-emitting elements on the pixel electrode can be performed by irradiating the pixel electrode with a laser to melt and bond the connection electrode and the pixel electrode.

[0032] Specific details of other embodiments are included in the detailed description and drawings.

[0033] According to one embodiment, a light-emitting element, a display device including the same, and a method for manufacturing the display device can omit a process of removing a first semiconductor layer by forming a contact electrode in contact with a side surface of a second semiconductor layer to drive light-emitting elements through a common electrode. Accordingly, process defects that may occur during the process of removing the first semiconductor layer can be prevented, and the productivity of the manufacturing process of the display device can be improved.

[0034] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0035] Figure 1 is a schematic plan view of a display device according to one embodiment.

[0036] FIG. 2 is a schematic layout diagram of circuit wirings of a display substrate of a display device according to one embodiment.

[0037] FIG. 3 is an equivalent circuit diagram of one pixel of a display device according to one embodiment.

[0038] Fig. 4 is an equivalent circuit diagram of one pixel of a display device according to another embodiment.

[0039] Fig. 5 is an equivalent circuit diagram of one pixel of a display device according to another embodiment.

[0040] Fig. 6 is a cross-sectional view schematically illustrating a display device according to one embodiment.

[0041] Fig. 7 is a plan view showing an example of light-emitting areas of a display device according to one embodiment.

[0042] Fig. 8 is a schematic diagram showing a light-emitting element according to one embodiment.

[0043] Fig. 9 is a perspective view showing a contact area of ​​a contact electrode and a second semiconductor layer of a light-emitting element according to one embodiment.

[0044] Fig. 10 is an enlarged view showing a light-emitting element portion of a display device according to one embodiment.

[0045] Fig. 11 is a drawing showing a light-emitting element according to another embodiment.

[0046] Fig. 12 is a drawing showing a light-emitting element according to another embodiment.

[0047] Fig. 13 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0048] Fig. 14 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0049] Fig. 15 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0050] Fig. 16 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0051] FIGS. 17 to 19 are enlarged views of a light-emitting element area of ​​a display device according to another embodiment.

[0052] Fig. 20 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0053] FIGS. 21 to 40 are drawings for explaining a method of manufacturing a display device according to one embodiment.

[0054] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0055] When an element or layer is referred to as "on" another element or layer, it includes both cases where it is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, when an element or layer is referred to as "below," "left," and "right," it includes both cases where it is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0056] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0057] Hereinafter, embodiments will be described with reference to the attached drawings.

[0058] Figure 1 is a schematic plan view of a display device according to one embodiment.

[0059] Referring to FIG. 1, a display device (10) according to one embodiment can be applied to various home appliances such as a smart phone, a mobile phone, a tablet PC, a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a television, a game console, a wristwatch-type electronic device, a head-mounted display, a monitor of a personal computer, a laptop computer, an automobile navigation system, an automobile dashboard, a digital camera, a camcorder, an external billboard, an electronic display, a medical device, an inspection device, a refrigerator, a washing machine, or the like, or an Internet of Things device. In this specification, a television is described as an example of a display device, and the TV can have a high resolution or ultra-high resolution such as HD, UHD, 4K, or 8K.

[0060] In addition, the display device (10) according to one embodiment may be classified in various ways according to the display method. For example, the classification of the display device may include an organic light emitting display (OLED display), an inorganic light emitting diode display (Inorganic LED display), a quantum dot light emitting display (QED), a micro-LED display, a nano-LED display, a plasma display panel (PDP), a field emission display (FED), a cathode ray tube display (CRT display), a liquid crystal display (LCD), an electrophoretic display (EPD), etc. In the following, an organic light emitting display will be described as an example of a display device, and unless a special distinction is required, an organic light emitting display applied to the embodiment will be simply referred to as a display device. However, the embodiment is not limited to an organic light emitting display device, and other display devices listed above or known in the art may be applied within the scope of sharing the technical idea.

[0061] In addition, in the drawings below, the first direction (DR1) refers to the horizontal direction of the display device (10), the second direction (DR2) refers to the vertical direction of the display device (10), and the third direction (DR3) refers to the thickness direction of the display device (10). In this case, “left,” “right,” “upper,” and “lower” indicate directions when the display device (10) is viewed from a plane. For example, “right” indicates one side of the first direction (DR1), “left” indicates the other side of the first direction (DR1), “upper” indicates one side of the second direction (DR2), and “lower” indicates the other side of the second direction (DR2). In addition, “upper” indicates one side of the third direction (DR3), and “lower” indicates the other side of the third direction (DR3).

[0062] The display device (10) according to one embodiment may have a square shape in a plan view, for example, a square shape. In addition, if the display device (10) is a television, it may have a rectangular shape with the long side positioned in the horizontal direction. However, the display device (10) is not limited thereto, and the long side may be positioned in the vertical direction, and may be installed so as to be rotatable so that the long side may be variably positioned in the horizontal or vertical direction. In addition, the display device (10) may have a circular or oval shape.

[0063] The display device (10) may include a display area (DPA) and a non-display area (NDA) surrounding the display area (DPA) along the periphery or edge of the display area (DPA). The display area (DPA) may be an active area where an image is displayed. The display area (DPA) may have a square shape in a plan view similar to the overall shape of the display device (10), but is not limited thereto.

[0064] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. For example, the plurality of pixels (PX) may be arranged along rows and columns of a matrix. The shape of each pixel (PX) may be a rectangle or a square in a plan view, but is not limited thereto, and may also be a rhombus shape with each side inclined with respect to one side direction of the display device (10). The plurality of pixels (PX) may include multi-color pixels (PX). For example, the plurality of pixels (PX) may include, but are not limited to, a first color pixel (PX) of red, a second color pixel (PX) of green, and a third color pixel (PX) of blue. Each color pixel (PX) may be a stripe type or a PenTile type. TM ) can be arranged alternately as types.

[0065] A non-display area (NDA) may be arranged around the display area (DPA). The non-display area (NDA) may completely or partially surround the display area (DPA). The display area (DPA) has a square shape, and the non-display area (NDA) may be arranged adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form a bezel of the display device (10).

[0066] A driving circuit or driving element for driving the display area (DPA) may be arranged in the non-display area (NDA). In one embodiment, a pad portion may be provided on the display substrate of the display device (10) in the non-display area (NDA) adjacent to the first side (the lower side in FIG. 1) of the display device (10), and an external device (EXD) may be mounted on the pad electrode of the pad portion. Examples of the external device (EXD) may include a connection film, a printed circuit board, a driving chip (DIC), a connector, a wiring connection film, and the like. A scan driving unit (SDR), or the like, which is directly formed on the display substrate of the display device (10), may be arranged in the non-display area (NDA) adjacent to the second side (the left side in FIG. 1) of the display device (10).

[0067] FIG. 2 is a schematic layout diagram of circuit wirings of a display substrate of a display device according to one embodiment.

[0068] Referring to FIG. 2, a plurality of wires are arranged on a substrate. The plurality of wires may include a scan line (SCL), a sensing signal line (SSL), a data line (DTL), a reference voltage line (RVL), a first power line (ELVDL), and the like.

[0069] A scan line (SCL) and a sensing signal line (SSL) may extend in a first direction (DR1). The scan line (SCL) and the sensing signal line (SSL) may be connected to a scan driver (SDR). The scan driver (SDR) may include a driving circuit. The scan driver (SDR) may be disposed on one side of a non-display area (NDA) on a display substrate, but is not limited thereto, and may be disposed on both sides of the non-display area (NDA). The scan driver (SDR) is connected to a signal connection line (CWL), and at least one end of the signal connection line (CWL) may form a pad (WPD_CW) on the first non-display area (NDA) and / or the second non-display area (NDA) to be connected to an external device ('EXD' in FIG. 1).

[0070] The data line (DTL) and the reference voltage line (RVL) may extend in a second direction (DR2) intersecting the first direction (DR1). The first power line (ELVDL) may include a portion extending in the second direction (DR2). The first power line (ELVDL) may further include a portion extending in the first direction (DR1). The first power line (ELVDL) may have a mesh structure, but is not limited thereto.

[0071] A wiring pad (WPD) may be arranged at at least one end of a data line (DTL), a reference voltage line (RVL), and a first power line (ELVDL). Each wiring pad (WPD) may be arranged in a pad portion (PDA) of a non-display area (NDA). In one embodiment, a wiring pad (WPD_DT, hereinafter referred to as a 'data pad') of the data line (DTL), a wiring pad (WPD_RV, hereinafter referred to as a 'reference voltage pad') of the reference voltage line (RVL), and a wiring pad (WPD_ELVD, hereinafter referred to as a 'first power pad') of the first power line (ELVDL) may be arranged in a pad portion (PDA) of the non-display area (NDA). As another example, the data pad (WPD_DT), the reference voltage pad (WPD_RV), and the first power pad (WPD_ELVD) may be arranged in different non-display areas (NDAs). An external device ('EXD' in Fig. 1) can be mounted on the wiring pad (WPD) as described above. The external device (EXD) can be mounted on the wiring pad (WPD) using an anisotropic conductive film, ultrasonic bonding, etc.

[0072] Each pixel (PX) on the display substrate includes a pixel driving circuit. The above-described wirings may pass through each pixel (PX) or its surroundings to apply a driving signal to each pixel driving circuit. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may be variously modified. Hereinafter, the pixel driving circuit will be described using a 3T1C structure including three transistors and one capacitor as an example, but the present invention is not limited thereto and various other modified pixel (PX) structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure may be applied.

[0073] FIG. 3 is an equivalent circuit diagram of one pixel of a display device according to one embodiment.

[0074] Referring to FIG. 3, each pixel (PX) of a display device according to one embodiment includes, in addition to a light-emitting element (LE), three transistors (DTR, STR1, STR2) and one storage capacitor (CST).

[0075] The light-emitting element (LE) emits light according to the current supplied through the driving transistor (DTR). The light-emitting element (LE) can be implemented as an inorganic light-emitting diode, an organic light-emitting diode, a micro light-emitting diode, a nano light-emitting diode, etc.

[0076] A first electrode (i.e., an anode electrode) of a light emitting element (LE) may be connected to a source electrode of a driving transistor (DTR), and a second electrode (i.e., a cathode electrode) may be connected to a second power line (ELVSL) to which a low-potential voltage (a second power voltage) lower than a high-potential voltage (a first power voltage) of a first power line (ELVDL) is supplied.

[0077] The driving transistor (DTR) controls the current flowing from the first power line (ELVDL) to which the first power voltage is supplied to the light-emitting element (LE) according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor (DTR) may be connected to the first electrode of the first transistor (ST1), the source electrode may be connected to the first electrode of the light-emitting element (LE), and the drain electrode may be connected to the first power line (ELVDL) to which the first power voltage is applied.

[0078] The first transistor (STR1) is turned on by a scan signal of a scan line (SCL) to connect the data line (DTL) to the gate electrode of the driving transistor (DTR). The gate electrode of the first transistor (STR1) may be connected to the scan line (SL), the first electrode may be connected to the gate electrode of the driving transistor (DTR), and the second electrode may be connected to the data line (DTL).

[0079] The second transistor (STR2) is turned on by a sensing signal of the sensing signal line (SSL) to connect the initialization voltage line (VIL) to the source electrode of the driving transistor (DTR). The gate electrode of the second transistor (ST2) may be connected to the sensing signal line (SSL), the first electrode may be connected to the initialization voltage line (VIL), and the second electrode may be connected to the source electrode of the driving transistor (DTR).

[0080] In one embodiment, the first electrode of each of the first and second transistors (STR1, STR2) may be a source electrode and the second electrode may be a drain electrode, but the present invention is not limited thereto and vice versa.

[0081] A capacitor (CST) is formed between the gate electrode and the source electrode of the driving transistor (DTR). The storage capacitor (CST) stores the difference between the gate voltage and the source voltage of the driving transistor (DTR).

[0082] The driving transistor (DTR) and the first and second transistors (STR1, STR2) may be formed as thin film transistors. In addition, although FIG. 3 has been described with the focus on the driving transistor (DTR) and the first and second switching transistors (STR1, STR2) being N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the present invention is not limited thereto. That is, the driving transistor (DTR) and the first and second switching transistors (STR1, STR2) may be P-type MOSFETs, or some may be N-type MOSFETs and others may be P-type MOSFETs.

[0083] Fig. 4 is an equivalent circuit diagram of one pixel of a display device according to another embodiment.

[0084] Referring to FIG. 4, a first electrode of a light-emitting element (LE) is connected to a first electrode of a fourth transistor (STR4) and a second electrode of a sixth transistor (STR6), and a second electrode of the light-emitting element (LE) may be connected to a second power line (ELVSL). A parasitic capacitance (Cel) may be formed between the first electrode and the second electrode of the light-emitting element (LE).

[0085] Each pixel (PX) includes a driving transistor (DTR), switch elements, and a capacitor (CST). The switch elements include first to sixth transistors (STR1, STR2, STR3, STR4, STR5, STR6).

[0086] A driving transistor (DTR) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DTR) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0087] A capacitor (CST) is formed between the gate electrode of the driving transistor (DTR) and the first power line (ELVDL). One electrode of the capacitor (CST) may be connected to the gate electrode of the driving transistor (DTR), and the other electrode may be connected to the first power line (ELVDL).

[0088] When the first electrode of each of the first to sixth transistors (STR1, STR2, STR3, STR4, STR5, STR6) and the driving transistor (DTR) is a source electrode, the second electrode may be a drain electrode. Alternatively, when the first electrode of each of the first to sixth transistors (STR1, STR2, STR3, STR4, STR5, STR6) and the driving transistor (DTR) is a drain electrode, the second electrode may be a source electrode.

[0089] The active layer of each of the first to sixth transistors (STR1, STR2, STR3, STR4, STR5, STR6) and the driving transistor (DTR) may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the semiconductor layer of each of the first to sixth transistors (STR1, STR2, STR3, STR4, STR5, STR6) and the driving transistor (DTR) is formed of polysilicon, the process for forming it may be a low temperature polysilicon (LTPS) process.

[0090] In addition, in FIG. 4, the first to sixth transistors (STR1, STR2, STR3, STR4, STR5, STR6) and the driving transistor (DTR) are described as being formed of P-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but are not limited thereto and may be formed of N-type MOSFETs. For example, the first transistor (STR1) may be formed of a P-type MOSFET and may include a first-first transistor (ST1-1) and a first-second transistor (ST1-2) that are connected to each other. In addition, the third transistor (STR3) may be formed of a P-type MOSFET and may include a third-first transistor (ST3-1) and a third-second transistor (ST3-2) that are connected to each other.

[0091] The gate electrode of the second transistor (STR2) and the gate electrode of the first transistor (STR1) may be connected to a write scan line (GWL), and the gate electrode of the fourth transistor (STR4) may be connected to a control scan line (GCL). In addition, the gate electrode of the third transistor (STR3) may be connected to an initialization scan line (GIL). The gate electrodes of the fifth transistor (STR5) and the sixth transistor (STR6) may be connected to a light emitting line (EL). The first power voltage of the first power line (ELVDL), the second power voltage of the second power line (ELVSL), and the third power voltage of the third power line (VIL) may be set in consideration of the characteristics of the driving transistor (DTR), the characteristics of the light emitting element (LE), and the like.

[0092] For example, a first transistor (STR1) may be connected between a second electrode and a gate electrode of a driving transistor (DTR). A second transistor (STR2) may be connected between a first electrode of the driving transistor (DTR) and a data line (DTL). A third transistor (STR3) may be connected between a gate electrode of the driving transistor (DTR) and a third power line (VIL). A fourth transistor (STR4) may be connected between a light-emitting element (LE) and a third power line (VIL). A fifth transistor (STR5) may be connected between a first electrode of the driving transistor (DTR) and a first power line (ELVDL). A sixth transistor (STR6) may be connected between a light-emitting element (LE) and a second electrode of the driving transistor (DTR).

[0093] Fig. 5 is an equivalent circuit diagram of one pixel of a display device according to another embodiment.

[0094] The embodiment of FIG. 5 differs from the embodiment of FIG. 4 in that the driving transistor (DTR), the second transistor (STR2), the fourth transistor (STR4), the fifth transistor (STR5), and the sixth transistor (STR6) are formed as P-type MOSFETs, and the first transistor (STR1) and the third transistor (STR3) are formed as N-type MOSFETs.

[0095] Referring to FIG. 5, the active layers of each of the driving transistor (DTR), the second transistor (STR2), the fourth transistor (STR4), the fifth transistor (STR5), and the sixth transistor (STR6), which are formed as P-type MOSFETs, may be formed of polysilicon, and the active layers of each of the first transistor (STR1) and the third transistor (STR3), which are formed as N-type MOSFETs, may be formed of oxide semiconductors.

[0096] In FIG. 5, there is a difference from the embodiment of FIG. 4 in that the gate electrode of the second transistor (STR2) and the gate electrode of the fourth transistor (STR4) are connected to the write scan line (GWL), and the gate electrode of the first transistor (STR1) is connected to the control scan line (GCL). In addition, in FIG. 5, since the first transistor (STR1) and the third transistor (STR3) are formed as N-type MOSFETs, a scan signal of a gate high voltage can be applied to the control scan line (GCL) and the initialization scan line (GIL). In contrast, since the second transistor (STR2), the fourth transistor (STR4), the fifth transistor (STR5), and the sixth transistor (STR6) are formed as P-type MOSFETs, a scan signal of a gate low voltage can be applied to the write scan line (GWL) and the light emitting line (EL).

[0097] Meanwhile, it should be noted that the equivalent circuit diagram of a pixel according to an embodiment of the present specification is not limited to that illustrated in FIGS. 3 to 5. The equivalent circuit diagram of a pixel according to an embodiment of the present specification may be formed with other known circuit structures that can be adopted by those skilled in the art in addition to the embodiments illustrated in FIGS. 3 to 5.

[0098] Fig. 6 is a cross-sectional view schematically illustrating a display device according to one embodiment. Fig. 7 is a plan view illustrating an example of light-emitting areas of a display device according to one embodiment.

[0099] Referring to FIG. 6, the display device (10) may include a display substrate (100) and a wavelength control unit (200) and a color filter layer (CFL) disposed on the display substrate (100).

[0100] The display substrate (100) may include a substrate (110) and a light emitting element portion (LEP) disposed on the substrate (110). The substrate (110) may be an insulating substrate. The substrate (110) may include a transparent material. For example, the substrate (110) may include a transparent insulating material such as glass, quartz, or the like. The substrate (110) may be a rigid substrate. However, the substrate (110) is not limited thereto and may include a plastic such as polyimide, or may have a flexible characteristic that can be bent, folded, or rolled. A plurality of light emitting areas (EA1, EA2, EA3) and a non-light emitting area (NEA) may be defined on the substrate (110).

[0101] Switching elements (T1, T2, T3) may be positioned on the substrate (110). In one embodiment, the first switching element (T1) may be positioned in the first light-emitting area (EA1) of the substrate (110), the second switching element (T2) may be positioned in the second light-emitting area (EA2), and the third switching element (T3) may be positioned in the third light-emitting area (LA3). However, this is not limited thereto, and in another embodiment, at least one of the first switching element (T1), the second switching element (T2), and the third switching element (T3) may be positioned in the non-light-emitting area (NEA).

[0102] In one embodiment, the first switching element (T1), the second switching element (T2), and the third switching element (T3) may each be a thin film transistor including amorphous silicon, polysilicon, or an oxide semiconductor. In addition, although not shown in the drawing, a plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) for transmitting signals to each switching element may be further positioned on the substrate (110).

[0103] Each switching element (T1, T2, T3) may include a semiconductor layer (65), a gate electrode (75), a source electrode (85a), and a drain electrode (85b). Specifically, a buffer layer (60) may be disposed on a substrate (110). The buffer layer (60) may be disposed to cover the entire surface of the substrate (110). The buffer layer (60) may include silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed of a single layer or double layer thereof.

[0104] A semiconductor layer (65) may be disposed on the buffer layer (60). The semiconductor layer (65) may form a channel of each switching element (T1, T2, T3). The semiconductor layer (65) may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the oxide semiconductor may include a binary compound (ABx), a ternary compound (ABxCy), or a quaternary compound (ABxCyDz) containing, for example, indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), or the like. In one embodiment, the semiconductor layer (65) may include IGZO (Indium tin zinc oxide).

[0105] A gate insulating layer (70) may be disposed on the semiconductor layer (65) and the buffer layer (60). The gate insulating layer (70) may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer (70) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. In one embodiment, the gate insulating layer (70) may be formed by including silicon oxide.

[0106] A gate electrode (75) may be disposed on the gate insulating layer (70). The gate electrode (75) may be disposed to overlap the semiconductor layer (65) in the third direction (DR3). The gate electrode (75) may include a conductive material. The gate electrode (75) may include a metal oxide such as ITO, IZO, ITZO, In2O3, or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). For example, the gate electrode (75) may be formed of a Cu / Ti bilayer in which an upper layer of copper is laminated on a lower layer of titanium, but is not limited thereto.

[0107] A first interlayer insulating layer (80) and a second interlayer insulating layer (82) may be disposed on the gate electrode (75) and the gate insulating layer (70). The first interlayer insulating layer (80) may be disposed directly on the gate electrode (75) and the gate insulating layer (70), and the second interlayer insulating layer (82) may be disposed directly on the first interlayer insulating layer (80). The first interlayer insulating layer (80) and the second interlayer insulating layer (82) may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, or the like. However, the present invention is not limited thereto, and the second interlayer insulating layer (82) may also include an organic insulating material capable of flattening a lower step.

[0108] A source electrode (85a) and a drain electrode (85b) may be disposed on the second interlayer insulating layer (82). The source electrode (85a) and the drain electrode (85b) may contact the semiconductor layer (65) through contact holes penetrating the first interlayer insulating layer (80), the second interlayer insulating layer (82), and the gate insulating layer (70), respectively. The source electrode (85a) and the drain electrode (85b) may include a metal oxide such as ITO, IZO, ITZO, In2O3, or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). For example, the source electrode (85a) and the drain electrode (85b) may be formed of a Cu / Ti bilayer in which an upper layer of copper is laminated on a lower layer of titanium, but is not limited thereto.

[0109] A first planarization layer (120) may be disposed on the first switching element (T1), the second switching element (T2), and the third switching element (T3). The first planarization layer (120) may include an organic material. For example, the first planarization layer (120) may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, or the like. In one embodiment, the first planarization layer (120) may include a positive photosensitive material or a negative photosensitive material.

[0110] A pixel connection electrode (125) may be disposed on the first planarization layer (120). The pixel connection electrode (125) is disposed to correspond to each of the first switching element (T1), the second switching element (T2), and the third switching element (T3), and may be electrically connected thereto. The pixel connection electrode (125) may connect the pixel electrodes (PE1, PE2, PE3) described below to the switching elements (T1, T2, T3) described above. The pixel connection electrode (125) may contact the switching elements (T1, T2, T3) through a contact hole penetrating the first planarization layer (120).

[0111] A second planarization layer (130) may be disposed on the first planarization layer (120) and the pixel connection electrode (125). The second planarization layer (130) planarizes the lower step and may include the same material as the first planarization layer (120) described above.

[0112] A light emitting element portion (LEP) may be arranged on the second planarization layer (130). The light emitting element portion (LEP) may include a plurality of pixel electrodes (PE1, PE2, PE3), a plurality of light emitting elements (LE), and a common electrode (CE). In addition, the light emitting element portion (LEP) may further include a pixel defining layer (PDL) and an organic layer (140) that define each light emitting area (EA1, EA2, EA3).

[0113] The plurality of pixel electrodes (PE1, PE2, PE3) may include a first pixel electrode (PE1), a second pixel electrode (PE2), and a third pixel electrode (PE3). The first pixel electrode (PE1), the second pixel electrode (PE2), and the third pixel electrode (PE3) may function as a first electrode of the light emitting element (LE) and may be an anode electrode or a cathode electrode. The first pixel electrode (PE1) may be positioned in the first light emitting area (EA1), the second pixel electrode (PE2) may be positioned in the second light emitting area (EA2), and the third pixel electrode (PE3) may be positioned in the third light emitting area (EA3). In an exemplary embodiment, the first pixel electrode (PE1) may completely overlap the first light emitting area (EA1), the second pixel electrode (PE2) may completely overlap the second light emitting area (EA2), and the third pixel electrode (PE3) may completely overlap the third light emitting area (EA3).

[0114] Each pixel electrode (PE1, PE2, PE3) is directly connected to a pixel connection electrode (125) through a contact hole penetrating the second planarization layer (130), and can be electrically connected to each switching element (T1, T2, T3) through the pixel connection electrode (125). The first pixel electrode (PE1), the second pixel electrode (PE2), and the third pixel electrode (PE3) may include a metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. In addition, the first pixel electrode (PE1), the second pixel electrode (PE2), and the third pixel electrode (PE3) may have a multilayer structure in which two or more metal layers are stacked. For example, the first pixel electrode (PE1), the second pixel electrode (PE2), and the third pixel electrode (PE3) may have a two-layer structure in which a copper layer is laminated on a titanium layer, but is not limited thereto.

[0115] A plurality of light emitting elements (LE) can be arranged on each of the first pixel electrode (PE1), the second pixel electrode (PE2), and the third pixel electrode (PE3).

[0116] As illustrated in FIGS. 6 and 7, the light emitting elements (LEs) may be arranged in each of the first light emitting area (EA1), the second light emitting area (EA2), and the third light emitting area (EA3). The light emitting elements (LEs) may be vertical light emitting diode elements that extend in a third direction (DR3). That is, the length of the light emitting elements (LEs) in the third direction (DR3) may be longer than the length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction (DR1) or the length in the second direction (DR2). A more detailed description of the light emitting elements (LEs) will be described later.

[0117] An organic layer (140) may be disposed on a plurality of pixel electrodes (PE1, PE2, PE3) and a pixel defining layer (PDL). The organic layer (140) may flatten a lower step so that a common electrode (CE) described later may be formed. The organic layer (140) may be formed to a predetermined height so that at least a portion of the plurality of light-emitting elements (LE) may protrude above the organic layer (140). That is, the height of the organic layer (140) based on the upper surface of the first pixel electrode (PE1) may be smaller than the height of the light-emitting elements (LE).

[0118] The organic layer (140) may include an organic material to level the lower step. For example, the organic layer (140) may include a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0119] A common electrode (CE) may be disposed on the organic layer (140) and a plurality of light-emitting elements (LE). Specifically, the common electrode (CE) is disposed on one surface of the substrate (110) on which the light-emitting elements (LE) are formed, and may be disposed throughout the display area (DPA). The common electrode (CE) is disposed to overlap each of the light-emitting areas (EA1, EA2, EA3) in the display area (DPA), and may be formed to be thin so that light can be emitted.

[0120] The common electrode (CE) may be directly disposed on the top and side surfaces of the plurality of light-emitting elements (LE). For example, the common electrode (CE) may be in contact with a contact electrode (CTE), which is a side surface of the light-emitting element (LE). The common electrode (CE) may be a common layer that covers the plurality of light-emitting elements (LE) and is disposed to commonly connect the plurality of light-emitting elements (LE).

[0121] The common electrode (CE) may include a material having low resistance since it is arranged on the entire substrate (110) and a common voltage is applied thereto. In addition, the common electrode (CE) may be formed to have a thin thickness so as to easily transmit light. For example, the common electrode (CE) may include a metal material having low resistance such as aluminum (Al), silver (Ag), copper (Cu), or a metal oxide such as ITO, IZO, or ITZO. The thickness of the common electrode (CE) may be approximately 10 Å to 200 Å, but is not limited thereto.

[0122] The above-described light emitting elements (LE) can receive a pixel voltage or an anode voltage from each pixel electrode (PE1, PE2, PE3) and can receive a common voltage through a common electrode (CE). The light emitting elements (LE) can emit light with a predetermined brightness depending on the voltage difference between the pixel voltage and the common voltage. In one embodiment, by arranging a plurality of light emitting elements (LE), i.e., inorganic light emitting diodes, on the pixel electrodes (PE1, PE2, PE3), the disadvantage of organic light emitting diodes being vulnerable to external moisture or oxygen can be eliminated, and the lifespan and reliability can be improved.

[0123] As illustrated in FIG. 7, light-emitting elements (LEs) may be arranged on each pixel electrode (PE1, PE2, PE3). The light-emitting elements (LEs) may be arranged in a regular manner according to a certain rule. For example, the light-emitting elements (LEs) may be arranged at regular intervals from each other. However, this is not limited thereto, and the light-emitting elements (LEs) may also be arranged irregularly.

[0124] Each light emitting element (LE) may generally be disposed on each pixel electrode (PE1, PE2, PE3). However, this is not limited thereto, and some light emitting elements (LE) may be disposed between each pixel electrode (PE1, PE2, PE3), may be disposed partially over one pixel electrode, or may not be disposed on any pixel electrode.

[0125] Meanwhile, a first capping layer (CPL1) may be disposed on a substrate (110) on which a common electrode (CE) is disposed. The first capping layer (CPL1) may be disposed directly on the common electrode (CE). The first capping layer (CPL1) covers components disposed thereunder, for example, light emitting elements (LEs) and the common electrode (CE), thereby protecting them from moisture or foreign substances.

[0126] The first capping layer (CPL1) may include an inorganic material. For example, the first capping layer (CPL1) may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. Meanwhile, although the drawing illustrates that the first capping layer (CPL1) is formed as a single layer, it is not limited thereto. For example, the first capping layer (CPL1) may be formed as a multilayer in which inorganic layers including at least one of the materials exemplified as materials that the first capping layer (CPL1) may include are alternately laminated. The thickness of the first capping layer (CPL1) may range from 0.05 μm to 2 μm, but is not limited thereto.

[0127] Meanwhile, a wavelength control unit (200) may be placed on the light emitting element unit (LEP). The wavelength control unit (200) may include a first wavelength conversion layer (WCL1), a second wavelength conversion layer (WCL2), and a light transmitting layer (TPL). In addition, the wavelength control unit (200) may further include a bank layer (BNL).

[0128] The bank layer (BNL) is disposed on the first capping layer (CPL1) and can define a plurality of light-emitting areas (EA1, EA2, EA3). The bank layer (BNL) is disposed to extend in the first direction (DR1) and the second direction (DR2) and can be formed in a grid-like pattern over the entire display area (DPA). In addition, the bank layer (BNL) does not overlap with the plurality of light-emitting areas (EA1, EA2, EA3) and can overlap with the non-light-emitting area (NEA).

[0129] The bank layer (BNL) may serve to provide a space for forming the first wavelength conversion layer (WCL1), the second wavelength conversion layer (WCL2), and the light-transmitting layer (TPL). For this purpose, the bank layer (BNL) may be formed in a range of 1 μm to 10 μm. The bank layer (BNL) may include an organic insulating material so as to be formed with a thick thickness. The organic insulating material may include, for example, an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0130] In one embodiment, the bank layer (BNL) may further include a light-blocking material and may include a dye or pigment having light-blocking properties. For example, the bank layer (BNL) may be a black matrix. External light incident from outside the display device (10) may cause a problem of distorting the color reproducibility of the wavelength control unit (200). According to the present embodiment, by arranging the bank layer (BNL) including a light-blocking material in the wavelength control unit (200), color distortion due to reflection of external light can be reduced. In addition, the bank layer (BNL) including a light-blocking material can prevent color mixing caused by light penetrating between adjacent light-emitting regions, thereby further improving the color reproducibility.

[0131] A first wavelength conversion layer (WCL1), a second wavelength conversion layer (WCL2), and a light-transmitting layer (TPL) may be disposed on light-emitting areas (EA1, EA2, EA3). The first wavelength conversion layer (WCL1) and the second wavelength conversion layer (WCL2) may convert or shift a peak wavelength of incident light into light of another specific peak wavelength and emit the light. The first wavelength conversion layer (WCL1) may convert blue light emitted from the light-emitting element (LE) into red light, and the second wavelength conversion layer (WCL2) may convert blue light into green light. The light-transmitting layer (TP) may transmit blue light as it is.

[0132] The first wavelength conversion layer (WCL1), the second wavelength conversion layer (WCL2), and the light-transmitting layer (TPL) can be arranged in each light-emitting area (EA1, EA2, EA3) partitioned by the bank layer (BNL), and can be arranged spaced apart from each other. That is, the first wavelength conversion layer (WCL1), the second wavelength conversion layer (WCL2), and the light-transmitting layer (TPL) can be formed as a dot-shaped island pattern spaced apart from each other.

[0133] The first wavelength conversion layer (WCL1) may be arranged to overlap the first light-emitting area (EA1). The first wavelength conversion layer (WCL1) may convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. In one embodiment, the first wavelength conversion layer (WCL1) may convert blue light emitted from the light-emitting element (LE) of the first light-emitting area (EA1) into red light having a single peak wavelength in the range of about 610 nm to about 650 nm and emit the converted light.

[0134] The first wavelength conversion layer (WCL1) may include a first base resin (BRS1), first wavelength conversion particles (WCP1), and a scatterer (SCP). The first base resin (BRS1) may include a light-transmitting organic material. For example, the first base resin (BRS1) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0135] The first wavelength conversion particle (WCP1) can convert blue light incident from the light-emitting element (LE) into red light. For example, the first wavelength conversion particle (WCP1) can convert light in the blue wavelength band into light in the red wavelength band. The first wavelength conversion particle (WCP1) may be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot may be a particulate material that emits a specific color when electrons transition from the conduction band to the valence band.

[0136] The quantum dot may be a semiconductor nanocrystal material. The quantum dot may have a specific band gap depending on its composition and size, and may absorb light and then emit light with a unique wavelength. Examples of the semiconductor nanocrystal of the quantum dot include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or combinations thereof.

[0137] The II-VI group compound is a binary compound selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; a ternary compound selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and a group consisting of four-element compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0138] The group III-V compound may be selected from the group consisting of binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof.

[0139] The group IV-VI compound may be selected from the group consisting of a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. The group IV element may be selected from the group consisting of Si, Ge, and mixtures thereof. The group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0140] Here, binary, ternary, or quaternary compounds may exist within the particle at a uniform concentration, or may exist within the same particle with partially different concentration distributions. Furthermore, one quantum dot may have a core / shell structure surrounding another quantum dot. The interface between the core and shell may have a concentration gradient, with the concentration of the element in the shell decreasing toward the center.

[0141] In one embodiment, the quantum dot may have a core-shell structure comprising a core comprising the aforementioned nanocrystals and a shell surrounding the core. The shell of the quantum dot may function as a protective layer to maintain semiconductor properties by preventing chemical modification of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or a multilayer. Examples of the shell of the quantum dot include a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0142] For example, the oxide of the metal or non-metal may be a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, but the present invention is not limited thereto.

[0143] In addition, the semiconductor compound may include, but is not limited to, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc.

[0144] A scatterer (SCP) can scatter light from a light-emitting element (LE) in a random direction. The scatterer (SCP) has a different refractive index from the first base resin (BRS1) and can form an optical interface with the first base resin (BRS1). For example, the scatterer (SCP) can be a light-scattering particle. The scatterer (SCP) is not particularly limited as long as it is a material that can scatter at least a portion of transmitted light, but can be, for example, a metal oxide particle or an organic particle. Examples of the metal oxide include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the material of the organic particle include an acrylic resin or a urethane resin. The scatterer (SCP) can scatter light in a random direction regardless of the incident direction of incident light without substantially converting the wavelength of the light.

[0145] The second wavelength conversion layer (WCL2) can be arranged to overlap the second light-emitting area (EA2). The second wavelength conversion layer (WCL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. In one embodiment, the second wavelength conversion layer (WCL2) can convert blue light emitted from the light-emitting element (LE) of the second light-emitting area (EA2) into green light having a peak wavelength in the range of about 510 nm to 550 nm and emit the converted green light.

[0146] The second wavelength conversion layer (WCL2) may include a second base resin (BRS2) and second wavelength conversion particles (WCP2) and scatterers (SCP) dispersed within the second base resin (BRS2).

[0147] The second base resin (BRS2) may be made of a material having high light transmittance, and may be made of the same material as the first base resin (BRS1) or may include at least one of the materials exemplified as their constituent materials.

[0148] The second wavelength conversion particle (WCP2) can convert or shift the peak wavelength of incident light to another specific peak wavelength. In one embodiment, the second wavelength conversion particle (WCP2) can convert and emit blue light provided from the light emitting element (LE) into green light having a peak wavelength in a range of about 510 nm to 550 nm. Examples of the second wavelength conversion particle (WCP2) include quantum dots, quantum rods, or phosphors. A more specific description of the second wavelength conversion particle (WCP2) is omitted as it is substantially the same as or similar to that described above in the description of the first wavelength conversion particle (WCP1).

[0149] The light-transmitting layer (TPL) may be arranged to overlap with the third light-emitting area (EA3). The light-transmitting layer (TPL) may transmit incident light. The light-transmitting layer (TPL) may transmit blue light emitted from the light-emitting element (LE) arranged in the third light-emitting area (EA3) as is. The light-transmitting layer (TPL) may include a third base resin (BRS3) and a scatterer (SCP) dispersed in the third base resin (BRS3). The third base resin (BRS3) is substantially the same as or similar to the first base resin (BRS3) described above, and thus, a description thereof will be omitted.

[0150] The light transmitted through the wavelength control unit (200) described above can transmit through the color filter layer (CFL) described later to implement full color.

[0151] The wavelength control unit (200) may further include a second capping layer (CPL2). The second capping layer (CPL2) covers the first wavelength conversion layer (WCL1), the second wavelength conversion layer (WCL2), the light-transmitting layer (TPL), and the bank layer (BNL) disposed thereunder, thereby protecting them from moisture or foreign substances. The second capping layer (CPL2) may include an inorganic material, and may include a material substantially the same as or similar to the first capping layer (CPL1) described above.

[0152] Meanwhile, a low refractive index layer (LRL) and a third capping layer (CPL3) may be disposed on the second capping layer (CPL2).

[0153] A low-refractive-index layer (LRL) may be disposed across each of the light-emitting regions (EA1, EA2, and EA3) and the non-light-emitting region (NEA). The low-refractive-index layer (LRL) may have a low refractive index. For example, the low-refractive-index layer (LRL) may have a refractive index of about 1.1 or more and about 1.4 or less.

[0154] The low refractive index layer (LRL) can reflect some of the light emitted from the bottom toward the top (third direction) back toward the lower substrate (110). That is, the low refractive index layer (LRL) can improve light output efficiency by recycling at least some of the light emitted in the upward direction, and consequently improve the light efficiency of the display device (10). The low refractive index layer (LRL) includes an organic material and may include particles dispersed therein. The particles may be, for example, hollow silica particles.

[0155] A third capping layer (CPL3) may be disposed on the low refractive index layer (LRL). The third capping layer (CPL3) can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive index layer (LRL).

[0156] A color filter layer (CFL) may be disposed on the third capping layer (CPL3). The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3).

[0157] A first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) may be disposed on a third capping layer (CPL3). The first color filter (CF1) may be disposed in the first light-emitting area (EA1), the second color filter (CF2) may be disposed in the second light-emitting area (EA2), and the third color filter (CF3) may be disposed in the third light-emitting area (EA2).

[0158] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may include a colorant such as a dye or pigment that absorbs wavelengths other than the corresponding color wavelengths. The first color filter (CF1) may selectively transmit red light and block or absorb blue light and green light. The second color filter (CF2) may selectively transmit green light and block or absorb blue light and red light. The third color filter (CF3) may selectively transmit blue light and block or absorb red light and green light. For example, the first color filter (CF1) may be a red color filter, the second color filter (CF2) may be a green color filter, and the third color filter (CF3) may be a blue color filter.

[0159] In one embodiment, light incident on the first color filter (CF1) may be light converted into red light in the first wavelength conversion layer (WCL1), light incident on the second color filter (CF2) may be light converted into green light in the second wavelength conversion layer (WCL2), and light incident on the third color filter (CF3) may be blue light transmitted through the light-transmitting layer (TPL). As a result, red light transmitted through the first color filter (CF1), green light transmitted through the second color filter (CF2), and blue light transmitted through the third color filter (CF3) may be emitted onto the substrate (110) to implement full color.

[0160] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can absorb a portion of the light entering from the outside of the display device (10) to reduce light reflected by external light. Therefore, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can prevent color distortion due to reflection of external light.

[0161] Additionally, a first color filter (CF1) is disposed in the non-emissive area (NEA), and at least one of a second color filter (CF2) and a third color filter (CF3) may be disposed in an overlapping manner. That is, a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) may be disposed in the non-emissive area (NEA).

[0162] Accordingly, not only can light emission from the display device be blocked in the non-emission area (NEA), but also external light reflection can be suppressed. Each color filter (CF1, CF2, CF3) blocks the emission of light of a color other than the corresponding color of each emission area (EA1, EA2, EA3), and thus, red, green, and blue light can all be blocked in the non-emission area (NEA). However, the present invention is not limited thereto, and an absorption member including a light absorbing material that absorbs a visible light wavelength band may be disposed in the non-emission area (NEA).

[0163] An overcoat layer (OC) may be disposed on the color filter layer (CFL). The overcoat layer (OC) may be disposed directly on the color filter layer (CFL). The overcoat layer (OC) may be disposed over the entire display area (DPA) and may have a flat surface. The overcoat layer (OC) may flatten the step formed by the underlying color filter layer (CFL). The overcoat layer (OC) may include a light-transmitting organic material.

[0164] Fig. 8 is a schematic diagram illustrating a light-emitting element according to one embodiment. Fig. 9 is a perspective view illustrating a contact electrode of a light-emitting element and a contact region of a second semiconductor layer according to one embodiment. Fig. 10 is an enlarged view illustrating a light-emitting element portion of a display device according to one embodiment.

[0165] Referring to FIGS. 8 to 10, the light emitting element (LE) is a particle-type element and may have a rod or cylindrical shape with a predetermined aspect ratio. The light emitting element (LE) may have a size in the nanometer scale (1 nm or more and less than 1 μm) or micrometer scale (1 μm or more and less than 1 mm). In one embodiment, the light emitting element (LE) may have both a diameter and a length in the nanometer scale, or both in the micrometer scale. In some other embodiments, the diameter of the light emitting element (LE) may have a nanometer scale, while the length of the light emitting element (LE) may have a micrometer scale. In some embodiments, some of the light emitting elements (LE) may have a nanometer scale diameter and / or length, while other some of the light emitting elements (LE) may have a micrometer scale diameter and / or length.

[0166] In one embodiment, the light-emitting element (LE) may be an inorganic light-emitting diode. Specifically, the light-emitting element (LE) may include a semiconductor layer doped with impurities of any conductive type (e.g., p-type or n-type). The semiconductor layer may receive an electrical signal applied from an external power source and emit the signal as light of a specific wavelength.

[0167] A light emitting element (LE) according to one embodiment may include a first semiconductor layer (SEM1), a second semiconductor layer (SEM2), a light emitting layer (MQW), a third semiconductor layer (SEM2), a device electrode layer (ELT), and a connection electrode (BON) that are sequentially stacked in the length direction. In addition, the light emitting element (LE) may further include a first insulating film (INS1) that surrounds outer surfaces of the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2), a contact electrode (CTE) that surrounds outer surfaces of the first insulating film (INS1) and the second semiconductor layer (SEM2), and a second insulating film (INS2) that surrounds outer surfaces of the contact electrode (CTE), the second semiconductor layer (SEM2), the light emitting layer (MQW), the third semiconductor layer (SEM2), the device electrode layer (ELT), and the connection electrode (BON).

[0168] The first semiconductor layer (SEM1) may include an undoped semiconductor and may be an n-type or p-type undoped material. The first semiconductor layer (SEM1) may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (SEM1) may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto. The length of the first semiconductor layer (SEM1) may range from 0.1 μm to 3 μm, but is not limited thereto.

[0169] The second semiconductor layer (SEM2) may be an n-type semiconductor. When the light emitting element (LE) emits light in the blue wavelength range, the second semiconductor layer (SEM2) may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it may be at least one of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer (SEM2) may be doped with an n-type dopant, and the n-type dopant may be Si, Ge, Sn, Se, or the like. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si. The length of the second semiconductor layer (SEM2) may be in the range of 1.5 μm to 5 μm, but is not limited thereto.

[0170] The light-emitting layer (MQW) may be disposed on the second semiconductor layer (SEM2). The light-emitting layer (MQW) may emit light by the combination of electron-hole pairs in response to an electric signal applied through the second semiconductor layer (SEM2). The light-emitting layer (MQW) may emit light in a blue wavelength band having a center wavelength band in a range of 450 nm to 495 nm.

[0171] The light-emitting layer (MQW) may include a material having a single or multiple quantum well structure. When the light-emitting layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately laminated. In this case, the well layers may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layers may be approximately 1 to 4 nm, and the thickness of the barrier layer may be 3 to 10 nm.

[0172] Alternatively, the light-emitting layer (MQW) may have a structure in which semiconductor materials having a large band gap energy and semiconductor materials having a small band gap energy are alternately laminated, and may include different group III to group V semiconductor materials depending on the wavelength of the light emitted. The light emitted by the light-emitting layer (MQW) is not limited to blue light, and may also emit light in a green wavelength band or a red wavelength band, depending on the case. In an exemplary embodiment, when indium is included among the semiconductor materials included in the light-emitting layer (MQW), the color of the emitted light may vary depending on the content of indium.

[0173] The third semiconductor layer (SEM3) may be disposed on the light-emitting layer (MQW). The third semiconductor layer (SEM3) may be a p-type semiconductor and may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it may be at least one of p-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The third semiconductor layer (SEM3) may be doped with a p-type dopant, and the p-type dopant may be Mg, Zn, Ca, Ba, or the like. For example, the third semiconductor layer (SEM3) may be p-GaN doped with p-type Mg. The thickness of the third semiconductor layer (SEM3) may range from 30 nm to 200 nm, but is not limited thereto.

[0174] The element electrode layer (ELT) may be disposed on the third semiconductor layer (SEM3). The element electrode layer (ELT) may be an Ohmic connection electrode. However, the present invention is not limited thereto, and may also be a Schottky connection electrode. The light-emitting element (LE) may include at least one element electrode layer (ELT). Although FIG. 8 illustrates that the light-emitting element (LE) includes one element electrode layer (ELT), the present invention is not limited thereto, and may include a plurality of element electrode layers (ELT).

[0175] The element electrode layer (ELT) may include a conductive metal. For example, the element electrode layer (ELT) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin-zinc oxide (ITZO). Additionally, the element electrode layer (ELT) may include a semiconductor material doped as n-type or p-type.

[0176] The connecting electrode (BON) may serve to transmit a light emitting signal from the first pixel electrode (PE1) to the light emitting element (LE). The connecting electrode (BON) may be arranged at the top of the light emitting element (LE). The connecting electrode (BON) may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connecting electrode (BON) may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0177] The first insulating film (INS1) may be arranged to surround the outer surfaces of the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) described above. Here, the outer surface may be an outer circumference, an outer side, or a side surface. For example, the first insulating film (INS1) may be arranged to surround at least the outer surface of the first semiconductor layer (SEM1), and may extend in one direction in which the light emitting element (LE) extends. The first insulating film (INS1) surrounds the first semiconductor layer (SEM1) so that the contact electrode (CTE) does not come into contact with it. The first insulating film (INS1) is formed to surround the side surfaces of the above-described members, and may be arranged to surround the side surface of a lower portion of the second semiconductor layer (SEM2). The first insulating film (INS1) is arranged to surround a portion of the side surface of the second semiconductor layer (SEM2), so that the contact electrode (CTE) comes into contact with the outer surface of the second semiconductor layer (SEM2).

[0178] The first insulating film (INS1) may include materials having insulating properties, such as oxides, fluorides, nitrides, organic-hybrid materials, etc. For example, the first insulating film (INS1) may include at least one or more of oxides such as Al2O3, HfO2, SiO2, TiO2, SrTiO3, Ta2O5, Gd2O3, ZrO2, Ga2O3, V2O5, Co3O4, ZnO, ZnO:Al, ZnO:B, In2O3:H, WO3, MoO3, Nb2O5, NiO, MgO, RuO2, etc.; fluorides such as MgF2, AlF3, etc.; nitrides such as TiN, TaN, Si3N4, AlN, GaN, WN, HfN, NbN, GdN, VN, ZrN, etc.; and organic-hybrid materials such as Alucone.

[0179] The thickness of the first insulating film (INS1) may range from 0.5 nm to 1.0 μm, but is not limited thereto. Preferably, the thickness of the first insulating film (INS1) may range from 10 nm to 30 nm.

[0180] The contact electrode (CTE) may be arranged to surround the outer surfaces of the first insulating film (INS1) and the second semiconductor layer (SEM2). For example, the contact electrode (CTE) may be arranged to surround at least the outer surface of the first insulating film (INS1) and to contact a portion of the outer surface of the second semiconductor layer (SEM2). The contact electrode (CTE) may extend from the lower end of the light-emitting element (LE) in one direction in which the light-emitting element (LE) extends. The contact electrode (CTE) may be spaced apart from the first semiconductor layer (SEM1) by the first insulating film (INS1) and may not be in contact with the first semiconductor layer (SEM1). The contact electrode (CTE) may be arranged to contact the second semiconductor layer (SEM2) and may serve to transmit a low-potential voltage applied from the common electrode (CE) to the light-emitting element (LE).

[0181] The contact electrode (CTE) may include a conductive metal. For example, the contact electrode (CTE) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin-zinc oxide (ITZO).

[0182] In one embodiment, the contact electrode (CTE) may contact a portion of a lower end of the light emitting element (LE). The light emitting element (LE) may have a contact area (CAR) in which the contact electrode (CTE2) and the second semiconductor layer (SEM2) are in contact with each other. The contact area (CAR) may be disposed in a portion of the second semiconductor layer (SEM2). For example, the contact area (CAR) may be disposed in a region ranging from 1% to 50% of the length of the second semiconductor layer (SEM2) from the interface between the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). However, the present invention is not limited thereto, and the contact area (CAR) may be disposed in a region ranging from 1% to 90% of the length of the second semiconductor layer (SEM2) from the interface between the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). In addition, the contact area (CAR) may be disposed in the entire region of the second semiconductor layer (SEM2).

[0183] The area of ​​the contact area (CAR) can be adjusted in consideration of the contact resistance between the contact electrode (CTE) and the second semiconductor layer (SEM2). For example, the area of ​​the contact area (CAR) can be in the range of 10 to 50% of the total area of ​​the outer surface of the second semiconductor layer (SEM2). However, the present invention is not limited thereto, and the area of ​​the contact area (CAR) can be in the range of 1 to 90% of the total area of ​​the outer surface of the second semiconductor layer (SEM2). In addition, the area of ​​the contact area (CAR) can be the same as the total area of ​​the outer surface of the second semiconductor layer (SEM2).

[0184] The second insulating film (INS2) may be arranged to surround the outer surfaces of the second semiconductor layer (SEM2), the light-emitting layer (MQW), the first semiconductor layer (SEM1), the element electrode layer (ELT), the connection electrode (BON), and the contact electrode (CTE) described above. For example, the second insulating film (INS2) may be arranged to surround at least the outer surface of the light-emitting layer (MQW), and may extend in one direction in which the light-emitting element (LE) extends. The second insulating film (INS2) may perform a function of insulating and protecting the second semiconductor layer (SEM2), the light-emitting layer (MQW), the first semiconductor layer (SEM1), the element electrode layer (ELT), the connection electrode (BON), and the contact electrode (CTE). The second insulating film (INS2) may be formed to surround side surfaces of the above-described members, but may be formed such that both longitudinal ends of the light-emitting element (LE) are exposed. For example, the second insulating film (INS2) may expose a portion of the connection electrode (BON) disposed at the upper end of the light emitting element (LE) and may expose a portion of the first semiconductor layer (SEM1), the first insulating film (INS1), and the contact electrode (CTE) disposed at the lower end of the light emitting element (LE). A portion of a side surface of the second insulating film (INS2) may be mutually aligned with a portion of a side surface of the contact electrode (CTE) and a portion of a side surface of the first insulating film (INS1). In some embodiments, a portion of a side surface of the second insulating film (INS2) may coincide with a portion of a side surface of the contact electrode (CTE) and a portion of a side surface of the first insulating film (INS1). However, the present invention is not limited thereto, and a portion of a side surface of the second insulating film (INS2) may not coincide with a portion of a side surface of the contact electrode (CTE) and a portion of a side surface of the first insulating film (INS1). The second insulating film (INS2) may be non-contact with the first insulating film (INS1).

[0185] The second insulating film (INS2) may include materials having insulating properties, such as oxides, fluorides, nitrides, organic-hybrid materials, etc. For example, the first insulating film (INS1) may include at least one or more of oxides such as Al2O3, HfO2, SiO2, TiO2, SrTiO3, Ta2O5, Gd2O3, ZrO2, Ga2O3, V2O5, Co3O4, ZnO, ZnO:Al, ZnO:B, In2O3:H, WO3, MoO3, Nb2O5, NiO, MgO, RuO2, etc.; fluorides such as MgF2, AlF3, etc.; nitrides such as TiN, TaN, Si3N4, AlN, GaN, WN, HfN, NbN, GdN, VN, ZrN, etc.; and organic-hybrid materials such as Alucone.

[0186] The thickness of the second insulating film (INS2) may range from 0.5 nm to 1.0 μm, but is not limited thereto. Preferably, the thickness of the second insulating film (INS2) may range from 10 nm to 30 nm.

[0187] In one embodiment, the second insulating film (INS2) may be formed of a single film or multiple films of materials having insulating properties. One or more insulating layers can prevent oxygen constituting the second insulating film (INS2) from diffusing into and deteriorating the second semiconductor layer (SEM2), the light-emitting layer (MQW), and the third semiconductor layer (SEM3) of the light-emitting element (LE). In addition, the second insulating film (INS2) can prevent an electrical short circuit that may occur when the light-emitting layer (MQW) directly contacts an electrode through which an electrical signal is transmitted to the light-emitting element (LE). In addition, since the second insulating film (INS2) protects the outer surface of the light-emitting element (LE) including the light-emitting layer (MQW), it can prevent a decrease in light-emitting efficiency.

[0188] As illustrated in FIG. 10, the light emitting element (LE) described above may be arranged to be coupled to the first pixel electrode (PE1). Specifically, the connection electrode (BON) of the light emitting element (LE) may be in direct contact with the first pixel electrode (PE1) so that a light emitting signal may be transmitted from the first pixel electrode (PE1). An organic layer (140) surrounding the light emitting element (LE) may be arranged around the light emitting element (LE) so as to expose a first semiconductor layer (SEM1), a first insulating film (INS1), and a contact electrode (CTE), which are one end of the light emitting element (LE). In FIG. 10, the upper portion of the first insulating film (INS1) of the light emitting element (LE) of FIG. 8 is illustrated as having been partially removed. This structural difference is due to the fact that the light emitting element (LE) is removed in a subsequent process after it is manufactured, and will be specifically described in the manufacturing method described below.

[0189] A common electrode (CE) may be disposed on the light-emitting element (LE) and the organic layer (140). The common electrode (CE) may cover the light-emitting element (LE) and the organic layer (140). The common electrode (CE) may be in direct contact with the upper surface of the first semiconductor layer (SEM1), the upper surface of the first insulating film (INS1), and the upper surface of the contact electrode (CTE). When the common electrode (CE) is in contact with the contact electrode (CTE), a low-potential voltage of the common electrode (CE) may be transferred to the light-emitting element (LE). For example, the low-potential voltage transferred from the common electrode (CE) may be transferred to the second semiconductor layer (SEM2) in contact with the contact electrode (CTE) through the contact electrode (CTE).

[0190] As described below, the first semiconductor layer (SEM1) is essentially formed to reduce the lattice constant difference between the sapphire substrate and the second semiconductor layer (SEM2) in the manufacturing process of the light emitting element (LE). However, since the first semiconductor layer (SEM1) is not doped and has very high resistance, an etching process of the first semiconductor layer (SEM1) must be performed after the light emitting element (LE) is bonded to the pixel electrode of the display substrate. In the process of etching the first semiconductor layer (SEM1) on the display substrate, it is very difficult to accurately etch the first semiconductor layer (SEM1) if other layers are etched in addition to the first semiconductor layer (SEM1) or if the light emitting element (LE) is tilted.

[0191] According to the above-described embodiment, the light-emitting element (LE) can be applied with a low potential voltage from the common electrode (CE) by having the contact electrode (CTE) contact the outer surface (or side) of the second semiconductor layer (SEM2). Accordingly, since the light-emitting element (LE) can be normally operated even if the first semiconductor layer (SEM1) is provided, there is an advantage in that the etching process of the first semiconductor layer (SEM1) can be omitted.

[0192] Fig. 11 is a drawing showing a light-emitting element according to another embodiment.

[0193] Referring to FIG. 11, this embodiment differs from the embodiments of FIGS. 6 to 10 described above in that the first insulating film (INS1) is disposed only on the outer surface of the first semiconductor layer (SEM1). Hereinafter, descriptions of the same configuration will be briefly or omitted, and the differences will be described in detail.

[0194] The first insulating film (INS1) may be arranged to surround an outer surface of the first semiconductor layer (SEM1) of the light emitting element (LE). The first insulating film (INS) may be formed to surround a side surface of the first semiconductor layer (SEM1), but may not surround outer surfaces of the second semiconductor layer (SEM2), the light emitting layer (MQW), the third semiconductor layer (SEM3) and the element electrode layer (ELT) of the light emitting element (LE). An upper surface of the first insulating film (INS1) may be mutually aligned with an upper surface of the first semiconductor layer (SEM1). In some embodiments, an upper surface of the first insulating film (INS1) may be aligned with an upper surface of the first semiconductor layer (SEM1). However, the present invention is not limited thereto, and an upper surface of the first insulating film (INS1) may not be aligned with an upper surface of the first semiconductor layer (SEM1). The first insulating film (INS1) may be in non-contact with the second semiconductor layer (SEM2). The first insulating film (INS1) can function to insulate between the first semiconductor layer (SEM1) and the contact electrode (CTE). For example, the first insulating film (INS1) prevents the contact electrode (CTE) from coming into contact with the first semiconductor layer (SEM1).

[0195] The contact electrode (CTE) can extend in the longitudinal direction of the second semiconductor layer (SEM2) from the interface between the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) and can be in contact with the second semiconductor layer (SEM2). Since the first insulating film (INS1) surrounds only the outer surface of the first semiconductor layer (SEM1), the contact area of ​​the contact electrode (CTE) with the second semiconductor layer (SEM2) can be increased. Accordingly, the contact area between the second semiconductor layer (SEM2) and the contact electrode (CTE) is increased, thereby improving the efficiency of the light emitting element (LE).

[0196] Fig. 12 is a drawing showing a light-emitting element according to another embodiment. Fig. 13 is an enlarged drawing of a light-emitting element area of ​​a display device according to another embodiment.

[0197] Referring to FIGS. 12 and 13, the light emitting element (LE) according to the present embodiment differs from the embodiments of FIGS. 6 to 10 described above in that the second insulating film (INS2) does not surround the outer surface of the contact electrode (CTE) and further includes a second organic layer (144).

[0198] Specifically, the second insulating film (INS2) may be arranged to surround the outer surfaces of the second semiconductor layer (SEM2), the light-emitting layer (MQW), the third semiconductor layer (SEM3), the element electrode layer (ELT), and the connection electrode (BON) of the light-emitting element (LE). The second insulating film (INS2) may be formed to surround a portion of the outer surface of the second semiconductor layer (SEM2), but may not surround the outer surface of the contact electrode (CTE) of the light-emitting element (LE). A lower surface of the second insulating film (INS2) may be in contact with an upper surface of the contact electrode (CTE3). A side surface of the second insulating film (INS2) may be mutually aligned with a side surface of the contact electrode (CTE3). In some embodiments, the side surface of the second insulating film (INS2) may be aligned with a side surface of the contact electrode (CTE3). However, this is not limited thereto, and the side surface of the second insulating film (INS2) may not be aligned with a side surface of the contact electrode (CTE3). The second insulating film (INS2) serves to protect the light emitting element (LE), but in the area where the second insulating film (INS2) is not disposed, a contact electrode (CTE) and the first insulating film (INS1) are disposed so that the light emitting element (LE) can be protected.

[0199] The above-described light-emitting element (LE) may be coupled onto the first pixel electrode (PE1). The first organic layer (140) disposed on the first pixel electrode (PE1) may surround the light-emitting element (LE) and expose a portion of the light-emitting element (LE). Specifically, the first organic layer (140) may cover the connection electrode (BON) of the light-emitting element (LE) and the second insulating film (INS2). The contact electrode (CTE), the first insulating film (INS1), and the first semiconductor layer (SEM1) of the light-emitting element (LE) may be exposed without being covered by the organic layer (140). The upper surface of the organic layer (140) may be mutually aligned with the upper surface of the second insulating film (INS2) of the light-emitting element (LE). For example, the upper surface of the organic layer (140) and the upper surface of the second insulating film (INS2) may be disposed on the same line. In some embodiments, the upper surface of the organic layer (140) may be aligned with the upper surface of the second insulating film (INS2) of the light emitting element (LE). However, this is not limited thereto, and the upper surface of the organic layer (140) may not be aligned with the upper surface of the second insulating film (INS2) of the light emitting element (LE).

[0200] A common electrode (CE) may be disposed on the light emitting element (LE) and the organic layer (140). The common electrode (CE) may cover the light emitting element (LE) and may directly contact the first semiconductor layer (SEM1), the first insulating film (INS1), and the contact electrode (CTE) of the light emitting element (LE). In particular, the common electrode (CE) may cover and contact the entire outer surface of the contact electrode (CTE), thereby reducing the contact resistance between the common electrode (CE) and the contact electrode (CTE), thereby improving the efficiency of the light emitting element (LE).

[0201] A second organic layer (144) may be disposed on the first organic layer (140). The second organic layer (144) may be formed to contact the upper surface of the common electrode (CE) and be aligned with the upper surface of the light emitting element (LE). In some embodiments, the upper surface of the second organic layer (144) may be aligned with the upper surface of the light emitting element (LE). However, this is not limited thereto, and the upper surface of the second organic layer (144) may not be aligned with the upper surface of the light emitting element (LE). The second organic layer (144) may perform a function of planarizing a step difference at the bottom of the common electrode (CE).

[0202] Fig. 14 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0203] Referring to FIG. 14, the display device (10) according to the present embodiment is different from the embodiments of FIGS. 6 to 10 described above in that a third insulating film (INS3) is further disposed between the common electrode (CE) and the light emitting element (LE).

[0204] A third insulating film (INS3) may be disposed on the light emitting element (LE). The third insulating film (INS3) may be disposed on the first semiconductor layer (SEM1) and the first insulating film (INS1) of the light emitting element (LE). The third insulating film (INS3) may be disposed to cover the first semiconductor layer (SEM1) and the first insulating film (INS1), but to be spaced apart from the contact electrode (CTE) so as not to cover the contact electrode (CTE).

[0205] The third insulating film (INS3) can be arranged between the common electrode (CE) and the first semiconductor layer (SEM1) to perform a function of preventing the common electrode (CE) and the first semiconductor layer (SEM1) from contacting each other. As described above, the first semiconductor layer (SEM1) is not doped and thus has a very high resistance, which increases the resistance between the common electrode (CE) and the light emitting element (LE), thereby reducing efficiency. Therefore, the third insulating film (INS3) can be arranged between the common electrode (CE) and the first semiconductor layer (SEM1) to prevent the common electrode (CE) from contacting the first semiconductor layer (SEM1), thereby allowing the low-potential voltage of the common electrode (CE) to be transmitted only to the contact electrode (CTE).

[0206] A common electrode (CE) may be disposed on the light emitting element (LE), the third insulating film (INS3), and the organic layer (140). The common electrode (CE) may contact a contact electrode (CTE) exposed around the third insulating film (INS3). Accordingly, the efficiency of the light emitting element (LE) may be increased by allowing a low potential voltage applied from the common electrode (CE) to be transferred to the contact electrode (CTE).

[0207] Fig. 15 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0208] Referring to FIG. 15, the display device (10) according to the present embodiment is different from the embodiments of FIGS. 6 to 10 described above in that the first insulating film (INS1) covers the upper surface of the contact electrode (CTE).

[0209] The light emitting element (LE) may be formed in the same structure as that of FIG. 8 described above. Specifically, the first insulating film (INS1) may be disposed on the uppermost portion of the light emitting element (LE). The upper surface of the first insulating film (INS1) may be mutually aligned with the upper surface of the first semiconductor layer (SEM1). In some embodiments, the upper surface of the first insulating film (INS1) may be aligned with the upper surface of the first semiconductor layer (SEM1). However, the present invention is not limited thereto, and the upper surface of the first insulating film (INS1) may not be aligned with the upper surface of the first semiconductor layer (SEM1).

[0210] The organic layer (140) is arranged to surround the light emitting element (LE), and may be arranged so as not to cover the side surfaces of the first insulating film (INS1), the contact electrode (CTE), and the second insulating film (INS2) so that they are exposed. For example, the height of the organic layer (140) may be lower than the height of the side surface of the contact electrode (CTE) exposed to the side surface of the light emitting element (LE). However, the present invention is not limited thereto, and the height of the organic layer (140) may be formed to be the same as the height of the second insulating film (INS2).

[0211] The common electrode (CE) covers the light emitting element (LE) and can be in direct contact with the contact electrode (CTE) exposed on the side of the light emitting element (LE). That is, since the organic layer (140) does not cover the side of the contact electrode (CTE), the common electrode (CE) can be in direct contact with the side of the contact electrode (CTE). Accordingly, a low potential voltage can be transmitted from the common electrode (CE) to the light emitting element (LE) through the contact electrode (CTE).

[0212] Fig. 16 is an enlarged view of a light emitting element area of ​​a display device according to another embodiment.

[0213] Referring to FIG. 16, the display device (10) according to the present embodiment is different from the embodiment of FIG. 15 described above in that the third insulating film (INS3) is disposed on the first semiconductor layer (SEM1) of the light emitting element (LE).

[0214] The third insulating film (INS3) may be disposed on the light emitting element (LE). The third insulating film (INS3) may be disposed on the first semiconductor layer (SEM1) of the light emitting element (LE) and may be disposed spaced apart from the first insulating film (INS1). The third insulating film (INS3) may be disposed directly on the upper surface of the first semiconductor layer (SEM1).

[0215] As described above, the third insulating film (INS3) is disposed between the common electrode (CE) and the first semiconductor layer (SEM1), and can perform a function of preventing the common electrode (CE) and the first semiconductor layer (SEM1) from contacting each other. Accordingly, the third insulating film (INS3) is disposed between the common electrode (CE) and the first semiconductor layer (SEM1), and can ensure that the low potential voltage of the common electrode (CE) is transmitted only to the contact electrode (CTE).

[0216] A common electrode (CE) may be disposed on the light emitting element (LE), the third insulating film (INS3), and the organic layer (140). The common electrode (CE) may contact a contact electrode (CTE) exposed on a side of the light emitting element (LE). Accordingly, the efficiency of the light emitting element (LE) may be increased by allowing a low potential voltage applied from the common electrode (CE) to be transferred to the contact electrode (CTE).

[0217] FIGS. 17 to 19 are enlarged views of a light-emitting element area of ​​a display device according to another embodiment.

[0218] Referring to FIGS. 17 to 19, the display device (10) according to the present embodiment is different from the embodiments of FIGS. 8 to 10 described above in that it further includes a reflective layer (RFL).

[0219] The reflective layer (RFL) may be arranged to surround the outer surface of the second insulating film (INS2). For example, the reflective layer (RFL) may be arranged to surround the outer surface of the second insulating film (INS2) and may extend in one direction in which the light-emitting element (LE) extends. The reflective layer (RFL) may perform a function of reflecting light emitted from the light-emitting layer (MQW) so that the light can be emitted in the direction of the first semiconductor layer (SEM1). The reflective layer (RFL) may be arranged to correspond to the outer surfaces of the second semiconductor layer (SEM2), the light-emitting layer (MQW), the third semiconductor layer (SEM3), and the element electrode layer (ELT) of the light-emitting element (LE). When the contact electrode (CTE) is formed of a reflective material, the reflective layer (RFL) may not be arranged in an area corresponding to the outer surface of the contact electrode (CTE) because the contact electrode (CTE) functions as a reflective layer.

[0220] As another example, as illustrated in FIG. 18, the reflective layer (RFL) may be disposed on the outer surface of the second insulating film (INS2) corresponding to the outer surface of the contact electrode (CTE). The reflective layer (RFL) may be disposed on the entire outer surface of the second insulating film (INS1).

[0221] The reflective layer (RFL) may be a distributed Bragg reflector (DBR). The reflective layer (RFL) may include multiple layers to function as a distributed Bragg reflector. The multiple layers may be arranged in an alternating manner of high-refractive-index layers and low-refractive-index layers.

[0222] Additionally, the reflective layer (RFL) may include insulating materials, such as oxides, fluorides, nitrides, organic-hybrid materials, etc. For example, the reflective layer (RFL) may include at least one or more of oxides such as Al2O3, HfO2, SiO2, TiO2, SrTiO3, Ta2O5, Gd2O3, ZrO2, Ga2O3, V2O5, Co3O4, ZnO, ZnO:Al, ZnO:B, In2O3:H, WO3, MoO3, Nb2O5, NiO, MgO, RuO2, etc.; fluorides such as MgF2, AlF3, etc.; nitrides such as TiN, TaN, Si3N4, AlN, GaN, WN, HfN, NbN, GdN, VN, ZrN, etc.; and organic-hybrid materials such as Alucone. The thickness of the reflective layer (RFL) may range from 0.5 nm to 1.0 μm, but is not limited thereto.

[0223] In this embodiment, by including a reflective layer (RFL) surrounding the outer surface of the light emitting element (LE), the light emission efficiency of light emitted from the light emitting layer (MQW) of the light emitting element (LE) can be improved.

[0224] Hereinafter, a manufacturing process of a display device (10) according to one embodiment will be described with reference to other drawings.

[0225] Fig. 20 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Figs. 21 to 40 are drawings for explaining a method for manufacturing a display device according to one embodiment.

[0226] FIGS. 21 to 40 illustrate cross-sectional views of the structures of the respective layers of the display device (10) according to the formation order. FIGS. 21 to 40 primarily illustrate the manufacturing process of the light emitting element portion (LEP) of the display device (10), which can generally correspond to the cross-sectional view of FIG. 6. In addition, the first light emitting area (EA1) of the display device (10) is illustrated as an example below. The following will describe a manufacturing method of the display device illustrated in FIGS. 21 to 40 in connection with FIG. 20.

[0227] Referring to FIG. 20, a method for manufacturing a display device (10) according to one embodiment may include a step of forming a plurality of light-emitting elements on a base substrate (S100), a step of forming a substrate including pixel electrodes (S110), a step of bonding the plurality of light-emitting elements on the pixel electrodes (S120), and a step of forming an organic layer and a common electrode on the light-emitting elements (S130).

[0228] First, referring to Fig. 21, a plurality of element loads (LEL) are formed on a base substrate (BSUB).

[0229] Specifically, a base substrate (BSUB) is prepared. The base substrate (BSUB) may be a sapphire substrate (Al2O3) or a silicon wafer containing silicon. However, the present invention is not limited thereto, and in one embodiment, a case in which the base substrate (BSUB) is a sapphire substrate is described as an example.

[0230] A plurality of semiconductor material layers (SEM1L, SEM2LMQML, SEM3L) are formed on a base substrate (BSUB). The plurality of semiconductor material layers can be formed by growing seed crystals grown by an epitaxial method. Here, a method for forming the semiconductor material layers may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and preferably, it can be formed by metal-organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0231] The precursor material for forming multiple semiconductor material layers is not particularly limited within a range that can be typically selected to form the target material. For example, the precursor material may be a metal precursor containing an alkyl group, such as a methyl group or an ethyl group. Examples thereof include, but are not limited to, compounds such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), and triethyl phosphate ((C2H5)3PO4).

[0232] Specifically, a first semiconductor material layer (SEM1L) is formed on a base substrate (BSUB). Although the drawing illustrates that the first semiconductor material layer (SEM1L) is laminated in one layer, the present invention is not limited thereto, and a plurality of layers may be formed. The first semiconductor material layer (SEM1L) may be arranged to reduce a difference in lattice constants between the second semiconductor material layer (SEM2L) and the base substrate (BSUB). For example, the first semiconductor material layer (SEM1L) may include an undoped semiconductor, and may be a material that is not doped as an n-type or p-type. In an exemplary embodiment, the first semiconductor material layer (SEM1L) may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0233] Using the method described above, a second semiconductor material layer (SEM2L), a light-emitting material layer (MQWL), and a third semiconductor material layer (SEM3L) are sequentially formed on a first semiconductor material layer (SEM1L).

[0234] Next, a device electrode material layer (ELTL) is laminated on the third semiconductor material layer (SEM3L).

[0235] Next, a plurality of first mask patterns (MP1) are formed on the element electrode material layer (ELTL). The first mask pattern (MP1) may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern (MP1) prevents the plurality of semiconductor material layers (SEM1L, SEM2L, MQML, SEM3L) and the element electrode material layer (ELTL) therebelow from being etched. Next, a first etching (1) is performed to etch a portion of the plurality of semiconductor material layers (SEM1L, SEM2L, MQML, SEM3L) and the element electrode material layer (ELTL) using the plurality of first mask patterns (MP1) as a mask. st etch) process is performed.

[0236] As illustrated in FIG. 22, on the base substrate (BSUB), a plurality of semiconductor material layers (SEM1L, MQML, SEM2L, SEM3L) that do not overlap with the first mask pattern (MP1) and a device electrode material layer (ELTL) are etched and removed, and a portion that is not etched and overlaps with the first mask pattern (MP1) can be formed as a device load (LEL).

[0237] Semiconductor material layers can be etched by a conventional method. For example, the process for etching semiconductor material layers can be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching is possible, so it can be suitable for vertical etching. When using the etching method described above, the etchant can be Cl2 or O2, etc., but is not limited thereto.

[0238] Next, referring to FIGS. 23 and 24, a first insulating material layer (INS1L) is formed on a base substrate (BSUB). The first insulating material layer (INS1L) is formed on the entire surface of the base substrate (BSUB) and can cover the element load (LEL). The first insulating material layer (INS1L) is formed on the entire surface of the first semiconductor layer (SEM1), the second semiconductor layer (SEM2), the light-emitting layer (MQW), the first semiconductor layer (SEM1), and the element electrode layer (ELT) of the element load (LEL).

[0239] Next, a first photoresist (PR1) is formed on the base substrate (BSUB). The first photoresist (PR1) can be formed on the first insulating material layer (INS1L) to a predetermined height of the element load (LEL). For example, the first photoresist (PR1) can be formed to a height higher than the height of the first semiconductor layer (SEM1) and up to a height of a portion of the second semiconductor layer (SEM2).

[0240] Next, a second etching (2) is performed to partially remove the first insulating material layer (INS1L). nd An etch process is performed. Specifically, the first insulating material layer (INS1L) exposed on the first photoresist (PR1) can be removed by etching. In this process, the first insulating material layer (INS1L) can be removed so that a part of the second semiconductor layer (SEM2) of the device load (LEL), the light-emitting layer (MQW), the first semiconductor layer (SEM1) and the device electrode layer (ELT) are exposed. Accordingly, the first insulating material layer (INS1L) can be formed to surround the outer surface of the first semiconductor layer (SEM1) of the device load (LEL) and a part of the outer surface of the second semiconductor layer (SEM2). After the etching process of the first insulating material layer (INS1L) is completed, the first photoresist (PR1) can be removed.

[0241] Next, referring to FIG. 25, a contact electrode material layer (CTEL) is laminated on a base substrate (BSUB). The contact electrode material layer (CTEL) is formed on the entire surface of the base substrate (BSUB) and can cover the element load (LEL). The contact electrode material layer (CTEL) is formed over the entire surface of the second semiconductor layer (SEM2), the light-emitting layer (MQW), the first semiconductor layer (SEM1), and the outer surface of the element electrode layer (ELT) of the element load (LEL). In addition, the contact electrode material layer (CTEL) is also formed on the outer surface and the upper surface of the first insulating material layer (INS1L).

[0242] Next, referring to FIG. 26, a second photoresist (PR2) is formed on the base substrate (BSUB). The second photoresist (PR2) may be formed on the contact electrode material layer (CTEL) to a predetermined height of the element load (LEL). For example, the second photoresist (PR2) may be formed to a height at least higher than the height of the first insulating material layer (INS1L) and up to a height of a portion of the second semiconductor layer (SEM2).

[0243] Next, referring to FIG. 27 together with FIG. 26, a third etching (3) is performed to partially remove the contact electrode material layer (CTEL). rd An etch process is performed. Specifically, the contact electrode material layer (CTEL) exposed on the second photoresist (PR2) can be etched and removed. In this process, the contact electrode material layer (CTEL) can be removed so that a part of the second semiconductor layer (SEM2) of the device load (LEL), the light-emitting layer (MQW), the first semiconductor layer (SEM1), and the device electrode layer (ELT) are exposed. Accordingly, the contact electrode material layer (CTEL) can be formed to surround the outer surface of the first insulating material layer (INS1L) and surround a part of the outer surface of the second semiconductor layer (SEM2) of the device load (LEL). After the etch process of the contact electrode material layer (CTEL) is completed, the second photoresist (PR2) can be removed.

[0244] Next, referring to FIG. 28, a portion of the second insulating material layer (INS2L) is etched to form an opening (OPN). The opening (OPN) can expose the top of the element load (LEL). A device electrode layer (ELT) is arranged on the top of the element load (LEL), so that a portion of the upper surface of the device electrode layer (ELT) can be exposed by the opening (OPN) of the second insulating material layer (INS2L).

[0245] Next, referring to FIGS. 29 and 30, a third photoresist (PR3) is formed on the base substrate (BSUB). The third photoresist (PR3) may be patterned to cover each of the device loads (LEL). The third photoresist (PR3) may be formed to cover the second insulating material layer (INS2L) including the device loads (LEL). The third photoresist (PR3) may be patterned in an island pattern shape to cover each of the device loads (LEL) and may be formed to be spaced apart from each other.

[0246] Next, a fourth etching (4) is performed to etch the first insulating material layer (INS1L), the contact electrode material layer (CTEL), and the second insulating material layer (INS2L). th An etching process is performed. The first insulating material layer (INS1L), the contact electrode material layer (CTEL), and the second insulating material layer (INS2L) exposed by the third photoresist (PR3) can be etched and removed. Accordingly, a plurality of device loads (LEL) including the first semiconductor layer (SEM1), the second semiconductor layer (SEM2), the light-emitting layer (MQW), the third semiconductor layer (SEM3), the device electrode layer (ELT), the first insulating film (INS1), the contact electrode (CTE), and the second insulating film (INS2) are formed. The plurality of device loads (LEL) can be spaced apart from each other on the base substrate (BSUB).

[0247] Next, referring to FIG. 31, a connection electrode (BON) is formed on the element load (LEL). The connection electrode (BON) can be formed through a patterning process after laminating a connection electrode material layer. The connection electrode (BON) can be formed in the opening (OPN) of the second insulating film (INS2). The connection electrode (BON) can be directly disposed on the element electrode layer (ELT) of the element load (LEL), and can be formed to protrude above the second insulating film (INS2). Thus, a light-emitting element (LE) including the element load (LEL) and the connection electrode (BON) is manufactured.

[0248] Next, referring to FIG. 32, a support film (SPF) is attached on a plurality of light emitting elements (LE) of the base substrate (BSUB) manufactured in FIG. 31.

[0249] Specifically, a support film (SPF) is attached on a plurality of light-emitting elements (LE). The support film (SPF) is aligned on the plurality of light-emitting elements (LE) and can be attached to each connecting electrode (BON) of the plurality of light-emitting elements (LE). Since the plurality of light-emitting elements (LE) are arranged in large numbers, they can be attached without being detached from the support film (SPF).

[0250] The support film (SPF) may be composed of a support layer and an adhesive layer disposed on the support layer. The support layer may be made of a material that is transparent and mechanically stable so that light can pass through it. For example, the support layer may include a transparent polymer such as polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The adhesive layer may include an adhesive material for adhering the light emitting element (LE). For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose adhesive strength changes when ultraviolet (UV) light or heat is applied, thereby allowing the adhesive layer to be easily separated from the light emitting element (LE).

[0251] Next, referring to FIG. 33, a first laser (1) is applied to the base substrate (BSUB). st The base substrate (BSUB) and the light emitting elements (LE) are separated by irradiating the base substrate (BSUB) with a laser. The base substrate (BSUB) is separated from the first semiconductor layer (SEM1) and the first insulating film (INS1) of the plurality of light emitting elements (LE).

[0252] The process of separating the base substrate (BSUB) and the light emitting element (LE) can be separated by the laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (wavelength 248 nm) can be used as the source. The energy density of the excimer laser is irradiated in the range of approximately 550 mJ / cm2 to 950 mJ / cm2, and the irradiation area (incident area) is 50 x 50 ㎛. 2 It may be in the range of 1 x 1㎠, but is not limited thereto.

[0253] Next, referring to Figure 34, a transfer film (LFL) is attached to a plurality of light emitting elements (LE).

[0254] Specifically, a transfer film (LFL) is attached on each of the first semiconductor layers (SEM1) and the first insulating film (INS1) of the plurality of light-emitting elements (LE). The transfer film (LFL) is aligned on the plurality of light-emitting elements (LE) and can be attached to the lower surface of each of the first semiconductor layers (SEM1) and the first insulating film (INS1) of the plurality of light-emitting elements (LE).

[0255] The transfer film (LFL) may include a stretchable material. The stretchable material may include, for example, polyolefin, polyvinyl chloride (PVC), elastomeric silicone, elastomeric polyurethane, elastomeric polyisoprene, etc. The transfer film (LFL) may also include a support layer and an adhesive layer, like the support film (SPF) described above, to adhere and support a plurality of light emitting elements (LE).

[0256] Next, referring to FIG. 35, the support film (SPF) is separated from the plurality of light-emitting elements (LE). By applying ultraviolet light or heat to the support film (SPF), the adhesive strength of the adhesive layer of the support film (SPF) is reduced, and then the support film (SPF) can be separated physically or naturally. The plurality of light-emitting elements (LE) can be arranged in a dot shape on the transfer film (LFL) at a predetermined first interval (D1).

[0257] Next, referring to FIG. 36, the transfer film (LFL) is stretched (ORI). The transfer film (LFL) can be stretched two-dimensionally, including in a first direction (DR1) and a second direction (DR2). As the transfer film (LFL) is stretched, the spacing between the plurality of light-emitting elements (LE) adhered on the transfer film (LFL) can be a second spacing (D2) that is increased from the first spacing (D1) of FIG. 35. The stretching strength (or tensile strength) of the transfer film (LFL) can be adjusted according to the desired spacing between the light-emitting elements (LE), and can be, for example, about 120 gf / inch. However, the present invention is not limited thereto. In the present embodiment, a single stretching process is described as an example, but the present invention is not limited thereto. The stretching process can be performed multiple times.

[0258] Next, referring to FIGS. 37 and 38, a transfer film (LFL) is bonded onto a substrate (110) and a plurality of light-emitting elements (LE) are bonded onto first pixel electrodes (PE1).

[0259] Specifically, a transfer film (LFL) is aligned on a substrate (110). At this time, the connection electrode (BON) of the light emitting element (LE) formed on the transfer film (LFL) is aligned so that it faces the substrate (110). The substrate (110) may have a plurality of pixel electrodes (PE1) and a pixel defining film (PDL) formed thereon, as illustrated in FIG. 6.

[0260] Next, the substrate (110) and the transfer film (LFL) are bonded. Specifically, the connection electrode (BON) of the light emitting element (LE) formed on the transfer film (LFL) is brought into contact with the first pixel electrodes (PE1) of the substrate (110). At this time, the connection electrode (BON) of the light emitting element (LE) is brought into contact with the first pixel electrode (PE1). Next, the substrate (110) and the transfer film (LFL) are bonded by melting and bonding the connection electrode (BON) of the light emitting element (LE) and the first pixel electrodes (PE1). At this time, a plurality of light emitting elements (LE) are bonded to the upper surface of the first pixel electrode (PE1).

[0261] Melt bonding can be performed by irradiating a laser onto the first pixel electrode (PE1) on top of the transfer film (LFL). The first pixel electrode (PE1) irradiated with the laser can adhere to the interface between the connection electrode (BON) of the light-emitting element (LE) and the first pixel electrode (PE1) by conducting the high heat of the laser. In particular, the first pixel electrodes (PE1) can include copper (Cu) with excellent heat conductivity, so that the adhesion properties with the connection electrode (BON) of the light-emitting element (LE) can be excellent. YAG can be used as the laser source used for melt bonding.

[0262] Next, the transfer film (LFL) is separated from the plurality of light emitting elements (LE).

[0263] Specifically, a transfer film (LFL) is separated from a first semiconductor layer (SEM1) of a light-emitting element (LE). The process of separating the transfer film (LFL) can be separated by a laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (248 nm wavelength) can be used as a source. The energy density of the excimer laser is irradiated in a range of about 550 mJ / cm2 to 950 mJ / cm2, and the irradiation area (incident area) is 50 x 50 ㎛. 2The range may be 1 x 1㎠, but is not limited thereto. By irradiating the laser onto the transfer film (LFL), the transfer film (LFL) can be separated from the light emitting element (LE).

[0264] As another example, the process of separating the transfer film (LFL) can also be physically separated in addition to the laser lift-off process. Since the bonding force between the transfer film (LFL) and the light-emitting element (LE) is lower than the melt-bonded bonding force between the connecting electrode (BON) of the light-emitting element (LE) and the first pixel electrode (PE1), the transfer film (LFL) can also be physically separated depending on the difference in adhesive strength.

[0265] Next, referring to FIG. 39, an organic layer (140) is formed on a substrate (110) on which light-emitting elements (LE) are formed. The organic layer (140) may be formed on a first pixel electrode (PE1) and a pixel defining layer (PDL). The organic layer (140) may be disposed on each light-emitting region and may be disposed spaced apart from each other between adjacent light-emitting regions. The organic layer (140) may be formed by applying using a solution process such as spin coating or inkjet printing and patterning through an exposure process. The organic layer (140) may be formed to a height smaller than the height of the first semiconductor layer (SEM1) of the light-emitting element (LE), but is not limited thereto.

[0266] Next, referring to FIGS. 39 and 40 together, a fifth etching (5) for etching a portion of the first insulating film (INS1) of each light emitting element (LE) th The etching process is performed. In the fifth etching process, a portion of the upper part of the first insulating film (INS1) may be etched and removed. For example, a portion of the first insulating film (INS1) covering the upper surface of the contact electrode (CTE) may be etched and removed.

[0267] As illustrated in Fig. 40, the first insulating film (INS1) is etched so as to be aligned with the upper surface of the contact electrode (CTE), so that the upper surface of the first insulating film (INS1) and the upper surface of the contact electrode (CTE) are formed to be mutually aligned. The upper surface of the contact electrode (CTE) can be exposed upward by the etching of the first insulating film (INS1).

[0268] Next, a common electrode (CE) is formed on the light-emitting element (LE) and the organic layer (140). The common electrode (CE) is formed continuously over the entire display area. The common electrode (CE) covers the organic layer (140) and the light-emitting element (LE) and is in direct contact with them. For example, the common electrode (CE) may contact a first semiconductor layer (SEM1), a first insulating film (INS1), and a contact electrode (CTE) of the light-emitting element (LE). By contacting the contact electrode (CTE) with the common electrode (CE), a low-potential voltage applied from the common electrode (CE) can be transmitted to the light-emitting element (LE) through the contact electrode (CTE).

[0269] Thereafter, as illustrated in FIG. 6, a display device (10) according to one embodiment is manufactured by forming a wavelength control layer, a color filter layer, etc.

[0270] A method for manufacturing a display device (10) according to one embodiment can electrically connect a common electrode (CE) and a light-emitting element (LE) while omitting the removal process of a first semiconductor layer (SEM1). Therefore, the manufacturing process of the display device (10) can be simplified and process defects can be prevented.

[0271] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. First semiconductor layer; A second semiconductor layer disposed on the first semiconductor layer; A light-emitting layer disposed on the second semiconductor layer; A third semiconductor layer disposed on the above light-emitting layer; A device electrode layer disposed on the third semiconductor layer; A connecting electrode arranged on the above element electrode layer; A first insulating film surrounding side surfaces of the first semiconductor layer and the second semiconductor layer; A contact electrode surrounding the side surface of the first insulating film and the second semiconductor layer; and It includes a second insulating film surrounding the side surface of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, the element electrode layer, and the connecting electrode. The above contact electrode is a light emitting element that contacts the side surface of the second semiconductor layer.

2. In paragraph 1, A light emitting element in which the first insulating film surrounds the entire side surface of the first semiconductor layer and surrounds a portion of the side surface of the second semiconductor layer.

3. In paragraph 1, The above contact electrode is a light emitting element that does not contact the first semiconductor layer.

4. In paragraph 1, A light emitting element in which the second insulating film surrounds the side of the contact electrode but does not contact the first insulating film.

5. In paragraph 1, A contact region in which the above contact electrode and the second semiconductor layer are in contact with each other is included, A light emitting element in which the contact region is arranged in an area of ​​1 to 90% of the length of the second semiconductor layer from the interface between the first semiconductor layer and the second semiconductor layer.

6. In paragraph 5, A light emitting element wherein the contact area is in a range of 1 to 90% of the total area of ​​the side surface of the second semiconductor layer.

7. In paragraph 1, A light emitting element in which the side of the first insulating film, the side of the contact electrode, and the side of the second insulating film are aligned with each other.

8. In paragraph 1, A light emitting element in which the first insulating film is not in contact with the second semiconductor layer.

9. In paragraph 1, A light emitting element in which the second insulating film is not in contact with the side surface of the contact electrode and is mutually aligned with the side surface of the contact electrode.

10. In paragraph 1, Further comprising a reflective layer surrounding the side surface of the second insulating film, A light emitting element in which the side surface of the above reflective layer is mutually aligned with the side surface of the above contact electrode.

11. In paragraph 1, A light-emitting device wherein the first semiconductor layer includes an undoped semiconductor, the second semiconductor layer includes an n-type semiconductor, and the third semiconductor layer includes a p-type semiconductor.

12. Substrate; A pixel electrode arranged on the above substrate; Light-emitting elements arranged on the pixel electrode; A first organic layer disposed on the pixel electrode and between the light-emitting elements; and A common electrode disposed on the first organic layer and the light-emitting elements, Each of the above light emitting elements, A connecting electrode arranged on the above pixel electrode; A device electrode layer disposed on the above connecting electrode; A third semiconductor layer disposed on the above-mentioned element electrode layer; A light-emitting layer disposed on the third semiconductor layer; A second semiconductor layer disposed on the above light-emitting layer; A first semiconductor layer disposed on the second semiconductor layer; A first insulating film surrounding side surfaces of the first semiconductor layer and the second semiconductor layer; A contact electrode surrounding the side surface of the first insulating film and the second semiconductor layer; and It includes a second insulating film surrounding the side surface of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, the element electrode layer, and the connecting electrode. A display device in which the contact electrode is arranged on a side surface of the second semiconductor layer, and the common electrode is connected to the contact electrode.

13. In paragraph 12, A display device in which the above-mentioned connecting electrode is connected to the above-mentioned pixel electrode, and the above-mentioned second semiconductor layer is electrically connected to the above-mentioned common electrode through the above-mentioned connecting electrode.

14. In paragraph 12, A display device in which the upper surface of the first organic layer is mutually aligned with the upper surface of the first insulating film and the upper surface of the contact electrode.

15. In paragraph 12, A display device in which the common electrode is disposed on the first semiconductor layer, the first insulating film, the contact electrode, and the first organic layer.

16. In paragraph 12, It further includes a third insulating film disposed between the first semiconductor layer and the common electrode, A display device in which the above common electrode is not in contact with the first semiconductor layer.

17. In paragraph 16, A display device in which the third insulating film is in contact with the first semiconductor layer and does not contact the first insulating film.

18. In paragraph 12, A display device in which the common electrode contacts the side of the first insulating film and the side of the contact electrode.

19. In paragraph 12, The above light-emitting element further includes a reflective layer surrounding a side surface of the second insulating film, A display device in which the first organic layer covers the reflective layer.

20. In paragraph 12, Further comprising a second organic layer disposed on the first organic layer, A display device wherein the common electrode is disposed between the first organic layer and the second organic layer.

21. In paragraph 20, A display device in which the common electrode surrounds and contacts a side surface of the contact electrode, and the second organic layer covers a portion of the common electrode.

22. A step of forming a pixel electrode on a substrate; A step of forming light-emitting elements on a base substrate; A step of combining the light-emitting elements formed on the base substrate onto the pixel electrode; A step of forming an organic layer between the light-emitting elements on the pixel electrode; and A step of forming a common electrode on the organic layer and the light-emitting elements is included. The step of forming light-emitting elements on the above base substrate is: A step of forming a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a third semiconductor layer, and an element electrode layer on the base substrate; A step of forming a first insulating film surrounding side surfaces of the first semiconductor layer and the second semiconductor layer; A step of forming a contact electrode surrounding side surfaces of the first insulating film and the second semiconductor layer; A step of forming a second insulating film surrounding side surfaces of the second semiconductor layer, the light-emitting layer, the third semiconductor layer, and the element electrode layer; and A method for manufacturing a display device, comprising the step of forming a connection electrode on the above-described element electrode layer.

23. In paragraph 22, A method for manufacturing a display device, wherein the first insulating film, the second insulating film, and the contact electrode are formed by simultaneously etching the first insulating material layer, the contact electrode material layer, and the second insulating material layer.

24. In paragraph 22, The step of combining the light-emitting elements formed on the base substrate onto the pixel electrode is: A step of bonding a support film on the connecting electrodes of the above light-emitting elements; A step of separating the base substrate from the light emitting elements; A step of adhering a transfer film to one surface of the light-emitting elements facing the support film; A step of separating the above support film from the above light-emitting elements; a step of bonding the connecting electrodes of the light-emitting elements onto the pixel electrode; and A method for manufacturing a display device, comprising the step of removing the transfer film from the light-emitting elements.

25. In paragraph 24, A method for manufacturing a display device, wherein after the step of separating the support film from the light-emitting elements, the transfer film is stretched to increase the spacing between the light-emitting elements.

26. In paragraph 24, A method for manufacturing a display device, wherein the step of bonding the connection electrodes of the light-emitting elements onto the pixel electrode comprises irradiating the pixel electrode with a laser to melt and bond the connection electrode and the pixel electrode.

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