Transistor, pixel circuit and display device
By designing a "L" or "U" type transistor structure to increase the channel width, the problem of high transistor power consumption in Micro LED display technology is solved, and lower power consumption and higher current output capability are achieved.
Patent Information
- Application Number
- PCT/CN2023/135094
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-11-29
- Publication Date
- 2025-07-31
AI Technical Summary
In the prior art, it is difficult for the micro LED display technology to effectively increase the channel width of the transistor within a limited pixel area, resulting in a large source/drain voltage difference of the transistor, increasing power consumption, and further reducing pixel power consumption in the display area.
A new transistor structure is designed, including a first gate and channel region of "L" type or "U" type, to reduce the source/drain voltage difference by increasing the width of the channel region, thereby reducing power consumption.
Under the same area, the channel width of the transistor is increased, the power consumption is effectively reduced, the current output capability and voltage stability are improved, and it is suitable for Micro LED display technology.
Smart Images
Figure CN2023135094_31072025_PF_FP_ABST
Abstract
Description
Transistor, pixel circuit and display device Technical Field
[0001] The present disclosure relates to the field of display technology, and in particular to a transistor, a pixel circuit, and a display device. Background Art
[0002] The display market is currently booming, and with increasing consumer demand for a wide range of display products, including laptops, smartphones, TVs, tablets, smartwatches, and fitness bands, more new display products are expected to emerge in the future. Micro-light-emitting diode (MLED) display technology boasts low power consumption, high brightness, ultra-high resolution and color saturation, fast response time, ultra-low power consumption, long lifespan, and high efficiency, making it considered the most competitive next-generation display technology.
[0003] Summary of the Invention
[0004] The present disclosure provides a transistor, a pixel circuit, and a display device, the specific solutions of which are as follows:
[0005] In one aspect, an embodiment of the present disclosure provides a transistor, comprising:
[0006] substrate;
[0007] a first gate, located on one side of the substrate; the first gate comprises a first portion and a second portion connected to each other; wherein the first portion extends along a first direction and comprises a first main portion connected to the second portion; and the second portion extends along a second direction and comprises a second main portion connected to the first portion, wherein the second direction is perpendicular to the first direction;
[0008] An active layer is arranged on the same side of the base substrate as the first gate electrode, the active layer includes a channel region, the orthographic projection of the channel region on the base substrate at least overlaps with the orthographic projection of the first main body on the base substrate and the orthographic projection of the second main body on the base substrate, and the width of the channel region is greater than or equal to the sum of the size of the first main body in the first direction and the size of the second main body in the second direction.
[0009] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the first gate also includes a third part connected to the second part, the third part extends along the first direction and is spaced apart from the first part in the second direction, the third part includes a third main body connected to the second part, and the orthographic projection of the third main body on the substrate overlaps with the orthographic projection of the channel region on the substrate.
[0010] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the width of the channel region is equal to the sum of the size of the first main body in the first direction, the size of the second part in the second direction, and the size of the third main body in the first direction.
[0011] In some embodiments, in the above-mentioned transistor provided by the embodiments of the present disclosure, the size of the first main body portion in the first direction is equal to or different from the size of the third main body portion in the first direction.
[0012] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the first gate further includes a connecting portion extending along a third direction, and the second main portion is connected to the first main portion or the third main portion through the connecting portion; the orthographic projection of the connecting portion on the substrate overlaps with the orthographic projection of the channel region on the substrate, and the third direction intersects with the first direction and the second direction.
[0013] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the width of the channel region is equal to the sum of the midline size of the first main body in the first direction, the midline size of the second part in the second direction, the midline size of the third main body in the first direction, and the midline size of the connecting part in the third direction.
[0014] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the size of the first main body in the second direction, the size of the second main body in the first direction, the size of the third main body in the second direction, and the size of the connecting portion in the fourth direction are equal, and the fourth direction is perpendicular to the third direction.
[0015] In some embodiments, in the above-mentioned transistor provided by the embodiments of the present disclosure, the connecting portion is straight-line or arc-shaped.
[0016] In some embodiments, in the above-mentioned transistor provided by the embodiments of the present disclosure, the first gate is located between the base substrate and the active layer, or is located on a side of the active layer away from the base substrate.
[0017] In some embodiments, the above-mentioned transistor provided in the embodiments of the present disclosure further includes a second gate, wherein one of the second gate and the first gate is located between the active layer and the base substrate, and the other is located on the side of the active layer away from the base substrate.
[0018] In some embodiments, the transistor provided in the embodiments of the present disclosure further includes a first electrode located on a side of the active layer away from the substrate;
[0019] The first gate is coupled to the second gate, or the first gate or the second gate located between the active layer and the base substrate is coupled to the first electrode.
[0020] In some embodiments, the above-mentioned transistor provided in the embodiments of the present disclosure further includes a first electrode located on the side of the active layer away from the base substrate; in the area enclosed by the first part and the second part, the orthographic projection of the first electrode on the base substrate, the orthographic projection of the first part on the base substrate, and the orthographic projection of the second part on the base substrate are respectively arranged at intervals.
[0021] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, the gate further includes a third portion connected to the second portion, the third portion extending along the first direction and having a first distance from the first portion in the second direction; the first portion, the second portion, and the third portion enclose a non-closed area;
[0022] The transistor further includes a first electrode located on a side of the active layer away from the base substrate. The first electrode is arranged on the opening-facing side of the non-closed region, and a size of the first electrode in the second direction is greater than or equal to the first distance.
[0023] In some embodiments, the above-mentioned transistor provided in the embodiments of the present disclosure further includes a second electrode located on the side of the active layer away from the base substrate, the orthographic projection of the second electrode on the base substrate is arranged around the orthographic projection of the first gate on the base substrate, and the orthographic projection shape of the second electrode on the base substrate is the same as the orthographic projection shape of the first gate on the base substrate.
[0024] In some embodiments, the transistor provided in the embodiments of the present disclosure further includes an insulating layer between the layer where the second electrode is located and the active layer, and the second electrode is coupled to the active layer through a plurality of vias penetrating the insulating layer.
[0025] In some embodiments, the above-mentioned transistor provided in the embodiment of the present disclosure further includes a second electrode located on the side of the active layer away from the substrate, and the orthographic projection of the second electrode on the substrate is located on one side of the orthographic projection of the first gate on the substrate.
[0026] In some embodiments, the transistor provided in the embodiments of the present disclosure further includes an insulating layer located between the layer where the second electrode is located and the active layer, and the second electrode is coupled to the active layer through a via hole penetrating the insulating layer.
[0027] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, the material of the active layer includes polysilicon, and the active layer also includes a disordered region adjacent to the channel region, and a peripheral region located on the side of the disordered region away from the channel region, wherein the polysilicon size of the channel region is 270nm~330nm, the polysilicon size of the disordered region is less than 100nm, and the polysilicon size of the peripheral region is 100nm~1000nm.
[0028] On the other hand, an embodiment of the present disclosure provides a pixel circuit, including the above-mentioned transistor provided by an embodiment of the present disclosure.
[0029] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned pixel circuit provided by an embodiment of the present disclosure, and a light-emitting unit coupled to the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG1 is a schematic diagram showing the composition of pixel power consumption in the display area;
[0031] FIG2 is a schematic diagram of a structure of a transistor in the related art;
[0032] FIG3 is another structural diagram of a transistor in the related art;
[0033] FIG4 is a schematic structural diagram of a transistor provided in an embodiment of the present disclosure;
[0034] FIG5 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0035] FIG6 is a cross-sectional view along line I-II in FIG5 ;
[0036] FIG7 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0037] FIG8 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0038] FIG9 is a cross-sectional view along line III-IV in FIG8 ;
[0039] FIG10 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0040] FIG11 is a schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;
[0041] FIG12 is a cross-sectional view along line V-VI in FIG11;
[0042] FIG13 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0043] FIG14 is a cross-sectional view along line VII-VIII in FIG13;
[0044] FIG15 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0045] FIG16 is a cross-sectional view along line IX-X in FIG15;
[0046] FIG17 is a schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;
[0047] FIG18 is a curve showing the relationship between the transistor area and the channel width according to an embodiment of the present disclosure;
[0048] FIG19 is a schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;
[0049] FIG20 is a schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;
[0050] FIG21 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0051] FIG22 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0052] FIG23 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0053] FIG24 is a schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;
[0054] FIG25 is another structural diagram of a transistor provided in an embodiment of the present disclosure;
[0055] FIG26 is a transfer characteristic curve of a transistor according to an embodiment of the present disclosure;
[0056] FIG27 is an Id-Vd high voltage test curve of the transistor shown in FIG5 provided by an embodiment of the present disclosure;
[0057] FIG28 is an Id-Vd high voltage test curve of the transistor shown in FIG25 provided by an embodiment of the present disclosure;
[0058] FIG29 is a picture of the m region in the transistor shown in FIG25 ;
[0059] FIG30 is a partial enlarged view of the channel region in FIG29;
[0060] FIG31 is a partial enlarged view of the disordered area in FIG29;
[0061] FIG32 is a partial enlarged view of the peripheral area in FIG29;
[0062] FIG33 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure applied to an LTPO backplane;
[0063] FIG34 is a schematic diagram of the structure of the LTPO backplane shown in FIG33 during the manufacturing process;
[0064] FIG35 is another structural schematic diagram of the LTPO backplane shown in FIG33 during the manufacturing process;
[0065] FIG36 is another structural schematic diagram of the LTPO backplane shown in FIG33 during the manufacturing process;
[0066] FIG37 is another structural schematic diagram of the LTPO backplane shown in FIG33 during the manufacturing process;
[0067] FIG38 is another structural schematic diagram of the LTPO backplane shown in FIG33 during the manufacturing process;
[0068] FIG39 is another structural schematic diagram of the LTPO backplane shown in FIG33 during the manufacturing process;
[0069] Figure 40 is another structural schematic diagram of the LTPO backplane shown in Figure 33 during the manufacturing process. DETAILED DESCRIPTION
[0070] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.
[0071] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0072] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.
[0073] The power consumption of MLED display backplane mainly includes the pixel power consumption of display (AA) area and logic power consumption. As shown in Figure 1, the pixel power consumption of display area P pixel Equal to the power consumption P of the light emitting diode (LED) LED , power consumption P of transistors (including light emitting control transistor S TFT and driving transistor D TFT) TFT , and the power consumption P caused by the voltage drop of high-level signal (VDD IR drop) and the voltage drop of low-level signal (VSS IR drop) IR_Drop , that is, P pixel =P LED +P TFT +P IR_Drop When the brightness is determined, at a fixed resolution (PPI), the light-emitting diodes require the same current, and their power consumption P LED is a fixed value; if you need to further reduce the pixel power consumption P pixel , it is necessary to reduce the power consumption P of the transistor in the current branch TFT And the loss P caused by the voltage drop (IR drop) in the display areaIR_Drop .
[0074] Transistor power consumption P TFT Equal to the transistor's output current I ds (equivalent to the operating current I of the light-emitting diode connected in series with the transistor LED ) and the transistor's source / drain voltage difference V ds The product of P TFT =I LED *V ds =I ds *V ds From this, we can see that by improving the current output capability of the transistor or reducing the source / drain voltage difference V under the required current ds Both can reduce transistor power consumption P TFT In addition to improving the current output capability of the transistor in terms of process, the source / drain voltage difference V can be reduced by increasing the channel width or reducing the channel length. ds As shown in Figures 2 and 3, a transistor includes a gate (G), a source (S), a drain (D), and an active layer (A). Usually, the transistor adopts the I-type structure shown in Figure 2. When the channel width is large, a similar series connection method as shown in Figure 3 is adopted. However, when the resolution (PPI) is fixed, several transistors, capacitors, and vias of the pixel circuit must be placed within the limited pixel area, resulting in extremely limited space for increasing the channel width of the transistor shown in Figure 3. Therefore, how to increase the channel width of the transistor and thus reduce the source / drain voltage difference V ds , thereby achieving the purpose of reducing power consumption, is a technical problem that technical personnel in this field urgently need to solve.
[0075] In order to at least improve the above technical problems existing in the related art, an embodiment of the present disclosure provides a transistor, as shown in FIG4 to FIG6 , including:
[0076] The base substrate 101 , optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like.
[0077] The first gate 102 is located on one side of the substrate 101; the first gate 102 may include a first portion 1021 and a second portion 1022 connected to each other; wherein the first portion 1021 extends along a first direction Y, and the first portion 1021 includes a first main portion 211 connected to the second portion 1022; the second portion 1022 extends along a second direction X, and the second portion 1022 includes a second main portion 221 connected to the first portion 1021, and the second direction X is perpendicular to the first direction Y. In the present disclosure, due to the limitations of process conditions or other factors such as measurement, the above-mentioned "perpendicular" relationship may be exactly 90°, or there may be some deviation (for example, a floating of plus or minus 5°). Therefore, as long as the "perpendicular" relationship between the above features meets the tolerance, it falls within the scope of protection of the present disclosure. In some embodiments, the material of the first gate 102 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., and the first gate 102 may have a single-layer structure or a stacked structure.
[0078] The active layer 103 is disposed on the same side of the base substrate 101 as the first gate 102, and includes a channel region 1031. The orthographic projection of the channel region 1031 on the base substrate 101 overlaps at least with the orthographic projection of the first main portion 211 and the orthographic projection of the second main portion 221 on the base substrate 101. The width a of the channel region 1031 is greater than or equal to the sum of the dimension a1 of the first main portion 211 in the first direction Y and the dimension a2 of the second main portion 221 in the second direction X. In some embodiments, the material of the active layer 103 may be polycrystalline silicon (P-Si), amorphous silicon (a-Si), an oxide (e.g., indium gallium zinc oxide (IGZO)), etc., without limitation herein.
[0079] Comparing the transistors shown in FIG. 4 and FIG. 5 of the present disclosure with the transistor shown in FIG. 2 of the related art, it can be seen that, under the same area, the channel width a of the transistor provided by the present disclosure is at least increased by the dimension a1 of the first main portion 211 in the first direction Y or the dimension a2 of the second main portion 221 in the second direction X compared to the transistor shown in FIG. 2 . Therefore, under the same resolution, the channel width of the transistor can be effectively increased, thereby reducing the source / drain voltage difference V of the transistor. ds , to achieve the purpose of reducing power consumption.
[0080] 4 , it can be seen that the first gate 102 can be composed of a first part 1021 and a second part 1022, that is, the first gate 102 has an "L"-shaped structure; the orthographic projection of the channel region 1031 on the base substrate 101 overlaps with the orthographic projection of the first main body 211 on the base substrate 101, and the orthographic projection of the second main body 221 on the base substrate 101, so that the channel region 1031 also has an "L"-shaped structure, and the width a of the channel region 1031 is equal to the sum of the dimension a1 of the first main body 211 in the first direction Y and the dimension a2 of the second main body 221 in the second direction X.
[0081] In other embodiments, as shown in FIG5 , the first gate 102 may further include a third portion 1023 connected to the second portion 1022. The third portion 1023 extends along the first direction Y and is spaced apart from the first portion 1021 in the second direction X. The third portion 1023 includes a third main portion 231 connected to the second portion 1022. The orthographic projection of the third main portion 231 on the substrate 101 overlaps with the orthographic projection of the channel region 1031 on the substrate 101. In this case, the first gate 102 and the channel region 1031 both have a "U"-shaped structure. Accordingly, the width a of the channel region 1031 is equal to the sum of the dimension a1 of the first main portion 211 in the first direction Y, the dimension a2' of the second portion 1022 in the second direction X, and the dimension a3 of the third main portion 231 in the first direction Y. This further increases the channel width a of the transistor, further reducing the source / drain voltage difference Vds of the transistor and lowering power consumption.
[0082] In some embodiments, the first gate 102 of the present disclosure can be a bottom gate located between the substrate 101 and the active layer 103, as shown in Figures 7 to 9; or the first gate 102 can be a top gate located on the side of the active layer 103 away from the substrate 101, as shown in Figures 10 to 12. In other words, the transistor provided by the present disclosure is a single-gate transistor having only a bottom gate or a top gate.
[0083] Optionally, when the first gate 102 is a bottom gate, a mask for making the bottom gate can be used for exposure to form a photoresist (PR) mask to complete the U-shaped channel doping. At this time, as shown in Figure 7, the orthographic projection of the channel region 1031 on the substrate 101 roughly coincides with the orthographic projection of the first main body 211 on the substrate 101 and the orthographic projection of the second main body 221 on the substrate 101; or, as shown in Figure 8, the orthographic projection of the channel region 1031 on the substrate 101 roughly coincides with the orthographic projection of the first main body 211 on the substrate 101, the second main body 221, and the orthographic projection of the third main body 231 on the substrate 101.
[0084] When the first gate 102 is a top gate, the U-shaped channel doping can be completed by shielding with the top gate; at this time, as shown in Figure 10, the orthographic projection of the channel region 1031 on the substrate 101 roughly coincides with the orthographic projection of the first main body 211 on the substrate 101, and the orthographic projection of the second main body 221 on the substrate 101; or, as shown in Figure 11, the orthographic projection of the channel region 1031 on the substrate 101 roughly coincides with the orthographic projection of the first main body 211 on the substrate 101, the second main body 221, and the orthographic projection of the third main body 231 on the substrate 101.
[0085] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the "rough overlap" may be exactly overlapped, or there may be some deviations (for example, a deviation of ±2μm). Therefore, as long as the "rough overlap" relationship between related features meets the error allowance, it falls within the scope of protection of the present disclosure.
[0086] In other embodiments, the transistor provided by the present disclosure may also be a dual-gate transistor. Specifically, as shown in Figures 4 to 6, the transistor further includes a second gate 104, and one of the second gate 104 and the first gate 102 is located between the active layer 103 and the base substrate 101, and the other is located on the side of the active layer 103 away from the base substrate 101. The present disclosure is explained by taking the example in which the first gate 102 is located on the side of the active layer 103 away from the base substrate 101 and the second gate 104 is located between the active layer 103 and the base substrate 101. During the fabrication of the dual-gate transistor, a top gate (e.g., the first gate 102) can be used for shielding to complete U-shaped channel doping; so that the orthographic projection of the channel region 1031 shown in FIG4 on the substrate 101 roughly coincides with the orthographic projection of the first main portion 211 on the substrate 101, and the orthographic projection of the second main portion 221 on the substrate 101; and the orthographic projection of the channel region 1031 shown in FIG5 on the substrate 101 roughly coincides with the orthographic projection of the first main portion 211 on the substrate 101, the second main portion 221, and the orthographic projection of the third main portion 231 on the substrate 101.
[0087] In some embodiments, the second gate 104 of the present disclosure can have the same structure as the first gate 102, that is, the second gate 104 can have the same components as the first gate 102. For example, in FIG4 , the first gate 102 and the second gate 104 are both "L"-shaped structures consisting of two parts; in FIG5 , the first gate 102 and the second gate 104 are both "U"-shaped structures consisting of three parts. Optionally, the orthographic projection of the first gate 102 on the substrate 101 can be the same size as the orthographic projection of the second gate 104 on the substrate 101. In other embodiments, such as in an oxide transistor, where the first gate 102 is the top gate and the second gate 104 is the bottom gate, the second gate 104, as the bottom gate, can be larger to prevent light from affecting the oxide active layer. That is, the orthographic projection of the first gate 102 on the substrate 101 can be located within the orthographic projection of the second gate 104 on the substrate 101.
[0088] In some embodiments, as shown in FIG13 , the first gate 102 and the second gate 104 can be coupled via a first via h1, so that the driving signals of the first gate 102 and the second gate 104 are the same, thereby improving the current output capability of the transistor. Continuing with FIG13 , it can be seen that the first gate 102 and the second gate 104 can be switched via a conductive structure 105. Optionally, the conductive structure 105 is formed in the same layer and material as the first electrode 106 and the second electrode 107 of the transistor, and as shown in FIG14 , the first via h1 connecting the first gate 102 and the conductive structure 105 penetrates the insulating layer 108 and the second gate insulating layer 109, and the first via h1 connecting the second gate 104 and the conductive structure 105 penetrates the insulating layer 108, the second gate insulating layer 109, the first gate insulating layer 110, and the first buffer layer 111. As can be seen from Figures 5 and 6 , the first electrode 106 is ohmically connected to the active layer 103 via a second via hole h2 extending through the insulating layer 108, the second gate insulating layer 109, and the first gate insulating layer 110. The second electrode 107 is ohmically connected to the active layer 103 via a third via hole h3 extending through the insulating layer 108, the second gate insulating layer 109, and the first gate insulating layer 110. When the first gate 102 and the second gate 104 are coupled via the conductive structure 105 on the same layer as the first electrode 106 and the second electrode 107, the first via hole h1, the second via hole h2, and the second via hole h3 can be fabricated using a single masking process, eliminating the need to separately mask the first gate insulating layer 110 and the first buffer layer 111 to form via holes to couple the first gate 102 and the second gate 104. Of course, in a specific implementation, the first gate insulating layer 110 and the first buffer layer 111 can also be masked to form vias separately, so that the first gate 102 is coupled to the second gate 104 through the first via h1 that penetrates the first gate insulating layer 110 and the first buffer layer 111, as shown in Figures 15 and 16. In other embodiments, as shown in Figure 17, the second gate 104 can be coupled to the first electrode 106, so that the second gate 104 and the first electrode 106 form the same signal, which can improve the current output stability of the transistor. In other embodiments, as shown in Figures 4 and 5, the first gate 102, the second gate 104, and the first electrode 106 are independent of each other, so that the threshold voltage (TFT V th ) and other characteristics.
[0089] In order to better illustrate that the transistor provided by the present disclosure can increase the channel width and reduce power consumption under the condition of fixed resolution, the U-type transistor shown in FIG5 provided by the present disclosure is compared with the I-type transistor shown in FIG2. Specifically, in FIG2 and FIG5, a represents the width of the channel region 1031, b represents the length of the channel region 1031, c represents the distance between the orthographic projection of the second gate 104 on the substrate 101 and the orthographic projection of the first pole 106 on the substrate 101, d represents the distance between the orthographic projection of the second gate 104 on the substrate 101 and the orthographic projection of the second pole 107 on the substrate 101, and e represents the distance between the orthographic projection of the second gate 104 on the substrate 101 and the orthographic projection of the first pole 102 on the substrate 101, f represents the distance that the orthographic projection of the first gate 102 on the substrate 101 exceeds the orthographic projection of the active layer 103 on the substrate 101, g represents the aperture of the ohmic contact hole (such as the second via h2, the third via h3), h represents the length of the first electrode 106 or the second electrode 107 wrapped around the via hole, i represents the length of the first electrode 106, and j represents the width of the first electrode 106, wherein a=(i+c+e+b / 2)*2+j+c*2+e*2+b in FIG5. Specifically, the area S of the I-type transistor shown in FIG2 is I The formula is S I =(2c+2e+2k+b)*W I +(b+2c+2e+2k)(2f+2e), where W I Equivalent to the area a of the I-type transistor shown in Figure 2; the area S of the U-type transistor in Figure 5 U The formula is S U =(2c+2e+1.5k+b)*W U +(b+2c+2e+1.5k)(2f+2e)+k(b+2c+2e+1.5k) where W U Equivalent to a of the U-type transistor shown in FIG5; k in both formulas = g + h * 2. Optionally, when other parameters other than a (i.e., channel width W) shown in FIG2 and FIG5 are constant, there will be an intersection point when the area of the two changes with the value of a (i.e., channel width W). When the value of a (i.e., channel width W) is less than the intersection point, the area S of the I-type transistor I Smaller than the area S of the U-shaped transistor U , when it is greater than the value of a (i.e., the channel width W) at the intersection, the area S of the U-shaped transistor U Smaller than the area S of an I-type transistor IFor example, when b (i.e., channel length L) is 5 μm, c is 1.5 μm, d is 1.5 μm, e is 0.6 μm, f is 2 μm, g is 1.8 μm, and h is 1.1 μm, as shown in FIG18 , the areas of the two are the same when a (i.e., channel width W) is 26 μm. When it is less than 26 μm, the area S of the I-type transistor is I Smaller than the area S of the U-shaped transistor U , when it is greater than 26μm, the area S of the U-type transistor U Smaller than the area S of an I-type transistor I When b (i.e., channel length L) is 3 μm, c is 1.5 μm, d is 1.5 μm, e is 0.6 μm, f is 2 μm, g is 1.8 μm, and h is 1.1 μm, as shown in FIG18 , the areas of the two are the same when a (i.e., channel width W) is 22 μm. When it is less than 22 μm, the area S of the I-type transistor is I Smaller than the area S of the U-shaped transistor U , when it is greater than 22μm, the area S of the U-type transistor U Smaller than the area S of an I-type transistor I Therefore, the U-shaped transistor provided by the present disclosure is more suitable for application scenarios where the channel width is larger and the power consumption can be reduced.
[0090] In addition, when setting the area S of the I-type transistor I The area S of the U-shaped transistor U Same (ie S I =S u ), the channel width W of the U-type transistor can be obtained u The channel width W of the I-type transistor I The relationship is: In this relationship, if b (i.e., channel length L) is 5 μm, c is 1.5 μm, d is 1.5 μm, e is 0.6 μm, f is 2 μm, g is 1.8 μm, and h is 1.1 μm, then W U =1.13*W I -3.03, for example W I When W is 50μm, U =53.5μm; if b (i.e. channel length L) is 3μm, c is 1.5μm, d is 1.5μm, e is 0.6μm, f is 2μm, g is 1.8μm, h is 1.1μm, then W U =1.15*W I -2.92, for example, W I When W is 50μm, U It can be seen that the U-type transistor provided by the present disclosure is more suitable for application scenarios with larger channel width and lower power consumption than the I-type transistor in the related art.
[0091] In some embodiments, in the above-mentioned transistor provided in the embodiment of the present disclosure, as shown in FIG5 , the dimension a1 of the first main portion 211 in the first direction Y is equal to the dimension a3 of the third main portion 231 in the first direction Y, so that the first gate 102 and the second gate 104 are both symmetrical "U"-shaped structures. It should be understood that due to the limitations of process conditions or the influence of other factors such as measurement, the "equal" in the present disclosure may be completely identical or there may be some deviation (e.g., a deviation of ±5%). Therefore, as long as the "equal" relationship between the relevant features meets the error tolerance, it falls within the scope of protection of the present disclosure. In other embodiments, as shown in FIG19 , the dimension a1 of the first main portion 211 in the first direction Y and the dimension a3 of the third main portion 231 in the first direction Y may also be unequal, for example, the dimension a1 of the first main portion 211 in the first direction Y is greater than the dimension a3 of the third main portion 231 in the first direction Y. In this case, the first gate 102 and the second gate 104 are both asymmetrical "U"-shaped structures.
[0092] In some embodiments, as shown in Figures 20 and 21, the first gate 102 may further include a connecting portion 1024 extending along a third direction Z (the third direction Z intersects with the first direction Y and the second direction X), and the second main body 221 is connected to the first main body 211 or the third main body 231 through the connecting portion 1024, so that the second main body 221 gradually transitions to the first main body 211 or the third main body 231 via the connecting portion 1024, avoiding that the connection between the second main body 221 and the first main body 211 or the third main body 231 is too abrupt. In a specific implementation, the connection portion 1024 can be a straight line extending along the third direction Z as shown in Figure 20, which is equivalent to making a bevel angle design at the connection between the second main body portion 221 and the first main body portion 211 or the third main body portion 231, for example, the bevel angle can be 45°; or, the connection portion 1024 can also be an arc type extending along the third direction Z as shown in Figure 21, which is equivalent to making a rounded corner treatment at the connection between the second main body portion 221 and the first main body portion 211 or the third main body portion 231, for example, the rounded corner can be 45°.
[0093] 20 and 21 , it can be seen that in some embodiments, the orthographic projection of the connecting portion 1024 on the base substrate 101 may overlap with the orthographic projection of the channel region 1031 on the base substrate 101. This ensures that the channel region 1031 gradually transitions at the intersection with the connecting portion 1024, so that the length b of the channel region 1031 is more uniform, specifically, the dimension b1 of the first main portion 211 in the second direction X, the dimension b2 of the second main portion 221 in the first direction Y, the dimension b3 of the third main portion 231 in the second direction X, and the dimension b4 of the connecting portion 1024 in the fourth direction Z' (the fourth direction Z' is perpendicular to the third direction Z) are equal, thereby improving the stability of the transistor output current.
[0094] In some embodiments, as shown in Figures 20 and 21, when the first gate 102 includes the connecting portion 1024, the orthographic projection of the first main portion 211 on the base substrate 101, the orthographic projection of the second main portion 221 on the base substrate 101, and the orthographic projection of the third main portion 231 on the base substrate 101 are no longer rectangular but trapezoidal, and the width a of the channel region 1031 can be equal to the sum of the midline dimension a1' of the first main portion 211 in the first direction Y, the midline dimension a2" of the second portion 1022 in the second direction X, the midline dimension a3' of the third main portion 231 in the first direction Y, and the midline dimension a4' of the connecting portion 1024 in the third direction Z.
[0095] It should be noted that, since the transistor provided in the present disclosure has both a first gate 102 and a second gate 104 , the second gate 104 has the same structure as the first gate 102 . Therefore, when the first gate 102 includes a connecting portion 1024 , the second gate 104 may also have a connecting portion 1024 .
[0096] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, as shown in Figures 4, 5, 19 to 21, in order to rationally utilize space, the first electrode 106 can be arranged in the area enclosed by the first part 1021 and the second part 1022, and in order to reduce the coupling capacitance between the first electrode 106 and the first gate 102, the orthographic projection of the first electrode 106 on the substrate 101 and the orthographic projection of the first part 1021 on the substrate 101 and the orthographic projection of the second part 1022 on the substrate 101 can be respectively spaced apart. Optionally, as shown in Figures 5 and 19, when the first gate 102 has a first part 1021, a second part 1022, and a third part 1023 at the same time, the first pole 106 can be specifically arranged in an area jointly enclosed by the first part 1021, the second part 1022, and the third part 1023 (i.e., within the U-shaped opening), and the orthographic projection of the first pole 106 on the base substrate 101 is spaced apart from the orthographic projection of the first part 1021 on the base substrate 101, the orthographic projection of the second part 1022 on the base substrate 101, and the orthographic projection of the third part 1023 on the base substrate 101. In addition, in Figures 20 and 21, the first gate 102 has a first portion 1021, a second portion 1022, a third portion 1023 and a connecting portion 1024. The first pole 106 can be specifically arranged in an area jointly enclosed by the first portion 1021, the second portion 1022, the third portion 1023, and the connecting portion 1024 (i.e., within the U-shaped opening), and the orthographic projection of the first pole 106 on the base substrate 101 is spaced apart from the orthographic projection of the first portion 1021 on the base substrate 101, the orthographic projection of the second portion 1022 on the base substrate 101, the orthographic projection of the third portion 1023 on the base substrate 101, and the orthographic projection of the connecting portion 1024 on the base substrate 101.
[0097] In some embodiments, in the above-mentioned transistor provided in the embodiments of the present disclosure, as shown in Figures 22 to 25, the first pole 106 can also be arranged on the opening-facing side (i.e., outside the U-shaped opening) of the non-closed area enclosed by the first part 1021, the second part 1022 and the third part 1023, and the dimension of the first pole 106 in the second direction X (i.e., the width j of the first pole 106) is greater than the first distance n between the first part 1021 and the third part 1023. Optionally, as shown in Figures 22 to 24, the first pole 106 can be arranged opposite the U-shaped opening, so that the orthographic projection of the area enclosed by the first part 1021, the second part 1022 and the third part 1023 (i.e., the U-shaped opening) in the second direction X is located within the orthographic projection of the first pole 106 in the second direction X; or, as shown in Figure 25, the first pole 106 can be offset relative to the U-shaped opening, so that the orthographic projection of the area enclosed by the first part 1021, the second part 1022 and the third part 1023 (i.e., the U-shaped opening) in the second direction X partially overlaps with the orthographic projection of the first pole 106 in the second direction X.
[0098] It should be understood that in the schemes described above in Figures 5 and 19 to 21 , where the first electrode 106 is positioned within the U-shaped opening, the first distance n between the first portion 1021 and the third portion 1023 satisfies the relationship: n = j + 2c, where j is the width of the first electrode 106 and c is the distance between the orthographic projection of the first electrode 106 on the substrate 101 and the orthographic projection of the second gate 104 on the substrate 101. In contrast, in the schemes described in Figures 22 to 25 , where the first electrode 106 is positioned outside the U-shaped opening, the first distance n between the first portion 1021 and the third portion 1023 can be less than or equal to the width j of the first electrode 106. Therefore, the value of the first distance n can be reduced. In some embodiments, the first distance n only needs to meet the exposure capability. A smaller first distance n can ensure a smaller transistor area. In addition, transistors of this structure can also have a larger channel width than "I"-type transistors. For example, compared with "I"-type transistors, under the same area, when the channel width of the "I"-type transistor is 30μm and the channel length is 5μm, the channel width of the "U"-type transistor can be 35μm and the channel length is still 5μm; when the channel width of the "I"-type transistor is 30μm and the channel length is 3μm, the channel width of the "U"-type transistor can be 38μm and the channel length is still 3μm.
[0099] In some embodiments, in the transistor provided in the embodiments of the present disclosure, as shown in FIG5 , the orthographic projection of the second electrode 107 on the substrate 101 is arranged around the orthographic projection of the first gate 102 on the substrate 101, and the orthographic projection of the second electrode 107 on the substrate 101 has the same shape as the orthographic projection of the first gate 102 on the substrate 101. In this case, due to the larger area of the second electrode 107, to enhance the ohmic contact effect, as shown in FIG5 , the second electrode 107 can be coupled to the active layer 103 via a plurality of third vias h3. Optionally, the orthographic projections of the plurality of third vias h3 on the substrate 101 are evenly dispersed around the orthographic projection of the first gate 102 on the substrate 101.
[0100] In Figure 5, the second pole 107 has a U-shaped structure. Considering that the second pole 107 with a U-shaped structure occupies a large area, in order to further reduce the area of the second pole 107 and thus reduce the area of the transistor, in other embodiments, as shown in Figure 25, the orthographic projection of the second pole 107 on the base substrate 101 can also be set on one side of the orthographic projection of the first gate 102 on the base substrate 101; optionally, the second pole 107 is coupled to the active layer 103 through a third via h3. Under the premise that the size of the transistor (channel width-to-length ratio of 30 / 5) remains unchanged, the lateral size of the transistor shown in Figure 5 in the second direction X is 34.4μm, and the lateral size of the transistor shown in Figure 25 in the second direction X is 21.5μm. The area of the transistor shown in Figure 25 can be reduced to 62.5% of the area of the transistor shown in Figure 5; at the same time, as shown in Figure 26, the transfer characteristics of the transistor (T25) shown in Figure 25 and the transistor (T5) shown in Figure 5 are almost the same; and by comparing the Id-Vd high-voltage test curve of the transistor in Figure 5 shown in Figure 27 and the Id-Vd high-voltage test curve of the transistor in Figure 25 shown in Figure 28, it can be seen that the transistor shown in Figure 25 has a stronger high-voltage tolerance capability. In the Id-Vd high-voltage test (VD: 0~-30V; VG: 0~-40V), the transistor shown in Figure 5 will fail when VG is -36V, while the characteristics of the transistor shown in Figure 25 are still normal when VG>-40V.
[0101] During the preparation of the transistor shown in FIG. 25 , amorphous silicon (a-Si) needs to be deposited on a U-shaped light-shielding structure (LS, which can be reused with the second gate 104 ) and then laser annealing (ELA) crystallized to form a polysilicon material for the active layer 103 . However, because the thermal conductivity of LS is strong, as shown in FIG29 , there is a clear dividing line (i.e., the disordered region 1033) between the polysilicon above LS (corresponding to the channel region 1031) and the polysilicon around LS (i.e., the peripheral region 1032); as shown in FIG30 , the polysilicon in the channel region 1031 has good size uniformity, with an average grain size of 270 nm to 330 nm, regular shape, and regular arrangement (mostly tetragonal grains); as shown in FIG31 , the polysilicon in the disordered region 1033 is all broken small grains, with a grain size generally less than 100 nm, irregular shape, and irregular arrangement; as shown in FIG32 , the polysilicon grains in the peripheral region 1032 are uneven in size, with a size distribution between 100 nm and 1000 nm, irregular shape, and irregular arrangement.
[0102] LTPO technology is a new type of display technology that can effectively reduce screen power consumption and improve display effects. LTPO technology can achieve a lower refresh rate and higher brightness on the display screen, and can extend battery life. Compared with traditional LTPS technology, it has the advantages of reduced power consumption, integrated gate drive to achieve narrow borders, and good resolution. The above-mentioned transistors provided in the present disclosure can be applied not only to LTPS products, but also to LTPO products. Optionally, in the LTPS product, the second via h2 for connecting the first electrode 106 and the active layer 103, and the third via h3 for connecting the second electrode 107 and the active layer 103 can be prepared in the previous process of manufacturing the first electrode 106 and the second electrode 107, as shown in Figure 5; in the LTPO product, the film layer is adjusted according to the specific process flow such as LTPO, and after the bottom gate 201, the oxide active layer 202, and the top gate 203 of the oxide transistor (Oxide TFT) 200 are completed, and before the source 204 and the drain 205 of the oxide transistor 200 are manufactured, holes (including the second via h2, the third via h3, the fourth via h4, and the fifth via h5) are opened to facilitate connecting the active layer 103 of the transistor provided by the present disclosure to the first electrode 106 through the second via h2, connecting the active layer 103 of the transistor provided by the present disclosure to the second electrode 107 through the third via h3, and connecting the active layer 103 of the transistor provided by the present disclosure to the second electrode 107 through the fourth via h4. The oxide active layer 202 of the oxide transistor is connected to the source 204 , and the oxide active layer 202 of the oxide transistor is connected to the drain 205 through a fifth via hole h5 , as shown in FIG. 33 .
[0103] The following describes the method for manufacturing the transistor shown in FIG5 provided in the embodiment of the present disclosure in conjunction with the manufacturing process of the LTPO backplane shown in FIG33.
[0104] In the first step, a first conductive layer is deposited on the base substrate 101 and patterned to form a second gate 104 , as shown in FIG34 ; and the second gate 104 has a “U”-shaped structure as shown in FIG5 .
[0105] In the second step, a first buffer layer 111 and an amorphous silicon layer are sequentially formed on the layer where the second gate 104 is located. After the amorphous silicon layer is crystallized into an intrinsic polysilicon layer by laser annealing (ELA), the intrinsic polysilicon layer is patterned to form the active layer 103, as shown in FIG35 . Optionally, during the laser annealing process, a certain energy density (depending on the buffer thickness) can be added to the OED based on the optimal energy density (OED) of the peripheral region as determined by the human eye and the thickness of the first buffer layer 111 as a crystallization condition above the second gate 104 to ensure the crystallization quality of the polysilicon above the second gate 104.
[0106] In the third step, as shown in FIG36 , a first gate insulating layer 110 and a second conductive layer are sequentially deposited on the active layer 103, and the second conductive layer is patterned to form a first gate 102. The first gate 102 is then used to shield the channel region 1031 of the active layer 103, and the region outside the exposed channel region 1031 (which may be referred to as the ohmic contact region) is heavily doped, so that the intrinsic polysilicon in the region outside the channel region 1031 (which may be referred to as the ohmic contact region) is converted into conductive heavily doped polysilicon, thereby facilitating ohmic contact between the active layer 103 and the subsequent first electrode 106 and second electrode 107. Specifically, the first gate 102 has a "U"-shaped structure as shown in FIG5 , and the channel region 1031 is also U-shaped.
[0107] In the fourth step, a second gate insulating layer 109 , a first interlayer dielectric layer 112 and a third conductive layer are sequentially formed on the layer where the first gate 102 is located, and the third conductive layer is patterned to form the bottom gate 201 of the oxide transistor 200 , as shown in FIG. 37 .
[0108] In the fifth step, a second buffer layer 113 and an oxide layer are sequentially formed on the layer where the bottom gate 201 is located, and after patterning the oxide layer, an oxide active layer 202 located above the bottom gate 201 is formed, as shown in FIG. 38 .
[0109] In the sixth step, a third gate insulating layer 114 and a fourth conductive layer are sequentially formed on the oxide active layer 202 , and the fourth conductive layer is patterned to form a top gate 203 located above the oxide active layer 202 , as shown in FIG. 39 .
[0110] In the seventh step, a second interlayer dielectric layer 115 is formed on the layer where the top gate 203 is located, and a fourth via hole h4 and a fifth via hole h5 are formed through the second interlayer dielectric layer 115 and the third gate insulating layer 114, as well as a second via hole h2 and a third via hole h3 are formed through the second interlayer dielectric layer 115, the third gate insulating layer 114, the second buffer layer 113, the first interlayer dielectric layer 112, the second gate insulating layer 109 and the first gate insulating layer 110, so as to facilitate connecting the active layer 103 of the "U"-shaped transistor to the first electrode 106 to be subsequently manufactured through the second via hole h2, connecting the active layer 103 of the "U"-shaped transistor to the second electrode 107 to be subsequently manufactured through the third via hole h3, connecting the oxide active layer 202 of the oxide transistor to the source electrode 204 to be subsequently manufactured through the fourth via hole h4, and connecting the oxide active layer 202 of the oxide transistor to the drain electrode 205 to be subsequently manufactured through the fifth via hole h5, as shown in Figure 40.
[0111] In the eighth step, a fifth conductive layer is formed on the second interlayer dielectric layer 115 and patterned to form the first electrode 106 and the second electrode 107 of the U-shaped transistor, and the source 204 and the drain 205 of the oxide transistor, as shown in FIG33 .
[0112] In some embodiments, the manufacturing process of the LTPO backplane may further include: forming a first flat layer, a first passivation layer, and a sixth conductive layer in sequence on the layer where the first pole 106 and the second pole 107 are located, and patterning the sixth conductive layer to form a high-level signal (VDD) line, etc., and then forming a second flat layer, a second passivation layer, and a seventh conductive layer in sequence on the layer where the high-level signal line is located, and patterning the seventh conductive layer to form a pad for binding the light-emitting device; finally, a third passivation layer may be formed on the layer where the pad is located, and the third passivation layer includes an opening to expose the pad. Of course, in specific implementation, the manufacturing process of the LTPO backplane may also include other steps well known to those skilled in the art, which will not be elaborated here.
[0113] It should be noted that in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process steps such as deposition, photoresist coating, mask template masking, exposure, development, etching, photoresist stripping, etc., but may also include other process steps, which are subject to the formation of the required patterned pattern in the actual manufacturing process and are not limited here. For example, a post-baking process may be included after development and before etching. In some embodiments, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which are not limited here; the mask plate used in the masking process may be a half-tone mask plate (Half Tone Mask), a single slit diffraction mask plate (Single Slit Mask) or a gray tone mask plate (Gray Tone Mask), which are not limited here; etching may be dry etching or wet etching, which are not limited here.
[0114] Based on the same inventive concept, an embodiment of the present disclosure provides a pixel circuit, including the above-mentioned transistor provided in the embodiment of the present disclosure. Since the principle of solving the problem by the pixel circuit is similar to the principle of solving the problem by the above-mentioned transistor, the implementation of the pixel circuit provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned transistor provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.
[0115] Based on the same inventive concept, embodiments of the present disclosure provide a display device, including the aforementioned pixel circuit provided in embodiments of the present disclosure, and a light-emitting unit coupled to the pixel circuit. Optionally, the light-emitting unit is an OLED light-emitting device, an MLED light-emitting device, or a light-emitting pixel composed of a pixel electrode, a liquid crystal layer, and a common electrode. Because the principles for solving the problem solved by the display device are similar to those for solving the problem solved by the aforementioned transistor, the implementation of the display device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned transistor provided in embodiments of the present disclosure, and any repetitions will not be repeated.
[0116] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.
[0117] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.
[0118] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.
Claims
1. A transistor, wherein, Comprising: A substrate; A first gate located on one side of the substrate; the first gate includes a first part and a second part connected to each other; wherein, the first part extends in a first direction, the first part includes a first main body connected to the second part; the second part extends in a second direction, the second part includes a second main body connected to the first part, and the second direction is perpendicular to the first direction; An active layer, which is disposed on the same side of the substrate and in a different layer from the first gate, the active layer includes a channel region, and the orthographic projection of the channel region on the substrate at least overlaps with the orthographic projection of the first main body on the substrate and the orthographic projection of the second main body on the substrate, and the width of the channel region is greater than or equal to the sum of the dimension of the first main body in the first direction and the dimension of the second main body in the second direction.
2. The transistor according to claim 1, wherein The first gate further includes a third part connected to the second part, the third part extends in the first direction and is spaced from the first part in the second direction, the third part includes a third main body connected to the second part, and the orthographic projection of the third main body on the substrate overlaps with the orthographic projection of the channel region on the substrate.
3. The transistor according to claim 2, wherein, The width of the channel region is equal to the sum of the dimension of the first main body in the first direction, the dimension of the second part in the second direction, and the dimension of the third main body in the first direction.
4. The transistor according to claim 2, wherein, The dimension of the first main body in the first direction is equal to or different from the dimension of the third main body in the first direction.
5. The transistor according to claim 2, wherein, The first gate further includes a connecting part extending in a third direction, the second main body is connected to the first main body or the third main body through the connecting part; the orthographic projection of the connecting part on the substrate overlaps with the orthographic projection of the channel region on the substrate, and the third direction intersects with the first direction and the second direction.
6. The transistor according to claim 5, wherein, The width of the channel region is equal to the sum of the median line dimension of the first main body in the first direction, the median line dimension of the second part in the second direction, the median line dimension of the third main body in the first direction, and the median line dimension of the connecting part in the third direction.
7. The transistor according to claim 5 or 6, wherein The dimension of the first main body in the second direction, the dimension of the second main body in the first direction, the dimension of the third main body in the second direction, and the dimension of the connecting part in a fourth direction are equal, and the fourth direction is perpendicular to the third direction.
8. The transistor according to any one of claims 5 to 7, wherein, The connecting part is linear or arc-shaped.
9. The transistor according to any one of claims 1 to 8, wherein, The first gate is located between the substrate and the active layer, or on the side of the active layer away from the substrate.
10. The transistor according to any one of claims 1 to 8, wherein, It further includes a second gate, and one of the second gate and the first gate is located between the active layer and the substrate, and the other is located on the side of the active layer away from the substrate.
11. The transistor according to claim 10, wherein, It further includes a first electrode located on the side of the active layer away from the substrate; The first gate is coupled to the second gate, or the first gate or the second gate located between the active layer and the substrate is coupled to the first pole.
12. The transistor according to any one of claims 1 to 11, wherein, It further includes a first pole located on a side of the active layer away from the substrate; within the region enclosed by the first portion and the second portion, the orthographic projection of the first pole on the substrate is spaced apart from the orthographic projection of the first portion on the substrate and the orthographic projection of the second portion on the substrate, respectively.
13. The transistor according to any one of claims 1 to 11, wherein, The gate further includes a third portion connected to the second portion, the third portion extends along the first direction and has a first distance from the first portion in the second direction; the first portion, the second portion, and the third portion enclose a non-closed region; The transistor further includes a first pole located on a side of the active layer away from the substrate, the first pole is disposed on the side where the opening of the non-closed region faces, and the dimension of the first pole in the second direction is greater than or equal to the first distance.
14. The transistor according to any one of claims 1 to 13, wherein, It further includes a second pole located on a side of the active layer away from the substrate, the orthographic projection of the second pole on the substrate surrounds the orthographic projection of the first gate on the substrate, and the shape of the orthographic projection of the second pole on the substrate is the same as the shape of the orthographic projection of the first gate on the substrate.
15. The transistor according to claim 14, wherein, It further includes an insulating layer located between the layer where the second pole is located and the active layer, and the second pole is coupled to the active layer through a plurality of vias penetrating the insulating layer.
16. The transistor according to any one of claims 1 to 13, wherein, It further includes a second pole located on a side of the active layer away from the substrate, the orthographic projection of the second pole on the substrate is located on one side of the orthographic projection of the first gate on the substrate.
17. The transistor according to claim 16, wherein, It further includes an insulating layer located between the layer where the second pole is located and the active layer, and the second pole is coupled to the active layer through one via penetrating the insulating layer.
18. The transistor according to any one of claims 1 to 17, wherein, The material of the active layer includes polysilicon, the active layer further includes a disordered region adjacent to the channel region and a peripheral region located on a side of the disordered region away from the channel region, wherein the polysilicon dimension of the channel region is 270 nm to 330 nm, the polysilicon dimension of the disordered region is less than 100 nm, and the polysilicon dimension of the peripheral region is 100 nm to 1000 nm.
19. A pixel circuit, wherein, It includes the transistor according to any one of claims 1 to 18.
20. A display device, wherein, It includes the pixel circuit according to claim 19 and a light-emitting unit coupled to the pixel circuit.