Light-emitting chip, manufacturing method for light-emitting chip, display panel, and display device

Abstract

Provided is a light-emitting chip, comprising: a base substrate; a chip main body, which is located on the base substrate and comprises: a first electrode arranged on the base substrate, a first semiconductor layer arranged on the side of the first electrode distant from the base substrate, a light-emitting layer arranged on the side of the first semiconductor layer distant from the base substrate, a second semiconductor layer arranged on the side of the light-emitting layer distant from the base substrate, and a second electrode arranged on the side of the second semiconductor layer distant from the base substrate; and an auxiliary electrode, comprising a first auxiliary electrode and / or a second auxiliary electrode. The first auxiliary electrode is at least partially arranged around the periphery of the side wall of the first semiconductor layer, the first auxiliary electrode is insulated from the first semiconductor layer, and the first auxiliary electrode is configured to be connected to a first preset voltage; and / or the second auxiliary electrode is at least partially arranged around the periphery of the side wall of the second semiconductor layer, the second auxiliary electrode is insulated from the second semiconductor layer, and the second auxiliary electrode is configured to be connected to a second preset voltage.

Description

Light-emitting chip, method for manufacturing light-emitting chip, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a light-emitting chip, a method for preparing the light-emitting chip, a display panel, and a display device. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) are a next-generation display technology, boasting advantages such as self-luminescence, high efficiency, and high brightness. With the continuous advancement of augmented reality (AR) and virtual reality (VR) technologies, the size of Micro LED chips needs to be continuously reduced to meet product requirements. Research has shown that while the operating current density remains constant, the external quantum efficiency of Micro LEDs decreases dramatically as chip size decreases. How to avoid this reduction in external quantum efficiency while reducing Micro LED chip size is a key concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a light-emitting chip is provided, the light-emitting chip comprising:

[0006] substrate;

[0007] The chip body is located on the substrate, and the chip body includes: a first electrode disposed on the substrate; a first semiconductor layer disposed on a side of the first electrode away from the substrate; a light-emitting layer disposed on a side of the first semiconductor layer away from the substrate; a second semiconductor layer disposed on a side of the light-emitting layer away from the substrate; and a second electrode disposed on a side of the second semiconductor layer away from the substrate; and

[0008] Auxiliary electrodes, including first auxiliary electrodes and / or second auxiliary electrodes,

[0009] The first auxiliary electrode is at least partially disposed around the periphery of the sidewall of the first semiconductor layer, the first auxiliary electrode is insulated from the first semiconductor layer, and the first auxiliary electrode is configured to be connected to a first preset voltage; and / or

[0010] The second auxiliary electrode is at least partially disposed around the outer periphery of the sidewall of the second semiconductor layer. The second auxiliary electrode is insulated from the second semiconductor layer and is configured to be connected to a second preset voltage.

[0011] According to some exemplary embodiments, the light emitting chip further comprises an insulating layer disposed on sidewalls of the first semiconductor layer, the light emitting layer, and the second semiconductor layer, and the first auxiliary electrode is disposed on a surface of the insulating layer away from the first semiconductor layer; and / or

[0012] At least a portion of the second auxiliary electrode is disposed on a surface of the insulating layer away from the second semiconductor layer.

[0013] According to some exemplary embodiments, the first auxiliary electrode is continuously disposed around the surface of the insulating layer; and / or

[0014] At least a portion of the second auxiliary electrode is continuously and surroundingly disposed on the surface of the insulating layer.

[0015] According to some exemplary embodiments, a first surface of the first auxiliary electrode close to the base substrate is flush with a first surface of the first semiconductor layer close to the base substrate; a second surface of the first auxiliary electrode away from the base substrate is flush with a second surface of the first semiconductor layer away from the base substrate; and / or

[0016] The first surface of the second auxiliary electrode close to the base substrate is flush with the first surface of the second semiconductor layer close to the base substrate, or the first surface of the second auxiliary electrode close to the base substrate is closer to the base substrate than the first surface of the second semiconductor layer close to the base substrate; the second surface of the second auxiliary electrode away from the base substrate is flush with the second surface of the second semiconductor layer away from the base substrate.

[0017] According to some exemplary embodiments, the material of the first auxiliary electrode is selected from a conductive metal oxide material or a metal material; and / or

[0018] The material of the second auxiliary electrode is selected from a conductive metal oxide material or a metal material.

[0019] According to some exemplary embodiments, the first auxiliary electrode is electrically connected to the first electrode, and the first electrode and the first auxiliary electrode are connected to the same first preset voltage.

[0020] According to some exemplary embodiments, the second electrode and the first auxiliary electrode are located in the same layer.

[0021] According to some exemplary embodiments, the base substrate further includes a first connection terminal, the first auxiliary electrode is electrically connected to the first connection terminal, and the first connection terminal is configured to provide a first preset voltage to the first auxiliary electrode.

[0022] According to some exemplary embodiments, the base substrate includes at least two first connection terminals, the at least two first connection terminals are respectively located on both sides of the chip body along the first direction, and the first auxiliary electrode is respectively electrically connected to the at least two first connection terminals.

[0023] According to some exemplary embodiments, an orthographic projection of the first electrode on the base substrate is located within an orthographic projection of the first semiconductor layer on the base substrate.

[0024] According to some exemplary embodiments, the light emitting chip further includes a first filling layer covering the insulating layer and the first auxiliary electrode, and a first surface of the first filling layer away from the base substrate is flush with a second surface of the second semiconductor layer away from the base substrate.

[0025] According to some exemplary embodiments, the light-emitting chip further includes a second filling layer, which is arranged around the periphery of the chip body, wherein the first surface of the second filling layer away from the base substrate is flush with the first surface of the second semiconductor layer close to the base substrate, and the second auxiliary electrode extends from the surface of the insulating layer and is arranged on the first surface of the second filling layer away from the base substrate.

[0026] According to some exemplary embodiments, the second auxiliary electrode is electrically connected to the second electrode, and the second electrode and the second auxiliary electrode are connected to the same second preset voltage.

[0027] According to some exemplary embodiments, the second auxiliary electrode is located in the same layer as the second electrode.

[0028] According to some exemplary embodiments, the base substrate further includes a second connection terminal, the second auxiliary electrode is electrically connected to the second connection terminal, and the second connection terminal is configured to provide a second preset voltage to the second auxiliary electrode.

[0029] According to some exemplary embodiments, the base substrate includes at least two second connection terminals, the at least two second connection terminals are respectively located on both sides of the chip body along the second direction, and the second auxiliary electrode is respectively electrically connected to the at least two second connection terminals.

[0030] According to some exemplary embodiments, the second filling layer has a via hole exposing at least a portion of the second connection terminal, and the second auxiliary electrode is overlapped with the second connection terminal through the via hole.

[0031] According to some exemplary embodiments, along a direction from the center of the chip body to the outside, a distance between a sidewall of the second filling layer close to the chip body and a sidewall of the via close to the chip body is greater than a size of the insulating layer.

[0032] According to some exemplary embodiments, an orthographic projection of the second electrode on the base substrate is located within an orthographic projection of the second semiconductor layer on the base substrate.

[0033] According to some exemplary embodiments, the first semiconductor layer is an N-type semiconductor layer, and the first preset voltage is a negative voltage; and / or

[0034] The second semiconductor layer is a P-type semiconductor layer, and the second preset voltage is a positive voltage.

[0035] In another aspect, a method for preparing a light-emitting chip is provided, the method comprising:

[0036] providing a substrate;

[0037] A chip body is formed on a substrate, the chip body comprising: a first electrode formed on the substrate; a first semiconductor layer formed on a side of the first electrode away from the substrate; a light-emitting layer formed on a side of the first semiconductor layer away from the substrate; a second semiconductor layer formed on a side of the light-emitting layer away from the substrate; and a second electrode formed on a side of the second semiconductor layer away from the substrate;

[0038] forming auxiliary electrodes, including first auxiliary electrodes and / or second auxiliary electrodes,

[0039] The first auxiliary electrode is at least partially disposed around the periphery of the sidewall of the first semiconductor layer, the first auxiliary electrode is insulated from the first semiconductor layer, and the first auxiliary electrode is configured to be connected to a first preset voltage; and / or

[0040] The second auxiliary electrode is at least partially disposed around the outer periphery of the sidewall of the second semiconductor layer. The second auxiliary electrode is insulated from the second semiconductor layer and is configured to be connected to a second preset voltage.

[0041] In another aspect, a display panel is provided. The display panel includes the light-emitting chip as described above.

[0042] In another aspect, a display device is provided, comprising the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0044] FIG1 shows a distribution diagram of the peak value of the external quantum efficiency of a light-emitting chip as the chip size changes.

[0045] FIG2 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0046] FIG3 schematically shows a cross-sectional view at the position A1 - A2 in FIG2 .

[0047] FIG4 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0048] FIG5 schematically shows a cross-sectional view at position B1 - B2 in FIG4 .

[0049] FIG6 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0050] FIG. 7 schematically shows a cross-sectional view at the position C1 - C2 in FIG. 6 .

[0051] FIG8 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0052] FIG9 schematically shows a cross-sectional view at position D1 - D2 in FIG8 .

[0053] FIG10 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0054] FIG11 schematically shows a cross-sectional view at the position E1 - E2 in FIG10 .

[0055] FIG12 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0056] FIG13 schematically shows a cross-sectional view at the position F1 - F2 in FIG12 .

[0057] FIG14 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0058] FIG15 schematically shows a cross-sectional view at the position G1-G2 in FIG14 .

[0059] FIG16 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure.

[0060] FIG17 schematically shows a cross-sectional view at the H1 - H2 position in FIG16 .

[0061] FIG18 shows a luminous intensity test diagram of the light-emitting chip 1 and the light-emitting chip 2. ...

[0062] FIG19 schematically shows a flow chart of a method for preparing a light-emitting chip according to an embodiment of the present disclosure.

[0063] 20A to 20F are diagrams illustrating a process of forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0064] 21A to 21H are diagrams illustrating a process of forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0065] 22A to 22F are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0066] 23A to 23H are diagrams illustrating a process of forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0067] 24A to 24F are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0068] 25A to 25H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0069] 26A to 26H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0070] 27A to 27H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0071] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0072] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0073] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0074] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0075] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0076] With the development of technology, Micro LED display technology has been developing rapidly. For example, Micro LED display technology has begun to be applied to AR and VR applications. In AR and VR applications, Micro LED display technology generally has a higher PPI, and Micro LED chips need to be smaller in size.

[0077] Experiments have shown that when the operating current density remains unchanged, the external quantum efficiency of the Micro LED chip drops sharply as the chip size decreases. Figure 1 shows the distribution of the peak external quantum efficiency of the light-emitting chip as the chip size changes. Referring to Figure 1, the peak external quantum efficiency of the red light-emitting chip, the green light-emitting chip, and the blue light-emitting chip all show a clear downward trend as the chip size decreases.

[0078] It should be understood that when photons strike the surface of a photosensitive device, some excite the material to generate electron-hole pairs, generating an electric current. The ratio of the collected electrons (through processes such as internal electron-hole recombination) to the total number of incident photons is called the external quantum efficiency (EQE). For a light-emitting diode or chip, the external quantum efficiency is equal to the ratio of the number of photons emitted per unit time in the plane to the number of electron-hole pairs injected per unit time in the plane.

[0079] The inventors discovered that this phenomenon occurs because the chip sidewalls, formed during the etching process, inevitably become damaged during chip fabrication. This creates numerous defects along the sidewalls, leading to non-radiative recombination. Furthermore, as chip size decreases, these sidewall defects become more pronounced, leading to a higher rate of non-radiative recombination. Consequently, the external quantum efficiency of Micro LED chips decreases dramatically with decreasing chip size.

[0080] FIG2 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG3 schematically shows a cross-sectional view at the position A1 - A2 in FIG2 .

[0081] 2 and 3 , the light-emitting chip 100 may include: a substrate 1; a chip body 2 located on the substrate 1; and auxiliary electrodes 3. The chip body 2 includes a first electrode 21 disposed on the substrate 1; a first semiconductor layer 22 disposed on a side of the first electrode 21 away from the substrate 1; a light-emitting layer 23 disposed on a side of the first semiconductor layer 22 away from the substrate 1; a second semiconductor layer 24 disposed on a side of the light-emitting layer 23 away from the substrate 1; and a second electrode 25 disposed on a side of the second semiconductor layer 24 away from the substrate 1. The auxiliary electrodes 3 include a first auxiliary electrode 31 that at least partially surrounds a sidewall of the first semiconductor layer 22, is insulated from the first semiconductor layer 22, and is configured to be connected to a first predetermined voltage.

[0082] Here, the first auxiliary electrode 31 arranged around the periphery of the side wall of the first semiconductor layer 22 will form a horizontal electric field approximately parallel to the substrate 1 in the space where the first semiconductor layer 22 is located after being connected to the first preset voltage. Under the action of this electric field, the carriers in the first semiconductor layer 22 will move from the edge of the chip body 2 toward the center to a certain extent, reducing the probability of Shockley-Read-Hall (SRH) recombination of carriers in the side wall area of ​​the chip body 2. At the same time, it allows more carriers to move and recombine in the central area of ​​the chip body 2, increasing the radiation recombination ratio and achieving higher external quantum efficiency and luminous brightness.

[0083] It should be noted that SRH recombination is a defect-mediated recombination process. When free electrons or free holes encounter defect levels in a material, they can undergo non-radiative recombination within the defect level, converting them into heat energy. This recombination process is considered one of the main sources of non-radiative losses.

[0084] For example, the substrate 1 includes a substrate and a driving circuit disposed on the substrate. The driving circuit is electrically connected to the first electrode 21 and the second electrode 25, respectively, and provides power signals to the first electrode 21 and the second electrode 25, respectively, to drive the chip body 2 to emit light. The material of the substrate may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, etc.

[0085] For example, one of the first electrode 21 and the second electrode 25 is a light-transmitting electrode, and the other is a light-opaque electrode.

[0086] For example, the first electrode 21 is an opaque electrode, and the material of the first electrode 21 is selected from metal materials, for example, one or more of aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), platinum (Pt), gold (Au), silver (Ag), chromium (Cr), etc.

[0087] For example, the second electrode 25 is a light-transmitting electrode. The material of the second electrode 25 is selected from a conductive metal oxide material, for example, it can include a combination of or at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and indium gallium oxide (IGO).

[0088] For example, one of the first semiconductor layer 22 and the second semiconductor layer 24 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. The P-type semiconductor layer may be made of P-type gallium nitride (GaN), denoted as P-GaN; and the N-type semiconductor layer may be made of N-type gallium nitride (GaN), denoted as N-GaN.

[0089] For example, the first semiconductor layer 22 is an N-type semiconductor layer, and the second semiconductor layer 24 is a P-type semiconductor layer.

[0090] For example, the light emitting layer 23 may be a single quantum well layer (Single Quantum Well, abbreviated as SQW) or a multiple quantum well layer (Multiple Quantum Well, abbreviated as MQW).

[0091] For example, the slope angle formed by the side walls of the first semiconductor layer 22 , the light emitting layer 23 , and the second semiconductor layer 24 and the bottom surface of the first semiconductor layer 22 is in the range of 70°-80°.

[0092] In some embodiments, referring to Figures 2 and 3 , the light-emitting chip 100 further includes an insulating layer 4 , which is disposed on the sidewalls of the first semiconductor layer 22 , the light-emitting layer 23 , and the second semiconductor layer 24 . The first auxiliary electrode 31 is disposed on the surface of the insulating layer 4 away from the first semiconductor layer 22 .

[0093] Here, the insulating layer 4 can passivate and repair the sidewalls of the chip body 2, reducing the probability of SRH recombination in the sidewall region to a certain extent, further improving the external quantum efficiency and luminous brightness of the light-emitting chip 100. In addition, the first auxiliary electrode 31 is disposed on the insulating layer 4 to insulate the first auxiliary electrode 31 from the first semiconductor layer 22.

[0094] In some embodiments, the insulating layer 4 completely covers the first semiconductor layer 22 , the light emitting layer 23 , and the sidewalls of the second semiconductor layer 24 , and the insulating layer 4 has an opening that exposes the second semiconductor layer 24 .

[0095] For example, the material of the insulating layer 4 may include but is not limited to SiNx (silicon nitride) or SiOx (silicon oxide) materials.

[0096] In some embodiments, the first auxiliary electrode 31 is in a continuous ring-shaped structure, and the first auxiliary electrode 31 is continuously disposed around the surface of the insulating layer 4 .

[0097] In some embodiments, the first auxiliary electrode 31 may include a plurality of first auxiliary sub-electrodes, which are arranged at intervals around the outside of the first semiconductor layer. For example, the first auxiliary electrode 31 includes two first auxiliary sub-electrodes, which are symmetrically arranged on both sides of the first semiconductor layer.

[0098] In some embodiments, referring to Figure 3, the first surface 31A of the first auxiliary electrode 31 close to the base substrate 1 is flush with the first surface 22A of the first semiconductor layer 22 close to the base substrate 1; the second surface 31B of the first auxiliary electrode 31 away from the base substrate 1 is flush with the second surface 22B of the first semiconductor layer 22 away from the base substrate 1, so as to ensure that an electric field is formed in the space within the thickness range of the first semiconductor layer 22.

[0099] During the actual manufacturing process, due to factors such as manufacturing process precision, it is difficult for the first surface 31A of the first auxiliary electrode 31, which is close to the base substrate 1, to be completely flush with the first surface 22A of the first semiconductor layer 22, which is close to the base substrate 1. Similarly, it is difficult for the second surface 31B of the first auxiliary electrode 31, which is far from the base substrate 1, to be completely flush with the second surface 22B of the first semiconductor layer 22, which is far from the base substrate 1. However, the first auxiliary electrode 31 should be arranged to surround at least three-quarters of the sidewall of the first semiconductor layer 22.

[0100] In some embodiments, referring to Figure 3, the first auxiliary electrode 31 can be electrically connected to the first electrode 21, and the first electrode 21 and the first auxiliary electrode 31 are connected to the same first preset voltage. In addition to providing the first preset voltage to the first auxiliary electrode 31 to form the required electric field, the first preset voltage also serves as the power supply voltage of the first electrode 21 to drive the chip body 2 to emit light. The first auxiliary electrode 31 can be connected to the first preset voltage through the same wiring as the first electrode 21, which simplifies the structure of the light-emitting chip 100.

[0101] In some embodiments, the insulating layer 4 is extended on the base substrate 1, covering the surface of the base substrate 1 where the chip body 2 is not set. The first electrode 21 has a connecting portion 211 extending to the outside of the first semiconductor layer 22. The insulating layer 4 has a hollow structure 41 that exposes at least part of the connecting portion 211. The hollow structure 41 exposes at least part of the connecting portion 211, and the first auxiliary electrode 31 is overlapped with the connecting portion 211 through the hollow structure 41.

[0102] The hollow structure 41 may be one or more via holes arranged at intervals, or the hollow structure 41 may be an annular groove arranged around the first semiconductor layer 22 .

[0103] In some embodiments, the second electrode 25 and the first auxiliary electrode 31 are located in the same layer, that is, the second electrode 25 and the first auxiliary electrode 31 are made by the same film formation and patterning process, and the second electrode 25 and the first auxiliary electrode 31 are made of the same material. Exemplarily, the second electrode 25 and the first auxiliary electrode 31 are made of a conductive metal oxide material, such as a combination of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and indium gallium oxide (IGO), or at least one thereof.

[0104] FIG4 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG5 schematically shows a cross-sectional view at a position B1 - B2 in FIG4 .

[0105] In some embodiments, referring to FIG5 , the second electrode 25 and the first auxiliary electrode 31 are located in different layers. That is, the second electrode 25 and the first auxiliary electrode 31 are formed using different film formation and patterning processes, and the second electrode 25 and the first auxiliary electrode 31 can be made of different materials. For example, the material of the first auxiliary electrode 31 can be selected from a metal material. The first auxiliary electrode 31 composed of a metal material generally has a high reflectivity. Therefore, the first auxiliary electrode 31 disposed on the periphery of the first semiconductor layer 22 can improve the sidewall light leakage phenomenon to a certain extent.

[0106] The first auxiliary electrode 31 is made of a metal material with good electrical conductivity, including but not limited to aluminum, copper, tin or other alloy materials.

[0107] In some embodiments, referring to Figures 4 and 5, the light-emitting chip 100 further includes a first filling layer 51, which covers the insulating layer 4 and the first auxiliary electrode 31, and the first filling layer 51 is flush with the first surface 51A of the first filling layer 51 away from the base substrate 1 and the second surface 24B of the second semiconductor layer 24 away from the base substrate 1.

[0108] FIG6 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG7 schematically shows a cross-sectional view at a position C1 - C2 in FIG6 .

[0109] In some embodiments, referring to Figures 6 and 7 , the base substrate 1 further includes a first connection terminal 11, the first auxiliary electrode 31 is electrically connected to the first connection terminal 11, and the first connection terminal 11 is configured to provide a first preset voltage to the first auxiliary electrode 31. In this structure, the first auxiliary electrode 31 and the first electrode 21 are independently connected to voltage signals, and the first preset voltage connected to the first auxiliary electrode 31 can be adjusted according to the operating state of the light-emitting chip.

[0110] In some embodiments, the base substrate 1 includes at least two first connection terminals 11 , which are respectively located on both sides of the chip body along the first direction X, and the first auxiliary electrode 31 is electrically connected to each first connection terminal 11 .

[0111] As exemplarily shown in Figures 6 and 7, the base substrate 1 includes two first connecting terminals 11, which are respectively located on both sides of the chip body along the first direction X. The insulating layer 4 includes a first via 42 that exposes at least a portion of the first connecting terminal 11. The first auxiliary electrode 31 is continuously arranged around the outside of the insulating layer 4, and at the same time extends toward the first connecting terminal 11 and overlaps with the first connecting terminal 11 through the first via 42 to achieve electrical connection.

[0112] In some embodiments, referring to FIG7 , the orthographic projection of the first electrode 21 on the substrate 1 is located within the orthographic projection of the first semiconductor layer 22 on the substrate 1. This arrangement facilitates the transmission and recombination of electrons and holes in the central region of the chip body, thereby reducing non-radiative recombination at sidewall defects to a certain extent.

[0113] FIG8 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG9 schematically shows a cross-sectional view at a position D1 - D2 in FIG8 .

[0114] In some embodiments, referring to Figures 8 and 9 , the first auxiliary electrode 31 is electrically connected to the first connection terminal 11, which is configured to provide a first preset voltage to the first auxiliary electrode 31. The second electrode 25 and the first auxiliary electrode 31 are located on different layers. The light-emitting chip further includes a first filling layer 51, which covers the insulating layer 4 and the first auxiliary electrode 31. The first filling layer 51 is flush with a first surface 51A of the first filling layer 51 away from the base substrate 1 and a second surface 24B of the second semiconductor layer 24 away from the base substrate 1.

[0115] FIG10 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG11 schematically shows a cross-sectional view at the position E1 - E2 in FIG10 .

[0116] In some embodiments, referring to Figures 10 and 11, the light-emitting chip further includes a second filling layer 52, which is arranged around the periphery of the chip body, and a first surface 52A of the second filling layer 52 away from the base substrate 1 is flush with a first surface 24A of the second semiconductor layer 24 close to the base substrate 1, and a second auxiliary electrode 32 extends from the surface of the insulating layer 4 and is arranged on the first surface 52A of the second filling layer 52 away from the base substrate 1.

[0117] Here, the second auxiliary electrode 32 arranged around the outer periphery of the side wall of the second semiconductor layer 24 will form a horizontal electric field approximately parallel to the substrate 1 in the space where the second semiconductor layer 24 is located after being connected to the second preset voltage. Under the action of this electric field, the carriers in the second semiconductor layer 24 will move from the edge of the chip body 2 toward the center to a certain extent, reducing the probability of Shockley-Read-Hall recombination of carriers in the side wall area of ​​the chip body 2. At the same time, it allows more carriers to move and recombine in the central area of ​​the chip body 2, increasing the radiation recombination ratio and achieving higher external quantum efficiency and luminous brightness.

[0118] In some embodiments, the second auxiliary electrode 32 has a continuous ring structure, and at least a portion of the second auxiliary electrode 32 is continuously disposed around the surface of the insulating layer 4. As exemplarily shown in Figures 10 and 11, the second auxiliary electrode 32 is continuously disposed around the surface of the insulating layer 4.

[0119] In some embodiments, the second auxiliary electrode 32 may include a plurality of second auxiliary sub-electrodes, which are spaced apart and arranged around the outside of the second semiconductor layer. For example, the second auxiliary electrode 32 includes two second auxiliary sub-electrodes, which are symmetrically arranged on both sides of the second semiconductor layer.

[0120] In some embodiments, referring to Figure 11, the first surface 32A of the second auxiliary electrode 32 close to the base substrate 1 is flush with the first surface 24A of the second semiconductor layer 24 close to the base substrate 1; the second surface 32B of the second auxiliary electrode 32 away from the base substrate 1 is flush with the second surface 24B of the second semiconductor layer 24 away from the base substrate 1, so as to ensure that an electric field is formed in the space within the thickness range of the second semiconductor layer 24.

[0121] During the actual manufacturing process, due to factors such as manufacturing process accuracy, it is difficult for the first surface 32A of the second auxiliary electrode 32, which is close to the base substrate 1, to be completely flush with the first surface 24A of the second semiconductor layer 24, which is close to the base substrate 1. Similarly, it is difficult for the second surface 32B of the second auxiliary electrode 32, which is far from the base substrate 1, to be completely flush with the second surface 24B of the second semiconductor layer 24, which is far from the base substrate 1. However, the second auxiliary electrode 32 should be arranged to surround at least three-quarters of the sidewall of the second semiconductor layer 24.

[0122] In some embodiments, the second auxiliary electrode 32 is electrically connected to the second electrode 25, and the second electrode 25 and the second auxiliary electrode 32 are connected to the same second preset voltage. In addition to providing the second preset voltage to the second auxiliary electrode 32 to form a desired electric field, the second preset voltage also serves as a power supply voltage for the second electrode 25 to drive the chip body 2 to emit light. The second auxiliary electrode 32 and the second electrode 25 can be connected to the first preset voltage through the same trace, simplifying the structure of the light-emitting chip 100.

[0123] In some embodiments, the second electrode 25 has a structure that extends toward the second auxiliary electrode 32 and overlaps the second auxiliary electrode 32, thereby achieving electrical connection between the second electrode 25 and the second auxiliary electrode 32. For example, referring to Figures 10 and 11, the second auxiliary electrode 32 is continuously disposed around the outside of the insulating layer 4, and the second electrode 25 is extended outward as a whole, and the outer edge of the second electrode 25 is connected to the upper edge of the second auxiliary electrode.

[0124] FIG12 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG13 schematically shows a cross-sectional view at the position F1 - F2 in FIG12 .

[0125] In some embodiments, referring to Figures 12 and 13 , a first auxiliary electrode 31 and a second auxiliary electrode 32 are provided in the light-emitting chip. The first auxiliary electrode 31 is electrically connected to the first connection terminal 11. A second filling layer 52 is disposed around the outside of the insulating layer 4, covering the first auxiliary electrode 31. The second auxiliary electrode 32 is disposed on the second filling layer 52 and electrically connected to the second electrode.

[0126] FIG14 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG15 schematically shows a cross-sectional view at a position G1 - G2 in FIG14 .

[0127] In some embodiments, referring to Figures 14 and 15 , the base substrate 1 further includes a second connection terminal 12, the second auxiliary electrode 32 is electrically connected to the second connection terminal 12, and the second connection terminal 12 is configured to provide a second preset voltage to the second auxiliary electrode 32. In this structure, the second auxiliary electrode 32 and the second electrode 25 are independently connected to voltage signals, and the second preset voltage connected to the second auxiliary electrode 32 can be adjusted according to the operating state of the light-emitting chip.

[0128] In some embodiments, the base substrate 1 includes at least two second connection terminals 12, the at least two second connection terminals 12 are respectively located on both sides of the chip body 2 along the second direction Y, and the second auxiliary electrodes 32 are respectively electrically connected to each second connection terminal 12. For example, the base substrate 1 includes two second connection terminals 12, the two second connection terminals 12 are respectively located on both sides of the chip body along the second direction Y, and the second auxiliary electrodes 32 are respectively electrically connected to the two second connection terminals 12.

[0129] In some embodiments, referring to Figure 15, the insulating layer 4 has a second via 43 exposing at least a portion of the second connection terminal 12, and the second filling layer 52 has a third via 521. The third via 521 penetrates the second via 43 and exposes at least a portion of the second connection terminal 12. The second auxiliary electrode 32 extends from the upper surface of the second filling layer 52 through the third via 521 and the hole wall of the second via 43 to overlap with the second connection terminal 12 to achieve electrical connection.

[0130] In some embodiments, referring to Figure 15, along the direction pointing outward from the center of the chip body, the distance D1 between the side wall of the second filling layer 52 close to the chip body 2 and the side wall of the third via 521 close to the chip body 2 is greater than the size D2 of the insulating layer 4. In this way, the part of the second auxiliary electrode 52 located in the third via 521 is as far away from the first auxiliary electrode 31 and the first electrode 21 as possible to avoid interference between the second auxiliary electrode 52 and the first auxiliary electrode 31 or the first electrode 21.

[0131] In some embodiments, the material of the second filling layer 52 is selected from organic insulating adhesives. In actual selection, an organic insulating adhesive with a relatively large dielectric constant is selected, for example, an organic insulating adhesive with a dielectric constant greater than that of the insulating layer 4 .

[0132] 15 , a first auxiliary electrode 31 and a second auxiliary electrode 32 are provided in the light emitting chip. The first auxiliary electrode 31 is electrically connected to the first electrode 21 , and the second auxiliary electrode 32 is electrically connected to the second connection terminal 12 .

[0133] FIG16 schematically shows a plan view of a light-emitting chip according to an embodiment of the present disclosure, and FIG17 schematically shows a cross-sectional view at the position H1 - H2 in FIG16 .

[0134] 16 and 17 , the light emitting chip is provided with a first auxiliary electrode 31 and a second auxiliary electrode 32 . The first auxiliary electrode 31 is electrically connected to the first connection terminal 11 , and the second auxiliary electrode 32 is electrically connected to the second connection terminal 12 .

[0135] In some embodiments, the base substrate 1 includes two first connecting terminals 11 and two second connecting terminals 12, the two first connecting terminals 11 are respectively located on both sides of the chip body 2 along the first direction X, and the two second connecting terminals 12 are respectively located on both sides of the chip body 2 along the second direction Y, the first auxiliary electrode 31 is electrically connected to the first connecting terminal 11, and the second auxiliary electrode 32 is electrically connected to the second connecting terminal 12.

[0136] In some embodiments, the first direction X is perpendicular to the second direction Y.

[0137] In some embodiments, the second auxiliary electrode 32 and the second electrode 25 are located in the same layer, that is, the second electrode 25 and the second auxiliary electrode 32 are made by the same film formation and patterning process, and the second electrode 25 and the second auxiliary electrode 32 are made of the same material. Exemplarily, the second electrode 25 and the second auxiliary electrode 32 are made of a conductive metal oxide material, such as a combination of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and indium gallium oxide (IGO), or at least one thereof.

[0138] In some embodiments, the second auxiliary electrode 32 and the second electrode 25 are located in different layers. That is, the second electrode 25 and the second auxiliary electrode 32 are made using different film formation and patterning processes, and the second auxiliary electrode 32 and the second electrode 25 can be made of different materials. For example, the second auxiliary electrode 32 can be made of a metal material. The second auxiliary electrode 32 made of a metal material generally has a high reflectivity. Therefore, the second auxiliary electrode 32 disposed on the periphery of the second semiconductor layer 24 can improve sidewall light leakage to a certain extent.

[0139] The second auxiliary electrode 32 is made of a metal material with good conductivity, such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), platinum (Pt), gold (Au), silver (Ag), chromium (Cr), and other materials.

[0140] In some embodiments, referring to Figures 14-17 , the orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1. This arrangement facilitates the transmission and recombination of electrons and holes in the central region of the chip body, thereby reducing non-radiative recombination at sidewall defects to a certain extent.

[0141] In some embodiments, the first semiconductor layer 22 is an N-type semiconductor layer, and the majority carriers in the N-type semiconductor layer are electrons. The first preset voltage is set to a negative voltage to form a horizontal electric field pointing from the center to the edge of the first semiconductor layer 22 to drive the electrons in the first semiconductor layer 22 to move from the edge to the center of the first semiconductor layer 22.

[0142] The second semiconductor layer is a P-type semiconductor layer, and the majority carriers in the P-type semiconductor layer are holes. The second preset voltage is set to a positive voltage to form a horizontal electric field pointing from the edge of the second semiconductor layer 24 to the center, so as to drive the holes in the second semiconductor layer 24 to move from the edge to the center of the second semiconductor layer 24.

[0143] 10 and 11 as examples, a light emitting chip 1 was prepared. A light emitting chip 2 was prepared using the structures shown in FIG10 and 11 as examples. The only difference from the light emitting chip 1 is that no second auxiliary electrode is provided around the second semiconductor layer.

[0144] The luminous intensity of the prepared light-emitting chips 1 and 2 was tested. During the test, the second auxiliary electrode in the light-emitting chip 1 was connected to a voltage of 3V. Figure 18 shows the luminous intensity test of the light-emitting chips 1 and 2. Referring to Figure 18, the test results show that the luminous intensity of the light-emitting chip 1 is significantly improved compared to that of the light-emitting chip 2. This confirms that the provision of the second auxiliary electrode on the periphery of the second semiconductor layer can effectively improve the luminous brightness of the light-emitting chip.

[0145] Similarly, disposing a first auxiliary electrode on the periphery of the first semiconductor layer can also effectively improve the luminance of the light-emitting chip.

[0146] An embodiment of the present disclosure further provides a method for preparing a light-emitting chip. FIG19 schematically shows a flow chart of the method for preparing a light-emitting chip according to an embodiment of the present disclosure. As shown in FIG19 , the method includes the following steps S10 to S30.

[0147] In step S10 , a base substrate is provided.

[0148] In step S20, a chip body is formed on the base substrate, and the chip body includes: a first electrode formed on the base substrate; a first semiconductor layer formed on the side of the first electrode away from the base substrate; a light-emitting layer formed on the side of the first semiconductor layer away from the base substrate; a second semiconductor layer formed on the side of the light-emitting layer away from the base substrate; and a second electrode formed on the side of the second semiconductor layer away from the base substrate.

[0149] In step S30, auxiliary electrodes are formed, including a first auxiliary electrode and / or a second auxiliary electrode, wherein the first auxiliary electrode is at least partially arranged around the periphery of the side wall of the first semiconductor layer, the first auxiliary electrode is insulated from the first semiconductor layer, and the first auxiliary electrode is configured to be connected to a first preset voltage; and / or the second auxiliary electrode is at least partially arranged around the periphery of the side wall of the second semiconductor layer, the second auxiliary electrode is insulated from the second semiconductor layer, and the second auxiliary electrode is configured to be connected to a second preset voltage.

[0150] 20A to 20F are diagrams illustrating a process of forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0151] As shown in the cross-sectional schematic diagram of the A3-A4 position in Figure 20A and Figure 20B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0152] For example, the base substrate 1 includes a substrate and a driving circuit provided on the substrate, and the first electrode 21 is located in the driving circuit.

[0153] For example, the first electrode 21 is an opaque electrode, and the material of the first electrode 21 may include one or more of aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), platinum (Pt), gold (Au), silver (Ag), chromium (Cr), etc.

[0154] For example, the steps of obtaining the stacked first semiconductor layer 22, the light emitting layer 23, and the second semiconductor layer 24 specifically include:

[0155] A suitable substrate is selected, and a first semiconductor film layer, a light-emitting layer, and a second semiconductor film layer are sequentially deposited on the substrate. The first semiconductor film layer, the light-emitting layer, and the second semiconductor film layer are etched under a mask to obtain a first semiconductor layer 22, a light-emitting layer 23, and a second semiconductor layer 24 with predetermined shapes. Finally, the stacked first semiconductor layer 22, the light-emitting layer 23, and the second semiconductor layer 24 are peeled off from the substrate.

[0156] Typically, the slope angle formed by the sidewalls of the first semiconductor layer 22 , the light emitting layer 23 and the second semiconductor layer 24 formed by etching and the bottom surface of the first semiconductor layer 22 is in the range of 70°-80°.

[0157] For example, the substrate may be a sapphire substrate or a silicon carbide substrate.

[0158] For example, the first semiconductor layer 22 is an N-type semiconductor layer, and the second semiconductor layer 24 is a P-type semiconductor layer. The material of the P-type semiconductor layer can be P-type gallium nitride (GaN), denoted as P-GaN; the material of the N-type semiconductor layer can be N-type gallium nitride (GaN), denoted as N-GaN.

[0159] For example, the light emitting layer 23 may be a single quantum well layer (Single Quantum Well, abbreviated as SQW) or a multiple quantum well layer (Multiple Quantum Well, abbreviated as MQW).

[0160] As shown in the cross-sectional schematic diagram at position A5-A6 in FIG. 20C and FIG. 20D , an insulating film layer is deposited and patterned to form insulating layer 4. Insulating layer 4 completely covers the sidewalls of first semiconductor layer 22, light-emitting layer 23, and second semiconductor layer 24, and has an opening exposing second semiconductor layer 24. Furthermore, insulating layer 4 has a hollow structure 41 that exposes at least a portion of first electrode 21.

[0161] For example, referring to FIG. 20C , the hollow structure 41 is a ring-shaped groove, and the portion of the first electrode 21 exposed by the hollow structure 41 is also ring-shaped.

[0162] For example, the material of the insulating layer 4 may include at least one of silicon nitride and silicon oxide.

[0163] As shown in the cross-sectional schematic diagram at position A1-A2 in FIG20E and FIG20F , a conductive film layer is deposited and patterned to form the second electrode 25 and the first auxiliary electrode 31. The second electrode 25 is located on the side of the second semiconductor layer 24 away from the base substrate 1, and the orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 overlaps the first electrode 21 through the hollow structure of the insulating layer 4.

[0164] For example, the second electrode 25 is a light-transmitting electrode. The material of the second electrode 25 and the first auxiliary electrode 31 may include a combination of or at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and indium gallium oxide (IGO).

[0165] 21A to 20H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0166] As shown in the cross-sectional schematic diagram of the B3-B4 position in Figure 21A and Figure 21B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0167] As shown in the cross-sectional view at position B5-B6 in FIG. 21C and FIG. 21D , an insulating film layer is deposited and patterned to form insulating layer 4. Insulating layer 4 completely covers the sidewalls of first semiconductor layer 22, light-emitting layer 23, and second semiconductor layer 24, and has an opening exposing second semiconductor layer 24. Furthermore, insulating layer 4 has a hollow structure 41 that exposes at least a portion of first electrode 21.

[0168] As shown in the cross-sectional schematic diagram at position B7-B8 in FIG. 21E and FIG. 21F , a first conductive film layer is deposited and then patterned to form a first auxiliary electrode 31. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 overlaps the first electrode 21 through the hollow structure of the insulating layer 4.

[0169] For example, the material of the first auxiliary electrode 31 may include a combination of or at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), and indium gallium oxide (IGO).

[0170] As shown in the cross-sectional schematic diagram at the B1-B2 position in Figure 21G and Figure 21H, an organic insulating adhesive layer is formed, and the organic insulating adhesive layer is patterned to obtain a first filling layer 51. The first filling layer 51 covers the insulating layer 4 and the first auxiliary electrode 31, and the first filling layer 51 is flush with the first surface 51A of the first filling layer 51 away from the base substrate 1 and the second surface 24B of the second semiconductor layer 24 away from the base substrate 1.

[0171] A second conductive film layer is deposited and patterned to obtain a second electrode 25. The second electrode 25 is located on a side of the second semiconductor layer 24 away from the base substrate 1, and the orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1.

[0172] 22A to 22F are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0173] As shown in the cross-sectional schematic diagram of the C3-C4 position in Figure 22A and Figure 22B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21 and a first connecting terminal 11, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0174] For example, the base substrate 1 includes a substrate and a driving circuit provided on the substrate, and the first electrode 21 and the first connection terminal 11 are located in the driving circuit.

[0175] For example, the substrate 1 includes two first connection terminals 11 , and the two first connection terminals 11 are respectively located on two sides of the first semiconductor layer 22 along the first direction X.

[0176] As shown in the cross-sectional view at position C5-C6 in FIG. 22C and FIG. 22D , an insulating film layer is deposited and patterned to form an insulating layer 4. The insulating layer 4 completely covers the sidewalls of the first semiconductor layer 22, the light-emitting layer 23, and the second semiconductor layer 24, and has an opening that exposes the second semiconductor layer 24. Furthermore, the insulating layer 4 has a first via 42 that exposes at least a portion of the first connection terminal 11.

[0177] As shown in the cross-sectional schematic diagram at position C1-C2 in FIG22E and FIG22F , a conductive film layer is deposited and patterned to form the second electrode 25 and the first auxiliary electrode 31. The second electrode 25 is located on the side of the second semiconductor layer 24 away from the base substrate 1, and the orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 is connected to the first connection terminal 11 through the first via 42 of the insulating layer 4.

[0178] 23A to 23H are diagrams illustrating a process of forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0179] As shown in the cross-sectional schematic diagram of the D3-D4 position in Figure 23A and Figure 23B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21 and a first connecting terminal 11, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0180] As shown in the cross-sectional schematic diagram at position D5-D6 in FIG. 23C and FIG. 23D , an insulating film layer is deposited and patterned to form an insulating layer 4. The insulating layer 4 completely covers the sidewalls of the first semiconductor layer 22, the light-emitting layer 23, and the second semiconductor layer 24, and has an opening that exposes the second semiconductor layer 24. Furthermore, the insulating layer 4 has a first via 42 that exposes at least a portion of the first connection terminal 11.

[0181] As shown in the cross-sectional schematic diagram at position D7-D8 in FIG23E and FIG23F , a first conductive film layer is deposited and then patterned to form a first auxiliary electrode 31. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 is connected to the first connection terminal 11 through the first via 42 in the insulating layer 4.

[0182] As shown in the cross-sectional schematic diagram of the D1-D2 position in Figure 23G and Figure 23H, an organic insulating adhesive layer is formed, and the organic insulating adhesive layer is patterned to obtain a first filling layer 51. The first filling layer 51 covers the insulating layer 4 and the first auxiliary electrode 31, and the first filling layer 51 is flush with the first surface 51A of the first filling layer 51 away from the base substrate 1 and the second surface 24B of the second semiconductor layer 24 away from the base substrate 1.

[0183] A second conductive film layer is deposited and patterned to obtain a second electrode 25. The second electrode 25 is located on a side of the second semiconductor layer 24 away from the base substrate 1, and the orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1.

[0184] 24A to 24F are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0185] As shown in the cross-sectional schematic diagram of the E3-E4 position in Figure 24A and Figure 24B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21 and a first connecting terminal 11, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0186] As shown in the cross-sectional schematic diagram of the E5-E6 position in Figure 24C and Figure 24D, an insulating film layer is deposited and patterned to obtain an insulating layer 4. The insulating layer 4 completely covers the side walls of the first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24, and has an opening that exposes the second semiconductor layer 24.

[0187] As shown in the cross-sectional schematic diagram at the E1-E2 position in Figure 24E and Figure 24F, an organic insulating adhesive layer is formed, and the organic insulating adhesive layer is patterned to obtain a second filling layer 52. The second filling layer 52 is arranged around the periphery of the first semiconductor layer 22 and the light-emitting layer 23. The first surface 52A of the second filling layer 52 away from the base substrate 1 is flush with the first surface 24A of the second semiconductor layer 24 close to the base substrate 1.

[0188] A conductive film layer is then deposited and patterned to form a second electrode 25 and a second auxiliary electrode 32. The second electrode 25 is located on the side of the second semiconductor layer 24 away from the base substrate 1, and the second auxiliary electrode 32 is located on the side of the insulating layer 4 away from the second semiconductor layer 32. The second auxiliary electrode 32 extends from the surface of the insulating layer 4 and is disposed on the first surface 52A of the second filling layer 52 away from the base substrate 1. The second electrode 25 is electrically connected to the second auxiliary electrode 32, and the outer edge of the second electrode 25 is connected to the edge of the second auxiliary electrode 32 away from the base substrate 1.

[0189] 25A to 25H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0190] As shown in the cross-sectional schematic diagram of the F3-F4 position in Figure 25A and Figure 25B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0191] As shown in the cross-sectional schematic diagram at position F5-F6 in FIG. 25C and FIG. 25D , an insulating film layer is deposited and patterned to form insulating layer 4. Insulating layer 4 completely covers the sidewalls of first semiconductor layer 22, light-emitting layer 23, and second semiconductor layer 24, and has an opening exposing second semiconductor layer 24. Furthermore, insulating layer 4 has a first via 42 that exposes at least a portion of first connection terminal 11.

[0192] As shown in the cross-sectional view at position F7-F8 in FIG. 25E and FIG. 25F , a first conductive film layer is deposited and then patterned to form a first auxiliary electrode 31. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 is connected to the first connection terminal 11 through the first via 42 in the insulating layer 4.

[0193] As shown in the cross-sectional schematic diagram at the F1-F2 position in Figure 25G and Figure 25H, an organic insulating adhesive layer is formed, and the organic insulating adhesive layer is patterned to obtain a second filling layer 52. The second filling layer 52 is arranged around the periphery of the first semiconductor layer 22 and the light-emitting layer 23. The first surface 52A of the second filling layer 52 away from the base substrate 1 is flush with the first surface 24A of the second semiconductor layer 24 close to the base substrate 1.

[0194] A second conductive film layer is then deposited and patterned to form a second electrode 25 and a second auxiliary electrode 32. The second electrode 25 is located on the side of the second semiconductor layer 24 away from the base substrate 1, and the second auxiliary electrode 32 is located on the side of the insulating layer 4 away from the second semiconductor layer 24. The second auxiliary electrode 32 extends from the surface of the insulating layer 4 and is disposed on the first surface 52A of the second filling layer 52 away from the base substrate 1. The second electrode 25 is electrically connected to the second auxiliary electrode 32, and the outer edge of the second electrode 25 is connected to the edge of the second auxiliary electrode 32 away from the base substrate 1.

[0195] 26A to 26H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0196] As shown in the cross-sectional schematic diagram of the G3-G4 position in Figure 26A and Figure 26B, a base substrate 1 is provided, the base substrate 1 includes a first electrode 21 and a second connecting terminal 12, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0197] For example, the substrate 1 includes two second terminals 12 , and the two second terminals 12 are respectively located on two sides of the first semiconductor layer 22 along the second direction Y.

[0198] As shown in the cross-sectional schematic diagram at position G5-G6 in FIG26C and FIG26D , an insulating film layer is deposited and patterned to form an insulating layer 4. The insulating layer 4 completely covers the sidewalls of the first semiconductor layer 22, the light-emitting layer 23, and the second semiconductor layer 24, and has an opening exposing the second semiconductor layer 24. Furthermore, the insulating layer 4 has a hollow structure 41 that exposes at least a portion of the first electrode 21, and a second via 43 that exposes at least a portion of the second connection terminal 12.

[0199] As shown in the cross-sectional schematic diagram at position G7-G8 in FIG26E and FIG26F , a first conductive film layer is deposited and then patterned to form a first auxiliary electrode 31. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 overlaps the first electrode 21 through the hollow structure of the insulating layer 4.

[0200] As shown in the cross-sectional view at position G1-G2 in FIG. 26G and FIG. 26H , an organic insulating adhesive layer is formed and patterned to obtain a second filling layer 52. The second filling layer 52 surrounds the first semiconductor layer 22 and the light-emitting layer 23. A first surface 52A of the second filling layer 52, distal from the base substrate 1, is flush with a first surface 24A of the second semiconductor layer 24, proximal to the base substrate 1. The second filling layer 52 has a third via 521, which extends through the second via 43 and exposes at least a portion of the second connection terminal 12.

[0201] A second conductive film layer is then deposited and patterned to form a second electrode 25 and a second auxiliary electrode 32. The second electrode 25 is located on the side of the second semiconductor layer 24 away from the base substrate 1. The orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1. The second auxiliary electrode 32 is located on the side of the insulating layer 4 away from the second semiconductor layer 24. The second auxiliary electrode 32 extends from the upper surface of the second filling layer 52 through the third via 521 and the wall of the second via 43 to overlap with the second connection terminal 12, thereby achieving electrical connection.

[0202] 27A to 27H are diagrams illustrating a process for forming a light-emitting chip according to at least one embodiment of the present disclosure.

[0203] As shown in the cross-sectional schematic diagram of the H3-H4 position in Figure 26A in Figures 27A and 27B, a base substrate 1 is provided, which includes a first electrode 21, a first connecting terminal 11 and a second connecting terminal 12, and the stacked first semiconductor layer 22, the light-emitting layer 23 and the second semiconductor layer 24 are transferred onto the base substrate 1, specifically, the first semiconductor layer 22 is transferred onto the first electrode 21 in alignment.

[0204] For example, the substrate 1 includes two first connection terminals 11 , and the two first connection terminals 11 are respectively located on two sides of the first semiconductor layer 22 along the first direction X.

[0205] For example, the substrate 1 includes two second connection terminals 12 , and the two second connection terminals 12 are respectively located on two sides of the first semiconductor layer 22 along the second direction Y.

[0206] For example, the first direction X is perpendicular to the second direction Y.

[0207] As shown in the cross-sectional schematic diagram at position H5-H6 in FIG27C and FIG27D , an insulating film layer is deposited and patterned to form an insulating layer 4. The insulating layer 4 completely covers the sidewalls of the first semiconductor layer 22, the light-emitting layer 23, and the second semiconductor layer 24, and has an opening exposing the second semiconductor layer 24. Furthermore, the insulating layer 4 has a first via 42 exposing at least a portion of the first connection terminal 11, and a second via 43 exposing at least a portion of the second connection terminal 12.

[0208] As shown in the cross-sectional view at position H7-H8 in FIG. 27E and FIG. 27F , a first conductive film layer is deposited and then patterned to form a first auxiliary electrode 31. The first auxiliary electrode 31 is located on the side of the insulating layer 4 away from the first semiconductor layer 22, and the first auxiliary electrode 31 is connected to the first connection terminal 11 through the first via 42 in the insulating layer 4.

[0209] As shown in the cross-sectional diagram at position H1-H2 in FIG. 27G and FIG. 27H , an organic insulating adhesive layer is formed and patterned to obtain a second filling layer 52. The second filling layer 52 surrounds the first semiconductor layer 22 and the light-emitting layer 23. A first surface 52A of the second filling layer 52, distal from the base substrate 1, is flush with a first surface 24A of the second semiconductor layer 24, proximal to the base substrate 1. The second filling layer 52 has a third via 521, which extends through the second via 43 and exposes at least a portion of the second connection terminal 12.

[0210] A second conductive film layer is then deposited and patterned to form a second electrode 25 and a second auxiliary electrode 32. The second electrode 25 is located on the side of the second semiconductor layer 24 away from the base substrate 1. The orthographic projection of the second electrode 25 on the base substrate 1 is located within the orthographic projection of the second semiconductor layer 24 on the base substrate 1. The second auxiliary electrode 32 is located on the side of the insulating layer 4 away from the second semiconductor layer 24. The second auxiliary electrode 32 extends from the upper surface of the second filling layer 52 through the third via 521 and the wall of the second via 43 to overlap with the second connection terminal 12, thereby achieving electrical connection.

[0211] The embodiments of the present disclosure further provide a display panel including the above-mentioned light-emitting chip. For example, the display panel includes a plurality of light-emitting chips arranged in an array.

[0212] The present disclosure also provides a display device including the above-mentioned display panel. For example, the display device can be a television, monitor, electronic picture frame, electronic photo frame, navigation system, laptop computer, tablet computer, smart phone, or other electronic product with display function.

[0213] It should be understood that the display panel and display device according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned light-emitting chip. These features and advantages can be referred to the above description of the light-emitting chip and will not be repeated here.

[0214] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0215] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A light-emitting chip, wherein, the light-emitting chip comprises: a substrate; a chip body located on the substrate, the chip body comprising: a first electrode disposed on the substrate; a first semiconductor layer disposed on a side of the first electrode away from the substrate; a light-emitting layer disposed on a side of the first semiconductor layer away from the substrate; a second semiconductor layer disposed on a side of the light-emitting layer away from the substrate; and a second electrode disposed on a side of the second semiconductor layer away from the substrate; and auxiliary electrodes, including a first auxiliary electrode and / or a second auxiliary electrode, wherein, the first auxiliary electrode is at least partially disposed around an outer periphery of a sidewall of the first semiconductor layer, the first auxiliary electrode is insulated from the first semiconductor layer and the first auxiliary electrode is configured to be connected to a first preset voltage; and / or the second auxiliary electrode is at least partially disposed around an outer periphery of a sidewall of the second semiconductor layer, the second auxiliary electrode is insulated from the second semiconductor layer and the second auxiliary electrode is configured to be connected to a second preset voltage.

2. The light-emitting chip according to claim 1, wherein, the light-emitting chip further comprises an insulating layer disposed at sidewalls of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and the first auxiliary electrode is disposed on a surface of the insulating layer away from the first semiconductor layer; and / or at least a part of the second auxiliary electrode is disposed on a surface of the insulating layer away from the second semiconductor layer.

3. The light-emitting chip according to claim 2, wherein, the first auxiliary electrode is continuously disposed around a surface of the insulating layer; and / or at least a part of the second auxiliary electrode is continuously disposed around a surface of the insulating layer.

4. The light-emitting chip according to claim 2, wherein, a first surface of the first auxiliary electrode close to the substrate is flush with a first surface of the first semiconductor layer close to the substrate; a second surface of the first auxiliary electrode away from the substrate is flush with a second surface of the first semiconductor layer away from the substrate; and / or a first surface of the second auxiliary electrode close to the substrate is flush with a first surface of the second semiconductor layer close to the substrate or the first surface of the second auxiliary electrode close to the substrate is closer to the substrate than the first surface of the second semiconductor layer close to the substrate; a second surface of the second auxiliary electrode away from the substrate is flush with a second surface of the second semiconductor layer away from the substrate.

5. The light-emitting chip according to claim 2, wherein, the material of the first auxiliary electrode is selected from a conductive metal oxide material or a metal material; and / or the material of the second auxiliary electrode is selected from a conductive metal oxide material or a metal material.

6. The light-emitting chip according to any one of claims 2-5, wherein, the first auxiliary electrode is electrically connected to the first electrode, and the first electrode and the first auxiliary electrode are connected to the same first preset voltage.

7. The light-emitting chip according to claim 6, wherein, The second electrode and the first auxiliary electrode are located on the same layer.

8. The light-emitting chip according to any one of claims 2-5, wherein, The substrate further includes a first connection terminal, the first auxiliary electrode is electrically connected to the first connection terminal, and the first connection terminal is configured to provide a first preset voltage to the first auxiliary electrode.

9. The light-emitting chip according to claim 8, wherein, The substrate includes at least two of the first connection terminals, at least two of the first connection terminals are respectively located on both sides of the chip body along the first direction, and the first auxiliary electrode is electrically connected to at least two of the first connection terminals respectively.

10. The light-emitting chip according to claim 8, wherein, The orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first semiconductor layer on the substrate.

11. The light-emitting chip according to claim 2, wherein, The light-emitting chip further includes a first filling layer, the first filling layer covers the insulating layer and the first auxiliary electrode, and a first surface of the first filling layer away from the substrate is flush with a second surface of the second semiconductor layer away from the substrate.

12. The light-emitting chip according to claim 2, wherein, The light-emitting chip further includes a second filling layer, the second filling layer is disposed around the periphery of the chip body, a first surface of the second filling layer away from the substrate is flush with a first surface of the second semiconductor layer close to the substrate, and the second auxiliary electrode extends from the surface of the insulating layer to a first surface of the second filling layer away from the substrate.

13. The light-emitting chip according to any one of claims 12, wherein, The second auxiliary electrode is electrically connected to the second electrode, and the second electrode and the second auxiliary electrode are connected to the same second preset voltage.

14. The light-emitting chip according to claim 13, wherein, The second auxiliary electrode and the second electrode are located on the same layer.

15. The light-emitting chip according to claim 12, wherein, The substrate further includes a second connection terminal, the second auxiliary electrode is electrically connected to the second connection terminal, and the second connection terminal is configured to provide a second preset voltage to the second auxiliary electrode.

16. The light-emitting chip according to claim 15, wherein, The substrate includes at least two of the second connection terminals, at least two of the second connection terminals are respectively located on both sides of the chip body along the second direction, and the second auxiliary electrode is electrically connected to at least two of the second connection terminals respectively.

17. The light-emitting chip according to claim 15, wherein, The second filling layer has a via exposing at least a part of the second connection terminal, and the second auxiliary electrode is overlapped with the second connection terminal through the via.

18. The light-emitting chip according to claim 17, wherein, Along the direction from the center of the chip body to the outside, the distance between the side wall of the second filling layer close to the chip body and the side wall of the via close to the chip body is greater than the size of the insulating layer.

19. The light-emitting chip according to claim 15, wherein, the orthographic projection of the second electrode on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate.

20. The light-emitting chip according to claim 1, wherein, the first semiconductor layer is an N-type semiconductor layer, and the first preset voltage is a negative voltage; and / or the second semiconductor layer is a P-type semiconductor layer, and the second preset voltage is a positive voltage.

21. A method for manufacturing a light-emitting chip, wherein, the manufacturing method includes: providing a substrate; forming a chip body on the substrate, the chip body including: a first electrode formed on the substrate; a first semiconductor layer formed on a side of the first electrode away from the substrate; a light-emitting layer formed on a side of the first semiconductor layer away from the substrate; a second semiconductor layer formed on a side of the light-emitting layer away from the substrate; and a second electrode formed on a side of the second semiconductor layer away from the substrate; forming auxiliary electrodes, including a first auxiliary electrode and / or a second auxiliary electrode, wherein, the first auxiliary electrode is at least partially disposed around the outer periphery of the sidewall of the first semiconductor layer, the first auxiliary electrode is insulated from the first semiconductor layer, and the first auxiliary electrode is configured to be connected to a first preset voltage; and / or the second auxiliary electrode is at least partially disposed around the outer periphery of the sidewall of the second semiconductor layer, the second auxiliary electrode is insulated from the second semiconductor layer, and the second auxiliary electrode is configured to be connected to a second preset voltage.

22. A display panel, wherein, the display panel includes the light-emitting chip according to any one of claims 1-20.

23. A display device, wherein, the display device includes the display panel according to claim 22.

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