Display panel and display device

Abstract

The present disclosure provides a display panel and a display device. The display panel comprises a display area and a peripheral area; a plurality of first signal lines located on a substrate are provided in the peripheral area; the first signal lines each comprise a signal connecting line portion; the orthographic projections of cross-line portions on the substrate partially overlap with the orthographic projections of at least some of second sub-signal lines among a plurality of second sub-signal lines on the substrate; the cross-line portions are spaced apart from the signal connecting line portions comprised in at least some of the second sub-signal lines among the plurality of second sub-signal lines by at least two insulating layers; and / or, the signal connecting line portions comprise a plurality of signal connecting line parts extending in a first direction; the width of the signal connecting line parts in a second direction is smaller than a width threshold; the signal connecting line portions extend in the first direction; and the second direction intersects with the first direction. The present disclosure alleviates the problem of short-circuit of the first signal lines.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, the AD (Abnormal Dislay, abnormal display) and DGS (Data-Gate Short, short circuit between data line and gate line) defects of the clock signal line refer to the short circuit between the source and drain metal layer and the gate metal layer caused by Cu (copper) diffusion, which in turn causes serious defects. In most cases, the diffusion of Cu is believed to be caused by the corrosion of Cu by water vapor infiltration to generate Cu+ and Cu2+ ions, and then the electromigration and thermal migration of Cu occur under the action of voltage. Other possible reasons include foreign matter and ESD (electrostatic discharge) causing the AD of the clock signal line. In the clock signal line area, the voltage difference between the sub-line located in the source and drain metal layer and the busbar located in the gate metal layer is large, and the overlapping area of ​​the source and drain metal layer and the gate metal layer is large, so short circuits often occur in the clock signal area. The overlapping area of ​​the gate metal layer in the source and drain metal layer is sloped, and the structural unevenness caused by film deformation will lead to uneven charge distribution. Generally, reducing the voltage difference between the busbar and the sub-line, or increasing the thickness of the insulating layer between the gate metal layer and the source / drain metal layer, will improve this problem. However, the above method will directly affect the MOS (metal-oxide-semiconductor) structure or cause problems such as film stress mismatch.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display panel, comprising a display area and a peripheral area surrounding the display area, wherein a plurality of first signal lines located on a substrate are provided in the peripheral area; the first signal lines include a signal connection line portion;

[0005] The plurality of first signal lines are divided into first sub-signal lines including a crossover portion and second sub-signal lines not including a crossover portion;

[0006] An orthographic projection of the line-crossing portion on the substrate partially overlaps with an orthographic projection of at least some of the second sub-signal lines among the plurality of second sub-signal lines on the substrate;

[0007] At least two insulating layers are spaced between the cross-line portion and a signal connection line portion included in at least some of the second sub-signal lines among the plurality of second sub-signal lines; and / or the signal connection line portion includes a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portion along the second direction is less than a width threshold;

[0008] The signal connection line portion extends along the first direction, and the second direction intersects with the first direction.

[0009] Optionally, the width threshold is greater than or equal to 5 μm and less than or equal to 8 μm.

[0010] Optionally, the display panel includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged away from the substrate; at least one insulating layer is provided between adjacent conductive layers;

[0011] The cross-line portion is located in the third conductive layer, and the signal connection line portion is located in the first conductive layer.

[0012] Optionally, the first conductive layer includes a light-shielding pattern disposed in the display area, the second conductive layer includes a gate line disposed in the display area, and the third conductive layer includes a data line disposed in the display area.

[0013] Optionally, the first signal line further includes a signal main line portion;

[0014] The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers;

[0015] The third main body line portion is electrically connected to the second main body line portion through a first via;

[0016] An orthographic projection of the first body line portion on the substrate, an orthographic projection of the second body line portion on the substrate, and an orthographic projection of the third body line portion on the substrate at least partially overlap.

[0017] Optionally, the first signal line further includes a signal conducting line portion;

[0018] The signal conducting wire portion is arranged between the signal main wire portion and the signal connecting wire portion;

[0019] The signal conductive line portion includes a first conductive line portion and a second conductive line portion located in different conductive layers;

[0020] The first conductive line portion is electrically connected to the second conductive line portion through a second via hole;

[0021] An orthographic projection of the first conductive wire portion on the substrate at least partially overlaps with an orthographic projection of the second conductive wire portion on the substrate.

[0022] Optionally, the signal connection line portion, the first main line portion and the first conductive line portion are electrically connected, and the third main line portion and the second conductive line portion are electrically connected.

[0023] Optionally, the first signal line further includes a signal main line portion;

[0024] The signal main line portion includes a first main line portion and a second main line portion located in different conductive layers;

[0025] The first main body line portion is electrically connected to the second main body line portion through a third via;

[0026] An orthographic projection of the first body line portion on the substrate and an orthographic projection of the second body line portion on the substrate at least partially overlap.

[0027] Optionally, the signal connection line portion is electrically connected to the first main line portion.

[0028] Optionally, an orthographic projection of the line-jumping portion on the substrate partially overlaps with an orthographic projection of a signal connection line portion included in a first signal line to which the line-jumping portion belongs on the substrate;

[0029] The cross-line portion is electrically connected to a signal connection line portion included in a first signal line to which the cross-line portion belongs through a fourth via hole.

[0030] Optionally, the display panel further includes a fourth conductive layer provided on a side of the third conductive layer away from the substrate;

[0031] The first signal line further includes a signal main line portion;

[0032] The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers;

[0033] The orthographic projection of the third body line portion on the substrate at least partially overlaps with the orthographic projection of the first body line portion on the substrate, and the orthographic projection of the third body line portion on the substrate at least partially overlaps with the orthographic projection of the second body line portion on the substrate;

[0034] The third body line portion is electrically connected to the second body line portion through a fifth via hole, and the third body line portion is electrically connected to the first body line portion through a sixth via hole.

[0035] Optionally, the fourth conductive layer includes a pixel electrode arranged in the display area.

[0036] Optionally, the first signal line further includes a first transition portion; an orthographic projection of the first transition portion on the substrate at least partially overlaps with an orthographic projection of a signal connection line portion of the first signal line to which the cross-line portion belongs on the substrate; an orthographic projection of the first transition portion on the substrate at least partially overlaps with an orthographic projection of the cross-line portion on the substrate;

[0037] The first transfer portion is electrically connected to the signal connection line portion through the seventh via hole, and the first transfer portion is electrically connected to the cross-line portion through the eighth via hole;

[0038] The first transfer portion and the signal connection line are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

[0039] Optionally, the display panel includes a second conductive layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer, and a fourth conductive layer arranged in sequence away from the substrate; the fifth conductive layer overlaps the sixth conductive layer; at least one insulating layer is provided between the second conductive layer and the third conductive layer, at least one insulating layer is provided between the third conductive layer and the fifth conductive layer, and at least one insulating layer is provided between the sixth conductive layer and the fourth conductive layer;

[0040] At least a portion of the cross-line portion is located in the sixth conductive layer, and the signal connection line portion is located in the second conductive layer.

[0041] Optionally, the second conductive layer includes gate lines arranged in the display area, the third conductive layer includes data lines arranged in the display area, the fifth conductive layer includes common electrodes arranged in the display area, and the sixth conductive layer includes auxiliary metal patterns arranged in the display area.

[0042] Optionally, the first signal line further includes a first transfer portion;

[0043] The first transfer portion is electrically connected to the signal connection line portion through a ninth via hole, and the first transfer portion is electrically connected to the cross-line portion through a tenth via hole;

[0044] The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

[0045] Optionally, the first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is overlapped with the crossover portion;

[0046] The first transfer portion is electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

[0047] The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

[0048] Optionally, the first signal line further includes a third adapter and a connecting line;

[0049] The third adapter portion is electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion is electrically connected to the connecting line through a twelfth via hole;

[0050] The third transfer portion and the cross-line portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

[0051] Optionally, the first signal line further includes a first connecting portion located in the fifth conductive layer; the first connecting portion is overlapped with the crossover portion;

[0052] The orthographic projection of the first connecting portion on the substrate covers the orthographic projection of the cross-line area on the substrate;

[0053] The cross-line region is an overlapping region between the cross-line portion and a signal connection line portion included in at least some of the second sub-signal lines in the plurality of second sub-signal lines.

[0054] Optionally, the cross-line portion includes a first cross-line portion and a second cross-line portion;

[0055] The orthographic projection of the first cross-line portion on the substrate covers the orthographic projection of the second cross-line portion on the substrate;

[0056] The first jumper portion is directly overlapped with the second jumper portion.

[0057] Optionally, the first signal line further includes a first transition portion and a second transition portion; the second transition portion is electrically connected to the first cross-line portion;

[0058] The first transfer portion is electrically connected to the clock signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

[0059] The first transfer portion and the signal connection line portion are located in different conductive layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

[0060] Optionally, the first signal line further includes a third adapter, a fourth adapter and a connecting line;

[0061] The fourth transition portion is electrically connected to the first cross-line portion; the fourth transition portion and the first cross-line portion are located in the same conductive layer;

[0062] The third adapter portion is electrically connected to the fourth adapter portion through the fifteenth via hole, and the third adapter portion is electrically connected to the connecting line through the sixteenth via hole;

[0063] The third transition portion and the fourth transition portion are located in different conductive layers, and the third transition portion and the connecting line are located in different conductive layers.

[0064] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a planar layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

[0066] FIG2 is a planar layout diagram of the light-shielding metal layer in FIG1 ;

[0067] FIG3 is a planar layout diagram of the gate metal layer in FIG1 ;

[0068] FIG4 is a planar layout diagram of the source and drain metal layers in FIG1 ;

[0069] FIG5 is a cross-sectional view of AA' in FIG4;

[0070] FIG6 is a BB' cross-sectional view in FIG4;

[0071] FIG7A is a cross-sectional view of FIG4 ;

[0072] FIG7B is a schematic diagram of components in the peripheral area ZY and the display area AA of the display panel;

[0073] FIG7C is a cross-sectional view KK' in FIG7B;

[0074] FIG8 is a pattern obtained by forming a light-shielding metal layer and etching it when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A;

[0075] FIG9 shows a pattern obtained by forming a buffer layer, forming a gate insulating layer, forming and etching a gate metal layer, and etching the gate insulating layer using the gate metal layer as a mask when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A;

[0076] FIG10 is a schematic diagram showing the formation of overlapping holes between the light-shielding metal layer, the gate metal layer, and the source / drain metal layer after the interlayer dielectric layer is formed when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A ;

[0077] FIG11 is a pattern obtained by forming a source / drain metal layer and etching it when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A ;

[0078] 12A, 12B, 12C, 12D, 12E, 12F and 12G are cross-sectional views of the above steps;

[0079] 13 is a planar layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

[0080] FIG14 is a planar layout diagram of the light-shielding metal layer in FIG13;

[0081] FIG15 is a planar layout diagram of the source / drain metal layer in FIG13 ;

[0082] FIG16 is a sectional view DD' in FIG13;

[0083] FIG17 is a layout diagram of first signal lines in a display panel according to at least one embodiment of the present disclosure;

[0084] FIG18 is a planar layout diagram of the light-shielding metal layer in FIG17;

[0085] FIG19 is a planar layout diagram of the source / drain metal layer in FIG17 ;

[0086] FIG20 is a planar layout diagram of the pixel electrode layer in FIG17;

[0087] FIG21 is a cross-sectional view of EE' in FIG17;

[0088] FIG22 is a planar layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

[0089] FIG23 is a planar layout diagram of the gate metal layer in FIG22;

[0090] FIG24 is a planar layout diagram of the source / drain metal layer in FIG22 ;

[0091] FIG25 is a planar layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

[0092] FIG26 is a planar layout diagram of the gate metal layer in FIG25;

[0093] FIG27 is a planar layout diagram of the source metal layer in FIG25;

[0094] FIG28 is a planar layout diagram of the metal auxiliary layer in FIG25;

[0095] FIG29A is a planar layout diagram of the pixel electrode layer in FIG25;

[0096] FIG29B is a schematic diagram of components in the peripheral area ZY and the display area AA of the display panel;

[0097] FIG29C is a cross-sectional view of FIG29B at LL';

[0098] FIG30 is a cross-sectional view of FIG25 ;

[0099] FIG31 is a cross-sectional view of FIG25 ;

[0100] FIG32 is a cross-sectional view of FIG25 ′;

[0101] 33 and 34 are plan layout diagrams of first signal lines in a display panel according to at least one embodiment of the present disclosure;

[0102] FIG35 is a cross-sectional view II' in FIG33;

[0103] FIG36 is a planar layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

[0104] FIG37 is a planar layout diagram of the gate metal layer in FIG36;

[0105] FIG38 is a planar layout diagram of the source / drain metal layer in FIG36 ;

[0106] FIG39 is a planar layout diagram of the common electrode layer in FIG36;

[0107] FIG40 is a planar layout diagram of the metal auxiliary layer in FIG36;

[0108] FIG41 is a planar layout diagram of the pixel electrode layer in FIG36;

[0109] FIG42 is a JJ' cross-sectional view in FIG36;

[0110] FIG43 is a planar layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

[0111] FIG44 is a planar layout diagram of the gate metal layer in FIG43;

[0112] FIG45 is a planar layout diagram of the source / drain metal layer in FIG43;

[0113] FIG46 is a planar layout diagram of the common electrode layer in FIG43;

[0114] FIG47 is a planar layout diagram of the metal auxiliary layer in FIG43;

[0115] FIG48 is a planar layout diagram of the pixel electrode layer in FIG43;

[0116] FIG49 is a diagram showing a pattern obtained after forming a gate metal layer when manufacturing the first signal line shown in FIG33;

[0117] FIG50 shows a pattern obtained by forming a gate insulating layer, forming and etching a semiconductor layer, and forming and etching a source / drain metal layer when manufacturing the first signal line shown in FIG33;

[0118] FIG51 shows a pattern obtained by forming a first passivation layer, coating, exposing and developing an organic layer, and forming and etching a common electrode layer when manufacturing the first signal line shown in FIG33 ;

[0119] FIG52 shows a pattern obtained by forming and etching a metal auxiliary layer when manufacturing the first signal line shown in FIG33;

[0120] FIG53 is a schematic diagram showing the arrangement of overlapping hole areas on the metal auxiliary layer, the gate metal layer, and the source / drain metal layer when fabricating the first signal line shown in FIG33 ;

[0121] FIG54 shows a pattern obtained by forming and etching a pixel electrode layer when manufacturing the first signal line shown in FIG33;

[0122] FIG55 is a diagram showing a pattern obtained by forming and etching a gate metal layer when manufacturing the first signal line shown in FIG43;

[0123] FIG56 shows a pattern obtained by forming a gate insulating layer, forming a semiconductor layer, etching, and forming a source / drain metal layer, and etching when manufacturing the first signal line shown in FIG43;

[0124] FIG57 shows a pattern obtained by forming a first passivation layer, coating, exposing and developing an organic layer, and forming and etching a common electrode layer when manufacturing the first signal line shown in FIG43;

[0125] FIG58 shows a pattern obtained by forming and etching a metal auxiliary layer when manufacturing the first signal line shown in FIG43;

[0126] FIG59 is a schematic diagram showing the arrangement of overlapping areas on the common electrode layer, the gate metal layer, and the source / drain metal layer when fabricating the first signal line shown in FIG43;

[0127] FIG60 shows a pattern obtained by forming and etching the pixel electrode layer when manufacturing the first signal line shown in FIG43. DETAILED DESCRIPTION

[0128] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0129] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0130] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0131] The display panel according to the embodiment of the present disclosure includes a display area and a peripheral area surrounding the display area. A plurality of first signal lines located on a substrate are provided in the peripheral area. The first signal lines include a signal connection line portion.

[0132] The plurality of first signal lines are divided into a plurality of first sub-signal lines including cross-line portions and a plurality of second sub-signal lines not including cross-line portions;

[0133] The orthographic projection of the cross-line portion on the substrate partially overlaps with the orthographic projection of the signal connection line portion included in at least some of the second sub-signal lines among the plurality of second sub-signal lines on the substrate;

[0134] At least two insulating layers are spaced between the cross-line portion and at least some of the second sub-signal lines of the plurality of second sub-signal lines; and / or the signal connection line portion includes a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portions along the second direction is less than a width threshold;

[0135] The signal connection line portion extends along the first direction, and the second direction intersects with the first direction.

[0136] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction; or, the first direction may be a horizontal direction, and the second direction may be a vertical direction; but the present invention is not limited thereto.

[0137] In each plan layout diagram of the present disclosure, an XY coordinate system is drawn, wherein the Y direction may be a first direction and the X direction may be a second direction; for example, the X direction may be a horizontal direction and the Y direction may be a vertical direction.

[0138] In at least one embodiment of the present disclosure, the signal connection line portion included in the cross-line portion and at least part of the second sub-signal lines in the plurality of second sub-signal lines is arranged to be separated by at least two insulating layers; and / or, the signal connection line portion is arranged to include a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portion along the second direction is set to be less than a width threshold, so as to improve the short circuit problem of the first signal line without affecting the MOS structure or causing problems such as film layer stress mismatch.

[0139] In at least one embodiment of the present disclosure, the width threshold is greater than or equal to 5 μm and less than or equal to 8 μm.

[0140] In a specific implementation, the width threshold may be greater than or equal to 5 μm and less than or equal to 8 μm. For example, the width threshold may be 6 μm; but the present invention is not limited thereto.

[0141] In at least one embodiment of the present disclosure, the first signal lines can be divided into two categories:

[0142] The first type is a first sub-signal line including a cross-line portion;

[0143] The second type is the second sub-signal line that does not include a crossover portion.

[0144] Optionally, the first signal line may be a clock signal line, but is not limited thereto.

[0145] In a specific implementation, the first signal line may also be a signal line of other types. At least one embodiment of the present disclosure may also be applicable to other via-hole connection scenarios in a display panel.

[0146] Optionally, the display panel includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged away from the substrate; at least one insulating layer is provided between adjacent conductive layers;

[0147] The cross-line portion is located in the third conductive layer, and the signal connection line portion is located in the first conductive layer.

[0148] In at least one embodiment of the present disclosure, the first conductive layer may be a light-shielding metal layer, the second conductive layer may be a gate metal layer, and the third conductive layer may be a source-drain metal layer;

[0149] A buffer layer and a gate insulating layer may be provided between the light-shielding metal layer and the gate metal layer, the buffer layer being provided between the gate insulating layer and the light-shielding metal layer, and an interlayer dielectric layer being provided between the gate metal layer and the source / drain metal layer;

[0150] The line-jumping portion may be located in the third conductive layer, the signal connection line may be located in the first conductive layer, and a buffer layer and an interlayer dielectric layer may be provided between the line-jumping portion and the signal connection line.

[0151] In at least one embodiment of the present disclosure, the first conductive layer may include a light-shielding pattern disposed in the display area, the second conductive layer may include a gate line disposed in the display area, and the third conductive layer may include a data line disposed in the display area.

[0152] As shown in FIG1 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1 ;

[0153] The second first signal line includes a second signal connection line portion LX2;

[0154] The orthographic projection of the cross-line portion LK1 on the substrate partially overlaps with the orthographic projection of the second signal connection line portion LX2 on the substrate;

[0155] The cross-line portion LK1 is formed in the source-drain metal layer, and the first signal connection line portion LX1 and the second signal connection line portion LX2 are formed in the light-shielding metal layer;

[0156] The first signal connection line portion LX1 and the second signal connection line portion LX2 extend in a vertical direction.

[0157] In a specific implementation, the first signal line can be set in the peripheral area of ​​the display panel. For example, the first signal line can be set on the left side and / or right side of the display area of ​​the display panel. The first signal line can extend in the vertical direction, but is not limited to this.

[0158] Figure 1 is a planar layout diagram of at least one embodiment of two first signal lines in a display panel, Figure 2 is a planar layout diagram of the light-shielding metal layer in Figure 1, Figure 3 is a planar layout diagram of the gate metal layer in Figure 1, and Figure 4 is a planar layout diagram of the source and drain metal layer in Figure 1.

[0159] In at least one embodiment of the present disclosure, the first signal line further includes a signal main line portion;

[0160] The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers;

[0161] The third main body line portion is electrically connected to the second main body line portion through a first via;

[0162] An orthographic projection of the first body line portion on the substrate, an orthographic projection of the second body line portion on the substrate, and an orthographic projection of the third body line portion on the substrate at least partially overlap.

[0163] In a specific implementation, the first signal line may further include a signal main line portion;

[0164] The signal main line portion may include a first main line portion, a second main line portion and a third main line portion, the first main line portion may be located in a first conductive layer, the second main line portion may be located in a second conductive layer, and the third main line portion may be located in a third conductive layer; the third main line portion may be electrically connected to the second main line portion through a first via.

[0165] As shown in FIG1-4 , the first first signal line further includes a first signal main line portion ZX1 , and the second first signal line further includes a second signal main line portion ZX2 ;

[0166] The first signal body line portion may include a first body line portion ZXB1, a second body line portion ZXB2, and a third body line portion ZXB3;

[0167] ZXB1 is located in the light-shielding metal layer, ZXB2 is located in the gate metal layer, and ZXB3 is located in the source and drain metal layer;

[0168] The third main body line portion ZXB3 is electrically connected to the second main body line portion ZXB2 through a first via hole H1.

[0169] In at least one embodiment of the present disclosure, the first signal line further includes a signal conducting line portion;

[0170] The signal conducting wire portion is arranged between the signal main wire portion and the signal connecting wire portion;

[0171] The signal conductive line portion includes a first conductive line portion and a second conductive line portion located in different conductive layers;

[0172] The first conductive line portion is electrically connected to the second conductive line portion through a second via hole;

[0173] An orthographic projection of the first conductive wire portion on the substrate at least partially overlaps with an orthographic projection of the second conductive wire portion on the substrate.

[0174] In a specific implementation, the first signal line may further include a signal conducting wire portion; the signal conducting wire portion may be arranged between the signal main line portion and the signal connecting line portion; the signal conducting wire portion may include a first conducting wire portion and a second conducting wire portion, the first conducting wire portion may be located in the first conductive layer, and the second conducting wire portion may be located in the third conductive layer; the first conducting wire portion may be electrically connected to the second conducting wire portion through a second via.

[0175] In at least one embodiment of the present disclosure, the signal connection line portion, the first main body line portion, and the first conductive line portion are electrically connected, and the third main body line portion and the second conductive line portion are electrically connected.

[0176] In a specific implementation, the signal connection line portion, the first main body line portion, and the first conductive line portion may be electrically connected to each other, and the third main body line portion and the second conductive line portion may be electrically connected to each other.

[0177] As shown in FIG1 to FIG4 , the first first signal line may include a first signal conducting line portion DX1; the second first signal line may include a second signal conducting line portion DX2;

[0178] DX1 is set between ZX1 and LX1;

[0179] The first signal conductive line portion DX1 includes a first conductive line portion DXB1 and a second conductive line portion DXB2; DXB1 may be located in the light shielding metal layer, and DXB2 may be located in the source / drain metal layer; DXB1 may be electrically connected to DXB2 through a second via H2;

[0180] The orthographic projection of the first conductive line portion DXB1 on the substrate at least partially overlaps with the orthographic projection of the second conductive line portion DXB2 on the substrate;

[0181] The signal connection line portion LX1, the first main line portion ZXB1, and the first conductive line portion DXB1 are electrically connected, and the third main line portion ZXB3 and the second conductive line portion DXB2 are electrically connected.

[0182] In at least one embodiment of the present disclosure, an orthographic projection of the line-jumping portion on the substrate partially overlaps with an orthographic projection of a signal connection line portion of a first signal line to which the line-jumping portion belongs on the substrate;

[0183] The cross-line portion is electrically connected to a signal connection line portion included in a first signal line to which the cross-line portion belongs through a fourth via hole.

[0184] As shown in FIG1 to FIG4 , the orthographic projection of the cross-line portion LK1 on the substrate partially overlaps with the orthographic projection of the first signal connection line portion LX1 on the substrate;

[0185] The cross-line portion LK1 is electrically connected to the first signal connection line portion LX1 through a fourth via H4 .

[0186] 5 is a cross-sectional view taken along line AA′ in FIG. 4 , FIG. 6 is a cross-sectional view taken along line BB′ in FIG. 4 , and FIG. 7A is a cross-sectional view taken along line CC′ in FIG. 4 .

[0187] In Figures 5-7A, numbered 10 is the substrate, numbered 11 is the light-shielding metal layer, numbered 12 is the buffer layer, numbered 13 is the gate insulating layer, numbered 14 is the gate metal layer, numbered 15 is the interlayer dielectric layer, numbered 16 is the source-drain metal layer, numbered 17 is the first passivation layer, and numbered 18 is the second passivation layer.

[0188] In at least one embodiment shown in Figures 1 to 7A, the crossing portion LK1 crosses the second first signal line to introduce the GOA (Gate On Array, a gate drive circuit provided on the array substrate) area. During the original interlayer dielectric layer etching process, the etching time is appropriately increased to ensure that the buffer layer is etched together with the interlayer dielectric layer, so that the source and drain metal layers can be directly connected to the light-shielding metal layer during film formation to complete signal transmission.

[0189] In at least one embodiment shown in Figures 1 to 7A, the spacing between the first first signal line and the second first signal line is about 7 μm, the width of the first main line portion ZXB1 along the horizontal direction can be about 17 μm, the width of the second main line portion ZXB2 along the horizontal direction can be about 14.6 μm, and the width of the third main line portion ZXB3 along the horizontal direction can be about 11.2 μm; based on the impedance reduction of the signal main line portion of the three-layer structure, the width of each main line portion along the horizontal direction can be appropriately reduced, thereby reducing the border width; for example, the width of each main line portion along the horizontal direction can be reduced by about 3.5 μm compared with the related art, which is beneficial to reducing the border width to a certain extent.

[0190] In at least one embodiment shown in Figures 1-7A, the insulating layer between the cross-line portion LK1 and the first signal connection line portion LX1 is a buffer layer and an interlayer dielectric layer. The total thickness of the insulating layer between LK1 and LX1 is approximately 8000 angstroms. Compared with the related art, the total thickness of the insulating layer has doubled, which can effectively improve the AD problem of the first signal line; at the same time, the three-layer metal structure of the first signal line can also reduce the resistance of the first signal line and reduce the signal load.

[0191] In at least one embodiment shown in Figures 1-7A , although the source and drain metal layers increase in height, the taper angle (slope angle) can be controlled through process parameters, preventing source and drain metal layer breakage from occurring. In a specific implementation, the thicknesses of the buffer layer, the first passivation layer, and the second passivation layer can be 4500 angstroms, 3000 angstroms, and 2000 angstroms, respectively, while the source and drain metal layers are between 3300 and 3500 angstroms thick, eliminating the source and drain metal layer breakage issue.

[0192] When at least one embodiment shown in Figures 1 to 7A is adopted, the thickness of the left and right frames of the display panel is changed. The increased thickness is the thickness of the light-shielding metal layer, which is 3300 angstroms. Therefore, in order to ensure the consistency of the overall box thickness of the display panel, a light-shielding metal layer can be added to the upper and lower frames of the display panel. In the upper and lower frames of the display panel, the original single-layer wiring can be changed to a double-layer wiring, the original double-layer wiring can be changed to a three-layer wiring, or a dummy three-layer structure can be made in the sealing area on the terminal side and the bottom side (the dummy three-layer structure includes a conductive pattern formed on the light-shielding metal layer, a conductive pattern formed on the gate metal layer, and a conductive pattern formed on the source and drain metal layer) to ensure the overall box thickness.

[0193] When manufacturing the first signal line in at least one embodiment shown in FIG. 1 to FIG. 7A , the specific improvement process is as follows:

[0194] 1. The light-shielding metal layer is formed and etched to obtain the pattern shown in FIG8 ;

[0195] 2. Forming a buffer layer, forming a gate insulating layer, forming a gate metal layer and etching the gate insulating layer, and using the gate metal layer as a mask to etch the gate insulating layer to obtain the pattern shown in FIG9 ;

[0196] 3. Form the interlayer dielectric layer, and increase the etching time to open holes at the position shown in Figure 10 to make overlapping holes between the light-shielding metal layer, the gate metal layer, and the source and drain metal layer;

[0197] 4. Form the source and drain metal layer and etch it to obtain the pattern shown in Figure 11;

[0198] The subsequent steps are forming a first passivation layer and forming a second passivation layer, which are no different from the processes in the related art.

[0199] Cross-sectional views of the above steps are shown in FIG. 12A , FIG. 12B , FIG. 12C , FIG. 12D , FIG. 12E , FIG. 12F , and FIG. 12G .

[0200] As shown in FIG12A , a light-shielding metal layer is formed and etched on the substrate 10 , and a buffer layer is formed;

[0201] As shown in FIG12B , a gate insulating layer and a gate metal layer are formed;

[0202] As shown in FIG12C , the gate metal layer is etched, and the gate insulating layer is etched using the gate metal layer as a mask;

[0203] As shown in FIG12D , the interlayer dielectric layer is formed;

[0204] As shown in FIG12E , the interlayer dielectric layer is etched;

[0205] As shown in FIG12F , the source and drain metal layers are formed and etched;

[0206] As shown in FIG12G , the first passivation layer and the second passivation layer are formed.

[0207] As shown in FIG7B , the two first signal lines shown in FIG1 are provided in the peripheral area ZY, and the gate line GL, the data line DL and the transistors in the sub-pixels are provided in the display area AA;

[0208] In FIG. 7B , ZX is a light-shielding pattern, A1 is an active pattern of the transistor, VCOM is a common electrode, and PX is a pixel electrode.

[0209] In at least one embodiment corresponding to Figure 7B, the shading pattern ZX is located in the shading metal layer, the active pattern A1 of the transistor is located in the semiconductor layer, the pixel electrode PX is located in the pixel electrode layer, the common electrode VCOM is located in the common electrode layer, the gate line GL is located in the gate metal layer, and the data line DL is located in the source and drain metal layer.

[0210] FIG. 7C is a cross-sectional view taken along line KK′ in FIG. 7B .

[0211] In Figure 7C, the number 10 is the substrate, the number 11 is the light-shielding metal layer, the number 12 is the buffer layer, the number 21 is the semiconductor layer, the number 13 is the gate insulating layer, the number 14 is the gate metal layer, the number 15 is the interlayer dielectric layer, the number 16 is the source and drain metal layer, the number 17 is the first passivation layer, the number 22 is the organic layer, the number 111 is the common electrode layer, the number 18 is the second passivation layer, and the number 19 is the pixel electrode layer. In the related art, dry etching of the gate insulation layer on the entire surface of a large glass plate may result in a poor taper angle of the gate insulation layer or even over-etching, thereby causing the subsequent interlayer dielectric layer to break, causing the source and drain metal layers to penetrate deep into the interlayer dielectric layer fracture during film formation, thereby shortening the local spacing between the source and drain metal layers and the gate metal layer, making the capacitor structure of the source and drain metal layer-interlayer dielectric layer-gate metal layer susceptible to breakdown, and increasing the probability of Cu interconnection. In order to avoid the problems of poor taper angle of the gate insulation layer and dry etching of the gate insulation layer caused by dry etching of the gate insulation layer, in at least one embodiment of the present disclosure, the first signal line can adopt a double-layer metal structure, and the signal main line portion can be set to include a first main line portion and a second main line portion, the first main line portion can be located in the first conductive layer, and the second main line portion can be located in the third conductive layer.

[0212] In at least one embodiment of the present disclosure, the multi-signal line further includes a signal main line portion;

[0213] The signal main line portion includes a first main line portion and a second main line portion located in different conductive layers;

[0214] The first main body line portion is electrically connected to the second main body line portion through a third via;

[0215] An orthographic projection of the first body line portion on the substrate and an orthographic projection of the second body line portion on the substrate at least partially overlap.

[0216] In a specific implementation, the first signal line may further include a signal main line portion, and the signal main line portion may include a first main line portion and a second main line portion;

[0217] Optionally, the first main line portion is located in the first conductive layer, and the second main line portion forms the third conductive layer.

[0218] In at least one embodiment of the present disclosure, the signal connection line portion is electrically connected to the first main body line portion.

[0219] As shown in FIG13 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1 ;

[0220] The second first signal line includes a second signal connection line portion LX2;

[0221] The orthographic projection of the cross-line portion LK1 on the substrate partially overlaps with the orthographic projection of the second signal connection line portion LX2 on the substrate;

[0222] The cross-line portion LK1 is formed in the source-drain metal layer, and the first signal connection line portion LX1 and the second signal connection line portion LX2 are formed in the light-shielding metal layer;

[0223] The first signal connection line portion LX1 and the second signal connection line portion LX2 extend in a vertical direction.

[0224] In a specific implementation, the first signal line can be set in the peripheral area of ​​the display panel. For example, the first signal line can be set on the left side and / or right side of the display area of ​​the display panel. The first signal line can extend in the vertical direction, but is not limited to this.

[0225] 13 is a planar layout diagram of at least one embodiment of two first signal lines in a display panel, FIG14 is a planar layout diagram of a light-shielding metal layer in FIG13 , and FIG15 is a planar layout diagram of a source / drain metal layer in FIG13 .

[0226] As shown in FIG13-15 , the first first signal line further includes a first signal main line portion ZX1 , and the second first signal line further includes a second signal main line portion ZX2 ;

[0227] The first signal main line portion may include a first main line portion ZXB1 and a second main line portion ZXB2;

[0228] ZXB1 is located in the light-shielding metal layer, and ZXB2 is located in the source and drain metal layer;

[0229] The first main body line portion ZXB1 is electrically connected to the second main body line portion ZXB2 through a third via H3;

[0230] An orthographic projection of the first body line portion ZXB1 on the substrate and an orthographic projection of the second body line portion ZXB2 on the substrate at least partially overlap.

[0231] FIG. 16 is a cross-sectional view taken along line DD′ in FIG. 13 .

[0232] In Figure 16, the number 10 is the substrate, the number 11 is the shading metal layer, the number 12 is the buffer layer, the number 15 is the interlayer dielectric layer, the number 16 is the source and drain metal layer, the number 17 is the first passivation layer, and the number 18 is the second passivation layer.

[0233] In specific implementation, in addition to the solution of directly connecting the source / drain metal layer and the light-shielding metal layer, a solution of overlapping the source / drain metal layer and the light-shielding metal layer with the pixel electrode layer may also be adopted.

[0234] In at least one embodiment of the present disclosure, the display panel further includes a fourth conductive layer disposed on a side of the third conductive layer away from the substrate;

[0235] The first signal line further includes a signal main line portion;

[0236] The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers;

[0237] The orthographic projection of the third body line portion on the substrate at least partially overlaps with the orthographic projection of the first body line portion on the substrate, and the orthographic projection of the third body line portion on the substrate at least partially overlaps with the orthographic projection of the second body line portion on the substrate;

[0238] The third body line portion is electrically connected to the second body line portion through a fifth via hole, and the third body line portion is electrically connected to the first body line portion through a sixth via hole.

[0239] In at least one embodiment of the present disclosure, the fourth conductive layer may include a pixel electrode disposed in the display area.

[0240] Optionally, the first main line portion is located in the first conductive layer, the second main line portion forms the third conductive layer, and the third main line portion is located in the fourth conductive layer.

[0241] In at least one embodiment of the present disclosure, the fourth conductive layer may be a pixel electrode layer, which may be made of, for example, ITO (indium tin oxide), and may be disposed on a side of the second passivation layer away from the source / drain metal layer.

[0242] Figure 17 is a plan layout diagram of at least one embodiment of two first signal lines in the display panel, Figure 18 is a plan layout diagram of the light-shielding metal layer in Figure 17, Figure 19 is a plan layout diagram of the source and drain metal layer in Figure 17, and Figure 20 is a plan layout diagram of the pixel electrode layer in Figure 17.

[0243] As shown in FIG17 to FIG20 , the first first signal line includes a first signal main line portion ZX1 , and the second first signal line includes a second signal main line portion ZX2 ;

[0244] The first signal body line portion may include a first body line portion ZXB1, a second body line portion ZXB2, and a third body line portion ZXB3;

[0245] ZXB1 can be located in the light-shielding metal layer, ZXB2 can be located in the source / drain metal layer, and ZXB3 can be located in the pixel electrode layer;

[0246] The orthographic projection of the third main body line portion ZXB3 on the substrate at least partially overlaps with the orthographic projection of the first main body line portion ZXB1 on the substrate, and the orthographic projection of the third main body line portion ZXB3 on the substrate at least partially overlaps with the orthographic projection of the second main body line portion ZXB2 on the substrate;

[0247] The third main line portion ZXB3 is electrically connected to the second main line portion ZXB2 through a fifth via hole H5 , and the third main line portion ZXB3 is electrically connected to the first main line portion ZXB1 through a sixth via hole H6 .

[0248] In at least one embodiment of the present disclosure, the first signal line further includes a first transition portion; an orthographic projection of the first transition portion on the substrate at least partially overlaps with an orthographic projection of a signal connection line portion of the first signal line to which the cross-line portion belongs on the substrate; an orthographic projection of the first transition portion on the substrate at least partially overlaps with an orthographic projection of the cross-line portion on the substrate;

[0249] The first transfer portion is electrically connected to the signal connection line portion through the seventh via hole, and the first transfer portion is electrically connected to the cross-line portion through the eighth via hole;

[0250] The first transfer portion and the signal connection line are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

[0251] In a specific implementation, the first signal line may further include a first transfer portion, the first transfer portion may be electrically connected to the signal connection line portion through a seventh via hole, and the first transfer portion may be electrically connected to the cross-line portion through an eighth via hole.

[0252] Optionally, the first transition portion is located in the fourth conductive layer.

[0253] As shown in FIG17 to FIG20 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1;

[0254] The second first signal line includes a second signal connection line portion LX2;

[0255] The orthographic projection of the cross-line portion LK1 on the substrate partially overlaps with the orthographic projection of the second signal connection line portion LX2 on the substrate;

[0256] The cross-line portion LK1 is formed in the source-drain metal layer, and the first signal connection line portion LX1 and the second signal connection line portion LX2 are formed in the light-shielding metal layer;

[0257] The first signal connection line portion LX1 and the second signal connection line portion LX2 extend in a vertical direction;

[0258] The first first signal line further includes a first transfer portion ZJ1;

[0259] The first connecting portion ZJ1 is located in the pixel electrode layer;

[0260] The orthographic projection of the first transition portion ZJ1 on the substrate at least partially overlaps with the orthographic projection of the first signal connection line portion LX1 on the substrate; the orthographic projection of the first transition portion ZJ1 on the substrate at least partially overlaps with the orthographic projection of the cross-line portion LX1 on the substrate;

[0261] The first transfer portion ZJ1 is electrically connected to the first signal connection line portion LX1 through the seventh via H7 , and the first transfer portion ZJ1 is electrically connected to the cross-line portion LK1 through the eighth via H8 .

[0262] FIG21 is a cross-sectional view taken along line EE′ in FIG17 .

[0263] As shown in Figures 17 to 21, the specific process of making the first signal line shown in Figure 17 is basically the same as the relevant process, that is, the etching time of the interlayer dielectric layer does not change, and a overlapping hole area is made above the light-shielding metal layer in the form of a sleeve hole (interlayer dielectric layer hole + passivation layer hole), and a passivation layer hole is opened above the source and drain metal layer, so that when the pixel electrode layer is formed, the light-shielding metal layer and the source and drain metal layer are overlapped together, and the pixel electrode layer is well climbed.

[0264] In Figure 21, the number 10 is the substrate, the number 11 is the light-shielding metal layer, the number 12 is the buffer layer, the number 15 is the interlayer dielectric layer, the number 16 is the source and drain metal layer, the number 17 is the first passivation layer, the number 18 is the second passivation layer, and the number 19 is the pixel electrode layer.

[0265] In actual operation, measurements were made of the gate insulation layer taper angle and over-etching after dry etching of gate metal layers with different line widths. It was found that poor gate insulation layer taper angle and over-etching only occur when the line width of the signal connection line portion formed in the gate metal layer is larger. Therefore, in at least one embodiment of the present disclosure, the signal connection line portion can be configured to include multiple signal connection line portions extending along a first direction, and the width of each signal connection line portion along a second direction can be less than a width threshold. For example, the line width of each signal connection line portion can be greater than or equal to 4μm and less than or equal to 6μm to ensure that the overall square resistance of the first signal line remains at the original level.

[0266] 22 is a planar layout diagram of at least one embodiment of two first signal lines in a display panel, FIG23 is a planar layout diagram of a gate metal layer in FIG22 , and FIG24 is a planar layout diagram of a source / drain metal layer in FIG22 .

[0267] As shown in FIG22 to FIG24 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1;

[0268] The second first signal line includes a second signal connection line portion LX2;

[0269] LK1 is located in the source and drain metal layer, and LX1 and LX2 are formed in the gate metal layer;

[0270] The second signal connection line portion includes a first signal connection line portion LXB1, a second signal connection line portion LXB2 and a third signal connection line portion LXB3;

[0271] LXB1, LXB2 and LXB3 all extend in a vertical direction, and LXB1, LXB2 and LXB3 are all located in the gate metal layer;

[0272] The width of LXB1 along the horizontal direction, the width of LXB2 along the horizontal direction, and the width of LXB3 along the horizontal direction may be greater than or equal to 4 μm and less than or equal to 6 μm;

[0273] The orthographic projection of LK1 on the base partially overlaps with the orthographic projection of LXB1 on the base, the orthographic projection of LK1 on the base partially overlaps with the orthographic projection of LXB2 on the base, and the orthographic projection of LK1 on the base partially overlaps with the orthographic projection of LXB3 on the base.

[0274] As shown in FIG22 to FIG24 , the first first signal line includes a first signal main line portion ZX1 , and the second first signal line includes a second signal main line portion ZX2 ;

[0275] The first signal main line portion may include a first main line portion ZXB1 and a second main line portion ZXB2;

[0276] ZXB1 is located in the gate metal layer, and ZXB2 is located in the source and drain metal layer;

[0277] ZXB1 is electrically connected to ZXB2 through a via hole, and the cross-line portion LK1 is electrically connected to LX1 through a via hole. The orthographic projection of LK1 on the substrate partially overlaps with the orthographic projection of LX1 on the substrate.

[0278] In the above embodiment, the first signal line may be applied to a display panel, and the GOA circuit in the display panel includes a top-gate self-alignment TFT (thin film transistor).

[0279] In at least one embodiment of the present disclosure, the structure of the first signal line may be applied to a display panel, and a GOA circuit in the display panel may include a BCE (back channel etched) TFT having a metal auxiliary layer.

[0280] In a BCE (back-channel etched) TFT with a metal auxiliary layer, a new metal auxiliary layer, known as the M3 layer, can be added to the BCE TFT. The M3 layer directly blocks the common electrode layer, which can be made of, for example, ITO. This reduces the sheet resistance of the common electrode layer, thereby reducing crosstalk defects and improving the yield of display products. At least one embodiment of the present disclosure utilizes the M3 process to improve the first signal line AD defect solution. Specifically, in the first signal line region, the crossover portion can be positioned within the metal auxiliary layer, separating the crossover portion from the signal connection portion by at least one insulating layer. This increases the thickness of the insulating layer between the crossover portion and the signal connection portion, thereby reducing the incidence of first signal line AD defects.

[0281] In at least one embodiment of the present disclosure, the display panel includes a second conductive layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer, and a fourth conductive layer arranged in sequence away from the substrate; the fifth conductive layer overlaps the sixth conductive layer; at least one insulating layer is provided between the second conductive layer and the third conductive layer, at least one insulating layer is provided between the third conductive layer and the fifth conductive layer, and at least one insulating layer is provided between the sixth conductive layer and the fourth conductive layer;

[0282] At least a portion of the cross-line portion is located in the sixth conductive layer, and the signal connection line portion is located in the second conductive layer.

[0283] In at least one embodiment of the present disclosure, the second conductive layer includes gate lines arranged in the display area, the third conductive layer includes data lines arranged in the display area, the fifth conductive layer includes common electrodes arranged in the display area, and the sixth conductive layer includes auxiliary metal patterns arranged in the display area.

[0284] Optionally, the second conductive layer may be a gate metal layer, the third conductive layer may be a source / drain metal layer, the fifth conductive layer may be a common electrode layer, the sixth conductive layer may be a metal auxiliary layer, and the fourth conductive layer may be a pixel electrode layer;

[0285] The common electrode layer may be directly overlapped with the metal auxiliary layer;

[0286] At least a portion of the cross-line portion may be located in the metal auxiliary layer, and the signal connection line portion may be located in the gate metal layer, but the present invention is not limited thereto.

[0287] In at least one embodiment of the present disclosure, the metal auxiliary layer may be made of copper, and the gate metal layer and the source / drain metal layer may also be made of copper, but the present invention is not limited thereto.

[0288] As shown in FIG. 25 to FIG. 29A , the first first signal line includes a first signal connection line portion LX1 and a cross-line portion LK1 ;

[0289] The second first signal line includes a second signal connection line portion LX2;

[0290] LX1 and LX2 are located in the gate metal layer, and LK1 is located in the metal auxiliary layer.

[0291] At least one embodiment shown in FIG25 is simple and feasible, does not increase the number of masks, and can significantly reduce the incidence of AD on the first signal line. In at least one embodiment shown in FIG25, in the first signal crossover region, the insulating layer between the crossover portion LK1 and the first signal connection line portion LX1 includes a gate insulating layer and a first passivation layer, and the thickness of the gate insulating layer and the thickness of the first passivation layer are approximately 4000 angstroms and 5000 angstroms, respectively. At least one embodiment of the present disclosure more than doubles the thickness of the insulating layer in the first signal crossover region, which can significantly reduce the AD problem of the first signal line caused by copper interconnection.

[0292] Figure 26 is a planar layout diagram of the gate metal layer in Figure 25, Figure 27 is a planar layout diagram of the source metal layer in Figure 25, Figure 28 is a planar layout diagram of the metal auxiliary layer in Figure 25, and Figure 29A is a planar layout diagram of the pixel electrode layer in Figure 25.

[0293] In at least one embodiment of the present disclosure, the thickness of the metal auxiliary layer may be approximately 3000 angstroms, but is not limited thereto.

[0294] In at least one embodiment of the present disclosure, the first signal line further includes a first transfer portion;

[0295] The first transfer portion is electrically connected to the signal connection line portion through a ninth via hole, and the first transfer portion is electrically connected to the cross-line portion through a tenth via hole;

[0296] The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

[0297] Optionally, the first transition portion is located in the fourth conductive layer.

[0298] As shown in FIG. 25 to FIG. 29A , the first first signal line may further include a first transition portion ZJ1;

[0299] The first transition portion ZJ1 may be located in the pixel electrode layer;

[0300] ZJ1 is electrically connected to the first signal connection line portion LX1 through the ninth via hole H9, and ZJ1 is electrically connected to the cross-line portion LK1 through the tenth via hole H10;

[0301] The orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of LX1 on the substrate, and the orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of the cross-line portion LK1 on the substrate.

[0302] In at least one embodiment of the present disclosure, the first signal line further includes a third transition portion and a connecting line;

[0303] The third adapter portion is electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion is electrically connected to the connecting line through a twelfth via hole;

[0304] The third transfer portion and the cross-line portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

[0305] Optionally, the third transition portion is located in the fourth conductive layer, and the connecting line is located in the third conductive layer.

[0306] In a specific implementation, the first signal line may further include a third transfer portion and a connecting line, the third transfer portion may be located in the pixel electrode layer, and the connecting line may be located in the source / drain metal layer;

[0307] The third adapter portion may be electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion may be electrically connected to the connecting line through a twelfth via hole;

[0308] The connecting line can be electrically connected to at least one TFT in the GOA circuit;

[0309] The third transfer portion, the eleventh via hole and the twelfth via hole may be arranged between the first signal line wiring area and the GOA TFT (the GOA TFT may be a TFT in a GOA circuit) distribution area.

[0310] As shown in FIG. 25 to FIG. 29A , the first first signal line may further include a third transition portion ZJ3 and a connecting line L1;

[0311] The third connecting portion ZJ3 is located in the pixel electrode layer, and the connecting line L1 is located in the source-drain metal layer;

[0312] The third transition portion ZJ3 is electrically connected to the cross-line portion LK1 through the eleventh via hole H11 , and the third transition portion ZJ3 is electrically connected to the connection line L1 through the twelfth via hole H12 .

[0313] FIG30 is a cross-sectional view taken along line FF′ in FIG25 .

[0314] In FIG30 , the number 10 is a substrate, the number 14 is a gate metal layer, the number 13 is a gate insulating layer, the number 17 is a first passivation layer, and the number 110 is a metal auxiliary layer.

[0315] FIG31 is a cross-sectional view taken along line GG′ in FIG25 , and FIG32 is a cross-sectional view taken along line HH′ in FIG25 .

[0316] In Figures 31 and 32, the number 10 is the substrate, the number 13 is the gate insulation layer, the number 14 is the gate metal layer, the number 16 is the source and drain metal layer, the number 17 is the first passivation layer, the number 18 is the second passivation layer, the number 19 is the pixel electrode layer, and the number 110 is the metal auxiliary layer.

[0317] As shown in FIG29B , the two first signal lines shown in FIG25 are provided in the peripheral area ZY, and the gate line GL, the data line DL and the transistors in the sub-pixels are provided in the display area AA;

[0318] In FIG29B , A1 is an active pattern of the transistor, VCOM is a common electrode, FX is an auxiliary metal pattern, and PX is a pixel electrode.

[0319] In at least one embodiment corresponding to Figure 29B, the active pattern A1 of the transistor is located in the semiconductor layer, the pixel electrode PX is located in the pixel electrode layer, the common electrode VCOM is located in the common electrode layer, and the auxiliary metal pattern FX is located in the metal auxiliary layer; the gate line GL is located in the gate metal layer, and the data line DL is located in the source and drain metal layer.

[0320] FIG29C is a cross-sectional view taken along line LL′ in FIG29B .

[0321] In Figure 29C, the number 10 is the substrate, the number 21 is the semiconductor layer, the number 13 is the gate insulating layer, the number 14 is the gate metal layer, the number 16 is the source and drain metal layer, the number 17 is the first passivation layer, the number 22 is the organic layer, the number 110 is the metal auxiliary layer, the number 111 is the common electrode layer, the number 18 is the second passivation layer, and the number 19 is the pixel electrode layer.

[0322] In at least one embodiment of the present disclosure, the first signal line further includes a first connecting portion located in the fifth conductive layer; the first connecting portion overlaps the crossover portion;

[0323] The orthographic projection of the first connecting portion on the substrate covers the orthographic projection of the cross-line area on the substrate;

[0324] The cross-line region is an overlapping region between the cross-line portion and a signal connection line portion included in at least some of the second sub-signal lines in the plurality of second sub-signal lines.

[0325] In a specific implementation, the first signal line may further include a first connecting portion, which may be located in the common electrode layer, and the first connecting portion is directly overlapped with the cross-line portion, and the orthographic projection of the first connecting portion on the substrate may cover the orthographic projection of the cross-line area on the substrate.

[0326] As shown in FIG33 , based on at least one embodiment shown in FIG25 , the first first signal line may further include a first connecting portion LJ1 ;

[0327] The first connection portion LJ1 may be located at the common electrode layer;

[0328] In FIG. 34 , the reference numeral JY indicates an overlapping region between the cross-line portion LK1 and the second signal connection line portion LX2 .

[0329] As shown in Figures 33 and 34 , the orthographic projection of the first connection portion LJ1 on the substrate overlaps the orthographic projection of the overlap region JY on the substrate, further enhancing the diffusion of the resistive copper and reducing the probability of the first signal line AD. At least one embodiment of the present disclosure requires no additional steps, requiring only a change in the mask pattern of the common electrode layer, and achieves even greater improvements in the first signal line AD.

[0330] As shown in Figures 33 and 34, in the cross-line area, the line width of the first connection part LJ1 can be 1μm-1.5μm larger than the line width of the cross-line part LK1, so that the orthographic projection of the first connection part LJ1 on the substrate can cover the orthographic projection of the overlapping area JY on the substrate.

[0331] FIG35 is a cross-sectional view taken along line II′ in FIG33 .

[0332] In FIG35 , the number 10 is the substrate, the number 14 is the gate metal layer, the number 13 is the gate insulating layer, the number 17 is the first passivation layer, the number 110 is the metal auxiliary layer, and the number 111 is the common electrode layer.

[0333] In at least one embodiment of the present disclosure, the first signal line further includes a first transition portion and a second transition portion; the second transition portion is overlapped with the crossover portion;

[0334] The first transfer portion is electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

[0335] The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

[0336] In a specific implementation, the first signal line may further include a first transfer portion and a second transfer portion, the first transfer portion may be located in the pixel electrode layer, the second transfer portion may be located in the common electrode layer, and the second transfer portion may be directly overlapped with the jumper portion; the first transfer portion may be electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion may be electrically connected to the second transfer portion through a fourteenth via hole, so that the signal connection line portion is electrically connected to the jumper portion.

[0337] Figure 37 is a planar layout diagram of the gate metal layer in Figure 36, Figure 38 is a planar layout diagram of the source and drain metal layer in Figure 36, Figure 39 is a planar layout diagram of the common electrode layer in Figure 36, Figure 40 is a planar layout diagram of the metal auxiliary layer in Figure 36, and Figure 41 is a planar layout diagram of the pixel electrode layer in Figure 36.

[0338] As shown in FIG36 to FIG41 , the first first signal line includes a cross-line portion LK1, a first signal connecting line portion LX1, a first transition portion ZJ1 and a second transition portion ZJ2; the second first signal line includes a second signal connecting line portion LX2;

[0339] LX1 is located in the gate metal layer, ZJ1 is located in the pixel electrode layer, ZJ2 is located in the common electrode layer, and LK1 is located in the metal auxiliary layer;

[0340] The second adapter ZJ2 is directly connected to the cross-line portion LK1;

[0341] The first transfer portion ZJ1 is electrically connected to the first signal connection line portion LX1 through the thirteenth via hole H13, and the first transfer portion ZJ1 is electrically connected to the second transfer portion ZJ2 through the fourteenth via hole H14;

[0342] The orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of the first signal connection line portion LX1 on the substrate, and the orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of ZJ2 on the substrate;

[0343] The second first signal line may include a second signal connection line portion LX2;

[0344] LX2 may be located at the gate metal layer.

[0345] As shown in FIG36 to FIG41 , the first first signal line may further include a third transition portion ZJ3 and a connecting line L1;

[0346] The third connecting portion ZJ3 is located in the pixel electrode layer, and the connecting line L1 is located in the source-drain metal layer;

[0347] The third transition portion ZJ3 is electrically connected to the cross-line portion LK1 through the eleventh via hole H11 , and the third transition portion ZJ3 is electrically connected to the connection line L1 through the twelfth via hole H12 .

[0348] As shown in FIG36 to FIG41 , ZJ3 may be located in the pixel electrode layer, and L1 may be located in the source / drain metal layer.

[0349] FIG42 is a JJ′ cross-sectional view in FIG36 .

[0350] In at least one embodiment of the present disclosure, the cross-line portion includes a first cross-line portion and a second cross-line portion;

[0351] The orthographic projection of the first cross-line portion on the substrate covers the orthographic projection of the second cross-line portion on the substrate;

[0352] The first jumper portion is directly overlapped with the second jumper portion.

[0353] Optionally, the first cross-line portion is located in the fifth conductive layer, and the second cross-line portion is located in the sixth conductive layer.

[0354] In a specific implementation, the cross-line portion may include a first cross-line portion located at the common electrode layer and a second cross-line portion located at the metal auxiliary layer, and the first cross-line portion may be directly overlapped with the second cross-line portion.

[0355] Figure 44 is a planar layout diagram of the gate metal layer in Figure 43, Figure 45 is a planar layout diagram of the source and drain metal layer in Figure 43, Figure 46 is a planar layout diagram of the common electrode layer in Figure 43, Figure 47 is a planar layout diagram of the metal auxiliary layer in Figure 43, and Figure 48 is a planar layout diagram of the pixel electrode layer in Figure 43.

[0356] As shown in FIG43 to FIG48 , the first first signal line may include a first signal connection line portion LX1 and a cross-line portion;

[0357] The second first signal line may include a second signal connection line portion LX2;

[0358] The first cross-line portion includes a first cross-line portion LKB1 and a second cross-line portion LKB2;

[0359] LKB1 may be located in the common electrode layer, and LKB2 may be located in the metal auxiliary layer;

[0360] The orthographic projection of LKB1 on the substrate covers the orthographic projection of the second cross-line portion LKB2 on the substrate, so as to ensure that the orthographic projection of LKB1 on the substrate covers the overlapping area of ​​LKB2 and LX2.

[0361] In at least one embodiment shown in FIG. 43 to FIG. 48 , in the line-crossing region, the line width of LKB1 may be 1 μm-1.5 μm greater than the line width of LKB2 .

[0362] In at least one embodiment of the present disclosure, the first signal line further includes a first transition portion and a second transition portion; the second transition portion is electrically connected to the first cross-line portion;

[0363] The first transfer portion is electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

[0364] The first transfer portion and the signal connection line portion are located in different conductive layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

[0365] As shown in FIG43 to FIG48 , the first first signal line may further include a first transition portion ZJ1 and a second transition portion ZJ2 , ZJ1 may be located at the pixel electrode layer, and ZJ2 may be located at the common electrode layer;

[0366] The second connecting portion ZJ2 can be electrically connected to the first cross-line portion LKB1;

[0367] The first transfer portion ZJ1 is electrically connected to the first signal connection line portion LX1 through the thirteenth via hole H13, and the first transfer portion ZJ1 is electrically connected to the second transfer portion ZJ2 through the fourteenth via hole H14;

[0368] The orthographic projection of ZJ1 on the base partially overlaps with the orthographic projection of LX1 on the base, and the orthographic projection of ZJ1 on the base partially overlaps with the orthographic projection of ZJ2 on the base.

[0369] In at least one embodiment of the present disclosure, the first signal line further includes a third transition portion, a fourth transition portion, and a connecting line;

[0370] The fourth transition portion is electrically connected to the first cross-line portion; the fourth transition portion and the first cross-line portion are located in the same conductive layer;

[0371] The third adapter portion is electrically connected to the fourth adapter portion through the fifteenth via hole, and the third adapter portion is electrically connected to the connecting line through the sixteenth via hole;

[0372] The third transition portion and the fourth transition portion are located in different conductive layers, and the third transition portion and the connecting line are located in different conductive layers.

[0373] Optionally, the third transition portion is located in the fourth conductive layer, the fourth transition portion is located in the fifth conductive layer; and the connecting line is located in the third conductive layer.

[0374] As shown in FIG43 to FIG48 , the first first signal line may further include a third transition portion ZJ3, a fourth transition portion ZJ4 and a connecting line L1;

[0375] ZJ3 may be located at the pixel electrode layer, and ZJ4 may be located at the common electrode layer;

[0376] ZJ4 can be electrically connected to LKB1;

[0377] ZJ3 is electrically connected to the fourth adapter ZJ4 through the fifteenth via hole H15, and ZJ3 is electrically connected to the connection line L1 through the sixteenth via hole H16;

[0378] L1 may be located at a source / drain metal layer.

[0379] ZJ3, ZJ4, H15 and H16 may be disposed between the first signal line wiring region and the GOA TFT (the GOA TFT may be a TFT in a GOA circuit) distribution region.

[0380] When manufacturing the first signal line shown in FIG33 , the specific process is as follows:

[0381] 1. Forming a gate metal layer to obtain the pattern shown in FIG49;

[0382] 2. Forming a gate insulating layer, forming a semiconductor layer, etching, and forming a source / drain metal layer, and etching to obtain the pattern shown in FIG50;

[0383] 3. Forming the first passivation layer, coating, exposing and developing the organic layer, forming and etching the common electrode layer to obtain the pattern shown in FIG51;

[0384] 4. Forming and etching the metal auxiliary layer to obtain the pattern shown in FIG52;

[0385] 5. Form the second passivation layer and etch the area indicated by the dotted line in FIG. 53 to leave overlapping areas on the metal auxiliary layer, the gate metal layer, and the source / drain metal layer;

[0386] 6. The pixel electrode layer is formed and etched to obtain the pattern shown in FIG54.

[0387] When manufacturing the first signal line shown in FIG43 , the specific process is as follows:

[0388] 1. The gate metal layer is formed and etched to obtain the pattern shown in FIG55 ;

[0389] 2. Forming a gate insulating layer, forming a semiconductor layer, etching, and forming a source / drain metal layer, etching to obtain the pattern shown in FIG56;

[0390] 3. Forming the first passivation layer, coating the organic layer, exposing and developing it, and forming and etching the common electrode layer to obtain the pattern shown in FIG57 ;

[0391] 4. Forming and etching the metal auxiliary layer to obtain the pattern shown in FIG58;

[0392] 5. Form a second passivation layer and etch the area indicated by the dotted line in FIG. 59 to leave overlapping areas on the common electrode layer, the gate metal layer, and the source / drain metal layer;

[0393] 6. The pixel electrode layer is formed and etched to obtain the pattern shown in FIG60.

[0394] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0395] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display panel includes a display area and a peripheral area surrounding the display area. In the peripheral area, a plurality of first signal lines are disposed on a substrate; the first signal lines include signal connection line portions; The plurality of first signal lines are divided into first sub-signal lines including crossover portions and second sub-signal lines not including crossover portions; A positive projection of the crossover portion on the substrate overlaps at least partially with positive projections of at least some of the plurality of second sub-signal lines on the substrate; At least two insulating layers are provided between the crossover portion and signal connection line portions included in at least some of the plurality of second sub-signal lines; and / or, the signal connection line portions include a plurality of signal connection line parts extending in a first direction, and a width of the signal connection line parts in a second direction is less than a width threshold; The signal connection line portions extend in the first direction, and the second direction intersects with the first direction.

2. The display panel according to claim 1, wherein, The width threshold is greater than or equal to 5 μm and less than or equal to 8 μm.

3. The display panel according to claim 1, wherein, The display panel includes a first conductive layer, a second conductive layer, and a third conductive layer arranged in sequence away from the substrate; at least one insulating layer is provided between adjacent conductive layers; The crossover portion is located in the third conductive layer, and the signal connection line portions are located in the first conductive layer.

4. The display panel according to claim 3, wherein, The first conductive layer includes a light-shielding pattern provided in the display area, the second conductive layer includes gate lines provided in the display area, and the third conductive layer includes data lines provided in the display area.

5. The display panel according to claim 3, wherein, The first signal lines further include signal main line portions; The signal main line portions include a first main line part, a second main line part, and a third main line part; the first main line part, the second main line part, and the third main line part are located in different conductive layers; The third main line part is electrically connected to the second main line part through a first via; Positive projections of the first main line part on the substrate, positive projections of the second main line part on the substrate, and positive projections of the third main line part on the substrate at least partially overlap.

6. The display panel according to claim 5, wherein, The first signal lines further include signal guiding line portions; The signal guiding line portions are provided between the signal main line portions and the signal connection line portions; The signal guiding line portions include a first guiding line part and a second guiding line part located in different conductive layers; The first guiding line part is electrically connected to the second guiding line part through a second via; Positive projections of the first guiding line part on the substrate and positive projections of the second guiding line part on the substrate at least partially overlap.

7. The display panel according to claim 6, wherein, The signal connection line portions, the first main line part, and the first guiding line part are electrically connected, and the third main line part and the second guiding line part are electrically connected.

8. The display panel according to claim 3, in, The first signal line also includes a signal main line portion; The signal main body line portion includes a first main body line portion and a second main body line portion located in different conductive layers; The first main body line portion is electrically connected to the second main body line portion through a third via; An orthographic projection of the first body line portion on the substrate and an orthographic projection of the second body line portion on the substrate at least partially overlap.

9. The display panel according to claim 8, in, The signal connection line portion is electrically connected to the first main body line portion.

10. The display panel according to claim 5 or 8, in, The orthographic projection of the line-jumping portion on the substrate partially overlaps with the orthographic projection of the signal connection line portion of the first signal line to which the line-jumping portion belongs on the substrate; The cross-line portion is electrically connected to a signal connection line portion included in a first signal line to which the cross-line portion belongs through a fourth via hole.

11. The display panel according to claim 3, in, The display panel further comprises a fourth conductive layer disposed on a side of the third conductive layer away from the substrate; The first signal line also includes a signal main line portion; The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers; The orthographic projection of the third main body line portion on the substrate at least partially overlaps with the orthographic projection of the first main body line portion on the substrate, and the orthographic projection of the third main body line portion on the substrate at least partially overlaps with the orthographic projection of the second main body line portion on the substrate; The third body line portion is electrically connected to the second body line portion through a fifth via hole, and the third body line portion is electrically connected to the first body line portion through a sixth via hole.

12. The display panel according to claim 11, in, The fourth conductive layer includes a pixel electrode disposed in the display area.

13. The display panel according to claim 11, in, The first signal line further includes a first transfer portion; the orthographic projection of the first transfer portion on the substrate at least partially overlaps with the orthographic projection of the signal connection line portion included in the first signal line to which the cross-line portion belongs on the substrate; The orthographic projection of the first transition portion on the substrate at least partially overlaps with the orthographic projection of the cross-line portion on the substrate; The first adapter portion is electrically connected to the signal connection line portion through a seventh via hole, and the first adapter portion is electrically connected to the cross-line portion through an eighth via hole; The first transfer portion and the signal connection line are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

14. The display panel according to claim 1, in, The display panel comprises a second conductive layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer and a fourth conductive layer arranged in sequence away from the substrate; the fifth conductive layer overlaps the sixth conductive layer; at least one insulating layer is provided between the second conductive layer and the third conductive layer, at least one insulating layer is provided between the third conductive layer and the fifth conductive layer, and at least one insulating layer is provided between the sixth conductive layer and the fourth conductive layer; At least a portion of the cross-line portion is located in the sixth conductive layer, and the signal connection line portion is located in the second conductive layer.

15. The display panel according to claim 14, in, The second conductive layer includes gate lines disposed in the display area, the third conductive layer includes data lines disposed in the display area, the fifth conductive layer includes common electrodes disposed in the display area, and the sixth conductive layer includes auxiliary metal patterns disposed in the display area.

16. The display panel according to claim 14, in, The first signal line further includes a first transfer portion; The first adapter portion is electrically connected to the signal connection line portion through a ninth via hole, and the first adapter portion is electrically connected to the cross-line portion through a tenth via hole; The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

17. The display panel according to claim 14, in, The first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is overlapped with the crossover portion; The first transfer portion is electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole; The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

18. The display panel according to any one of claims 14 to 17, in, The first signal line also includes a third adapter and a connecting line; The third adapter portion is electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion is electrically connected to the connection line through a twelfth via hole; The third transfer portion and the cross-line portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

19. The display panel according to any one of claims 14 to 17, in, The first signal line further includes a first connecting portion located in the fifth conductive layer; the first connecting portion is overlapped with the crossover portion; The orthographic projection of the first connecting portion on the substrate covers the orthographic projection of the cross-line area on the substrate; The cross-line region is an overlapping region between the cross-line portion and a signal connection line portion included in at least some of the second sub-signal lines in the plurality of second sub-signal lines.

20. The display panel according to claim 14, in, The crossover portion includes a first crossover portion and a second crossover portion; The orthographic projection of the first cross-line portion on the substrate covers the orthographic projection of the second cross-line portion on the substrate; The first jumper portion is directly overlapped with the second jumper portion.

21. The display panel according to claim 20, in, The first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is electrically connected to the first cross-line portion; The first transfer portion is electrically connected to the clock signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole; The first transfer portion and the signal connection line portion are located in different conductive layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

22. The display panel according to claim 20, in, The first signal line also includes a third adapter, a fourth adapter and a connecting line; The fourth transfer portion is electrically connected to the first cross-line portion; the fourth transfer portion and the first cross-line portion are located in the same conductive layer; The third adapter is electrically connected to the fourth adapter through a fifteenth via hole, and the third adapter is electrically connected to the connection line through a sixteenth via hole; The third transfer portion and the fourth transfer portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

23. A display device comprising the display panel according to any one of claims 1 to 22.

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