Drive backplane, light-emitting substrate, and display device

Abstract

A drive backplane (10) comprises a circuit board (50), a first bonding electrode (30), and an adhesive layer (60). The circuit board (50) comprises a substrate (51), a plurality of conductive layers (52), and a plurality of insulating layers (53). The plurality of conductive layers (52) include a first conductive layer (520), and the first conductive layer (520) is the conductive layer (52) farthest from the substrate (51) among the plurality of conductive layers (52). The plurality of insulating layers (53) include at least one first insulating layer (530), and the first insulating layer (530) is the insulating layer (53) located on the side of the first conductive layer (520) away from the substrate (51) among the plurality of insulating layers (53). The first conductive layer (520) comprises a plurality of conductive portions (526), the at least one first insulating layer (530) is provided with a plurality of via holes (501), at least part of each conductive portion (526) is exposed by one via hole (501), and a pad is the part of the conductive portion (526) exposed by the via hole (501). The first bonding electrode (30) is arranged on the side of the pad away from the substrate (51). The surface of the first bonding electrode (30) away from the substrate (51) is located on the side of the at least one first insulating layer (530) away from the substrate (51). The adhesive layer (60) is arranged on the side of the first insulating layer (530) away from the substrate (51). The adhesive layer (60) covers at least part of the side wall of the first bonding electrode (30) and exposes the surface of the first bonding electrode (30) away from the substrate (51).

Description

Driving backplane, light-emitting substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a light-emitting substrate, and a display device. Background Art

[0002] With the development of light-emitting diode (LED) technology, display devices using submillimeter (Micro) or even micron-scale light-emitting diodes (LEDs) have gained widespread application. This not only allows displays using Micro or Mini LEDs to achieve the same contrast as organic light-emitting diode (OLED) displays, but also allows them to retain the technical advantages of LCDs, such as low cost, high brightness, and high reliability. This improves the display quality and provides users with a better visual experience.

[0003] Summary of the Invention

[0004] In one aspect, a drive backplane is provided. The drive backplane includes a circuit board, a first bonding electrode, and an adhesive layer. The circuit board includes a substrate, and multiple conductive layers and multiple insulating layers disposed on one side of the substrate. The multiple conductive layers include a first conductive layer, which is the conductive layer farthest from the substrate. The multiple insulating layers include at least one first insulating layer, which is located on the side of the multiple insulating layers away from the substrate.

[0005] The first conductive layer includes a plurality of conductive portions, the at least one first insulating layer is provided with a plurality of vias penetrating the at least one first insulating layer, at least a portion of each conductive portion is exposed by one of the vias, and the conductive portion includes a pad, which is the portion of the conductive portion exposed by the via. The first bonding electrode is disposed on a side of the pad away from the substrate. The first bonding electrode is located away from the surface of the substrate and on a side of the at least one first insulating layer away from the substrate. The adhesive layer is disposed on a side of the at least one first insulating layer away from the substrate. Furthermore, the adhesive layer covers at least a portion of the sidewall of the first bonding electrode and exposes the surface of the first bonding electrode away from the substrate.

[0006] In some embodiments, the first bonding electrode includes a plurality of first-type sub-electrodes arranged in a stacked manner, with at least one first-type sub-electrode located on a side of the at least one first insulating layer away from the substrate. Among the first-type sub-electrodes located on a side of the at least one first insulating layer away from the substrate, the first-type sub-electrode closest to the substrate is a first target sub-electrode, and the first-type sub-electrode adjacent to the first target sub-electrode and located on the side of the first target sub-electrode closer to the substrate is a second target sub-electrode. The boundary between the bonding surface of the adhesive layer and the first bonding electrode away from the substrate is a first boundary, and the first boundary is located on the side of the interface between the first target sub-electrode and the second target sub-electrode away from the substrate.

[0007] In some embodiments, the first bonding electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode stacked in sequence, the first sub-electrode is electrically contacted with the pad, and the second sub-electrode and the third sub-electrode are both located on the side of the at least one first insulating layer away from the substrate.

[0008] In some embodiments, the first boundary is located between two surfaces of the second sub-electrode close to and far from the substrate, or between two surfaces of the third sub-electrode close to and far from the substrate.

[0009] In some embodiments, the ratio of the minimum distance between the first boundary and a target interface to the thickness of the first type of sub-electrode on a side of the target interface away from the substrate is greater than or equal to 1 / 4. The target interface is an interface among the plurality of first type sub-electrodes that is located on a side of the first boundary close to the substrate and adjacent to the first boundary.

[0010] In some embodiments, the first bonding electrode is away from the surface of the substrate and is located on a side of the adhesive layer away from the substrate.

[0011] In some embodiments, the thickness of the adhesive layer is 0.05 μm to 4 μm.

[0012] In some embodiments, the material of the adhesive layer includes an inorganic insulating material.

[0013] In some embodiments, along a direction perpendicular to the substrate and away from the substrate, the multilayer conductive layer sequentially includes a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a source-drain conductive layer, and an electrode layer. The multilayer insulating layer sequentially includes a first gate insulating layer, a second gate insulating layer, an interlayer insulating layer, a first planarizing layer, a first passivation layer, and a second planarizing layer.

[0014] Among them, the first gate insulation layer is arranged between the first semiconductor layer and the first gate conductive layer, the second gate insulation layer is arranged between the first gate conductive layer and the second gate conductive layer, the interlayer insulation layer is arranged between the second gate conductive layer and the source-drain conductive layer, the first flattening layer is arranged between the source-drain conductive layer and the electrode layer, and the first passivation layer and the second flattening layer are arranged on the side of the electrode layer away from the substrate.

[0015] In another aspect, a light-emitting substrate is provided. The light-emitting substrate comprises a driving backplane according to any one of the above embodiments, a light-emitting device, and a second bonding electrode. The light-emitting device is connected to the first bonding electrode of the driving backplane via the second bonding electrode.

[0016] In some embodiments, the light-emitting device includes a surface electrode, a first light-emitting stacking layer, and a first connecting electrode. The surface electrode is electrically connected to the driving backplane. The first light-emitting stacking layer is arranged on a side of the surface electrode close to the driving backplane and is connected to the surface electrode. The first connecting electrode is arranged on a side of the first light-emitting stacking layer away from the surface electrode and is connected to the first light-emitting stacking layer. The second bonding electrode is arranged on a surface of the first connecting electrode away from the first light-emitting stacking layer. Or,

[0017] The light-emitting device includes a second light-emitting stacked layer, a second connecting electrode, and a third connecting electrode. The second connecting electrode and the third connecting electrode are disposed on the same side of the second light-emitting stacked layer and are respectively connected to the second light-emitting stacked layer. The second bonding electrode is disposed on a surface of the second connecting electrode and the third connecting electrode that is away from the second light-emitting stacked layer.

[0018] In some embodiments, the light-emitting substrate further includes a filling layer, which is disposed on a side of the adhesive layer of the driving backplane away from the substrate and at least covers side walls of the first bonding electrode and the second bonding electrode.

[0019] In another aspect, a display device is provided. The display device includes a light-emitting substrate and a housing. The light-emitting substrate is the light-emitting substrate described in any of the above embodiments. The light-emitting substrate is disposed in the housing.

[0020] In some embodiments, the etching sequence of the multiple etchings includes at least one of sequentially etching from one side to the other side of the conductive layer, alternately etching from the middle to both sides of the conductive layer, and alternately etching from both sides to the middle of the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0022] FIG1 is a structural diagram of a display device according to some embodiments;

[0023] FIG2 is a structural diagram of another display device according to some embodiments;

[0024] FIG3 is a cross-sectional view of the display device shown in FIG1 along section line AA′;

[0025] FIG4 is a cross-sectional view of another display device shown in FIG1 along section line AA′;

[0026] FIG5 is a top view of a light emitting substrate according to some embodiments;

[0027] FIG6 is a cross-sectional view of the display device shown in FIG5 along section line DD′;

[0028] FIG7 is a cross-sectional view of another display device shown in FIG5 along section line DD′;

[0029] FIG8 is a structural diagram of a flip-chip light-emitting device according to some embodiments;

[0030] FIG9 is a structural diagram of a driving backplane according to some embodiments;

[0031] FIG10 is a structural diagram of another driving backplane according to some embodiments;

[0032] FIG11 is a process diagram of a method for preparing a light-emitting substrate according to some embodiments;

[0033] 12 to 15 are flow charts of methods for preparing a light-emitting substrate according to some embodiments. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0037] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0038] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0039] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0040] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0041] As used herein, "parallel," "perpendicular," and "equal" include the stated conditions and conditions that are similar to the stated conditions, within an acceptable range of deviations as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "equal" includes both absolute equality and approximate equality, where the acceptable range of deviations for approximate equality may include, for example, a difference between two conditions that is less than or equal to 5% of either condition.

[0042] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0043] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0044] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays an image, whether in motion (eg, video) or stationary (eg, still image), and whether textual or graphic.

[0045] For example, referring to Figures 1 and 2, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0046] For example, as shown in FIG1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in FIG1 . For another example, referring to FIG2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in FIG2 .

[0047] It should be noted that, depending on different application scenarios, the shape of the display surface of the display device 1000 is not unique. The shape of the display surface of the display device 1000 can be any one of circular, elliptical or polygonal, which is not specifically limited in the embodiments of the present disclosure.

[0048] In some embodiments, referring to FIG. 3 and FIG. 4 , a display device 1000 includes a light emitting substrate 100 , a driving circuit board 200 , a housing 300 , and a cover plate 400 .

[0049] The cover plate 400 is disposed on the light-emitting side of the light-emitting substrate 100. The driving circuit board 200 is disposed on the non-light-emitting side of the light-emitting substrate 100 and is connected to the light-emitting substrate 100 to provide a light-emitting signal to the light-emitting substrate 100.

[0050] It should be noted that the light-emitting substrate 100 has a relative light-emitting side and a non-light-emitting side. The light-emitting side refers to the side of the light-emitting substrate 100 that can emit light (the upper side of the light-emitting substrate 100 in Figures 3 and 4), and the non-light-emitting side refers to the other side opposite to the light-emitting side (the lower side of the light-emitting substrate 100 in Figures 3 and 4).

[0051] In addition, the shell 300 can be a box-shaped structure with an opening, the light-emitting substrate 100 and the driving circuit board 200 can be arranged in the shell 300, and the cover plate 400 is arranged on the light-emitting side of the light-emitting substrate 100 and is located at the opening of the shell 300.

[0052] It should be understood that the display device 1000 may be a liquid crystal display (LCD) or a mini / micro light emitting display (MLED), which is not specifically limited in the embodiments of the present disclosure.

[0053] In some embodiments, as shown in FIG3 , the display device 1000 may be a liquid crystal display device. In this case, the light-emitting substrate 100 may serve as a backlight source in the liquid crystal display device, providing backlight for the display panel 500. The display panel 500 may adjust the intensity (grayscale) of light passing through the display panel 500 to display an image.

[0054] 3 , the display device 1000 further includes a display panel 500 and a plurality of optical films 600 . The display panel 500 is disposed on the light emitting side of the light emitting substrate 100 , and the plurality of optical films 600 are disposed between the display panel 500 and the light emitting substrate 100 .

[0055] The light-emitting substrate 100 can directly emit white light, which is then homogenized by the multiple optical films 600 and then emitted toward the display panel 500. Alternatively, the light-emitting substrate 100 can also emit light of other colors (e.g., blue light), which is then color-converted and homogenized by the multiple optical films 600 and then emitted toward the display panel 500.

[0056] In other embodiments, referring to FIG4 , the display device 1000 may be a micro-luminescent display device. In this case, the luminescent substrate 100 may serve as the display panel of the micro-luminescent display device, directly displaying the image. The luminescent substrate 100 may emit light of multiple colors to achieve full-color display.

[0057] The following uses the display device 1000 as a micro-luminescent display device as an example to exemplify some embodiments of the present disclosure, but the implementation of the present disclosure is not limited thereto, and any other display device can also be considered as long as the same technical concept is applied.

[0058] In some embodiments, referring to FIG5 , a light-emitting substrate 100 includes a light-emitting region A and a peripheral region B disposed on at least one side of the light-emitting region A. FIG5 illustrates an example in which the peripheral region B surrounds the light-emitting region A. The light-emitting region A can be configured to house the light-emitting device 20, and the peripheral region B includes a binding portion C, which can be configured to connect to the driver circuit board 200.

[0059] Exemplarily, as shown in FIG5 , the light-emitting substrate 100 includes a driving backplane 10 and a light-emitting device 20 . The light-emitting device 20 is disposed on the driving backplane 10 and is located in the light-emitting area A.

[0060] The light-emitting device 20 may include, for example, a Micro LED and / or a Mini LED. For example, the size (e.g., length) of a Micro LED is less than 50 μm, such as 10 μm to 50 μm. For another example, the size (e.g., length) of a Mini LED is 50 μm to 150 μm, such as 80 μm to 120 μm.

[0061] The light emitting device 20 is connected to the driving backplane 10 to receive a first voltage signal and a second voltage signal. It should be noted that the first voltage signal and the second voltage signal are different, so as to provide a power supply voltage to the light emitting device 20.

[0062] For example, referring to FIG6 , the light emitting device 20 is a vertical structure light emitting device 20 , and includes a planar electrode 21 , a first light emitting stacked layer 22 , and a first connecting electrode 23 .

[0063] As shown in Figures 5 and 6, the planar electrode 21 can cover the light-emitting area A and extend to the peripheral area B. In the peripheral area B, the planar electrode 21 can be electrically connected to the driver backplane 10 via a connecting trace to receive the first voltage signal. This arrangement allows all light-emitting devices 20 to be connected to the planar electrode 21, which is easily connected to the driver backplane 10, resulting in a simple process and low cost.

[0064] It should be noted that the surface electrode 21 is the light-emitting side of the light-emitting device 20, and the transmittance of the surface electrode 21 is greater than or equal to 99%. Exemplarily, the material of the surface electrode 21 includes a transparent metal material, for example, the material of the surface electrode 21 includes indium tin oxide and / or indium zinc oxide.

[0065] As shown in FIG6 , the first light-emitting stacked layer 22 is disposed on a side of the planar electrode 21 close to the driving backplane 10 and is connected to the planar electrode 21. The first light-emitting stacked layer 22 includes a quantum well layer 222, and a first semiconductor doping layer 221 and a second semiconductor doping layer 223 disposed on opposite sides of the quantum well layer 222.

[0066] It should be noted that one of the first semiconductor doping layer 221 and the second semiconductor doping layer 223 is an N-type doped semiconductor layer, and the other is a P-type doped semiconductor layer. For example, the material of the first semiconductor doping layer 221 is an N-type doped semiconductor layer, and the material of the second semiconductor doping layer 223 is P-type doped gallium nitride. The material of the quantum well layer 222 includes gallium nitride and / or indium gallium nitride.

[0067] As shown in FIG. 5 and FIG. 6 , the first connection electrode 23 is disposed on a side of the first light-emitting stacked layer 22 away from the planar electrode 21 and is connected to the first light-emitting stacked layer 22 .

[0068] In the light-emitting area A, the first connection electrode 23 is bonded to the driver backplane 10 to receive a second voltage signal. For example, the light-emitting substrate 100 further includes a first bonding electrode 30 and a second bonding electrode 40. The driver backplane 10 is provided with the first bonding electrode 30, and the second bonding electrode 40 is disposed on a surface of the first connection electrode 23 that is away from the first light-emitting stacked layer 22. Furthermore, the light-emitting device 20 is connected to the first bonding electrode 30 of the driver backplane 10 via the second bonding electrode 40.

[0069] It should be noted that the material of the first connection electrode 23 includes a metal material. Exemplarily, the material of the first connection electrode 23 includes at least one of nickel, gold, copper, and silver. The material of the first bonding electrode 30 and the second bonding electrode 40 includes a metal material. Exemplarily, the material of the first bonding electrode 30 and the second bonding electrode 40 includes at least one of gold, copper, silver, tin, titanium, and molybdenum.

[0070] On this basis, as shown in FIG6 , the vertical light emitting device 20 may further include a passivation layer 24 . The passivation layer 24 at least covers the sidewalls of the first light emitting stacked layer 22 to provide insulation protection.

[0071] It should be noted that the material of the passivation layer 24 includes an inorganic insulating material. Exemplarily, the material of the passivation layer 24 includes at least one of silicon oxide, silicon nitride, and aluminum oxide.

[0072] 7 and 8 , the light emitting device 20 is a flip-chip light emitting device 20 , and includes a second connecting electrode 25 , a second light emitting stacked layer 26 , and a third connecting electrode 27 .

[0073] As shown in FIG5 , FIG7 and FIG8 , the second connection electrode 25 and the third connection electrode 27 are disposed on the same side of the second light-emitting stacked layer 26 and are respectively connected to the second light-emitting stacked layer 26 .

[0074] In the light-emitting area A, the second connection electrode 25 and the third connection electrode 27 can be bonded to the driver backplane 10, respectively, to receive the first voltage signal and the second voltage signal. For example, the light-emitting substrate 100 further includes a first bonding electrode 30 and a second bonding electrode 40. The driver backplane 10 is provided with the first bonding electrode 30, and the second connection electrode 25 and the third connection electrode 27 are both provided with the second bonding electrode 40 on the surface away from the second light-emitting stack layer 26. Furthermore, the light-emitting device 20 is connected to the first bonding electrode 30 of the driver backplane 10 via the second bonding electrode 40.

[0075] It should be noted that the flip-chip light-emitting device 20 further includes a substrate 201, the material of which may include, for example, glass and / or sapphire. The materials of the second connecting electrode 25 and the third connecting electrode 27 may be similar to those of the first connecting electrode 23. The structure of the second light-emitting stacked layer 26 is the same as that of the first light-emitting stacked layer 22, and is not further described in detail in the present embodiment.

[0076] Below, some embodiments of the present disclosure are exemplarily described by taking the light emitting device 20 as a vertical structure light emitting device 20 as an example, but the implementation of the present disclosure is not limited to this, and any other structure of the light emitting device 20 can also be considered as long as the same technical concept is applied.

[0077] In related technologies, after the light-emitting device is bonded to the driver backplane, and during subsequent processes such as cleaning and photolithography, the first bonding electrode is prone to delamination or breakage, causing the light-emitting device to fail or even fall off, resulting in low product yield.

[0078] Based on this, referring to FIG. 9 and FIG. 10 , some embodiments of the present disclosure provide a driving backplane 10 including a circuit board 50 and an adhesive layer 60 .

[0079] As shown in Figures 9 and 10 , circuit board 50 may be an FR4 type printed circuit board (PCB) or a flexible PCB that is easily deformable. For example, the material used for circuit board 50 may include at least one of silicon nitride, aluminum nitride, and aluminum oxide, or may include a metal or metal compound, such as a metal core printed circuit board (Metal Core PCB) or a metal copper clad laminate (MCCL).

[0080] Exemplarily, as shown in FIG. 9 and FIG. 10 , the circuit board 50 includes a substrate 51 , and a multi-layer conductive layer 52 and a multi-layer insulating layer 53 disposed on one side of the substrate 51 .

[0081] It should be noted that the material of the substrate 51 includes at least one of epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate two formal acid glycol ester (PEN), polyimide (PI), glass, sapphire and polymethyl methacrylate (PMMA).

[0082] The multilayer conductive layer 52 includes a first conductive layer 520, which is the conductive layer 52 farthest from the substrate 51 in the multilayer conductive layer 52. The multilayer insulating layer 53 includes at least one first insulating layer 530, which is the insulating layer 53 located on the side of the first conductive layer 520 farthest from the substrate 51 in the multilayer insulating layer 53.

[0083] 9 and 10 , along a direction perpendicular to the substrate 51 and away from the substrate 51, the multilayer conductive layer 52 sequentially includes a first semiconductor layer 521, a first gate conductive layer 522, a second gate conductive layer 523, a source / drain conductive layer 524, and an electrode layer 525. The multilayer insulating layer 53 sequentially includes a first gate insulating layer 531, a second gate insulating layer 532, an interlayer insulating layer 533, a first planarizing layer 534, a first passivation layer 535, and a second planarizing layer 536.

[0084] Moreover, the first gate insulating layer 531 is arranged between the first semiconductor layer 521 and the first gate conductive layer 522, the second gate insulating layer 532 is arranged between the first gate conductive layer 522 and the second gate conductive layer 523, the interlayer insulating layer 533 is arranged between the second gate conductive layer 523 and the source-drain conductive layer 524, the first planarizing layer 534 is arranged between the source-drain conductive layer 524 and the electrode layer 525, and the first passivation layer 535 and the second planarizing layer 536 are arranged on the side of the electrode layer 525 away from the substrate 51.

[0085] At this time, the first conductive layer 520 is an electrode layer 525 , and the first insulating layer 530 includes a first passivation layer 535 and a second planarization layer 536 .

[0086] On this basis, the first conductive layer 520 includes a plurality of conductive portions 526, the first insulating layer 530 is provided with a plurality of vias 501 penetrating the first insulating layer 530, at least a portion of each conductive portion 526 is exposed by a via 501, and the conductive portion 526 includes a pad P, which is the portion of the conductive portion 526 exposed by the via 501. That is, the first passivation layer 535 and the second planarizing layer 536 are provided with vias 501 penetrating the first passivation layer 535 and the second planarizing layer 536, and the portion of the conductive portion 526 not covered by the first passivation layer 535 and the second planarizing layer 536 forms the pad P.

[0087] As shown in Figures 9 and 10 , the first bonding electrode 30 is disposed on a side of the pad P away from the substrate 51. Furthermore, the first bonding electrode 30 is away from the surface of the substrate 51 and is located on a side of the first insulating layer 530 away from the substrate 51. In other words, the first bonding electrode 30 extends beyond the surface of the circuit board 30.

[0088] As shown in Figures 9 and 10, the adhesive layer 60 is disposed on the side of the first insulating layer 530 away from the substrate 51. Specifically, the adhesive layer 60 is disposed on the side of the second planar layer 536 away from the substrate 51. The adhesive layer 60 covers at least a portion of the sidewalls of the first bonding electrode 30 to improve adhesion between the first bonding electrode 30 and the circuit board 50. Furthermore, the adhesive layer 60 exposes the surface of the first bonding electrode 30 away from the substrate 51, facilitating bonding of the light-emitting device 20 to the first bonding electrode 30 via the second bonding electrode 50.

[0089] The thickness of the adhesive layer 60 may be 0.05 μm to 4 μm. For example, the thickness of the adhesive layer 60 is any one of 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, and 4 μm.

[0090] It should be noted that the material of the bonding layer 60 may include an organic material or an inorganic insulating material. Exemplarily, the material of the bonding layer 60 includes an inorganic insulating material. For example, the material of the bonding layer 60 includes silicon nitride and / or silicon oxide. Silicon nitride and / or silicon oxide have good high temperature resistance, which can prevent the high temperature (e.g., 300°C) in the bonding process from adversely affecting the bonding layer 60.

[0091] Based on this, the adhesive layer 60 can cover the side wall of the first bonding electrode 30 that extends beyond the circuit board 50, thereby increasing the adhesion of the first bonding electrode 30 on the circuit board 50, reducing the risk of delamination or falling off between the first bonding electrode and the pad P of the circuit board 50, and the risk of fracture of the portion of the first bonding electrode 30 covered by the adhesive layer 60 is reduced, thereby improving the phenomenon of delamination or fracture of the portion bonded to the circuit board 50 of the light-emitting device 20, reducing the risk of failure or even falling off of the light-emitting device 20, and improving product yield.

[0092] It should be understood, referring to FIG. 9 and FIG. 10 , that the first bonding electrode 30 and the second bonding electrode 40 may be a single-layer structure or a multi-layer structure.

[0093] In some embodiments, as shown in FIG. 9 and FIG. 10 , the first bonding electrode 30 includes a plurality of first-type sub-electrodes 310 stacked together, and at least one first-type sub-electrode 310 is located on a side of the insulating layer 53 away from the substrate 51 .

[0094] Among them, among the first type of sub-electrodes 310 located on the side of the insulating layer 53 away from the substrate 51, the first type of sub-electrode 310 closest to the substrate 51 is the first target sub-electrode 311, and the first type of sub-electrode 310 adjacent to the first target sub-electrode 311 and located on the side of the first target sub-electrode 311 close to the substrate 51 is the second target sub-electrode 312.

[0095] On this basis, referring to Figures 9 and 10, the boundary of the bonding surface between the adhesive layer 60 and the first bonding electrode 30 away from the substrate 51 is the first boundary L1, and the first boundary L1 is located on the side of the interface between the first target sub-electrode 311 and the second target sub-electrode 312 away from the substrate 51.

[0096] Exemplarily, as shown in Figures 9 and 10, the first bonding electrode 30 includes a first sub-electrode 31, a second sub-electrode 32 and a third sub-electrode 33 stacked in sequence, the first sub-electrode 31 is electrically contacted with the pad P, and the second sub-electrode 32 and the third sub-electrode 33 are both located on the side of the insulating layer 53 away from the substrate 51.

[0097] The material of the above-mentioned first sub-electrode 31 can include any one of nickel, nickel-copper alloy, nickel-copper-aluminum alloy, molybdenum-titanium-nickel alloy, copper-magnesium-aluminum alloy and copper-titanium alloy to improve the adhesion of the second sub-electrode 32 and slow down the diffusion rate of the solder (such as the third sub-electrode 33) to avoid the diffusion of the solder to the pad P.

[0098] The thickness of the first sub-electrode 31 is 0.1 μm to 1 μm. For example, the thickness of the first sub-electrode 31 is any one of 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm and 1 μm.

[0099] The material of the second sub-electrode 32 may include metal. For example, the material of the second sub-electrode 32 includes copper or silver, which has good conductivity and low resistance.

[0100] The thickness of the second sub-electrode 32 is 1 μm to 4 μm. For example, the thickness of the second sub-electrode 32 is any one of 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm and 4 μm.

[0101] The third sub-electrode 33 is made of a metal and can form a first intermetallic compound with the second sub-electrode 32 and a second intermetallic compound with the first sub-electrode 31. The reaction rate between the third sub-electrode 33 and the second sub-electrode 32 is greater than the reaction rate between the third sub-electrode 33 and the first sub-electrode 31. The third sub-electrode 33 can be made of tin.

[0102] The thickness of the third sub-electrode 33 is 0.5 μm to 2 μm. For example, the thickness of the second sub-electrode 32 is any one of 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm and 2 μm.

[0103] Based on the above, the first target sub-electrode 311 is the second sub-electrode 32 , and the second target sub-electrode 312 is the first sub-electrode 31 . That is, the first boundary L is located on the side of the interface between the second sub-electrode 32 and the first sub-electrode 31 away from the substrate 51 .

[0104] For example, as shown in FIG9 , the first boundary L is located between the two surfaces of the second sub-electrode 32 close to and away from the substrate 51. In this case, the adhesive layer 60 can cover the interface between the second sub-electrode 32 and the first sub-electrode 31 in the first bonding electrode 30, thereby reducing the delamination or fracture between the second sub-electrode 32 and the first sub-electrode 31, thereby further reducing the risk of failure or even falling off of the light-emitting device 20 and improving product yield.

[0105] For another example, as shown in FIG10 , the first boundary L is located between the two surfaces of the third sub-electrode 33 close to and away from the substrate 51. In this case, the adhesive layer 60 can cover the interface between the second sub-electrode 32 and the first sub-electrode 31, as well as the interface between the second sub-electrode 32 and the third sub-electrode 33 in the first bonding electrode 30, thereby reducing the delamination or fracture between the first sub-electrode 31 and the second sub-electrode 32, and between the second sub-electrode 32 and the third sub-electrode 33, thereby further reducing the risk of failure or even detachment of the light-emitting device 20 and improving product yield.

[0106] In some embodiments, referring to FIG. 6 and FIG. 7 , the second bonding electrode 40 includes a plurality of second-type sub-electrodes 410 arranged in a stacked manner.

[0107] Exemplarily, as shown in FIG6 and FIG7 , the second bonding electrode 40 includes a fourth sub-electrode 41 and a fifth sub-electrode 42 stacked in sequence, and the fourth sub-electrode 41 is in electrical contact with the first connection electrode 23 of the light-emitting device 20 .

[0108] The material of the fourth sub-electrode 41 can include any one of nickel, nickel-copper alloy, nickel-copper-aluminum alloy, molybdenum-titanium-nickel alloy, copper-magnesium-aluminum alloy, and copper-titanium alloy, and the fourth sub-electrode 41 can form a third intermetallic compound with the third sub-electrode 33. The fourth sub-electrode 41 is used to improve the adhesion of the fifth sub-electrode 42 and slow down the diffusion rate of the solder (e.g., the third sub-electrode 33) to prevent the solder from diffusing to the first connection electrode 23.

[0109] The material of the fifth sub-electrode 42 can include metal. For example, the material of the fifth sub-electrode 42 includes copper or silver, which has good conductivity and low resistance. Furthermore, the fifth sub-electrode 42 can form a fourth intermetallic compound with the third sub-electrode 33. The reaction rate between the third sub-electrode 33 and the fifth sub-electrode 42 is greater than the reaction rate between the fourth sub-electrode 41 and the first sub-electrode 31.

[0110] In some embodiments, as shown in FIG9 and FIG10 , the ratio of the minimum distance between the first boundary L1 and the target interface to the thickness of the first type of sub-electrode 310 on the side of the target interface away from the substrate 51 is greater than or equal to 1 / 4.

[0111] For example, as shown in Figures 9 and 10 , the minimum distance between the first boundary L1 and the target interface is greater than or equal to 1 μm. For example, the minimum distance between the first boundary L1 and the target interface is any one of 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, and 4 μm. The target interface is an interface among the multiple interfaces of the first-type sub-electrodes 310 that is located on the side of the first boundary L1 close to the substrate 51 and is adjacent to the first boundary L1.

[0112] In this case, the adhesive layer 60 covers a larger area of ​​the first type sub-electrode 310 on the side of the target interface away from the substrate 51, which can effectively avoid stratification or fracture between the two first type sub-electrodes 310 on both sides of the target interface, thereby avoiding failure or even falling off of the light-emitting device 20 and improving product yield.

[0113] In any of the above embodiments, as shown in FIG9 and FIG10 , the first bonding electrode 30 is located away from the surface of the substrate 51, for example, on the side of the adhesive layer 60 away from the substrate 51. That is, the first bonding electrode 30 extends beyond the surface of the adhesive layer 60, thereby facilitating alignment and bonding of the second bonding electrode 40 to the first bonding electrode 30, thereby reducing process difficulty.

[0114] In some embodiments, referring to Figures 6 and 7 , the light-emitting substrate 100 further includes a filling layer 70. The filling layer 70 is disposed on the side of the adhesive layer 60 of the driving backplane 10 that is away from the substrate 51 and at least covers the sidewalls of the first bonding electrode 30 and the second bonding electrode 40. Exemplarily, as shown in Figure 6 , the surface of the filling layer 70 away from the substrate 51 is located between the surfaces of the light-emitting stacked layer 22 that are away from and closer to the driving backplane 10. Exemplarily, as shown in Figure 7 , the surface of the filling layer 70 away from the substrate 51 is located on the side of the light-emitting device 20 that is away from the substrate 51.

[0115] In this case, the filling layer 70 can also cover the side walls of the first bonding electrode 30 and the second bonding electrode 40, thereby further reducing the risk of delamination or breakage of the part where the light-emitting device 20 is bonded to the circuit board 50, thereby reducing the risk of failure or even falling off of the light-emitting device 20 and improving product yield.

[0116] Some embodiments of the present disclosure further provide a method for preparing a light-emitting substrate 100 , referring to FIG. 11 and FIG. 12 , which includes steps S100 to S400 .

[0117] S100 : preparing a first bonding electrode 30 and an adhesive layer 60 on a circuit board 50 .

[0118] In the above steps, the first bonding electrode 30 may include, for example, a first sub-electrode 31 , a second sub-electrode 32 and a third sub-electrode 33 stacked in sequence, and the first sub-electrode 31 is connected to the circuit board 50 .

[0119] On this basis, as shown in FIG. 11 and FIG. 13 , S100 may include, for example, S110 to S130 .

[0120] S110 : forming a first sub-electrode 31 and a second sub-electrode 32 in sequence on the circuit board 50 .

[0121] In the above steps, the first sub-electrode 31 and the second sub-electrode 32 can be formed by at least one of a thin film deposition process, an electroplating process, and an electroless plating process. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0122] S120 : forming an adhesive layer 60 on the circuit board 50 .

[0123] In the above steps, the adhesive layer 60 covers at least a portion of the sidewalls of the first bonding electrode 30 to improve the adhesion between the first bonding electrode 30 and the circuit board 50. Furthermore, the adhesive layer 60 exposes the surface of the first bonding electrode 30 away from the substrate 51, facilitating the corresponding bonding connection between the light-emitting device 20 and the first bonding electrode 30 via the second bonding electrode 50. The adhesive layer 60 can be formed by first a thin film deposition process and then a photolithography process.

[0124] S130 : forming a third sub-electrode 33 on a surface of the second sub-electrode 32 away from the circuit board 50 .

[0125] In the above steps, the third sub-electrode 33 may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process.

[0126] S200 : preparing the light emitting device 20 and the second bonding electrode 40 on the first transfer substrate 80 .

[0127] In the above steps, the light-emitting device 20 may include a first light-emitting stacked layer 22 and a first connecting electrode 23. The surface electrode 21 may be prepared after the light-emitting device 20 is bonded to the first bonding electrode 30 of the circuit board 50. For details, refer to the following. The second bonding electrode 40 may include, for example, a fourth sub-electrode 41 and a fifth sub-electrode 42, with the fourth sub-electrode 41 electrically contacting the first connecting electrode 23 of the light-emitting device 20.

[0128] It should be noted that the embodiment of the present disclosure does not limit the process sequence of S100 and S200. S100 may be performed first and then S200; S200 may be performed first and then S100; or S100 and S200 may be performed simultaneously.

[0129] On this basis, as shown in FIG. 11 and FIG. 14 , S200 may include, for example, S210 to S220 .

[0130] S210 : forming a plurality of light emitting devices 20 on a first transfer substrate 80 .

[0131] In the above steps, a temporary bonding adhesive 81 may be provided between the light emitting device 20 and the first transfer substrate 80 to facilitate peeling off the first transfer substrate 80 in a subsequent process.

[0132] S220 : forming a fourth sub-electrode 41 and a fifth sub-electrode 42 in sequence on a side of the light-emitting device 20 away from the first transfer substrate 80 .

[0133] In the above steps, the fourth sub-electrode 41 and the fifth sub-electrode 42 may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process.

[0134] S300 : connecting the light emitting device 20 on the first transfer substrate 80 to the first bonding electrode 30 on the circuit board 50 via the second bonding electrode 40 .

[0135] In the above steps, the first bonding electrode 30 and the second bonding electrode 40 can be aligned and contacted, and at a high temperature of 230°C to 260°C, the third sub-electrode 33 reacts with the second sub-electrode 32 to form a first intermetallic compound, and the third sub-electrode 33 reacts with the fifth sub-electrode 42 to form a fourth intermetallic compound, thereby realizing the connection between the light-emitting device 20 and the first bonding electrode 30 on the circuit board 50 through the second bonding electrode 40.

[0136] S400 : removing the first transfer substrate 80 .

[0137] In the above steps, the first transfer substrate 80 can be removed by at least one of laser debonding, thermal sliding debonding, chemical debonding, and mechanical debonding. For example, the first transfer substrate 80 can be debonded by laser, causing the temporary bonding adhesive 81 to absorb the laser light, thereby eroding the interface between the first transfer substrate 80 and the temporary bonding adhesive 81, thereby removing the first transfer substrate 80.

[0138] In some embodiments, referring to FIG. 11 and FIG. 15 , the preparation method further includes S500 and S600 .

[0139] S500 : forming a filling layer 70 .

[0140] In the above steps, the filling layer 70 is disposed on the side of the adhesive layer 60 of the driving backplane 10 away from the substrate 51 and at least covers the sidewalls of the first bonding electrode 30 and the second bonding electrode 40. The filling layer 70 can be formed by a thin film deposition process.

[0141] S600 : forming the surface electrode 21 .

[0142] In the above steps, the surface electrode 21 can be formed by a thin film deposition process. The surface electrode 21 is disposed on a side of the light emitting device 20 away from the circuit board 50 , and the light emitting stacked layers 22 of multiple light emitting devices 20 are connected to the same surface electrode 21 .

[0143] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0144] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A driving backplane, comprising: A circuit board, including a substrate, and a plurality of conductive layers and a plurality of insulating layers provided on one side of the substrate; the plurality of conductive layers include a first conductive layer, and the first conductive layer is the conductive layer farthest from the substrate among the plurality of conductive layers; the plurality of insulating layers include at least one first insulating layer, and the first insulating layer is the insulating layer located on the side of the first conductive layer away from the substrate among the plurality of insulating layers; wherein, the first conductive layer includes a plurality of conductive portions, the at least one first insulating layer is provided with a plurality of vias penetrating the at least one first insulating layer, at least a part of each conductive portion is exposed by one of the vias, and the conductive portion includes a pad, and the pad is the part of the conductive portion exposed by the via; A first bonding electrode, provided on the side of the pad away from the substrate; the surface of the first bonding electrode away from the substrate is located on the side of the at least one first insulating layer away from the substrate; An adhesive layer, provided on the side of the at least one first insulating layer away from the substrate; and, the adhesive layer covers at least a part of the side wall of the first bonding electrode and exposes the surface of the first bonding electrode away from the substrate.

2. The driving backplane according to claim 1, wherein, The first bonding electrode includes a plurality of first-type sub-electrodes stacked, and at least one first-type sub-electrode is located on the side of the at least one first insulating layer away from the substrate; Among the first-type sub-electrodes located on the side of the at least one first insulating layer away from the substrate, the first-type sub-electrode closest to the substrate is the first target sub-electrode, and the first-type sub-electrode adjacent to the first target sub-electrode and located on the side of the first target sub-electrode close to the substrate is the second target sub-electrode; The boundary of the bonding surface of the adhesive layer and the first bonding electrode away from the substrate is the first boundary, and the first boundary is located on the side of the interface of the first target sub-electrode and the second target sub-electrode away from the substrate.

3. The driving backplane according to claim 2, wherein, The first bonding electrode includes a first sub-electrode, a second sub-electrode and a third sub-electrode stacked in sequence, the first sub-electrode is in electrical contact with the pad, and both the second sub-electrode and the third sub-electrode are located on the side of the at least one first insulating layer away from the substrate.

4. The driving backplane according to claim 3, wherein, The first boundary is located between the two surfaces of the second sub-electrode close to and away from the substrate; or, the first boundary is located between the two surfaces of the third sub-electrode close to and away from the substrate.

5. The driving backplane according to any one of claims 2 to 4, wherein, The ratio of the minimum distance between the first boundary and the target interface to the thickness of the first-type sub-electrode on the side of the target interface away from the substrate is greater than or equal to 1 / 4; The target interface is the interface of the plurality of first-type sub-electrodes, which is located on the side of the first boundary close to the substrate and adjacent to the first boundary.

6. The driving backplane according to any one of claims 1 to 5, wherein, The first bonding electrode is away from the surface of the substrate and located on the side of the adhesive layer away from the substrate.

7. The driving backplane according to any one of claims 1 to 6, wherein, the thickness of the adhesive layer is 0.05 μm to 4 μm.

8. The driving backplane according to any one of claims 1 to 7, wherein, the material of the adhesive layer includes an inorganic insulating material.

9. The driving backplane according to any one of claims 1 to 8, wherein, along the direction perpendicular to the substrate and away from the substrate, the multi-layer conductive layer sequentially includes a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a source-drain conductive layer, and an electrode layer, and the multi-layer insulating layer sequentially includes a first gate insulating layer, a second gate insulating layer, an interlayer insulating layer, a first planarization layer, a first passivation layer, and a second planarization layer; the first gate insulating layer is disposed between the first semiconductor layer and the first gate conductive layer, the second gate insulating layer is disposed between the first gate conductive layer and the second gate conductive layer, the interlayer insulating layer is disposed between the second gate conductive layer and the source-drain conductive layer, the first planarization layer is disposed between the source-drain conductive layer and the electrode layer, and the first passivation layer and the second planarization layer are disposed on the side of the electrode layer away from the substrate.

10. A light-emitting substrate, comprising: a driving backplane, which is the driving backplane according to any one of claims 1 to 9; a light-emitting device and a second bonding electrode, and the light-emitting device is connected to the first bonding electrode of the driving backplane through the second bonding electrode.

11. The light-emitting substrate according to claim 10, wherein, the light-emitting device includes: a surface electrode, which is electrically connected to the driving backplane; a first light-emitting stack layer, which is disposed on the side of the surface electrode close to the driving backplane and is connected to the surface electrode; a first connecting electrode, which is disposed on the side of the first light-emitting stack layer away from the surface electrode and is connected to the first light-emitting stack layer; the second bonding electrode is disposed on the surface of the first connecting electrode away from the first light-emitting stack layer; or, the light-emitting device includes: a second light-emitting stack layer; a second connecting electrode and a third connecting electrode, the second connecting electrode and the third connecting electrode are disposed on the same side of the second light-emitting stack layer and are respectively connected to the second light-emitting stack layer; the second bonding electrode is disposed on the surfaces of the second connecting electrode and the third connecting electrode away from the second light-emitting stack layer.

12. The light-emitting substrate according to claim 10 or 11, further comprising: a filling layer, which is disposed on the side of the adhesive layer of the driving backplane away from the substrate and at least covers the side walls of the first bonding electrode and the second bonding electrode.

13. A display device, comprising: a light-emitting substrate, which is the light-emitting substrate according to any one of claims 10 to 12; a housing, and the light-emitting substrate is disposed in the housing.

Images