Link training method and apparatus

Abstract

A link training method and apparatus, which relate to the technical field of communications. The method comprises: starting a link training process for a link, wherein the link comprises at least one channel; receiving a first control frame, wherein the first control frame comprises a first training sequence; on the basis of the first control frame, locking a clock of the at least one channel, and sending a first logic layer management packet, wherein the first logic layer management packet indicates that the clock of the at least one channel has been successfully locked; receiving a second control frame, wherein the second control frame comprises a second training sequence, which comprises a pseudo-random sequence; on the basis of the second control frame, executing equalization training of the at least one channel, and sending a second logic layer management packet, wherein the second logic layer management packet indicates that the equalization training of the at least one channel has succeeded; receiving a third control frame, wherein the third control frame comprises a third training sequence, which comprises a pseudo-random sequence, and the second training sequence is different from the third training sequence; and on the basis of the third control frame, locking a data boundary of the at least one channel, and sending a third logic layer management packet, wherein the third logic layer management packet indicates a channel that has been successfully locked and / or a channel that has failed to be locked among the at least one channel.

Description

Link training method and device Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a link training method and device. Background Art

[0002] To meet the diverse signal transmission requirements between devices, the industry has defined a variety of high-speed signal transmission interfaces. The high-speed signal transmission interfaces of each device can be coupled via cables to enable inter-device signal transmission. Before transmitting signals between devices, the devices can establish a link (referred to as link establishment) using varying numbers of channels based on the application and service bandwidth to achieve a stable data transmission channel. This process is also known as link training. However, different buses use different encoding schemes during link training. For example, the universal serial bus (USB) uses 64b / 66b and 128b / 132b encoding, while the peripheral component interconnect express (PCIe) uses 128b / 130b encoding. Therefore, the link training processes of different bus types are incompatible.

[0003] Summary of the Invention

[0004] The present application provides a link training method and device, which solves the problem that different types of buses need to be encoded in a specific manner before link training can be performed, thereby improving the generalization of the link training process for different links.

[0005] This application adopts the following technical solution.

[0006] In the first aspect, the present application provides a link training method. The link training method is applied to a second device or a chip or processor in the second device, and the second device is connected to an intermediate device or a first device through a unified multimedia interconnection channel. The link training method includes: the second device starts a link training process of a link, and the link includes at least one channel; the second device receives a first control frame, and the first control frame includes a first training sequence; according to the first control frame, the clock of the aforementioned at least one channel is locked, and a first logical layer management packet is sent, and the first logical layer management packet indicates that the clock of at least one channel is locked successfully. And, the second device receives a second control frame, and the second control frame includes a second training sequence, and the second training sequence includes a pseudo-random sequence; according to the second control frame, equalization training of at least one channel is performed, and a second logical layer management packet is sent, and the second logical layer management packet indicates that the equalization training of at least one channel is successful. Finally, the second device receives a third control frame, which includes a third training sequence, the third training sequence includes a pseudo-random sequence, and the second training sequence and the third training sequence are different; locks the data boundary of at least one channel according to the third control frame, and sends a third logical layer management packet, which indicates: a channel that is successfully locked and / or a channel that fails to be locked in at least one channel.

[0007] This application does not limit the encoding method of each training sequence. The second device can implement the link training process without using a specific encoding method to encode or decode the training sequence. Moreover, during the link training process, the second training sequence used to perform channel equalization and the third training sequence used to perform channel locking are different. That is, the second device uses different training sequences to perform channel equalization training and channel locking during the link training process. Since the second training sequence and the third training sequence are both pseudo-random sequences, that is, the spectral distribution of the sequences is randomized, after the second device performs channel equalization training and channel locking based on these two training sequences, the link trained by the second device can also ensure communication reliability in more severe communication environments, which is conducive to improving the robustness of the communication process between devices.

[0008] In conjunction with the link training method provided in the first aspect, in an optional implementation, the link training method provided in this application further includes: the second device receiving multiple fourth control frames, the fourth control frames including a data start identifier, the data start identifier being used to mark the start of new data transmission. Furthermore, the second device performs multi-channel alignment on successfully locked channels based on the multiple fourth control frames. In this application, the second device only needs to perform multi-channel alignment on successfully locked channels, reducing the process of processing channels that failed to lock, which is beneficial to improving the efficiency of link training.

[0009] In a second aspect, the present application provides another link training method. This link training method is applied to a first device or a chip or processor within the first device, wherein the first device is connected to an intermediate device or a second device via a unified multimedia interconnection channel. The link training method comprises: the first device initiating a link training process for a link, wherein the link comprises at least one channel; the first device sending a first control frame, wherein the first control frame includes a first training sequence; the first device receiving a first logical layer management packet, wherein the first logical layer management packet indicates that the clock of at least one channel has been successfully locked. Furthermore, the first device sending a second control frame, wherein the second control frame includes a second training sequence, wherein the second training sequence includes a pseudo-random sequence; the first device receiving a second logical layer management packet, wherein the second logical layer management packet indicates that equalization training of at least one channel has been successfully completed. Finally, the first device sending a third control frame, wherein the third training sequence includes a pseudo-random sequence, wherein the second training sequence and the third training sequence are different; the first device receiving a third logical layer management packet, wherein the third logical layer management packet indicates which of the at least one channels has been successfully locked and / or which channels have failed to be locked. This application does not limit the encoding method of each training sequence. The first device can implement the link training process without encoding the training sequence using a specific encoding method. Moreover, during the link training process, the second training sequence used to perform channel equalization and the third training sequence used to perform channel locking are different. That is, the first device sends different training sequences to perform channel equalization training and channel locking during the link training process. Since the second training sequence and the third training sequence are both pseudo-random sequences, that is, the spectral distribution of the sequences is randomized, after the second device performs channel equalization training and channel locking based on these two training sequences, the link trained by the first device can also ensure communication reliability in more severe communication environments, which is conducive to improving the robustness of the communication process between devices.

[0010] In conjunction with the link training method provided in the second aspect, in an optional implementation, the link training method provided in this application further includes: the first device sending multiple fourth control frames to the successfully locked channels, the fourth control frames including a data start identifier, which is used to mark the beginning of a new data transmission. In this application, the second device only needs to perform multi-channel alignment on the successfully locked channels, reducing the process of processing channels that failed to lock, which is beneficial to improving the efficiency of link training.

[0011] In combination with the link training method provided by the first aspect and the second aspect, in an optional implementation manner, the Hamming distance between the sequence included in the data start identifier and the pseudo-random sequence is greater than or equal to a distance threshold.

[0012] In combination with the link training method provided in the first aspect and the second aspect, in an optional implementation, the pseudo-random sequence satisfies a pseudo-random binary sequence pattern.

[0013] In combination with the link training method provided in the first aspect and the second aspect, in an optional implementation, the second training sequence and the third training sequence are different, including: the first bit of the second training sequence and the second bit in the third training sequence are inverted, and the position of the first bit in the second training sequence is the same as the position of the second bit in the third training sequence.

[0014] In conjunction with the link training methods provided in the first and second aspects, in an optional implementation, the first training sequence includes: one or more groups of 1 sequences of a first length, and one or more groups of 0 sequences of a second length. The 1 sequences of the first length and the 0 sequences of the second length are arranged alternately.

[0015] In combination with the link training method provided in the first aspect and the second aspect, in an optional implementation, the first training sequence includes 0xAA.

[0016] In combination with the link training method provided in the first aspect and the second aspect, in an optional implementation, any of the aforementioned control frames includes: at least one frame header, and the frame header includes a frame type and a checksum.

[0017] Exemplarily, if any control frame includes multiple frame headers, two or more frame headers among the multiple frame headers are consistent.

[0018] In a third aspect, the present application provides a link training device, which includes a module for executing the method of any one of the implementations of the first aspect or the second aspect.

[0019] In a fourth aspect, the present application provides a communication device. The communication device includes a transceiver and a processor. The processor is configured to initiate a link training process for a link and to collaborate with the transceiver to perform the steps of the method according to any one of the implementations of the first or second aspects.

[0020] In a fifth aspect, the present application provides a communication system. The communication system includes at least two communication devices provided in the fourth aspect, wherein the communication device for sending control frames is a first device, and the communication device for receiving control frames is a second device. The first device is configured to implement the functions of the first device in any implementation of the second aspect, and the second device is configured to implement the functions of the second device in any implementation of the first aspect. Therefore, the communication system can also achieve the beneficial effects of the methods described in the first and second aspects above, which will not be elaborated here.

[0021] In a sixth aspect, the present application provides a readable storage medium. The readable storage medium includes a computer program or instructions, and when the computer program or instructions are executed on a computer, the computer executes the operating steps of the method of any implementation of the first aspect or the second aspect.

[0022] In a seventh aspect, the present application provides a computer program product. The computer program product includes a computer program or instructions, and when the computer program or instructions are executed on a computer, the computer performs the operation steps of the method of any implementation of the first aspect or the second aspect.

[0023] Regarding the beneficial effects of the third to seventh aspects, reference may be made to the description of any implementation in the first and second aspects, which will not be repeated here. Based on the implementation provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a structural diagram of a communication system provided by the present application;

[0025] FIG2 is a second structural diagram of a communication system provided by the present application;

[0026] FIG3 is a third structural diagram of a communication system provided by the present application;

[0027] FIG4 is a schematic diagram of the structure of a control frame provided by this application;

[0028] FIG5 is a flowchart of a link training method provided by the present application;

[0029] FIG6 is a second flow chart of a link training method provided by the present application;

[0030] FIG7 is a schematic diagram of a clock locking process at a channel transmitter provided by the present application;

[0031] FIG8 is a schematic diagram of a clock locking process at a channel receiving end provided by the present application;

[0032] FIG9 is a schematic diagram of clock locking interaction provided by the present application;

[0033] FIG10 is a schematic diagram of a channel transmitting end equalization process provided by the present application;

[0034] FIG11 is a schematic diagram of a channel receiving end equalization process provided by the present application;

[0035] FIG12 is a schematic diagram of the channel equalization interaction process provided by this application;

[0036] FIG13 is a schematic diagram of a multi-channel skew measurement process provided by this application;

[0037] FIG14 is a schematic diagram of delay deviation before multi-channel skew adjustment provided by the present application;

[0038] FIG15 is a schematic diagram of delay deviation after multi-channel skew adjustment provided by the present application;

[0039] FIG16 is a schematic diagram of a multi-channel alignment process at a transmitting end provided by this application;

[0040] FIG17 is a schematic diagram of a multi-channel alignment process at a receiving end provided by this application;

[0041] FIG18 is a schematic diagram of a normal mode multi-channel alignment interaction provided by the present application;

[0042] FIG19 is a schematic diagram of a multi-channel alignment interaction in a test mode provided by the present application;

[0043] FIG20 is a structural diagram of a link training device provided by the present application;

[0044] FIG21 is a second structural diagram of a link training device provided by the present application;

[0045] FIG22 is a schematic diagram of the structure of the communication device provided in this application. DETAILED DESCRIPTION

[0046] The present application provides a link training method, in which the communication device does not limit the encoding method of each training sequence, and the communication device does not need to use a specific encoding method to encode or decode the training sequence to implement the link training process. Moreover, during the link training process, the second training sequence used to perform channel equalization and the third training sequence used to perform channel locking are different, that is, the communication device uses different training sequences to perform channel equalization training and channel locking during the link training process. Since the second training sequence and the third training sequence are both pseudo-random sequences, that is, the spectral distribution of the sequences is randomized, therefore, after the communication device performs channel equalization training and channel locking according to these two training sequences, the link trained by the communication device can also ensure communication reliability in more severe communication environments, which is conducive to improving the robustness of the communication process between devices.

[0047] The technical solutions involved in this application may be applicable not only to current audio and video transmission technologies, audio and video standards, or communication standards, but also to future audio and video transmission technologies, audio and video standards, or communication standards. The terms used in the implementation methods of this application are only used to explain the specific embodiments of this application and are not intended to limit this application. The following is a brief introduction to some concepts that may be involved in this application.

[0048] Audio and video service flows include audio streams and / or video streams. An audio stream is a data stream used to transmit audio data in real time. A video stream is the transmission of video data. For example, a video stream can be processed as a stable and continuous flow over a network. A video stream consists of multiple video frames, each of which corresponds to an image.

[0049] In this embodiment, "video" is a general term that refers to a sequence of multiple consecutive frames, with one frame corresponding to one image. "Audio and video" is an information application technology term that refers to video, audio, or multimedia content that includes both video and audio. Furthermore, this application does not limit the type of service flow. For example, the service flow in this application can be an audio and video service flow or a USB service flow. The following description will primarily use audio and video service flows as an example.

[0050] Lane: A lane is a path for signal transmission. It can be unidirectional or bidirectional. A unidirectional lane consists of a pair of differential signal lines, while a bidirectional lane consists of two pairs of differential signal lines.

[0051] Link: A link is a collection of channels or a conductor line used for power supply. A link generally includes one channel or multiple channels. When a channel in a link is working, a transmitter and a receiver are turned on at each end of the channel, and data (signals) are transmitted from the transmitter to the receiver. The side of the link where the transmitter is located is called the transmitter side (or the transmitter side (Tx Side)), and the side of the link where the receiver is located is called the receiver side (or the receiver side (Rx Side)). Links can be divided into uplinks and downlinks. The uplink refers to the link when a slave device (for example, a game controller) sends a signal to a master device (for example, a display), and the downlink refers to the link when a master device (for example, a routing device) sends a signal to a slave device (for example, a display).

[0052] Main link (ML): The main link is used for high-speed data transmission, such as audio and video signals, third-party protocol data, and other high-speed data transmission.

[0053] Sideband Link (SL): A sideband link is used to transmit low-speed data, such as device management signals, port management signals, bandwidth management signals, and power management signals. It is also used to transmit control messages. The reliability of data transmission on the sideband link is higher than that on the main link.

[0054] Link training: For newly opened channels in a link, a process such as channel clock recovery and locking, channel equalization, channel locking, and lane-to-lane de-skew is performed to enable the channel to exchange data normally. This process is called link training, or link establishment.

[0055] Channel clock recovery and lock: During link training, the process by which the channel receiver extracts the receive clock from the received data message is called channel clock recovery and lock, or channel clock recovery.

[0056] Channel equalization: During link training, a signal is transmitted from the transmitter through a channel to the receiver. During transmission, factors such as transmission rate, electromagnetic interference, and channel quality can cause signal distortion, affecting the receiver's ability to accurately interpret the signal. The greater the signal distortion, the higher the bit error rate (BER), resulting in poorer channel performance. To ensure a high-quality signal that is easily interpreted by the receiver, signal conditioning can be performed at the transmitter, during transmission, or before the receiver makes a decision. This process is called channel equalization, or signal compensation.

[0057] Channel locking: During link training, the process by which the receiver determines when to begin transmitting bit symbols is called channel locking. This process can also be called determining the boundaries of channel-transmitted data or determining the boundaries of data transmitted by the channel.

[0058] Multi-channel alignment: When a link includes multiple channels, the transmission delay of each channel varies during link training. To ensure that the receiver can correctly combine the data received by multiple channels after experiencing different transmission delays, it is necessary to adjust and compensate for each channel. This process of adjusting and compensating for each channel is called multi-channel de-skew.

[0059] Training sequence (TS): A special character sent during link training. Training sequences include: Logic Layer Training Sequence 0 (LLCF_TS0), Logic Layer Training Sequence 1 (LLCF_TS1), and Logic Layer Training Sequence 2 (LLCF_TS2). Logic Layer Training Sequence 0 (LLCF_TS0) is used for channel clock recovery and lock during link training. Logic Layer Training Sequence 1 (LLCF_TS1) is used for channel equalization during link training. Logic Layer Training Sequence 2 (LLCF_TS2) is used for channel lock during link training.

[0060] The technical solutions provided in the embodiments of the present application can be applied to a communication system comprising multiple devices, wherein the devices in the communication system can be connected directly or through a routing device. Signals can be transmitted directly between the devices or through an interface device, and the signals can be transmitted to the processing unit within the device via a bus within the device.

[0061] For example, FIG1 is a structural diagram of a communication system provided by the present application. The communication system 100 includes a first device 110 and a second device 120, which are directly connected via a cable to enable signal transmission between the first device 110 and the second device 120. For example, the first device 110 may be a set-top box, and the second device 120 may be a display, and audio and video data may be transmitted between the set-top box and the display via a cable. Alternatively, the first device 110 may be a display, and the second device 120 may be a game controller, and control information may be transmitted between the display and the game controller via a cable.

[0062] Optionally, the device 110 may include an interface device 111 , and the device 120 may include an interface device 121 . The interface device 111 in the device 110 and the interface device 121 in the device 120 are directly connected via a cable to achieve signal transmission between the devices 110 and 120 .

[0063] For another example, FIG2 is a second structural diagram of a communication system provided by the present application. The communication system 200 includes multiple devices 210 and a routing device 220. Among them, any two devices 210 in the multiple devices 210 can transmit signals through the routing device 220, for example, transmitting audio and video data or transmitting charging signals. For example, the multiple devices 210 may include a display, a set-top box, and an audio player (for example, a Moving Picture Experts Group Audio Layer III (MP3) device). The set-top box can transmit audio and video data to the display through the routing device 220, and the set-top box can also transmit audio data to the audio player through the routing device 220. In addition, there may be two directly connected devices in the multiple devices 210. For example, the multiple devices 210 may also include a game controller, which can be directly connected to the display through a cable and transmit control information to the display.

[0064] Optionally, each of the multiple devices 210 may include an interface device, and the routing device 220 may include multiple interface devices. The interface device of each of the multiple devices 210 may be connected to one of the multiple interface devices of the routing device 220. For example, the multiple devices 210 may include a display, a set-top box, and an audio player. The multiple interface devices of the routing device 220 may include first to third interface devices. The interface device of the display is connected to the first interface device of the routing device 220 via a cable, the interface device of the set-top box is connected to the second interface device of the routing device 220 via a cable, and the interface device of the audio player is connected to the third interface device of the routing device 220 via a cable.

[0065] In the two aforementioned communication systems, the interconnected devices can be referred to as communication devices. When the communication devices are electronic devices, they can be deployed on land, including indoors or outdoors, and can be handheld or vehicle-mounted. They can also be deployed on water (such as ships) or in the air (such as aircraft, balloons, and satellites). Exemplarily, the communication device may include, but is not limited to: a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a camera, a wearable device (such as a smart watch, a smart bracelet, a pedometer, etc.), an audio device, an audio and video player, a set-top box, a game console, a printer, a mouse, a keyboard, an in-vehicle device (such as a car, a bicycle, an electric car, an airplane, a ship, a train, a high-speed train, etc.), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a smart home device (such as a refrigerator, a television, an air conditioner, an electric meter, etc.), an intelligent robot, a workshop device, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, or a smart home. Wireless terminals in homes, flying devices (e.g., smart robots, hot air balloons, drones, airplanes), etc. Optionally, the signals transmitted between the above communication devices may include, but are not limited to: audio and video signals, radio frequency signals, IoT data, and charging signals.

[0066] When the communication device is an interface device, the interface device may be a chip. It is understood that the communication system is a chip-to-chip interconnection system, and the chip may be an interface chip on an electronic device, cable, docking station, adapter, or router. The docking station may be connected to a gigabit Ethernet port, a video graphics array (VGA) port, a high-definition multimedia interface (HDMI) port, a TF card (trans-flash card), an SD card (secure digital memory card), a charging port, and a universal serial bus (USB) port, among others.

[0067] In this application, when the communication device is a chip, the chip may include an interface module. That is, this application can be applied to the interface module that interconnects two chips. This interface module can be understood as an IP integrated within the chip. Alternatively, the interface module can be sold separately as an IP.

[0068] For example, when the chip can be a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU), the present application can be applied to the interface modules of chips such as SoC, CPU, and GPU. When the chip is a small chip such as a die, the interface module can be understood as the transmitting circuit and / or receiving circuit in the die. The chip can also be an input / output (I / O) die that only includes interface functions.

[0069] In the embodiments of the present application, when signals are transmitted between devices in a communication system, the interface specifications adopted may include, but are not limited to, the Universal Serial Bus (USB) interface specification, the HDMI specification, the Display Port (DP) specification, the Unified Multimedia Interconnection (UMMI) interface specification, and the Peripheral Component Interconnect Express (PCIE) interface specification. Accordingly, the high-speed signal transmission interface may be an HDMI interface, a miniHDMI interface, a micro HDMI interface, a Type-A interface, a Type-B interface, a Micro-B interface, and a Type-C interface.

[0070] For example, in the above communication system 100, when the first device 110 is a set-top box and the second device 120 is a television, the set-top box and the television can be connected via an HDMI cable, following the HDMI interface specification. When the first device 110 is a game controller and the second device 120 is a display, the game controller and the display can be connected via a USB cable, following the USB interface specification.

[0071] The embodiment of the present application also provides another interface standard that can replace the above-mentioned interface standards (such as USB interface or HDMI interface): unified media interconnection interface. The unified multimedia interconnection interface also supports direct connection between devices, or multi-device networking connection (for example, devices are connected through routing devices, or devices are connected through expansion docks). For example, the unified multimedia interconnection interface can be applied to the devices in the above-mentioned communication system 100, or to the devices in the communication system 200. The unified multimedia interconnection interface can not only adapt and transmit data, but also realize the charging function. Of course, the unified multimedia interconnection interface can also be other interface names. When the unified multimedia interconnection interface is replaced with other interface names, other interfaces can be used to realize the functions of the unified multimedia interconnection interface in this application, and the embodiment of the present application does not limit this.

[0072] A unified multimedia interconnection channel refers to a channel connected based on a unified multimedia interconnection interface provided by a source device and a host device. The unified multimedia interconnection channel can be used to connect a charger to charge an electronic device (such as the above-mentioned smart TV, set-top box or audio and video playback device), can also be used to transmit data between electronic devices and peripheral devices, and can also be used to connect headphones to play audio through headphones. The above-mentioned unified multimedia interconnection interface can also be used to connect other electronic devices, such as AR devices. When the unified multimedia interconnection channel is used to implement data communication functions between devices, the unified multimedia interconnection channel can support uncompressed video and compressed video transmission, as well as various advanced features such as quick video transport (QVT), automatic low latency mode (ALLM), and dynamic frame rate refresh (DFR). In addition, the unified multimedia interconnection channel can also support LPCM format audio and video and various HDR protocols, such as HDR Vivid. The unified multimedia interconnection channel also supports encryption control protection for audio and video data transmission. In some optional implementations, the channel 125 may also refer to other types of channels that can implement the functions supported by the above-mentioned unified multimedia interconnection channel, such as a UMI (unified multimedia interconnection) channel.

[0073] In this embodiment, the unified multimedia interconnection interface is suitable for transmitting high-speed signals for audio and video devices, third-party protocol devices (such as USB / PCIe / Ethernet), etc. A device using the unified multimedia interconnection interface is called a unified multimedia interconnection device, and a system composed of multiple unified multimedia interconnection devices connected together is called a unified multimedia interconnection system. The capabilities provided by the unified multimedia interconnection interface include: ① Bidirectional transmission of audio and video, which meets the audio and video transmission requirements of devices such as TVs, PCs, and mobile phones, and supports audio and video content transmission protection, visual lossless compression, etc. ② Third-party protocol data transmission, which enables interaction between the unified multimedia interconnection device and third-party protocol devices. For example, the supported third-party protocols include USB3, and Ethernet, PCIe, etc. will be supported in the future. ③ Bidirectional power supply, which meets the power supply requirements of electronic devices whose power does not exceed a certain power value, such as 480W, 500W or other values. It should be understood that the number of devices and screens in the home is increasing. The unified multimedia interconnection interface solves the problem of free connection between screens and devices, allowing users to freely operate all devices in the home regardless of which room they are in. The link training method provided in this application can be applied to the following scenarios: Scenario 1, playing the video on the set-top box in the living room in the bedroom; Scenario 2, playing games in the study through a monitor connected to the game console in the living room; Scenario 3, working in the living room through a TV connected to the PC in the study. The unified multimedia interconnection interface is also suitable for multi-room scenarios, such as supporting star networking, device discovery, capability discovery, etc.; as well as point-to-point stream management (cross-room video delivery), cross-device transmission of HID events (HID Passthrough), and long-line transmission (15 meters or longer), etc. It is worth noting that the unified multimedia interconnection interface can be integrated into consumer electronic products such as PCs, laptops, TVs, set-top boxes, and mobile phones to realize functions such as interconnection communication and information transmission between multiple devices.

[0074] In some examples, the communication network formed by the channels used to implement audio and video transmission between devices is also referred to as an audio and video interface network or an audio and video interface network. It is worth noting that in this embodiment, the term "channel" is a general term referring to a communication path or a medium for signal transmission. A channel may also be referred to as a bus, data line, communication channel, communication connection, link, or path, etc., and this application does not limit this.

[0075] When devices are interconnected using the above-mentioned high-speed signal transmission interface, the links between the devices include a main link and an auxiliary link. The main link is used to transmit high-speed data such as audio and video signals and third-party protocol data, and the auxiliary link is used to transmit low-speed data such as device management signals, port management signals, bandwidth management signals, and power supply management signals, as well as control messages.

[0076] For example, as shown in FIG3 , the interconnection between devices in the communication system 100 is achieved through a unified multimedia interconnection interface. The link between the first device 110 and the second device 120 includes a main link 130 and an auxiliary link 140. For the first device 110, the main link 130 includes a transmission channel TX0-TXn and a receiving channel RX0-RXm, and the auxiliary link 140 includes a transmission channel SBTX and a receiving channel SBRX. n and m are positive integers, and the embodiment of the present application does not limit the specific values ​​of n and m. For the second device 120, the main link 130 includes a receiving channel RX0-RXn and a transmission channel TX0-TXm, and the auxiliary link 140 includes a receiving channel SBRX and a receiving channel SBRX. The maximum transmission rate of the channel in the main link 130 is greater than the maximum transmission rate of the channel in the auxiliary link 140. For example, the maximum transmission rate of the channel in the main link 130 is 8 gigabits per second (Gbps), and the maximum transmission rate of the channel in the auxiliary link 140 is 12.5 megabits per second (Mbps). When the first device 110 is a display and the second device is a routing device, the display is a slave device and the routing device is a master device. The display can send signals to the routing device through the transmission channels TX0-TXn in the main link 130. The link composed of the transmission channels TX0-TXn can be called an uplink. The routing device can send signals to the display through the transmission channels TXo-TXm in the main link 130. The link composed of the transmission channels TX0-TXm can be called a downlink.

[0077] Between the first device 110 and the second device 120 in the communication system 100, before transmitting signals, the first device 110 and / or the second device 120 can use different numbers of channels to establish a link (referred to as establishing a link) based on the application form and service bandwidth to obtain a stable data transmission channel. This process is also called a link training process.

[0078] During link training, the first device 110 and the second device 120 transmit information such as link management or training sequences via a logic layer control frame (LLCF). In this document, the logic layer control frame is referred to as a control frame. The control frame is sent in its entirety on a single lane, and the insertion location of the control frame is indicated by a control frame send location message (CFSLM). The frame structure of the control frame is shown in FIG4 , which is a schematic diagram of the structure of the control frame provided in this application.

[0079] A control frame consists of at least one header and a payload. The header includes the frame type and checksum. For example, the control frame shown in Figure 4 includes three headers. Header 1 includes B0 for the frame type and B1 for the checksum. The payload carries information such as link management and training sequences.

[0080] Optionally, if the control frame includes multiple frame headers, two or more of the multiple frame headers are identical. For example, in the control frame structure, frame headers 1, 2, and 3 have the same content, forming a repetition code. Alternatively, a "two-out-of-three redundancy" approach (where at least two of the three transmissions have to be completely identical) is employed to improve the reliability of frame header recognition in the control frame.

[0081] Optionally, unless otherwise specified, the control frame (frame header + payload) is not scrambled or pre-coded.

[0082] Table 1 below provides a possible example for different fields in a control frame.

[0083] Table 1

[0084] Table 2 below provides the contents of the payload carried in different types of control frames.

[0085] Table 2

[0086] In this embodiment, LLCF_TS0 is also called the first logic layer control frame training sequence (logic layer control frame, training sequence0) or the first control frame training sequence (control frame, training sequence0, CF_TS0) or the first training sequence. LLCF_TS1 is also called the second logic layer control frame training sequence (logic layer control frame, training sequence1) or the second control frame training sequence (control frame, training sequence1, CF_TS1) or the second training sequence. LLCF_TS2 is also called the third logic layer control frame training sequence (logic layer control frame, training sequence2) or the third control frame training sequence (control frame, training sequence1, CF_TS2) or the third training sequence. LLCF_DS is also called the logic layer data start (logic layer control frame, data start), data start, data start information or data start identifier, etc.

[0087] LLCF_EI is the logic layer control frame, electrical idle, LLCF_DST is the logic layer channel deviation elimination test (logic layer control frame, de-skew test), LLCF_EIE is the logic layer control frame, electrical idle, and LLCF_PAD is the response message of the control frame.

[0088] The implementation of the link training method provided in the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0089] Here, the link training method of the embodiment of the present application is applied to the first device 110 and the second device 120 shown in Figure 3 as an example for description. Figure 5 is a flowchart of a link training method provided by the present application. The link training method provided by this embodiment includes the following steps S501 to S509.

[0090] S501: Start a link training process of a link.

[0091] The link refers to a wired transmission medium between the first device 110 and the second device 120. The link includes at least one lane, which refers to a path for transmitting signals between devices.

[0092] S501 includes: the first device 110 starts a link training process of the link, or the second device 120 starts a link training process of the link.

[0093] Optionally, the method for implementing the above-mentioned S501 may include but is not limited to: after the first device 110 is powered on, it is found that the device connected to the first device 110 through the unified multimedia interconnection interface is also powered on, and the first device 110 sends a link training start message (TSM) to the second device 120, and the TSM instructs the second device 120 to start the link training process of the link.

[0094] S502: The first device 110 sends a first control frame.

[0095] Corresponding to the process of S502 , the second device 120 receives the first control frame.

[0096] The first control frame includes a first training sequence. Exemplarily, the first training sequence is LLCF_TS0 (CF_TS0 for short) in Table 2 above.

[0097] Optionally, the first training sequence includes: one or more groups of 1 sequences of a first length, and one or more groups of 0 sequences of a second length. The 1 sequences of the first length and the 0 sequences of the second length are arranged alternately. That is, in this embodiment, the first training sequence includes a frequently changing 01 sequence or 10 sequence.

[0098] For example, the first training sequence includes 0xAA of any length. When 0xAA is represented by a binary sequence: 10101010.

[0099] S503: The second device 120 locks the clock of at least one channel according to the first control frame, and sends a first logical layer management packet.

[0100] Corresponding to the process of S503 , the first device 110 receives the first logical layer management package.

[0101] In this article, the logical layer management packet is also called a message packet, a management packet or other names.

[0102] The first logic layer management package indicates that the clock of the at least one channel is locked successfully.

[0103] Optionally, when the clock lock of the at least one channel fails, the second device 120 sends another logical layer management packet, where the other logical layer management packet is used to request the first device 110 to adjust the swing of the corresponding channel and indicate the gear requested for adjustment.

[0104] In this embodiment, the first logical layer management packet and the aforementioned another logical layer management packet are also referred to as clock lock feedback messages (CLFM).

[0105] After receiving the first logical layer management packet, the first device 110 switches the code type of the clock-locked channel, and continues to send the second training sequence after the switching, as shown in the following S504.

[0106] S504: The first device 110 sends a second control frame.

[0107] Corresponding to the process of S504 , the second device 120 receives the second control frame.

[0108] The second control frame includes a second training sequence, and the second training sequence is used for channel parameter tuning calculation in the training phase.

[0109] The second training sequence includes a pseudo-random sequence. Exemplarily, the second training sequence refers to LLCF_TS1 in Table 2 above.

[0110] Optionally, the pseudo-random sequence satisfies a pseudo-random binary sequence (PRBS) pattern or a sequence pattern of another base (such as quaternary, octal, decimal, or hexadecimal). This embodiment is described using the pseudo-random sequence satisfying the PRBS pattern as an example. PRBS refers to a pseudo-random sequence containing only 0s and 1s.

[0111] For example, the second training sequence may be generated by a PRBS pattern generator. Table 3 below provides several polynomials for generating PRBS patterns supported by the first device 110.

[0112] Table 3

[0113] The first device 110 generates the second training sequence in the form of PRBS11 (the corresponding polynomial is: G(x)=x 11 +x 2 +1), the adopted seed is: 0x7FF, and the payload of the generated second training sequence (LLCF_TS1, abbreviated as CF_TS1) is as shown in Table 4 below.

[0114] Table 4

[0115] Table 4 above represents the payload of the second training sequence in hexadecimal. Other bases may also be used, and this application is not limited to this. In this embodiment, the second training sequence includes a training sequence of any length whose payload is PRBS11. It should be understood that the second training sequence may also be generated using other PRBS pattern generation methods or other seeds, and this application is not limited to this.

[0116] S505: The second device 120 performs equalization training on at least one channel according to the second control frame, and sends a second logical layer management packet.

[0117] Corresponding to the process of S505 , the first device 110 receives the second logical layer management package.

[0118] The second logic layer management package indicates that equalization training of at least one channel is successful.

[0119] In this embodiment, successful equalization training means that the equalization training results meet expectations. For example, one or more of the voltage level, jitter value, eye diagram (such as eye height and fundus), or other parameters of the equalized signal meet set conditions.

[0120] Optionally, if equalization training for a channel is unsuccessful, the second device may request the first device 110 to adjust the FFE parameters for the corresponding channel through another logical layer management packet and indicate the gear to be adjusted. After receiving the other logical layer management packet, the transmitting end completes the FFE update for the channel for which the FFE parameters need to be adjusted.

[0121] In this embodiment, the second logical layer management packet and the aforementioned another logical layer management packet may also be referred to as an equilibrium feedback message (EQFM).

[0122] After receiving the second logical layer management packet, the first device 110 switches the code type of the channel for which equalization training has succeeded, and continues to send the third training sequence after the switching, as shown in the following S506.

[0123] S506: The first device 110 sends a third control frame.

[0124] Corresponding to the process of S506 , the second device 120 receives the third control frame.

[0125] The third control frame includes a third training sequence, the third training sequence includes a pseudo-random sequence, and the second training sequence is different from the third training sequence.

[0126] Exemplarily, the first bit in the second training sequence and the second bit in the third training sequence are inverted, and the position of the first bit in the second training sequence is the same as the position of the second bit in the third training sequence.

[0127] The following exemplifies the bit inversion of the second training sequence and the third training sequence in three possible scenarios.

[0128] In the first possible scenario, the length of the second training sequence is smaller than that of the third training sequence. The second bit in the third training sequence is inverted from the first bit in the second training sequence, but the values ​​of other bits in the third training sequence that exceed the second training sequence are not limited.

[0129] In the second possible scenario, the length of the second training sequence is greater than that of the third training sequence. The second bit in the third training sequence is inverted from the first bit in the second training sequence, but there is no restriction on the values ​​of other bits in the second training sequence that exceed the third training sequence.

[0130] In a third possible scenario, the length of the second training sequence is equal to the length of the third training sequence, and the second bit in the third training sequence is inverted from the first bit in the second training sequence.

[0131] The above three possible situations are merely examples provided in this embodiment and should not be construed as limitations on this application.

[0132] In this embodiment, the first device 110 may also generate the third training sequence in the manner provided in Table 3. For example, when the content of the second training sequence is as shown in Table 4, the manner in which the first device 110 generates the third training sequence is PRBS11 (the corresponding polynomial is: G(x)=x 11 +x 2 +1), the seed used is: 0x7FF, and the generated PRBS11 sequence is bit-inverted to obtain the payload of the third training sequence (LLCF_TS2, abbreviated as CF_TS2) as shown in Table 5 below.

[0133] Table 5

[0134] Combining the contents of Table 4 and Table 5, it can be seen that the payloads of LLCF_TS2 and LLCF_TS1 are bit-inverted.

[0135] As an optional implementation, the length of the third training sequence is fixed, and the length of the third training sequence can be set according to the requirements of the channel equalization training. In this embodiment, combined with Table 2, the length of the third training sequence is fixed to 8B for exemplary description, which will not be repeated later.

[0136] In this embodiment, the third training sequence is used to confirm the synchronization state. After the second device 120 receives the third control frame carrying the third training sequence, the following S507 is executed.

[0137] S507: The second device 120 locks the data boundary of at least one channel according to the third control frame, and sends a third logical layer management packet.

[0138] Corresponding to the process of S507 , the first device 110 receives the third logical layer management package.

[0139] The third logic layer management package indicates: a channel that is successfully locked and / or a channel that fails to be locked in the at least one channel.

[0140] In this embodiment, no matter whether the channel locking succeeds or fails, the second device 120 determines that the locking process of the single channel is completed.

[0141] In an optional example, the RX whose channel is successfully locked enters the multi-channel alignment (de-skew) phase, and the RX whose channel fails to be locked needs to be closed (the state machine of the corresponding channel needs to be set to the INIT state).

[0142] For example, after each channel enters the channel locking process, the tLaneLockTimeout timer must be enabled. If channel RX (second device 120) can complete channel locking within tLaneLockTimeout, the channel lock is considered successful. If it cannot complete channel locking within tLaneLockTimeout, the channel lock is considered failed. The exception is reported to the software.

[0143] In one possible scenario, if all channels in the link fail to lock, the link training process fails.

[0144] In another possible scenario, if only one channel in the link is successfully locked, after the second device 120 sends the third logical layer management packet to the first device 110, the first device 110 and the second device 120 can start transmitting data based on the successfully locked channel.

[0145] In this way, the embodiments of the present application do not limit the encoding method of each training sequence, and the second device does not need to use a specific encoding method to encode or decode the training sequence to implement the link training process.

[0146] Furthermore, during link training, the second training sequence used for channel equalization and the third training sequence used for channel locking are different. This means that the second device uses different training sequences to perform channel equalization training and channel locking during link training. Because both the second and third training sequences are pseudo-random sequences, meaning their spectral distributions are randomized, after the second device performs channel equalization training and channel locking based on these two training sequences, the link trained between the first and second devices can maintain communication reliability even in harsher communication environments, thereby improving the robustness of inter-device communication.

[0147] In another possible scenario, if two or more lanes in the link are locked successfully, the first device 110 and the second device 120 continue to perform multi-lane de-skew, as shown in S508 and S509 below.

[0148] S508: The first device 110 sends multiple fourth control frames to the successfully locked channel.

[0149] Corresponding to the process of S508 , the second device 120 receives a plurality of fourth control frames.

[0150] Among them, the fourth control frame includes a data start identifier, and the data start identifier is used to mark the start of a new data transmission. As a feasible example, the data start identifier can be LLCF_DS (abbreviated as CF_DS) in Table 2. For example, the first device 110 transmits LLCF_DS simultaneously on all valid lanes (such as the channels that are successfully locked as mentioned above) during the first transmission or lane number switching (including low power reasons). In non-delay correction scenarios, the skew of LLCF_DS on the line should be less than T tx_skew .

[0151] The new data may refer to one or more logical layer blocks (LLBs) or data of other data management granularity.

[0152] As an optional implementation, the Hamming distance between the sequence included in the above-mentioned data start identifier and the aforementioned pseudo-random sequence is greater than or equal to the distance threshold. Exemplarily, CF_DS is a delimited frame format for a specific function, or a data pattern. In this embodiment, the selection (or design) principle of the CF_DS is to ensure that the 1s and 0s in the data pattern are close to the number of bits, and that the CF_DS and other code sequences such as CF_TS2 or CF_TS1 have as large a Hamming distance or Hamming distance as possible. This allows the data start identifier to be used to mark the start of transmission of new data, that is, the starting position of transmission of new data. Optionally, other distances can also be used to control the difference between CF_DS and CF_TS2 or CF_TS1, such as Euclidean distance, Euler distance, or others.

[0153] S509: The second device 120 performs multi-channel alignment on the successfully locked channels according to the multiple fourth control frames.

[0154] In this embodiment, the second device only needs to perform multi-channel alignment on the channels that are successfully locked, which reduces the process of processing the channels that fail to be locked, and is conducive to improving the efficiency of link training.

[0155] The signal transmission delays of each channel vary due to hardware implementation, such as PCB layout. To ensure that the receiving end of the high-speed link (such as the second device) can still correctly obtain data from multiple channels of parallel transmission after experiencing different communication delays, this is done.

[0156] During the multi-channel alignment phase, the transmitters (first device) of all channels to be aligned simultaneously send a CF_DS or send it with pre-set CF_DS delay parameters for different channels. The receivers (such as the second device) of all channels to be aligned need to continuously detect the agreed multiple CF_DSs. At the receiver (such as the second device), link-level De-Skew and Bonding are implemented by identifying the DS sequences of different lanes and aligning them after caching based on the different Skews. After the receiver (such as the second device) performs multi-channel alignment based on CF_DS, it starts to receive high-speed service data (LLB).

[0157] The above S501 to S509 include different stages of link training, as shown in Figure 6, which is a flow chart of a link training method provided by this application. Taking the receiving end of the unified multimedia interconnection interface as an example, the link training method provided by this embodiment includes the following four stages.

[0158] Phase 1, Channel Clock Recovery and Lock: The receiver receives the first training sequence (CF_TS0) carried in the control frame (CF) and recovers and locks the receiver channel's clock based on CF_TS0. If lock fails, link training fails, and the link training process ends or returns to the initial state and restarts. If lock succeeds, the process proceeds to Phase 2, Channel Equalization.

[0159] Phase 2, Channel Equalization: The receiver receives the second training sequence (CF_TS1) carried in the control frame (CF) and performs equalization training on the receiving channel based on CF_TS1. If equalization training fails, it indicates link training failure, and the link training process ends or returns to the initial state and restarts the link training process. If lock is successful, the process enters Phase 3, Channel Lock.

[0160] Phase 3, Channel Lock: The receiver receives the third training sequence (CF_TS2) carried in the control frame (CF) and locks the data boundaries of the receiving channel based on CF_TS2. If no channel is successfully locked, link training fails, and the link training process ends or returns to the initial state and restarts. If only one channel is successfully locked, data is transmitted based on that channel. If multiple channels are successfully locked, the process proceeds to Phase 4, Multi-Channel Alignment.

[0161] Phase 4: Multi-lane alignment: The receiver continuously detects multiple CF_DS packets. It then identifies the CF_DS sequences of different lanes and aligns them after caching based on skew differences, achieving link-level de-skew and bonding. After performing multi-lane alignment based on CF_DS packets, the receiver begins receiving high-speed service data.

[0162] The above four stages are described in detail below.

[0163] 1. Channel clock recovery and locking.

[0164] (1) Introduction to the process

[0165] After the link training phase begins, the channel to be trained needs to be initialized at the specified rate, and then the channel clock is recovered and locked.

[0166] During channel clock recovery and lock, the transmitter of the channel to be trained continuously sends LLCF_TS0 packets. The transmitter then sends a logical layer management packet (TSM) to the receiver, indicating the numbers of all channels initiating training in the TSM. After the receiver receives the TSM, the corresponding channel can begin clock recovery and lock.

[0167] To prevent the receiving end from failing to lock the clock, the sending end is recommended to provide 8 levels of swing adjustment.

[0168] Implementation Note: Each manufacturer can customize the evaluation method for "whether clock lock is successful." It is sufficient to ensure that the CDR at the receiving end is locked.

[0169] If the clock lock fails for a channel on the receiving end, the transmitting end can request the corresponding channel to adjust its swing parameters using a logical layer management packet (CLFM) (corresponding to another logical layer management packet in the example of S503). The packet specifies the desired swing position. Upon receiving the CLFM, the transmitting end completes the swing adjustment for the channel requiring adjustment and then sends an ACK corresponding to the CLFM to the receiving end. Upon detecting the ACK, the receiving end re-evaluates the clock lock and recovery of the adjusted channel.

[0170] If a channel's receiving end still cannot lock after traversing all swing positions, the receiving end needs to notify the sending end through the logical layer management packet CLFM and indicate that the channel training has failed. After receiving the CLFM, the sending end closes the channel (setting the corresponding channel state machine to the INIT state) and then sends an ACK corresponding to the CLFM to the receiving end. After receiving the ACK, the receiving end closes the channel (setting the corresponding channel state machine to the INIT state).

[0171] If the clock of a channel on the receiving end is successfully locked, the receiving end needs to notify the transmitting end through a logical layer management packet CLFM (corresponding to the first logical layer management packet in the example of S503) and indicate that the clock of the channel is successfully locked. If the CLFM indicates that the clock of the channel is successfully locked, the transmitting end will switch the code type of the clock-locked channel after receiving the CLFM, and then continue to send LLCF_TS1 after switching. Then, it will send back the ACK corresponding to the CLFM to the receiving end, and the channel on the transmitting end that is clock-locked will enter the channel equalization stage. After the receiving end detects the ACK, the channel on the receiving end that is clock-locked will enter the channel equalization stage.

[0172] If all channels in this link fail to lock the clock, the current link training process fails.

[0173] The clock locking process of a single-channel transmitter is shown in FIG7 , which is a schematic diagram of the clock locking process of the channel transmitter provided in this application.

[0174] In Figure 7, if tWaitRxTrainStart times out, the number of timeouts must be counted and reported to the software. Each timeout count is incremented by one. When the send link is reestablished, the timeout counter is cleared. After tLinkTrainTimeout times out, the timeout count must be reported to the management adapter.

[0175] The clock locking process of a single-channel receiving end is shown in FIG8 , which is a schematic diagram of the clock locking process of a channel receiving end provided in this application.

[0176] In Figure 8, after tSingleClTimeout times out, the above process can be followed. After tTotalClTimeout times out, it needs to be reported to the management adapter.

[0177] (2) Example of port interaction process.

[0178] Here is an example of the clock locking process for any channel. The channel is numbered Z, device A is the sending device of channel Z, device B is the receiving device of channel Z, device A and device B are directly connected to each other, and Figure 9 below shows the interaction information of their connected ports. Figure 9 is a schematic diagram of the clock locking interaction provided by this application.

[0179] Please refer to Figure 9. The specific process of clock lock interaction is as follows:

[0180] 1) After the TX end of channel Z completes initialization, it starts to perform channel clock recovery, and device A continues to send LLCF_TS0 back-to-back on channel Z.

[0181] 2) Device A sends a TSM to device B, indicating that the transmitter of channel Z has started sending the channel clock lock pattern LLCF_TS0. For example, it is only necessary to ensure that the time of sending the TSM is no earlier than the time when channel Z sends LLCF_TS0.

[0182] Note: TSM supports transmission via both the primary and secondary links. If the high-speed transmission link of device A is available (not in low-power or disconnected state, i.e., the corresponding TXLKSM is in HS state), device A can currently send TSM to device B via the high-speed transmission link. Otherwise, TSM needs to be sent to device B via the secondary link.

[0183] In subsequent processes, the sending specifications of logical layer management packets that can be transmitted through the primary link all follow this rule. That is, if the local end has a high-speed transmission link and the high-speed transmission link is available, it is recommended to send the logical layer management packet through the high-speed transmission link. Otherwise, the logical layer management packet is sent through the auxiliary link.

[0184] 3) Device B receives the TSM, and the RX end of channel Z can start channel clock locking.

[0185] The RX of channel Z starts to execute channel clock lock. If the clock cannot be locked, the RX of channel Z is requested to switch to new swing parameters through CLFM.

[0186] 4) After device A receives the CLFM corresponding to the swing parameter of channel Z, it executes the following sequence.

[0187] Step 1: Adjust the swing parameters of the TX of channel Z based on the CLFM message instruction;

[0188] Step 2: Device A sends an ACK corresponding to CLFM to notify device B that the TX of channel Z has adjusted the swing parameters.

[0189] Note: To prevent loss of the ACK message corresponding to the CLFM, device A must reply with a corresponding ACK message each time it receives a CLFM message from device B. Furthermore, to ensure efficient message transmission, device A must reply with a corresponding ACK message over the auxiliary channel after receiving a duplicate CLFM message from device B. The EQFM, LLFM, LPRM, LWAM, LDAM, and ERR_RM messages described below all follow the same response mechanism and are not further detailed in the following examples.

[0190] 5) After receiving the ACK indicating that the swing parameters of channel Z have been adjusted, device B begins to re-evaluate the channel clock lock. If the parameters do not meet expectations, it requests new parameters through CLFM (same as process 4). If they meet expectations, it notifies device A through CLFM that the clock lock of channel Z has been successfully completed. After receiving the corresponding ACK, it begins the channel equalization process.

[0191] Note: To prevent CLFM message loss, each time device B sends CLFM, if it does not receive an ACK response message from device A within tCLFMAck, it needs to resend CLFM through the auxiliary channel. Resend CLFM for a maximum of LMP_MaxReSendTime (see the detailed description in the "Training Parameter Requirements" section). If no ACK response is received from device A after resending CLFM for LMP_MaxReSendTime, it is necessary to send ERR_RM to device A to report an LMP handshake exception. The EQFM, LLFM, LPRM, LWAM, LDAM, and ERR_RM messages mentioned below all follow the same LMP retransmission and handshake exception reporting mechanism, and will not be repeated in subsequent embodiments.

[0192] 6) After device A receives the CLFM indicating that the clock of channel Z is successfully locked, it means that the clock of channel Z is locked. Channel Z switches the code type to be sent. After the switch, it continues LLCF_TS1. Then device A feeds back the ACK corresponding to the CLFM to device B to the receiving end and starts the channel equalization process.

[0193] 7) Device B starts the channel equalization process after receiving the ACK corresponding to the CLFM indicating that the clock of channel Z is successfully locked.

[0194] 2. Channel balance.

[0195] (1) Introduction to the process

[0196] After the channel clock is locked, both the transmitter and receiver of the channel enter the channel equalization phase.

[0197] When performing channel equalization, the transmitter of the channel to be trained continuously sends LLCF_TS1. The receiver receives and detects LLCF_TS1, performs equalization training on the receiver of the channel, and evaluates the equalization training results.

[0198] To prevent the equalization training results on the receiving end from not meeting expectations, the sending end is recommended to provide 5 levels of adjustable FFE parameters.

[0199] Implementation Note: The "equalization training results meet expectations" mentioned here can be evaluated by various vendors through methods such as bit error detection and eye diagram measurement. It is sufficient to ensure that the bit error rate after equalization training is less than the protocol specification (10^-12).

[0200] If the receiving end of the channel detects 128-byte continuous LLCF_TS1 and the equalization training result meets the expectations, the equalization training of the channel is considered successful.

[0201] If equalization training for a channel on the receiving end fails, the transmitting end can request, through a logical layer management packet (EQFM), that the transmitting end adjust the FFE parameters for the corresponding channel and specify the desired adjustment level. Upon receiving the EQFM, the transmitting end completes the FFE update for the channel requiring FFE parameter adjustment and then sends an ACK corresponding to the EQFM to the receiving end. After detecting the ACK, the receiving end re-performs channel equalization training and LLCF_TS1 testing for the channel with adjusted FFE parameters.

[0202] If a channel still cannot be locked after traversing all FFE gears, the receiver needs to notify the transmitter through the logical layer management packet EQFM and indicate that the channel training has failed. After receiving the EQFM, the transmitter closes the channel (setting the corresponding channel state machine to the INIT state) and then feeds back the corresponding ACK of the EQFM to the receiver. After receiving the ACK, the receiver closes the channel (setting the corresponding channel state machine to the INIT state).

[0203] If equalization training succeeds on a channel at the receiving end, the receiving end notifies the transmitting end via the logical layer management packet EQFM, indicating the channel training success. Upon receiving the EQFM, the transmitting end switches the code pattern for the channel indicated in the EQFM. After switching, it continuously sends LLCF_TS2 and then sends an ACK corresponding to the EQFM to the receiving end. The transmitting end of the channel enters the channel lock phase. After the receiving end detects the ACK, the receiving end of the channel enters the channel lock phase.

[0204] If all channel equalization training on this link fails, the current rate training fails.

[0205] The detailed process of single-channel transmitter equalization is shown in Figure 10, which is a schematic diagram of the channel transmitter equalization process provided by this application.

[0206] The detailed process of single-channel receiving end equalization is shown in Figure 11, which is a schematic diagram of the channel receiving end equalization process provided by this application.

[0207] In Figure 11, after tSingleEQTimeout times out, the above process can be followed. After tTotalEQTimeout times out, it needs to be reported to the management adapter.

[0208] To enhance the channel's ability to recover quickly, the channel recovery phase (LNSM.recovery) also needs to support a mechanism in which the receiving end of the channel switches the transmitting end's FFE parameters based on EQFM.

[0209] Note: For the receiving end of the channel, the following implementation suggestions are made when executing the equalization process: ① The receiving end can poll multiple sets of FFE parameters of the transmitting end to achieve the optimal equalization effect; ② It is recommended that the receiving end save the adaptive parameters after successful equalization of each rate and store them in the non-volatile storage space of the device to facilitate rapid link establishment the next time.

[0210] (2) Example of port interaction process.

[0211] Here is an example of the balancing process for any channel. The channel is numbered Z, device A is the transmitting end of channel Z, device B is the receiving end of channel Z, device A and device B are directly connected to each other, and Figure 12 below shows the interaction information of their connected ports. Figure 12 is a schematic diagram of the channel balancing interaction process provided by this application.

[0212] Please refer to Figure 12. The specific process of channel equalization interaction is as follows:

[0213] 1) After device A receives the CLFM indicating that channel Z has completed clock lock and returns the corresponding ACK, the TX of channel Z begins the channel equalization process. During the equalization phase, the TX of channel Z continuously sends the link training sequence LLCF_TS1.

[0214] 2) After device B receives the ACK corresponding to the CLFM indicating that channel Z has completed clock lock, the RX of channel Z starts to perform equalization training and evaluates whether the equalization training meets expectations. If not, it requests channel Z through EQFM and the transmitter switches to new FFE parameters.

[0215] 3) After receiving the EQFM corresponding to the FFE parameter switching of channel Z, device A executes the following sequence:

[0216] Step 1: Adjust the FFE parameters of the TX of channel Z based on the EQFM message instruction;

[0217] Step 2: Device A sends an ACK corresponding to the EQFM to notify Device B that the TX of channel Z has adjusted the FFE parameters.

[0218] 4) After receiving the ACK indicating that the FFE parameters of channel Z have been adjusted, device B starts re-equalization and evaluates whether the equalization training meets expectations. If not, it requests new parameters through EQFM (same as process 3). If it meets expectations, it notifies device A through EQFM that equalization of channel Z has been successfully completed.

[0219] 5) After device A receives the EQFM indicating that channel Z is successfully equalized, channel Z switches the code pattern it sends, and continues for LLCF_TS2 after the switch. Then device A feeds back the ACK corresponding to the EQFM to device B to the receiving end, and starts the channel locking process.

[0220] 6) Device B starts the channel locking process after receiving the EQFM corresponding ACK indicating that channel Z is successfully equalized.

[0221] 3. Channel lock.

[0222] (1) Introduction to the process

[0223] The channel will enter channel lock mode in the following scenarios:

[0224] ① In the initial link establishment (normal link establishment) process, after the channel equalization training is completed, the channel lock phase begins.

[0225] ② In the initial link establishment (fast link establishment) process, after the channel initialization is completed, it enters the channel locking stage.

[0226] In this process, after the training channel is initialized, the channel transmitter continuously sends LLCF_TS2 packets. The transmitter then sends a logical layer management packet (TSM) to the receiver, indicating the channel numbers of all channels initiating channel locks in the TSM. After the receiver receives the TSM, the corresponding channel can begin channel locks.

[0227] ③. When the link is restored, it enters the channel locking phase.

[0228] In this embodiment, channel locking is mainly used to lock the data boundary of the channel.

[0229] During channel locking, the transmitter of the channel to be trained continuously sends LLCF_TS2. The receiver samples the received bit stream, matches it with the LLCF_TS2 pattern (a match is considered successful only if both the header and payload match), and identifies the start and end points of the LLCF_TS2. The receiver can be in three lock states: lost, aligned, and locked.

[0230] ①. Unlocked state: When the channel starts to lock, it is in this state by default. In this state, the RX end of the channel continuously receives and detects the bit stream and matches it with LLCF_TS2. Once the match is completed, the data boundary alignment is completed, the current boundary alignment position is recorded, and the alignment state is entered.

[0231] ②Aligned State: In this state, the RX end of the channel continuously receives and detects the bit stream according to the original boundary alignment position, and matches it with the LLCF_TS2. If it matches four consecutive LLCF_TS2 (a match is considered successful only if both the frame header and payload match), it jumps to the Locked State. If it cannot identify consecutive LLCF_TS2, it jumps back to the Lost Lock State.

[0232] ③. Locked state: The main link completes channel locking and adjustment of the boundary lock position is not allowed.

[0233] When the receiving end of the channel enters the locked state, the channel is considered to be locked successfully.

[0234] After each channel enters the channel lock process, the tLaneLockTimeout timeout must be enabled. If the channel RX can complete the channel lock within the tLaneLockTimeout time, the channel lock is considered successful. If the channel lock cannot be completed within the tLaneLockTimeout time, the channel lock is considered failed and the exception is reported to the software.

[0235] Whether the channel locking is successful or failed, it is considered that the single channel locking process is completed.

[0236] During the initial link establishment (normal link establishment) process, after all RX channels to be locked on the receiving end of this link complete the single channel locking process, the link receiving end needs to uniformly inform the link transmitting end through the logical layer management package LLFM (such as the third logical layer management package mentioned above), and indicate the channels that have been successfully locked and the channels that have failed to be locked. The RX channels that have successfully locked enter the multi-channel de-skew phase, and the RX channels that have failed to be locked need to be closed (the corresponding channel state machine needs to be set to the INIT state).

[0237] After the transmitter receives the LLFM, the TX of the channel corresponding to the successful channel lock enters the multi-channel de-skew phase, and the TX of the channel that fails to lock needs to be closed (the corresponding channel state machine needs to be set to the INIT state).

[0238] Note: During the initial link establishment (normal link establishment) process, the RX channel to be locked refers to the channel that is designated for link establishment at the beginning and has successfully completed the channel clock lock and channel equalization processes. (Channels that fail to lock the channel clock or channel equalization are not channels to be locked.)

[0239] During the initial link establishment (fast link establishment) process and link recovery, if any channel lock fails, the channel lock timeout is immediately reported through ERR_RM, and the link returns to the initial state.

[0240] 4. Multi-channel alignment.

[0241] The transmission delay of each channel varies to a certain extent. To ensure that the receiving end of the high-speed link can still correctly merge the high-speed data of multiple channels after experiencing different transmission delays, on a link in a certain direction, all channels that need to be trained or recovered must complete the channel locking process and then perform the multi-channel alignment process.

[0242] To facilitate compatibility with cable or circuit designs that have significant inter-channel delay variations, this protocol also provides a method for testing inter-channel delay variations. This protocol also offers user-selectable multi-channel alignment test modes and inter-channel skew adjustment.

[0243] Multi-channel alignment is divided into a normal mode (link layer inter-channel skew measurement indication skew_tst=0) and a test mode (link layer inter-channel skew measurement indication skew_tst=1).

[0244] Note: The inter-lane skew measurement indicator, skew_tst, indicates the multi-lane alignment mode for the port's transmitter. For example, skew_tst = 1 indicates test mode; in this mode, the port's transmitter sends LLCF_DST when performing lane alignment during link training. Another example, skew_tst = 0 indicates normal mode; in this mode, the port's transmitter sends LLCF_DS when performing lane alignment during link training. The skew_tst information is software-defined. This document introduces the skew_tst indicator for ease of presentation and does not elaborate further.

[0245] During the multi-lane alignment phase, if the current mode is normal, the transmitters of all lanes to be aligned simultaneously send an LLCF_DS. If the current mode is test, the transmitters of all lanes to be aligned simultaneously send an LLCF_DST.

[0246] During the multi-channel alignment phase, the receivers of all channels to be aligned must continuously detect LLCF_DS or LLCF_DST to determine whether the current multi-channel alignment mode is normal or test mode.

[0247] (a) Multi-channel alignment in normal mode.

[0248] In normal mode multi-lane alignment, after the link transmit termination completes channel lock, it immediately sends an LLCF_DS on the link where the LLFM indicates successful clock lock, and then starts sending high-speed service data on these channels.

[0249] During multi-channel alignment, after the receiver of the aligned channel completes channel locking, it continues to detect LLCF_DS or LLCF_DST within the tWaitDsTimeout time.

[0250] Note that during the multi-channel alignment phase, there are two scenarios for determining whether the receiving end has completed channel locking:

[0251] The first scenario: The peer end completes LLFM feedback.

[0252] The second scenario: the RX to be recovered at the local end detects 16 LLCF_TS2s in the RECOVERY.fast_lock phase of LSNM(RX).

[0253] The following description of the determination of whether the receiving end of the channel to be aligned completes channel locking during multi-channel alignment is the same as above and will not be repeated.

[0254] If LLCF_DS is detected, the receiving end may determine that the current alignment mode is the normal mode, perform multi-channel alignment based on LLCF_DS, and then start receiving high-speed service data.

[0255] Otherwise, follow the multi-lane alignment process for test mode (see below).

[0256] (2) Multi-channel alignment of test patterns.

[0257] If the peer device supports channel skew measurement, the software can enable the link layer inter-channel skew measurement indicator skew_tst before link training begins. If skew_tst = 1 during the multi-channel alignment phase, test mode multi-channel alignment will be performed. After the multi-channel alignment test is completed, the link establishment process ends and the link returns to the initial state.

[0258] During multi-lane alignment in test mode, upon receiving LLFM, the transmitters of all channels to be aligned immediately send one LLCF_DST + four LLCF_EIs, then stop sending data and wait for the peer end to provide a de-skew feedback message (DSFM) within the tDsTstTimeout time. Upon receiving the DSFM message from the peer end, the transmitter must report the test results to the software, which will initiate link retraining and specify the multi-lane alignment mode and transmitter skew adjustment information for the new link establishment during the link retraining. (Skew adjustment configuration is only possible if the transmitter supports multi-lane skew adjustment; see the inter-channel skew adjustment section below for details.)

[0259] During multi-channel alignment, after the receiver of the channel to be aligned completes channel lock, it continuously checks for LLCF_DS or LLCF_DST within the tWaitDsTimeout period. If the receiver detects LLCF_DST, it determines that the current alignment mode is test mode. The receiver performs multi-channel skew measurement based on LLCF_DST and feeds the test results back to the transmitter via DSFM.

[0260] The measurement method of multi-channel skew measurement is shown in FIG13 , which is a schematic diagram of the multi-channel skew measurement process provided in this application.

[0261] The multi-channel skew measurement method includes the following steps 1 to 5.

[0262] Step 1) On the TX channel of device A, simultaneously insert LLCF_DST on each lane where the skew value needs to be measured.

[0263] Step 2) Device B's Rx maintains a global relative delay timer (Glb_Relative_Delay). When any lane receives LLCF_DST, Glb_Relative_Delay is reset and timing starts. This continues until all lanes whose skew needs to be measured receive LLCF_DST or Glb_Relative_Delay >= tRxDsDetMaxTime (some lanes may not receive LLCF_DST due to anomalies). Each lane then converts the Glb_Relative_Delay duration into the corresponding number of bytes and latches it as its own Relative_Delay.

[0264] Step 3) After device B's Rx completes skew measurement (stops Glb_Relatvie_Delay timing), it needs to notify device A of the number of Relative_Delay bytes for each Lane through DSFM (i.e., DLY0 to 7 in DSFM; the Relative_Delay of the Lane that first receives LLCF_DST is 0).

[0265] Step 4) Device A's Tx receives the DSFM information, which can be used to subsequently adjust the deviation of each Lane sending LLCF_DS / LLCF_DST (adjustment is only possible if the local end supports it).

[0266] Step 5) If the local Tx does not receive DSFM within tDsTstTimeout after sending LLCF_DST, it is determined that the skew measurement has failed and the exception needs to be reported to the software.

[0267] (3) Inter-channel skew adjustment.

[0268] After completing multi-lane alignment in test mode and receiving DSFM feedback from the peer end, if the local TX device supports inter-lane skew adjustment, the software can calculate the appropriate number of delay bytes to match the local design based on the skew measurement value in DSFM (i.e., the relative delay information recorded in the DLY0-7 fields, denoted as Relative_Delays), and configure the data delay indicator LaneX_tx_data_dly for each lane. Link retraining is then initiated.

[0269] During subsequent link training or link recovery, in the multi-channel alignment stage at the transmitting end, it is necessary to send 1 LLCF_PAD + 1 LLCF_DS (or LLCF_DST) on each channel simultaneously to perform skew alignment or measurement between channels, where the length deviation value of the LLCF_PAD sent by each channel is the LaneX_tx_data_dly configured for the corresponding channel, see Figures 14 and 15 below, Figure 14 is a schematic diagram of the delay deviation before multi-channel skew adjustment provided in this application, and Figure 15 is a schematic diagram of the delay deviation after multi-channel skew adjustment provided in this application.

[0270] For Lanes with large Relative_Delay values, a shorter LLCF_PAD is sent, and for Lanes with small Relative_Delay values, a longer LLCF_PAD is sent.

[0271] The data delay indication of each lane, LaneX_tx_data_dly = the LLCF_PAD length to be inserted in each TX channel - the shortest length of LLCF_PAD = (maximum Relative_Delays bytes - Relative_Delays bytes of this Lane).

[0272] (4) Multi-channel alignment process.

[0273] After all TXs complete channel locking, they enter the TX channel alignment state. The process of TX executing channel alignment is shown in Figure 16 below. Figure 16 is a schematic diagram of the multi-channel alignment process of the transmitter provided in this application.

[0274] After RX completes channel locking, it enters the RX channel alignment state. The process of RX performing channel alignment is shown in Figure 17 below. Figure 17 is a schematic diagram of the receiving end multi-channel alignment process provided by this application.

[0275] (5) Port interaction process.

[0276] (V)-1. Multi-channel alignment in normal mode.

[0277] Device A and device B are directly connected to each other. Figure 18 below shows the interaction information of their connected ports. Figure 18 is a schematic diagram of the normal mode multi-channel alignment interaction provided by this application.

[0278] Please refer to Figure 18. The specific process of normal mode multi-channel alignment interaction is as follows:

[0279] 1) After all transmit terminals of the channels to be aligned on device A complete channel lock (LLFM is received), the TX terminals of all channels simultaneously send one LLCF_PAD and one LLCF_DS. Then, normal service data is sent.

[0280] Note: During multi-lane alignment during link training (link state machine is in training) and link recovery (link state machine is in recovery), the length of the LLCF_PAD (LLCF_PAD immediately before LLCF_DS) sent by different lanes can vary. The length deviation value is the LaneX_tx_data_dly configured by the software.

[0281] When the channel direction and link width are switched (the link state machine is in the HS state), the lengths of the LLCF_PADs (LLCF_PADs immediately preceding the LLCF_DS) sent by different channels cannot differ. The PADs sent by all channels are equal to cf_pad_length.

[0282] 2) If device B detects CF_DS, the receiver determines that the current alignment mode is normal and performs multi-channel alignment based on CF_DS. If an anomaly in multi-channel alignment is detected (the skew deviation of CF_DS between multiple channels is too large, or some channels cannot receive CF_DS), ERR_RM is used to feedback to device A that the current link receiver deskew is abnormal, and the link is rolled back to the initial state, awaiting retraining. If no anomaly in multi-channel alignment is detected, the service data is received and parsed normally.

[0283] 3) If device A receives ERR_RM feedback from device B indicating that there is an abnormality in the link receiving end deskew, it needs to report the abnormality, roll back to the initial state of the link, and initiate retraining (restart the link training process).

[0284] (V)-2. Multi-channel alignment of test patterns.

[0285] Device A and device B are directly connected to each other. Figure 19 below shows the interaction information of their connected ports. Figure 19 is a schematic diagram of the multi-channel alignment interaction in the test mode provided in this application.

[0286] The specific process of test mode multi-channel alignment interaction is as follows:

[0287] 1) After all transmit terminations of the channels to be aligned on device A complete channel lock (LLFM is received), the TX terminals of all channels simultaneously send one PAD and one LLCF_DST. They then send one LLCF_EI control frame.

[0288] The length deviation value of the PAD in different channels is LaneX_tx_data_dly configured by the software.

[0289] 2) If device B detects LLCF_DST, the receiver determines that the current alignment mode is test mode and performs an inter-channel skew test based on LLCF_DST. The receiver then feeds the test results back to device A via DSFM and returns the link to its initial state, awaiting software retraining. If no anomalies are detected in multi-channel alignment, service data is received and parsed normally.

[0290] 3) If device A receives the multi-channel skew feedback from device B through DSFM, it needs to report the test results to the software and roll back to the initial link state, waiting for the software to initiate retraining (restarting the link training process).

[0291] It is understandable that in order to implement the functions in the above embodiments, the first device and the second device include hardware structures and / or software modules corresponding to the execution of each function. It should be readily apparent to those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in hardware or in a computer software-driven hardware manner depends on the specific application scenario and design constraints of the technical solution.

[0292] The link training method provided according to this embodiment is described in detail above with reference to FIG. 1 to FIG. 19 . The link training device provided according to this embodiment will be described below with reference to FIG. 20 and FIG. 21 .

[0293] Figure 20 is a schematic diagram of the structure of a link training device provided in this application. The link training device 2000 can be used to implement the functions of the first device in the above-mentioned method embodiment, thereby also achieving the beneficial effects of the above-mentioned method embodiment. In this embodiment, the link training device 2000 can be the first device 110 shown in Figure 1, the set-top box shown in Figure 2, or the first device provided in subsequent embodiments. It should be understood that the link training device 2000 can also be a module (such as a chip) applied to any of the aforementioned devices.

[0294] As shown in Figure 20 , the link training device 2000 includes a startup module 2010, a receiving module 2020, and a processing module 2030. The startup module 2010, the receiving module 2020, and the processing module 2030 can collaboratively implement the various steps in the aforementioned method embodiment. A more detailed description of the startup module 2010, the receiving module 2020, and the processing module 2030 can be directly obtained by referring to the description of the first device in the method embodiment shown in the aforementioned figures, and is not repeated here.

[0295] Figure 21 is a second schematic diagram of the structure of a link training device provided in this application. This link training device 2100 can be used to implement the functions of the second device in the above-mentioned method embodiment, thereby also achieving the beneficial effects of the above-mentioned method embodiment. In this embodiment, the link training device 2100 can be the second device 120 shown in Figure 1, the display shown in Figure 2, or the second device provided in subsequent embodiments. It should be understood that the link training device 2100 can also be a module (such as a chip) applied to any of the aforementioned devices.

[0296] As shown in Figure 21 , the link training device 2100 includes a startup module 2110, a sending module 2120, and a receiving module 2130. The startup module 2110, the sending module 2120, and the receiving module 2130 can collaboratively implement the various steps in the aforementioned method embodiment. A more detailed description of the startup module 2110, the sending module 2120, and the receiving module 2130 can be directly obtained by referring to the description of the second device in the method embodiment shown in the aforementioned figures, and is not further elaborated here.

[0297] When the link training device implements the link training method shown in any of the aforementioned figures through software, the link training device and its various units may also be software modules. The link training method is implemented by a processor calling the software module. The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0298] It can be understood that the link training devices shown in Figures 20 and 21 are only examples provided in this embodiment. Depending on the different audio and video transmission processes, the link training device may include more or fewer units, and this application does not limit this.

[0299] When the link training device is implemented via hardware, the hardware may be implemented via a processor, a chip, or a chip system. The chip system includes one or more chips, each of which includes an interface circuit and a control circuit. The interface circuit is used to receive data from devices outside the chip and transmit it to the control circuit, or to send data from the control circuit to devices outside the chip. The control circuit and the interface circuit implement the method of any possible implementation method in the above-described embodiments via logic circuits or by executing code instructions. The beneficial effects can be found in the description of any aspect of the above-described embodiments and will not be elaborated upon here.

[0300] It is understood that the processor in the embodiments of the present application may be a CPU, or other general-purpose processor, digital signal processor (DSP), ASIC, FPGA or other programmable logic device, transistor logic device, hardware component or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0301] In addition, the link training device 2000 shown in Figure 20 or the link training device 2100 shown in Figure 21 can also be implemented through a communication device, as shown in Figure 22. Figure 22 is a structural diagram of the communication device provided in this application. The communication device 700 includes: a memory 710 and at least one processor 720. The processor 720 can implement the link training method provided in the above embodiment. The memory 710 is used to store software instructions corresponding to the above link training method.

[0302] As an optional implementation, in hardware, the communication device 700 may refer to a chip or chip system encapsulating one or more processors 720. For example, when the communication device 700 is used to implement the method steps in the above embodiments, the processor 720 included in the communication device 700 executes the steps of the first device or the second device in the above methods and their possible sub-steps. In an optional scenario, the communication device 700 may also include a communication interface 730, which may be used to transmit and receive data. For example, the communication interface 730 is used to receive audio data or transmit audio streams; the communication interface 730 may be implemented by an interface circuit included in the communication device 700. Therefore, in some examples, the communication interface 730 may also be referred to as the transceiver of the communication device. In this embodiment, the communication interface 730 supports wired connections using a unified multimedia interconnect interface (such as a UMI interface).

[0303] In an embodiment of the present application, the communication interface 730, the processor 720, and the memory 710 may be connected via a bus 740, which may be divided into an address bus, a data bus, a control bus, etc. The bus 740 may be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or other types of buses.

[0304] It is worth noting that the communication device 700 can also perform the functions of the link training device 2000 shown in Figure 20 and the link training device 2100 shown in Figure 21, which are not described here in detail.

[0305] The communication device 700 provided in this embodiment may be the above-mentioned set-top box, display, game controller, first device, second device, etc., or other devices with link training functions, and this application is not limited to this. For example, when the aforementioned communication device also has a link training function, the communication device 700 may refer to any of the aforementioned devices.

[0306] The method steps in the embodiments of the present application can also be implemented by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a network device or a terminal device. Of course, the processor and storage medium can also exist as discrete components in multimedia devices and communication devices.

[0307] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the process or function described in the embodiments of the present application is performed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instruction can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (SSD).

[0308] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A link training method, characterized in that, the method includes: Starting the link training process of the link, the link includes at least one channel; Receiving a first control frame, the first control frame includes a first training sequence; Locking the clocks of the at least one channel according to the first control frame, and sending a first logical layer management packet, the first logical layer management packet indicates that the clocks of the at least one channel are locked successfully; Receiving a second control frame, the second control frame includes a second training sequence, the second training sequence includes a pseudo-random sequence; Performing equalization training on the at least one channel according to the second control frame, and sending a second logical layer management packet, the second logical layer management packet indicates that the equalization training of the at least one channel is successful; Receiving a third control frame, the third control frame includes a third training sequence, the third training sequence includes a pseudo-random sequence, and the second training sequence and the third training sequence are different; Locking the data boundaries of the at least one channel according to the third control frame, and sending a third logical layer management packet, the third logical layer management packet indicates the channels in the at least one channel that are locked successfully and / or the channels that are locked unsuccessfully.

2. The method according to claim 1, characterized in that, the method further includes: Receiving a plurality of fourth control frames, the fourth control frame includes a data start identifier, and the data start identifier is used to mark the start of a new data transmission; Performing multi-channel alignment on the channels locked successfully according to the plurality of fourth control frames.

3. The method according to claim 2, characterized in that, The Hamming distance between the sequence included in the data start identifier and the pseudo-random sequence is greater than or equal to a distance threshold.

4. The method according to any one of claims 1-3, characterized in that, The pseudo-random sequence satisfies the pseudo-random binary sequence pattern.

5. The method according to any one of claims 1-4, characterized in that, The difference between the second training sequence and the third training sequence includes: the first bit of the second training sequence and the second bit of the third training sequence are inverted, and the position of the first bit in the second training sequence is the same as the position of the second bit in the third training sequence.

6. The method according to any one of claims 1-5, characterized in that, The first training sequence includes: one or more groups of 1 sequences of the first length, and one or more groups of 0 sequences of the second length; the 1 sequences of the first length and the 0 sequences of the second length are arranged at intervals.

7. The method according to claim 6, characterized in that, The first training sequence includes 0xAA.

8. The method according to any one of claims 1-7, characterized in that, Any one of the control frames includes: at least one frame header, and the frame header includes a frame type and a checksum.

9. The method according to claim 8, characterized in that, If any one of the control frames includes a plurality of frame headers, two or more of the plurality of frame headers are the same.

10. A link training method, characterized in that, the method includes: Start the link training process for the link, where the link includes at least one channel; Send a first control frame, where the first control frame includes a first training sequence; Receive a first logical layer management packet, where the first logical layer management packet indicates that the clock of the at least one channel is locked successfully; Send a second control frame, where the second control frame includes a second training sequence, and the second training sequence includes a pseudo-random sequence; Receive a second logical layer management packet, where the second logical layer management packet indicates that the equalization training of the at least one channel is successful; Send a third control frame, where the third control frame includes a third training sequence, the third training sequence includes a pseudo-random sequence, and the second training sequence and the third training sequence are different; Receive a third logical layer management packet, where the third logical layer management packet indicates the channels in the at least one channel that are locked successfully and / or the channels that are locked unsuccessfully.

11. The method according to claim 10, wherein, the method further includes: Send a plurality of fourth control frames to the channels that are locked successfully, where the fourth control frame includes a data start identifier, and the data start identifier is used to mark the start of a new data transmission.

12. The method according to claim 11, wherein, the Hamming distance between the sequence included in the data start identifier and the pseudo-random sequence is greater than or equal to a distance threshold.

13. The method according to any one of claims 10-12, wherein, the pseudo-random sequence satisfies the pseudo-random binary sequence pattern.

14. The method according to any one of claims 10-13, wherein, the difference between the second training sequence and the third training sequence includes: the first bit of the second training sequence and the second bit of the third training sequence are inverted, and the position of the first bit in the second training sequence is the same as the position of the second bit in the third training sequence.

15. The method according to any one of claims 10-14, wherein, the first training sequence includes: one or more groups of 1 sequences of a first length, and one or more groups of 0 sequences of a second length; the 1 sequences of the first length and the 0 sequences of the second length are arranged at intervals.

16. The method according to claim 15, wherein, the first training sequence includes 0xAA.

17. The method according to any one of claims 10-16, wherein, any one of the control frames includes: at least one frame header, and the frame header includes a frame type and a checksum.

18. The method according to claim 17, wherein, if any one of the control frames includes a plurality of frame headers, two or more of the plurality of frame headers are the same.

19. A link training device, wherein, it includes: A start module for starting the link training process for the link, where the link includes at least one channel; A receiving module for receiving a first control frame, where the first control frame includes a first training sequence; A processing module, configured to lock the clocks of the at least one channel according to the first control frame and send a first logical layer management packet, where the first logical layer management packet indicates that the clocks of the at least one channel are successfully locked; The receiving module is further configured to receive a second control frame, where the second control frame includes a second training sequence, and the second training sequence includes a pseudo-random sequence; The processing module is further configured to perform equalization training on the at least one channel according to the second control frame and send a second logical layer management packet, where the second logical layer management packet indicates that the equalization training of the at least one channel is successful; The receiving module is further configured to receive a third control frame, where the third control frame includes a third training sequence, the third training sequence includes a pseudo-random sequence, and the second training sequence and the third training sequence are different; The processing module is further configured to lock the data boundaries of the at least one channel according to the third control frame and send a third logical layer management packet, where the third logical layer management packet indicates the channels in the at least one channel that are successfully locked and / or the channels that are locked unsuccessfully.

20. A link training device Characterized in that It includes: A start module, configured to start the link training process of the link, where the link includes at least one channel; A sending module, configured to send a first control frame, where the first control frame includes a first training sequence; A receiving module, configured to receive a first logical layer management packet, where the first logical layer management packet indicates that the clocks of the at least one channel are successfully locked; The sending module is further configured to send a second control frame, where the second control frame includes a second training sequence, and the second training sequence includes a pseudo-random sequence; The receiving module is further configured to receive a second logical layer management packet, where the second logical layer management packet indicates that the equalization training of the at least one channel is successful; The sending module is further configured to send a third control frame, where the third control frame includes a third training sequence, the third training sequence includes a pseudo-random sequence, and the second training sequence and the third training sequence are different; The receiving module is further configured to receive a third logical layer management packet, where the third logical layer management packet indicates the channels in the at least one channel that are successfully locked and / or the channels that are locked unsuccessfully.

21. A communication device Characterized in that It includes: A transceiver and a processor; The processor is configured to start the link training process of the link, and the transceiver and the processor are configured to cooperate to execute the method according to any one of claims 1-9.

22. [Corrected according to Rule 91 on 04.01.2024] A communication device Characterized in that It includes: A transceiver and a processor; The processor is configured to start the link training process of the link, and the transceiver and the processor are configured to cooperate to execute the method according to any one of claims 10-18.

23. A readable storage medium Characterized in that The readable storage medium includes a computer program or instruction, and when the computer program or instruction runs on a computer, the computer executes the method according to any one of claims 1-9, or the method according to any one of claims 10-18.

24. A computer program product, characterized in that, the computer program product includes a computer program or instructions, and when the computer program or instructions are run on a computer, the computer executes the method described in any one of claims 1-9 or the method described in any one of claims 10-18.

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