Shift register unit and driving method therefor, and gate driving circuit and display apparatus

Abstract

Provided in the present disclosure are a shift register unit and a driving method therefor, and a gate driving circuit and a display apparatus. In the shift register unit provided in the present disclosure, a potential control sub-circuit is arranged between a second clock signal end and a second node. The potential control sub-circuit can control the potential of the second node under the control of the second clock signal end, so that the change amplitude of the potential difference between the second node and the second clock signal end is less than an amplitude threshold value. On this basis, when the second clock signal end changes to a low potential, the potential control sub-circuit can pull down the potential of the second node, so that the potential between the second node and a third node can be balanced. Therefore, current leakage from the third node to the second node can be prevented, thereby ensuring that an output sub-circuit is more stable when outputting a low potential of a second clock signal.

Description

Shift register unit and driving method thereof, gate driving circuit, and display device

[0001] This disclosure claims priority to Chinese patent application number 202311629495.X, filed on November 30, 2023, entitled “Gate drive circuit, display device, and gate drive method,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0003] A display device typically includes a gate driver circuit and multiple rows of pixels. The gate driver circuit enables progressive scanning of the rows of pixels. The gate driver circuit typically utilizes a gate driver on array (GOA) substrate. Using a GOA eliminates the need for integrated circuits related to scanning drivers, reducing the manufacturing cost of the gate driver circuit.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device.

[0006] A first aspect of the present disclosure provides a shift register unit, comprising:

[0007] a first control subcircuit, connected to the first node and the second node, respectively, and configured to control the potential of the first node and the potential of the second node under the control of the start signal terminal, the first clock signal terminal, and the first low-voltage power terminal;

[0008] a second control subcircuit, connected to the first node and the second node, respectively, and configured to control the connection and disconnection between the high-voltage power supply terminal and the second node under the control of the second clock signal terminal and the first node;

[0009] a switch sub-circuit, connected to the second node and the third node respectively, and configured to control the connection and disconnection of the second node and the third node under the control of the first low-voltage power supply terminal;

[0010] an output sub-circuit, connected to the first node, the third node, and the output terminal of the shift register unit, respectively, and configured to control the connection and disconnection between the high-voltage power supply terminal and the output terminal under the control of the first node, and to control the connection and disconnection between the second clock signal terminal and the output terminal under the control of the third node;

[0011] The potential control subcircuit is respectively connected to the second clock signal terminal and the second node, and is used to control the potential of the second node under the control of the second clock signal terminal so that the change amplitude of the potential difference between the second node and the second clock signal terminal is less than the amplitude threshold.

[0012] Optionally, the potential control subcircuit includes: a first capacitor, which is connected in series between the second clock signal terminal and the second node.

[0013] Optionally, the potential control subcircuit further includes: a first transistor;

[0014] The first capacitor and the first transistor are connected in series between the second clock signal terminal and the second node.

[0015] Optionally, a first electrode of the first transistor is connected to the second clock signal terminal, a second electrode of the first transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the second node.

[0016] Optionally, one end of the first capacitor is connected to the second clock signal end, the other end of the first capacitor is connected to the first electrode of the first transistor, and the second electrode of the first transistor is connected to the second node.

[0017] Optionally, the gate of the first transistor is connected to the first low voltage power supply terminal.

[0018] Optionally, the gate of the first transistor is connected to a second low-voltage power supply terminal, and a potential of the second low-voltage power supply terminal is lower than a potential of the first low-voltage power supply terminal.

[0019] Optionally, the gate of the first transistor is connected to the second clock signal terminal.

[0020] Optionally, the shift register unit includes at least one potential control sub-circuit connected in series between the first clock signal terminal and the second node.

[0021] Optionally, the second control subcircuit includes: a second transistor and a third transistor;

[0022] The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the high voltage power supply terminal, and the second electrode of the second transistor is connected to the first electrode of the third transistor;

[0023] A gate of the third transistor is connected to the second clock signal terminal, and a second electrode of the third transistor is connected to the second node.

[0024] Optionally, the first control subcircuit includes: a fourth transistor, a fifth transistor and a sixth transistor;

[0025] The gate of the fourth transistor is connected to the first clock signal terminal, the first electrode of the fourth transistor is connected to the start signal terminal, and the second electrode of the fourth transistor is connected to the second node;

[0026] The gate of the fifth transistor is connected to the first clock signal terminal, the first electrode of the fifth transistor is connected to the first node, and the second electrode of the fifth transistor is connected to the first low voltage power supply terminal;

[0027] A gate of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to the first clock signal terminal.

[0028] Optionally, the output sub-circuit includes: a seventh transistor, a second capacitor, an eighth transistor and a third capacitor;

[0029] The gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the high voltage power supply terminal, and the second electrode of the seventh transistor is connected to the output terminal;

[0030] One end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the high voltage power supply terminal;

[0031] The gate of the eighth transistor is connected to the third node, the first electrode of the eighth transistor is connected to the output terminal, and the second electrode of the eighth transistor is connected to the second clock signal terminal;

[0032] One end of the second capacitor is connected to the third node, and the other end of the second capacitor is connected to the output end.

[0033] Optionally, the switch sub-circuit includes: a ninth transistor;

[0034] The gate of the ninth transistor is connected to the first low voltage power supply terminal, the first electrode of the ninth transistor is connected to the second node, and the second electrode of the ninth transistor is connected to the third node.

[0035] Optionally, all transistors included in the shift register unit are P-type transistors.

[0036] Optionally, the transistors included in the shift register unit are all low temperature poly-silicon (LTPS) transistors.

[0037] Based on the same inventive concept, a second aspect of the present disclosure provides a method for driving a shift register unit, for driving the shift register unit provided in the first aspect, the method comprising:

[0038] During a first time period, the start-up signal terminal and the first clock signal terminal are at a first potential, the second clock signal terminal is at a second potential, the first control subcircuit controls the potentials of the first node and the second node to be both at the first potential, and the switch subcircuit connects the second node and the third node so that the potential of the third node is at the first potential, and the first potential is lower than the second potential;

[0039] In a second time period, the start signal terminal is at the first potential, the first clock signal terminal is at the second potential, the first control subcircuit controls the potential of the first node to be the second potential, and the output subcircuit outputs the potential of the second clock signal terminal to the output terminal;

[0040] Wherein, in the second time period, when the second clock signal terminal is at the first potential, the potential control subcircuit pulls down the potential of the second node.

[0041] Optionally, the method further includes:

[0042] In a third time period, the start signal terminal and the first clock signal terminal are both at the second potential, the potential of the first node is at the second potential, and the output sub-circuit outputs the potential of the second clock signal terminal to the output terminal;

[0043] Wherein, in the third time period, when the second clock signal terminal is at the first potential, the potential control subcircuit pulls down the potential of the second node.

[0044] Optionally, the method further includes:

[0045] In the fourth time period, the start signal terminal is the second potential, the first clock signal terminal is the first potential, the first control sub-circuit controls the potential of the first node to be the first potential, the second control sub-circuit controls the potential of the second node to be the second potential, the switch sub-circuit connects the second node and the third node, and the output sub-circuit outputs the second potential to the output terminal.

[0046] Based on the same inventive concept, the third aspect of the present disclosure provides a gate driving circuit, which includes: at least two cascaded shift register units as provided in the first aspect.

[0047] Based on the same inventive concept, the fourth aspect of the present disclosure provides a display device comprising a plurality of pixels and the gate driving circuit as described in the third aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] FIG1A is a circuit structure diagram of a shift register unit in some embodiments;

[0050] FIG1B is a driving timing diagram of a shift register unit in some embodiments;

[0051] FIG2A is a circuit structure diagram of a shift register unit according to an embodiment of the present disclosure;

[0052] FIG2B is a circuit structure diagram of a shift register unit according to an embodiment of the present disclosure in which a first transistor is added;

[0053] FIG2C is a circuit structure diagram of a gate driving circuit according to another embodiment of the present disclosure incorporating a first transistor;

[0054] 2D is a circuit structure diagram of a gate driving circuit according to an embodiment of the present disclosure in which the gate of the first transistor is connected to the second low-voltage power supply terminal;

[0055] 2E is a circuit structure diagram of a gate driving circuit in another embodiment of the present disclosure in which the gate of the first transistor is connected to the second low-voltage power supply terminal;

[0056] 2F is a circuit structure diagram of a gate driving circuit in an embodiment of the present disclosure in which the gate of the first transistor is connected to the second clock signal terminal;

[0057] 2G is a circuit structure diagram of a gate driving circuit in another embodiment of the present disclosure in which the gate of the first transistor is connected to the second clock signal terminal;

[0058] FIG2H is a driving timing diagram of a shift register unit according to an embodiment of the present disclosure;

[0059] FIG3 is a schematic diagram of a driving method of a shift register unit provided by an embodiment of the present disclosure;

[0060] FIG4 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure;

[0061] FIG5 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.

[0062] Description of the drawings:

[0063] 10. Gate drive circuit;

[0064] 20, pixels;

[0065] 200, shift register unit;

[0066] 210, first control subcircuit, T24, fourth transistor, T25, fifth transistor, T26, sixth transistor;

[0067] 220, second control subcircuit, T22, second transistor, T23, third transistor;

[0068] 230, switch subcircuit, T29, ninth transistor;

[0069] 240, output sub-circuit, C22, second capacitor, T27, seventh transistor, T28, eighth transistor, C23, third capacitor;

[0070] 250, potential control subcircuit, C21, first capacitor, T21, first transistor. DETAILED DESCRIPTION

[0071] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0072] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0073] In the description of the present disclosure, "A and / or B" may include the case of A alone, the case of B alone, or any of the cases of A and B, where A and B are only used for example, and may be any technical feature connected by "and / or" in the present disclosure.

[0074] Several signal terminals used in this disclosure are explained below:

[0075] VGH: High-voltage power supply terminal, also known as high-voltage signal terminal, i.e., high-voltage signal line, used to receive and provide high-voltage signals. For example, the voltage of the high-voltage signal can be around 7.5V.

[0076] VGL: a first low voltage power supply terminal, also called a first low voltage signal terminal, that is, a first low voltage signal line, used to receive and provide a first low voltage signal.

[0077] VGL2: A second low-voltage power supply terminal, also known as a second low-voltage signal terminal, or a second low-voltage signal line, used to receive and provide a second low-voltage signal with a voltage lower than the first low-voltage signal. For example, the voltage of the first low-voltage signal can be around -5V, while the voltage of the second low-voltage signal can be around -8V.

[0078] STV: Turn on signal terminal, also known as driving clock signal terminal, that is, driving clock signal line, used to receive and provide turn on signal, also known as driving clock signal.

[0079] CK: a first clock signal terminal, i.e., a first clock signal line, used to receive and provide a first clock signal.

[0080] CB: Second clock signal terminal, i.e., second clock signal line, used to receive and provide a second clock signal. The frequency of the second clock signal can be the same as the frequency of the first clock signal, and the period when the second clock signal is at the first potential does not overlap with the period when the first clock signal is at the first potential. The first potential is an effective potential and can be a lower potential relative to the second potential. That is, the first potential is a low potential and the second potential is a high potential.

[0081] As shown in Figure 1A, a traditional 8T2C shift register unit (also known as a GOA unit) is shown. 8T2C refers to eight transistors (T) and two capacitors (C). The corresponding driving timing of this scheme is shown in Figure 1B. Referring to Figure 1B, it can be seen that the driving process of this shift register unit is mainly divided into the following periods:

[0082] 1. Period t1: The start signal terminal STV is low, the first clock signal terminal CK is low, and transistors T11, T13, and T18 are turned on. At this point, nodes N11, N12, and N13 are written to a low level. Then, the first clock signal terminal CK goes high, transistor T12 turns on, and node N13 is set to a high level through the turned-on transistor T12. At this point, transistor T15 turns off, transistor T14 turns on, and output terminal OUT outputs the waveform of the second clock signal terminal CB.

[0083] 2. Period t2: The start signal terminal STV becomes high, but the first clock signal terminal CK remains high, and the potentials of nodes N11, N12, and N13 remain unchanged. Transistor T15 turns off, transistor T14 turns on, and the output terminal OUT continues to output the waveform of the second clock signal terminal CB.

[0084] 3. Period t3: The first clock signal terminal CK becomes low, and the high potential of the start signal terminal STV remains unchanged. At this time, transistors T11 and T18 are turned on, writing the high potential of the start signal terminal STV to nodes N11 and N12. Simultaneously, transistor T13 is turned on, and the low potential of the first low-voltage power supply terminal VGL is input to node N13, causing transistors T16 and T17 to turn on, also writing the high potential of the high-voltage power supply terminal VGH to nodes N11 and N12. At this time, transistor T14 is turned off, and transistor T15 is turned on. The high potential of the high-voltage power supply terminal VGH is output to the output terminal OUT through the turned-on transistor T15, causing the voltage at the output terminal OUT to be high.

[0085] In a display device, for example, in an organic light-emitting diode (OLED) display device, a LTPS transistor is generally used to form a GOA unit. Thus, the frame of the display device can be effectively reduced to achieve a narrow frame design. However, due to the large Ioff (cut-off current) of LTPS, during the t2 period, when the output terminal OUT outputs the waveform of the second clock signal terminal CB, when the potential of the second clock signal terminal CB is low, the low potential of the node N12 is continuously pulled high by the node N11. This is because under the bootstrap effect of the capacitor C12, the potential of the node N12 will be lower than the potential of the node N11, so the node N12 will continue to leak to the node N11 through the transistor T18, ultimately affecting the stability of the potential output by the output terminal OUT.

[0086] Based on the above-described situation, the present disclosure provides a shift register unit 200, also called a GOA unit. As shown in FIG2A , the shift register unit 200 includes:

[0087] The first control sub-circuit 210 is connected to the first node N21 and the second node N22, respectively, and is used to control the potentials of the first node N21 and the second node N22 under the control of the start signal terminal STV, the first clock signal terminal CK and the first low voltage power supply terminal VGL.

[0088] Optionally, the first control sub-circuit 210 can electrically connect the first low-voltage power supply terminal VGL to the first node N21 and electrically connect the start-up signal terminal STV to the second node N22 when the first clock signal terminal CK is at a first potential (e.g., a low potential). After the start-up signal terminal STV is electrically connected to the second node N22, if the start-up signal terminal STV is at the first potential, the first control sub-circuit 210 can further electrically connect the first clock signal terminal CK to the first node N21.

[0089] The second control sub-circuit 220 is connected to the first node N21 and the second node N22 respectively, and is used to control the connection and disconnection between the high-voltage power supply terminal VGH and the second node N22 under the control of the second clock signal terminal CB and the first node N21.

[0090] Optionally, the second control sub-circuit 220 may connect the high-voltage power supply terminal VGH to the second node N22 to increase the potential of the second node N22 when both the second clock signal terminal CB and the first node N21 are at the first potential. When either the second clock signal terminal CB or the first node N21 is at the second potential (e.g., a high potential), the path between the high-voltage power supply terminal VGH and the second node N22 is disconnected.

[0091] The switch sub-circuit 230 is connected to the second node N22 and the third node N23, respectively, and is used to control the on and off of the second node N22 and the third node N23 under the control of the first low voltage power supply terminal VGL.

[0092] Optionally, when the potential of the third node N23 is higher than the potential of the first low-voltage power supply terminal VGL, the switch sub-circuit 230 may, under the control of the first low-voltage power supply terminal VGL, conduct the second node N22 and the third node N23, i.e., the switch sub-circuit 230 is in the on state. When the potential of the third node N23 is lower than the potential of the first low-voltage power supply terminal VGL, the switch sub-circuit 230 may disconnect the path between the second node N22 and the third node N23, i.e., the switch sub-circuit 230 is in the off state.

[0093] The output sub-circuit 240 is respectively connected to the first node N21, the third node N23 and the output terminal OUT of the shift register unit, and is used to control the connection and disconnection of the high voltage power supply terminal VGH and the output terminal OUT under the control of the first node N21, and to control the connection and disconnection of the second clock signal terminal CB and the output terminal OUT under the control of the third node N23.

[0094] Optionally, when the first node N21 is at a first potential, the output sub-circuit 240 can connect the high-voltage power supply terminal VGH to the output terminal OUT, so that the output terminal OUT outputs the high potential of the high-voltage power supply terminal VGH. When the third node N23 is at a first potential, the output sub-circuit 240 can connect the second clock signal terminal CB to the output terminal OUT, so that the output terminal OUT outputs the waveform of the second clock signal terminal CB. In other words, the output terminal OUT outputs the second clock signal from the second clock signal terminal CB.

[0095] The potential control subcircuit 250 is connected to the second clock signal terminal CB and the second node N22 respectively, and is used to control the potential of the second node N22 under the control of the second clock signal terminal CB so that the change amplitude of the potential difference between the second node N22 and the second clock signal terminal CB is less than the amplitude threshold.

[0096] In other words, the potential control subcircuit 250 can prevent a sudden change in the potential difference between the second node N22 and the second clock signal terminal CB. Accordingly, after the potential of the second clock signal terminal CB changes from a high potential to a low potential, the potential control subcircuit 250 can also lower the potential of the second node N22 to ensure that the change in the potential difference between the two is small.

[0097] In some embodiments, as shown in FIG2A , the potential control subcircuit 250 includes:

[0098] The first capacitor C21 is connected in series between the second clock signal terminal CB and the second node N22.

[0099] It is understood that, during the process of outputting the waveform of the second clock signal terminal CB at the output terminal OUT, when the second clock signal terminal CB changes from a high potential to a low potential, the potential of the third node N23 is pulled down by the output sub-circuit 240. In the embodiment of the present disclosure, when the second clock signal provided by the second clock signal terminal CB changes from a high potential to a low potential, that is, when a low-voltage pulse appears in the second clock signal, the bootstrap effect of the first capacitor C21 (that is, the characteristic that the potential difference across the first capacitor C21 cannot change suddenly) can also pull down the potential of the second node N22. Thus, the potential difference between the second node N22 and the third node N23 can be ensured to be small, that is, the potential difference between the second node N22 and the third node N23 can always be maintained at a relatively stable level, thereby effectively preventing leakage of the switch sub-circuit 230 from affecting the stability of the potential output by the output terminal OUT.

[0100] In some embodiments, as shown in FIG2B , the potential control subcircuit 250 may further include:

[0101] The first transistor T21, the first capacitor C21, and the first transistor T21 can be connected in series between the second clock signal terminal CB and the second node N22. The series connection node between the first capacitor C21 and the first transistor T21 is a fourth node N24. When the second clock signal terminal CB is at a first potential (i.e., when a low-voltage pulse appears in the second clock signal), the first transistor T21 is in an on state.

[0102] The first capacitor C21 and the first transistor T21 are connected in series, which may mean that one of the first electrode and the second electrode of the first transistor T21 is connected to one end of the first capacitor C21, and the other of the first electrode and the second electrode of the first transistor T21 and the other end of the capacitor C21 are respectively connected to the second clock signal terminal CB and the second node N22.

[0103] One of the first electrode and the second electrode of the transistor is a source electrode, and the other is a drain electrode. For example, the first electrode can be a drain electrode, and the second electrode can be a source electrode.

[0104] Through the above solution, the potential of the second node N22 can be controlled by the cooperation of the first transistor T21 and the first capacitor C21. Furthermore, the addition of the first transistor T21 can further enhance the effect of lowering the potential of the second node N22, bringing the low potential of the second node N22 closer to the low potential of the third node N23. This allows the switch sub-circuit 230 to be more completely shut off, ensuring a more stable second clock signal output by the output sub-circuit 240.

[0105] As a possible series connection, as shown in FIG2B , the first electrode of the first transistor T21 is connected to the second clock signal terminal CB, the second electrode of the first transistor T21 is connected to one end of the first capacitor C21, and the other end of the first capacitor C21 is connected to the second node N22.

[0106] As another possible series connection method, as shown in Figure 2C, one end of the first capacitor C21 is connected to the second clock signal terminal CB, the other end of the first capacitor C21 is connected to the first electrode of the first transistor T21, and the second electrode of the first transistor T21 is connected to the second node N22.

[0107] It is understandable that the first capacitor C21 and the first transistor T21 are connected in series, and the specific arrangement order of the two can be selected according to actual needs, thereby adding multiple options for the arrangement and layout of the shift register unit 200.

[0108] In the embodiment of the present disclosure, the gate of the first transistor T21 may have various connection modes.

[0109] As a first possible connection mode, as shown in Figures 2B and 2C, the gate of the first transistor T21 is connected to the first low-voltage power supply terminal VGL. Accordingly, the first transistor T21 can maintain a normally open (i.e., normally on) state. The potential of the first low-voltage power supply terminal VGL connected to the gate of the first transistor T21 can be equal to the low potential of the second clock signal (i.e., the low voltage value during the low-voltage pulse).

[0110] As a second possible connection method, as shown in Figures 2D and 2E, the gate of the first transistor T21 is connected to the second low-voltage power supply terminal VGL2. Accordingly, the first transistor T21 can remain in a normally-on state. Moreover, because the potential of the second low-voltage power supply terminal VGL2 is lower than that of the first low-voltage power supply terminal VGL, after the potential of the second clock signal terminal CB jumps to a low potential, the first capacitor C21 can pull the second node N22 down to a lower potential through the conductive first transistor T21. This can make the low potential of the second node N22 closer to the low potential of the third node N23, thereby making the switch sub-circuit 230 shut down more completely, effectively avoiding the generation of leakage current. Accordingly, the waveform of the second clock signal terminal CB output by the output sub-circuit 240 can be more stable.

[0111] As a third possible connection method, as shown in Figures 2F and 2G, the gate of the first transistor T21 can be directly connected to the second clock signal terminal CB. Based on this connection method, the first transistor T21 is turned on when the second clock signal terminal CB is at a low potential, so that the first capacitor C21 pulls down the potential of the second node N22 through a bootstrap effect.

[0112] In the third connection mode, since the gate and the first electrode (or the second electrode) of the first transistor T21 are both connected to the second clock signal terminal CB, the connection lines can be effectively saved and the structure and wiring complexity of the shift register unit 200 can be avoided from being increased.

[0113] In some embodiments, as shown in FIG. 2A to FIG. 2G , the second control sub-circuit 220 includes a second transistor T22 and a third transistor T23 .

[0114] The gate of the second transistor T22 is connected to the first node N21 , the first electrode of the second transistor T22 is connected to the high voltage power supply terminal VGH, and the second electrode of the second transistor T22 is connected to the first electrode of the third transistor T23 .

[0115] A gate of the third transistor T23 is connected to the second clock signal terminal CB, and a second electrode of the third transistor T23 is connected to the second node N22.

[0116] It can be understood that when the first node N21 is at the first potential, the second transistor T22 is turned on, thereby writing the potential of the high-voltage power supply terminal VGH to the first electrode of the third transistor T23. When the second clock signal terminal CB is at the first potential, the third transistor T23 is turned on, thereby writing the potential of the high-voltage power supply terminal VGH to the second node N22.

[0117] In some embodiments, as shown in FIG. 2A to FIG. 2G , the first control sub-circuit 210 includes:

[0118] The fourth transistor T24 has a gate connected to the first clock signal terminal CK, a first electrode connected to the start signal terminal STV, and a second electrode connected to the second node N22.

[0119] The fifth transistor T25 has a gate connected to the first clock signal terminal CK, a first electrode connected to the first node N21, and a second electrode connected to the first low voltage power supply terminal VGL.

[0120] The sixth transistor T26 has a gate connected to the second node N22, a first electrode connected to the first node N21, and a second electrode connected to the first clock signal terminal CK.

[0121] It can be understood that when the first clock signal terminal CK is at the first potential, the fourth transistor T24 and the fifth transistor T25 are turned on. At this point, the first low-voltage power supply terminal VGL can write the first potential (i.e., a low potential) to the first node N21, and the start signal terminal STV writes its potential to the second node N22. If the start signal terminal STV is at the first potential, the sixth transistor T26 is turned on, thereby writing the potential of the first clock signal terminal CK to the first node N21.

[0122] In some embodiments, with continued reference to FIG. 2A to FIG. 2G , the output sub-circuit 240 includes two parts:

[0123] The first part includes: a seventh transistor T27 and a second capacitor C22, wherein the gate of the seventh transistor T27 is connected to the first node N21, the first electrode is connected to the high voltage power supply terminal VGH, and the second electrode is connected to the output terminal OUT.

[0124] One end of the second capacitor C22 is connected to the first node N21 , and the other end is connected to the high voltage power supply terminal VGH.

[0125] The second part includes: an eighth transistor T28 and a third capacitor C23, wherein the eighth transistor T28 has a gate connected to the third node N23, a first electrode connected to the output terminal OUT, and a second electrode connected to the second clock signal terminal CB.

[0126] One end of the third capacitor C23 is connected to the third node N23, and the other end is connected to the output terminal OUT.

[0127] It can be understood that when the first node N21 is at the first potential, the seventh transistor T27 is turned on, and the high voltage power supply terminal VGH can output a high potential to the output terminal OUT. When the third node N23 is at the first potential, the eighth transistor T28 is turned on, and the second clock signal terminal CB can output the second clock signal to the output terminal OUT.

[0128] It is understood that when the potential of the second clock signal terminal CB (i.e., the potential of the second clock signal) changes from a high potential to a low potential, the bootstrap effect of the third capacitor C23 can further lower the potential of the third node N23. When the potential of the third node N23 is lower than the potential of the first low-voltage power supply terminal VGL, the switch sub-circuit 230 disconnects the path between the second node N22 and the third node N23, i.e., the switch sub-circuit 230 is in the off state.

[0129] In some embodiments, with continued reference to FIG. 2A to FIG. 2G , the switch sub-circuit 230 may include a ninth transistor T29 , whose gate is connected to the first low voltage power supply terminal VGL, whose first electrode is connected to the second node N22 , and whose second electrode is connected to the third node N23 .

[0130] It is understood that the ninth transistor T29 can remain normally on under the control of the low potential provided by the first low-voltage power supply terminal VGL. However, when the potential of the third node N23 is lower than the potential of the first low-voltage power supply terminal VGL, the ninth transistor T29 can be turned off. This prevents the potential of the second node N22 from affecting the potential of the third node N23. Alternatively, it can be understood that it is used to prevent the bootstrap voltage generated by the third node N23 from leaking to the second node N22.

[0131] The working process of the shift register unit 200 in each time period is described in detail below based on FIG. 2H :

[0132] During the first time period t1, the start signal provided by the start signal terminal STV is at the first potential, and the first clock signal provided by the first signal terminal CK is at the first potential. That is, both the start signal terminal STV and the first signal terminal CK are at a low potential. At this time, the fourth transistor T24 and the fifth transistor T25 are turned on. The low potential of the start signal is written to the second node N22 via the fourth transistor T24. The switch sub-circuit 230 (e.g., the ninth transistor T29) is turned on, and the low potential of the start signal is then written to the third node N23 via the fourth transistor T24 and the switch sub-circuit 230. Simultaneously, the first low voltage signal from the first low voltage power supply terminal VGL is written to the first node N21 via the fifth transistor T25.

[0133] During the second time period t2, the start signal provided by the start signal terminal STV continues to maintain the first potential, and the first clock signal provided by the first signal terminal CK changes to the second potential (i.e., a high potential). At this time, the sixth transistor T26 turns on and writes the second potential of the first clock signal to the first node N21, i.e., the potential of the first node N21 is set to a high potential. At this time, the seventh transistor T27 turns off, and the eighth transistor T28 turns on, and the output terminal OUT of the output sub-circuit 240 outputs the second clock signal from the second clock signal terminal CB.

[0134] During the third time period t3, the start signal provided by the start signal terminal STV is at the second potential. At this time, the first clock signal provided by the first signal terminal CK is also at the second potential. Therefore, the second node N22 and the third node N23 maintain the first potential, the first node N21 maintains the second potential, the eighth transistor T28 remains on, and the output terminal OUT of the output sub-circuit 240 continues to output the second clock signal.

[0135] As can be seen from FIG. 2H , between the second time period t2 and the third time period t3, the start signal provided by the start signal terminal STV and the first clock signal provided by the first signal terminal CK are both at the first potential. The operating principle of the shift register unit during this period is the same as that of the first time period t1 and will not be further described here. In other words, the shift register unit can sequentially perform the operations of the first time period t1, the second time period t2, and the first time period t1 before performing the operations of the third time period t3.

[0136] In the second time period t2 and the third time period t3, when the second clock signal provided by the second clock signal terminal CB is at the first potential (i.e., a low-voltage pulse), the potential control subcircuit 250 can further lower the first potential of the second node N22. For example, the first potential of the second node N22 can be further lowered by the bootstrap effect of the first capacitor C21 in the potential control subcircuit 250. As a result, the potential difference between the second node N22 and the third node N23 can be made less than the potential difference threshold, so that the third node N23 does not leak electricity to the second node N22, and the second clock signal output by the output terminal OUT can be relatively stable.

[0137] During the fourth time period t4, the start signal provided by the start signal terminal STV reaches the second potential, and the first clock signal changes to the first potential. At this point, the fourth transistor T24 and the ninth transistor T29 are turned on, writing the second potential of the start signal to the second node N22 and the third node N23, causing the eighth transistor T28 to turn off. Simultaneously, the fifth transistor T25 is turned on, and the first potential of the first low-voltage power supply terminal VGL is input to the first node N21, causing the seventh transistor T27 to turn on. The second potential of the high-voltage power supply terminal VGH is then output to the output terminal OUT of the output sub-circuit 240 via the seventh transistor T27, setting the potential of the output terminal OUT of the output sub-circuit 240 to a high potential.

[0138] Through the above solution, the potential control subcircuit 250 is connected between the second clock signal terminal CB and the second node N22. Thus, when the second clock signal at the second clock signal terminal CB is at the first potential, i.e., a low-voltage pulse, the potential control subcircuit 250 is used to further lower the potential of the second node N22. This allows the potential difference between the second node N22 and the third node N23 to be less than the potential difference threshold, thereby balancing the potentials between the second node N22 and the third node N23 and preventing leakage from the third node N23 to the second node N22. Accordingly, the switch subcircuit 230 can be more completely shut off, effectively blocking the bootstrap voltage of the third node N23. This also ensures that the voltage at the output terminal OUT of the output subcircuit 240 is more stable when outputting the low-voltage pulse of the second clock signal, further improving the stability of the shift register unit 200.

[0139] Based on the above analysis, it can be seen that the potential control subcircuit 250 plays a very critical role. When the potential of the third node N23 is pulled down to a potential lower than that of the second node N22 by the bootstrap effect, it can promptly lower the potential of the second node N22. As a result, the potential difference between the second node N22 and the third node N23 can be maintained at a relatively stable level when the potential is low, that is, the potential difference is less than the potential difference threshold. In other words, the low potentials of the second node N22 and the third node N23 are similar, preventing leakage from the third node N23 to the second node N22.

[0140] In some embodiments, the number of potential control sub-circuits 250 disposed between the second clock signal terminal CB and the second node N22 in the shift register unit may be at least one. That is, the shift register unit may include one potential control sub-circuit 250 disposed between the second clock signal terminal CB and the second node N22, or may include multiple potential control sub-circuits 250 connected in series between the second clock signal terminal CB and the second node N22.

[0141] In order to further improve the potential lowering effect, a plurality of potential control sub-circuits 250 may be provided for the shift register unit. The specific number of potential control sub-circuits 250 may be selected according to actual needs and is not specifically limited here.

[0142] In addition, the transistors in the shift register unit 200 provided in the embodiment of the present disclosure can all be P-type transistors. For example, the transistors in the shift register unit 200 can all be field-effect transistors. Alternatively, the transistors in the shift register unit 200 can all be LTPS transistors.

[0143] Based on the same inventive concept, the present disclosure provides a driving method for the shift register unit described in the above embodiment. As shown in FIG3 , the method includes:

[0144] Step 301: In the first time period, the start signal terminal and the first clock signal terminal are at the first potential, the second clock signal terminal is at the second potential, the first control subcircuit controls the potential of the first node and the potential of the second node to be the first potential, and the switch subcircuit connects the second node and the third node to make the potential of the third node the first potential.

[0145] Referring to Figure 2H , the start signal provided at the start signal terminal STV is at a first potential, and the first clock signal provided at the first signal terminal CK is at a first potential. That is, both the start signal terminal STV and the first signal terminal CK are at a low potential. At this point, the fourth transistor T24 and the fifth transistor T25 are turned on. The low potential of the start signal is written to the second node N22 via the fourth transistor T24. The switch sub-circuit 230 (e.g., the ninth transistor T29) is turned on, and the low potential of the start signal is then written to the third node N23 via the fourth transistor T24 and the switch sub-circuit 230. Simultaneously, the first low voltage signal from the first low-voltage power supply terminal VGL is written to the first node N21 via the fifth transistor T25.

[0146] Step 302: In the second time period, the start signal terminal is at the first potential, the first clock signal terminal is at the second potential, the first control subcircuit controls the potential of the first node to be the second potential, and the output subcircuit outputs the potential of the second clock signal terminal to the output terminal. When the second clock signal terminal is at the first potential, the potential control subcircuit pulls down the potential of the second node.

[0147] Referring to FIG. 2H , during a second time period t2, the start signal provided by the start signal terminal STV continues to maintain the first potential, and the first clock signal provided by the first signal terminal CK changes to the second potential (i.e., a high potential). At this time, the sixth transistor T26 turns on and writes the second potential of the first clock signal to the first node N21, turning off the seventh transistor T27. Furthermore, since the third node N23 remains at the first potential, the eighth transistor T28 turns on, and the output terminal OUT outputs the second clock signal from the second clock signal terminal CB.

[0148] When the second clock signal provided by the second clock signal terminal CB jumps from the second potential to the first potential (i.e., a low-voltage pulse), the bootstrap effect of the third capacitor C23 further lowers the potential of the third node N23. Simultaneously, the potential control subcircuit 250 can also further lower the potential of the second node N22. Thus, the potential difference between the second node N22 and the third node N23 can be made less than the potential difference threshold, thereby ensuring that the ninth transistor T29 in the switch subcircuit 230 is more completely turned off. This prevents the third node N23 from leaking electricity to the second node N22, i.e., the ninth transistor T29 does not generate leakage current, thereby making the second clock signal output by the output terminal OUT more stable.

[0149] Step 303, in the third time period, the start signal terminal and the first clock signal terminal are both at the second potential, the potential of the first node is the second potential, the output sub-circuit outputs the potential of the second clock signal terminal to the output terminal, and when the second clock signal terminal is at the first potential, the potential control sub-circuit pulls down the potential of the second node.

[0150] Continuing with FIG. 2H , during a third time period t3, the start signal provided by the start signal terminal STV is at the second potential. At this time, the first clock signal provided by the first signal terminal CK is also at the second potential. Therefore, the second node N22 and the third node N23 maintain the first potential, while the first node N21 maintains the second potential. Accordingly, the seventh transistor T27 remains off, the eighth transistor T28 remains on, and the output terminal OUT continues to output the second clock signal.

[0151] As described in step 302 above, when the second clock signal provided by the second clock signal terminal CB is at the first potential, the bootstrap effect of the third capacitor C23 further lowers the potential of the third node N23. Simultaneously, the potential control subcircuit 250 can also further lower the potential of the second node N22. This reduces the potential difference between the second node N22 and the third node N23 to less than the potential difference threshold, thereby making the second clock signal output by the output terminal OUT relatively stable.

[0152] Step 304, in the fourth time period, the start signal terminal is at the second potential, the first clock signal terminal is at the first potential, the first control subcircuit controls the potential of the first node to be the first potential, the second control subcircuit controls the potential of the second node to be the second potential, the switch subcircuit connects the second node and the third node, and the output subcircuit outputs the second potential to the output terminal.

[0153] Continuing with FIG. 2H , during the fourth time period t4, the start signal provided by the start signal terminal STV is at the second potential, and the first clock signal is at the first potential. At this point, the fourth transistor T24 and the ninth transistor T29 are turned on, writing the second potential of the start signal to the second node N22 and the third node N23, causing the eighth transistor T28 to turn off. Simultaneously, the fifth transistor T25 is turned on, and the first potential of the first low-voltage power supply terminal VGL is input to the first node N21, causing the seventh transistor T27 to turn on. The second potential of the high-voltage power supply terminal VGH is then output via the seventh transistor T27 to the output terminal OUT of the output sub-circuit 240, setting the potential of the output terminal OUT of the output sub-circuit 240 to a high potential.

[0154] With the above solution, when the output sub-circuit outputs the low-voltage pulse of the second clock signal at the second clock signal terminal CB, the potential control sub-circuit further lowers the potential of the second node N22, so that the potential difference between the low potential of the second node and the low potential of the third node is less than the potential difference threshold. Consequently, the voltages between the second and third nodes are balanced, preventing leakage from the third node to the second node. This ensures more complete shutdown of the switch sub-circuit and better blocks the bootstrap voltage of the third node. Furthermore, the potential of the output sub-circuit is more stable when outputting the low-voltage pulse of the second clock signal, further improving the stability of the shift register unit.

[0155] The method of the above embodiment is applied to the corresponding shift register unit in any of the above embodiments, and has the beneficial effects of the corresponding shift register unit embodiment, which will not be described in detail here.

[0156] Based on the same inventive concept, embodiments of the present disclosure provide a gate drive circuit. As shown in FIG4 , the gate drive circuit includes at least two cascaded shift register units 200 as described in the above embodiments. This gate drive circuit has the same technical effects as the shift register units 200 described in the above embodiments, and will not be further described here.

[0157] Based on the same inventive concept, the presently disclosed embodiments provide a display device. As shown in FIG5 , the display device includes the gate drive circuit 10 described in the above embodiments, and a plurality of pixels 20. The gate drive circuit 10 is connected to the plurality of pixels 20 and is configured to transmit a gate drive signal to the plurality of pixels 20 to drive the plurality of pixels 20 to emit light. The display device has the same technical effects as the shift register unit 200 described in the above embodiments, and therefore will not be further described here.

[0158] Optionally, the plurality of pixels 20 in the display device may all be OLEDs, that is, the display device may be an OLED display device.

[0159] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may also be combined, and there are many other variations of different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0160] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

[0161] In the description of the present disclosure, reference to the terms "one embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present disclosure and features of different embodiments or examples without contradiction.

Claims

1. A shift register unit, comprising: A first control subcircuit, connected to the first node and the second node respectively, and used to control the potential of the first node and the potential of the second node under the control of the start signal terminal, the first clock signal terminal and the first low voltage power terminal; A second control subcircuit, connected to the first node and the second node respectively, and used to control the connection and disconnection between the high voltage power supply terminal and the second node under the control of the second clock signal terminal and the first node; a switch subcircuit, connected to the second node and the third node respectively, and used to control the on and off of the second node and the third node under the control of the first low-voltage power supply terminal; an output subcircuit, connected to the first node, the third node and the output end of the shift register unit respectively, and used to control the on-off of the high voltage power supply end and the output end under the control of the first node, and to control the on-off of the second clock signal end and the output end under the control of the third node; The potential control subcircuit is respectively connected to the second clock signal terminal and the second node, and is used to control the potential of the second node under the control of the second clock signal terminal so that the change amplitude of the potential difference between the second node and the second clock signal terminal is less than the amplitude threshold.

2. The shift register unit according to claim 1, wherein: The potential control subcircuit comprises: A first capacitor is connected in series between the second clock signal terminal and the second node.

3. The shift register unit according to claim 2, wherein: The potential control subcircuit further includes: a first transistor; The first capacitor and the first transistor are connected in series between the second clock signal terminal and the second node.

4. The shift register unit according to claim 3, wherein: A first electrode of the first transistor is connected to the second clock signal terminal, a second electrode of the first transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the second node.

5. The shift register unit according to claim 3, wherein: One end of the first capacitor is connected to the second clock signal end, the other end of the first capacitor is connected to the first electrode of the first transistor, and the second electrode of the first transistor is connected to the second node.

6. The shift register unit according to any one of claims 3 to 5, wherein: The gate of the first transistor is connected to the first low voltage power supply terminal.

7. The shift register unit according to any one of claims 3 to 5, wherein: The gate of the first transistor is connected to a second low voltage power supply terminal, and a potential of the second low voltage power supply terminal is lower than a potential of the first low voltage power supply terminal.

8. The shift register unit according to any one of claims 3 to 5, wherein: A gate of the first transistor is connected to the second clock signal terminal.

9. The shift register unit according to any one of claims 1 to 8, wherein: The shift register unit includes at least one potential control subcircuit connected in series between the first clock signal terminal and the second node.

10. The shift register unit according to any one of claims 1 to 9, wherein: The second control subcircuit includes: a second transistor and a third transistor; The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the high voltage power supply terminal, and the second electrode of the second transistor is connected to the first electrode of the third transistor; A gate of the third transistor is connected to the second clock signal terminal, and a second electrode of the third transistor is connected to the second node.

11. The shift register unit according to any one of claims 1 to 10, wherein: The first control subcircuit includes: a fourth transistor, a fifth transistor and a sixth transistor; The gate of the fourth transistor is connected to the first clock signal terminal, the first electrode of the fourth transistor is connected to the start signal terminal, and the second electrode of the fourth transistor is connected to the second node; The gate of the fifth transistor is connected to the first clock signal terminal, the first electrode of the fifth transistor is connected to the first node, and the second electrode of the fifth transistor is connected to the first low voltage power supply terminal; A gate of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to the first clock signal terminal.

12. The shift register unit according to any one of claims 1 to 11, wherein: The output subcircuit comprises: a seventh transistor, a second capacitor, an eighth transistor and a third capacitor; The gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the high voltage power supply terminal, and the second electrode of the seventh transistor is connected to the output terminal; One end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the high voltage power supply terminal; The gate of the eighth transistor is connected to the third node, the first electrode of the eighth transistor is connected to the output terminal, and the second electrode of the eighth transistor is connected to the second clock signal terminal; One end of the second capacitor is connected to the third node, and the other end of the second capacitor is connected to the output end.

13. The shift register unit according to any one of claims 1 to 12, wherein: The switch subcircuit comprises: a ninth transistor; A gate of the ninth transistor is connected to the first low voltage power supply terminal, a first electrode of the ninth transistor is connected to the second node, and a second electrode of the ninth transistor is connected to the third node.

14. The shift register unit according to any one of claims 3 to 13, wherein: The transistors included in the shift register unit are all P-type transistors.

15. The shift register unit according to any one of claims 3 to 14, wherein: The transistors included in the shift register unit are all low temperature polysilicon LTPS transistors.

16. A driving method of a shift register unit, the shift register unit comprising a first control subcircuit, a second control subcircuit, a switch subcircuit, an output subcircuit and a potential control subcircuit, the method comprising: In a first time period, the start signal terminal and the first clock signal terminal are at a first potential, the second clock signal terminal is at a second potential, the first control subcircuit controls the potential of the first node and the potential of the second node to be the first potential, and the switch subcircuit conducts the second node and the third node so that the potential of the third node is the first potential, wherein the first potential is a lower potential than the second potential; In a second time period, the start signal terminal is at the first potential, the first clock signal terminal is at the second potential, the first control subcircuit controls the potential of the first node to be the second potential, and the output subcircuit outputs the potential of the second clock signal terminal to the output terminal; Wherein, in the second time period, when the second clock signal end is at the first potential, the potential control subcircuit pulls down the potential of the second node.

17. The method according to claim 16, wherein: The method further comprises: In a third time period, the start signal terminal and the first clock signal terminal are both at the second potential, the potential of the first node is at the second potential, and the output subcircuit outputs the potential of the second clock signal terminal to the output terminal; Wherein, in the third time period, when the second clock signal terminal is at the first potential, the potential control subcircuit pulls down the potential of the second node.

18. The method according to claim 16 or 17, wherein: The method further comprises: In a fourth time period, the start signal terminal is the second potential, the first clock signal terminal is the first potential, the first control subcircuit controls the potential of the first node to be the first potential, the second control subcircuit controls the potential of the second node to be the second potential, the switch subcircuit connects the second node and the third node, and the output subcircuit outputs the second potential to the output terminal.

19. A gate driving circuit, the gate driving circuit comprising: At least two cascaded shift register units according to any one of claims 1 to 15.

20. A display device, comprising: A plurality of pixels, and a gate driving circuit as claimed in claim 19; The gate driving circuit is connected to the plurality of pixels and is used to transmit a gate driving signal to the plurality of pixels. To drive the multiple pixels to emit light.

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