Array substrate, display panel, and display device

Abstract

An array substrate, comprising a base, a plurality of pixel circuits, a first conductive layer, and a second conductive layer. The plurality of pixel circuits are arranged on the base, and the plurality of pixel circuits are arranged in multiple rows and multiple columns. The first conductive layer comprises a plurality of conductive patterns, the plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and each conductive pattern comprises at least two contact parts which are spaced apart. The second conductive layer is arranged on the side of the first conductive layer distant from the base. The second conductive layer comprises a plurality of first signal lines, and the plurality of first signal lines are spaced apart in a first direction and all extend in a second direction. One first signal line is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact parts of the conductive pattern.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311635363.8, filed on November 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0003] Organic Light-Emitting Diode (OLED) display panels have gradually become one of the mainstream products in the display field due to their excellent performance, such as self-luminescence, no need for backlight, high contrast, thin thickness, wide viewing angle, fast response speed, application in flexible panels, wide operating temperature range, simple structure and process. OLED display panels can be widely used in terminal products such as smartphones, tablets, TVs and wearable devices (such as watches).

[0004] OLED display panels consist of an array substrate and light-emitting devices mounted on it. The array substrate also includes multiple signal lines, which transmit control signals to the array substrate to drive the display panel for image display. Preventing static electricity buildup on these signal lines is a pressing technical issue in display panels.

[0005] Summary of the Invention

[0006] On the one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of pixel circuits, a first conductive layer, and a second conductive layer. The plurality of pixel circuits are provided on the substrate, and the plurality of pixel circuits are arranged in multiple rows and columns. The first conductive layer includes multiple conductive patterns, the multiple conductive patterns are spaced apart from the multiple pixel circuits, and the pixel circuits include at least two contact portions spaced apart. The second conductive layer is provided on a side of the first conductive layer away from the substrate. The second conductive layer includes multiple first signal lines, the multiple first signal lines are spaced apart along a first direction and all extend along a second direction; one first signal line is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact portions of the conductive pattern. The first direction is the row direction in which the multiple pixel circuits are arranged, and the second direction is the column direction in which the multiple pixel circuits are arranged.

[0007] In some embodiments, the first conductive layer further comprises a plurality of first connecting lines, the plurality of first connecting lines being arranged at intervals along the second direction and extending along the first direction. The second conductive layer further comprises a plurality of data lines, one data line being electrically connected to a column of pixel circuits; the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being respectively located on either side of the plurality of second data lines; and one first data line being connected to one first connecting line. The plurality of first signal lines comprising a plurality of fan-out lines, one fan-out line being electrically connected to one first connecting line. The plurality of conductive patterns comprising a plurality of first conductive patterns, the fan-out line being electrically connected to at least one first conductive pattern.

[0008] In some embodiments, the fan-out line includes a plurality of fan-out sub-lines spaced apart along the second direction, and two adjacent ends of two adjacent fan-out sub-lines close to each other are electrically connected to the same first conductive pattern.

[0009] In some embodiments, the first conductive pattern includes an extension portion and two contact portions, the extension portion extending along the second direction, the two contact portions respectively connected to the ends of the extension portion along the second direction, and the size of the contact portion along the first direction is larger than the size of the extension portion along the first direction. An opening is provided between two adjacent fan-out sub-lines, and the adjacent ends of the two adjacent fan-out sub-lines are respectively electrically connected to the two contact portions of the same first conductive pattern.

[0010] In some embodiments, the fan-out line is continuous along the second direction; the first conductive pattern includes a plurality of contact portions and at least one extension portion alternately connected along the second direction, the extension portion extending along the second direction, and a dimension of the contact portion along the first direction being greater than a dimension of the extension portion along the first direction. The fan-out line is electrically connected to the plurality of contact portions of the first conductive pattern.

[0011] In some embodiments, the plurality of first conductive patterns are arranged in a plurality of columns along the first direction, each column including a plurality of first conductive patterns arranged along the second direction, and a fan-out line is electrically connected to the plurality of first conductive patterns in a column.

[0012] In some embodiments, the plurality of first conductive patterns are evenly arranged along the second direction, and the arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.

[0013] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are disposed in the display area. The array substrate further includes a first power bus located in the peripheral area and configured to be electrically connected to the cathode of the light-emitting device. The plurality of first signal lines further include a plurality of first power signal lines, at least one end of each of the plurality of first power signal lines being electrically connected to the first power bus along the second direction. The plurality of conductive patterns further include a plurality of second conductive patterns, and one first power signal line is electrically connected to at least one second conductive pattern.

[0014] In some embodiments, along the second direction, one first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are evenly arranged.

[0015] In some embodiments, the plurality of conductive patterns include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the plurality of first conductive patterns have the same arrangement density as the plurality of second conductive patterns.

[0016] In another aspect, a display device is provided. The display device includes a plurality of light-emitting devices and an array substrate as described in any of the above embodiments. The plurality of light-emitting devices are disposed on the array substrate, and one light-emitting device is connected to one pixel circuit of the array substrate.

[0017] In another aspect, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0019] FIG1 is a schematic diagram of a display device according to some embodiments;

[0020] FIG2 is a diagram of a driving architecture of a display device according to yet other embodiments;

[0021] FIG3 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0022] FIG4 is a top view of the structure of the first conductive layer and the second conductive layer according to some embodiments;

[0023] FIG5 is a partial enlarged view of area B in FIG4 ;

[0024] FIG6 is a cross-sectional view taken along section line A1-A1 in FIG5;

[0025] FIG7 is a partial structural diagram of an array substrate according to some embodiments;

[0026] FIG8 is a top view of the structure of the first conductive layer and the second conductive layer according to some embodiments;

[0027] FIG9 is a partial enlarged view of area C in FIG8 ;

[0028] FIG10 is a cross-sectional view taken along section line A2-A2 in FIG9;

[0029] FIG11 is a diagram illustrating a connection structure between a first signal line and a conductive pattern according to some embodiments;

[0030] FIG. 12 is a top view of the array substrate without the second conductive layer according to some embodiments. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0032] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0034] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0035] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0036] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0037] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0038] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0039] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0040] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] 1 , an embodiment of the present disclosure provides a display device 1000 , which is a product having an image display function. For example, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0042] For example, the display device 1000 may be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone, a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (e.g., a rearview camera display in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function. For example, as shown in FIG1 , the display device 1000 may be a mobile phone.

[0043] From the perspective of the light-emitting type of the display device 1000, the above-mentioned display device 1000 may be an organic light-emitting diode display device, a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; abbreviated as: QLED) or a micro light-emitting diode (Mini / Micro Light Emitting Display; abbreviated as: MLED), etc. From the perspective of the form of the display device 1000, the above-mentioned display device 1000 may be a flat display device, a curved display device or a foldable display device, etc. From the perspective of the shape of the display device 1000, the above-mentioned display device 1000 may be rectangular or circular, etc. The embodiments of the present disclosure do not specifically limit this. The following takes an organic light-emitting diode display device with a rectangular and flat display device as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited to this, and any other display devices can also be considered as long as the same technical ideas are applied.

[0044] Referring to Figure 2, in some embodiments, the display device 1000 includes a display panel 1100 and a driver circuit board 1200. The driver circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driver circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording, fingerprint recognition or face recognition, which are not specifically limited here.

[0045] 2 , the display panel 1100 has a display area AA and a peripheral area BB. The peripheral area BB is located at least on one side of the display area AA. Exemplarily, the peripheral area BB is disposed around the display area AA.

[0046] The display area AA is the area on the display panel 1100 used for displaying images. The display area AA is provided with a plurality of sub-pixels P, which are the smallest light-emitting units on the display panel 1100 and are used for displaying images. The peripheral area BB can be used, for example, to provide a gate driver on array (GOA) and control signal lines (such as clock signal lines and power supply voltage signal lines). Of course, the functions of the peripheral area BB are not limited to these, and non-disclosed embodiments will not be described in detail here.

[0047] The multiple sub-pixels P may emit light of different colors. For example, the multiple sub-pixels P include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light.

[0048] The plurality of sub-pixels P are arranged in a plurality of rows and columns, each row including a plurality of sub-pixels P arranged along a first direction X, and the plurality of rows of sub-pixels P are arranged along a second direction Y. Each column including a plurality of sub-pixels P arranged along the second direction Y, and the plurality of columns of sub-pixels P are arranged along the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.

[0049] The sub-pixel P includes a pixel circuit 120 and a light-emitting device 200. The pixel circuit 120 includes a plurality of thin film transistors (TFTs) and at least one capacitor Cst. Exemplarily, the pixel circuit 120 may be a "3T1C" circuit, a "7T1C" circuit, or an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits may also be considered as long as the same technical concept is applied. Wherein, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0050] Referring to FIG3 , in some embodiments, a display panel 1100 includes a stacked array substrate 100, a light-emitting device 200, and an encapsulation layer 300. Of course, the display panel 1100 may also include a functional stack disposed on a side of the encapsulation layer 300 away from the array substrate 100. The functional stack may be, for example, one or more of a touch-sensitive functional layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, to enable the display panel to achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the type and quantity of the functional stack.

[0051] The light-emitting device 200 includes an anode 201, a light-emitting functional layer 202, and a cathode layer 203, which are stacked together. The cathode layers 203 of multiple light-emitting devices 200 are interconnected to form a continuous, integrated structure. The display panel 1100 may further include a pixel definition layer (PDL), which is disposed on a side of the anode 201 away from the array substrate 100. The pixel definition layer (PDL) includes multiple openings, and at least a portion of each light-emitting functional layer 202 is located within one of the openings.

[0052] The encapsulation layer 300 is configured to reduce the risk of moisture and oxygen from the external environment entering the light-emitting device 200, thereby increasing the service life of the display panel 1100. The encapsulation layer 300 can be an encapsulation film or an encapsulation substrate. For example, as shown in FIG3 , the encapsulation layer 300 can be an encapsulation film. In this case, the encapsulation layer 300 can include a first inorganic encapsulation layer 301, an organic encapsulation layer 302, and a second inorganic encapsulation layer 303, which are stacked in sequence.

[0053] The array substrate 100 includes a substrate 110 and a pixel circuit disposed on the substrate 110. Each pixel circuit is connected to a light-emitting device and is configured to drive the light-emitting device to emit light. The substrate 110 can be a rigid substrate, such as a material including glass. Alternatively, the substrate 110 can be a flexible substrate, such as a material including polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0054] The array substrate 100 may include multiple conductive layers configured to form multiple pixel circuits and multiple signal lines for driving the pixel circuits. For example, the multiple conductive layers may include a first semiconductor layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, a second semiconductor layer ACT2, a third gate conductive layer GT3, a first source / drain conductive layer SD1, and a second source / drain conductive layer SD2, arranged in a direction perpendicular to and away from the substrate 110. Of course, the array substrate may also include other conductive layers, such as a third source / drain conductive layer, which is not specifically limited here, as long as the same technical principles are employed. The thin-film transistor TFT may include a semiconductor pattern 101 located on the first semiconductor layer ACT1, a gate 102 located on the first gate conductive layer GT1, and a source electrode 103 and a drain electrode 104 located on the first source / drain conductive layer SD1. The storage capacitor Cst may include a first electrode C1 located on the first gate conductive layer GT1 and a second electrode C2 located on the second gate conductive layer GT2.

[0055] The array substrate 100 may further include insulating layers located between adjacent conductive layers. For example, the array substrate 100 may include a first gate insulating layer GI1 located between the first semiconductor layer ACT1 and the first gate conductive layer GT1, a second gate insulating layer GI2 located between the first gate conductive layer GT1 and the second gate conductive layer GT2, a first interlayer dielectric layer ILD1 located between the second gate conductive layer GT2 and the second semiconductor layer ACT2, a second interlayer dielectric layer ILD2 located between the second semiconductor layer ACT2 and the third gate conductive layer GT3, a first planarizing layer PLN1 located between the third gate conductive layer GT3 and the first source / drain conductive layer SD1, and a second planarizing layer PLN2 located between the first source / drain conductive layer SD1 and the second source / drain conductive layer SD2. Of course, the array substrate 100 may further include other insulating film layers, which will not be described in detail herein.

[0056] 4 , 5 and 6 , the array substrate 100 provided in an embodiment of the present disclosure includes a first conductive layer 10 and a second conductive layer 20 . The second conductive layer 20 is disposed on a side of the first conductive layer 10 away from the substrate 110 .

[0057] The first conductive layer 10 includes a plurality of conductive patterns 11, and the plurality of conductive patterns 11 are spaced apart from the plurality of pixel circuits. The spaced-apart conductive patterns 11 mean that the conductive patterns 11 are not directly connected to the pixel circuits 120, or in other words, the conductive patterns 11 are not used to transmit signals to the pixel circuits 120. For example, when the first conductive layer 10 is the first source-drain conductive layer SD1, the pixel circuit may include a source and a drain located on the first source-drain conductive layer SD1, and the conductive patterns are spaced apart from the source and drain of the pixel circuit. Furthermore, the conductive patterns 11 are not connected to other conductive layers (such as the first gate conductive layer and the second gate conductive layer) on the substrate side of the first conductive layer 10, nor to the semiconductor layer.

[0058] The second conductive layer 20 includes a plurality of first signal lines 21, which are arranged at intervals along a first direction X and extend along a second direction Y. The first direction X is the row direction (horizontal direction in FIG. 4 ) in which the plurality of pixel circuits 120 are arranged, and the second direction Y is the column direction in which the plurality of pixel circuits 120 are arranged. The first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.

[0059] A first signal line 21 is electrically connected to at least one conductive pattern 11. Since the conductive pattern 11 is spaced apart from the pixel circuit, the first signal line 21 does not transmit electrical signals to the pixel circuit through the conductive pattern 11. Based on this, the position of the conductive pattern 11 can be set arbitrarily as long as it does not interfere with other structures of the array substrate (such as contact or electrical coupling).

[0060] If static electricity is generated on the first signal line 21, it will accumulate on the protrusions, corners, or other protruding sharp corners of the first signal line 21. At the connection point between the first signal line 21 and the conductive pattern 11, a via 105 is formed in the insulating layer between the first conductive layer 10 and the second conductive layer 20. A portion of the first signal line 21 is located within the via 105, forming a protrusion within the via 105. In other words, the first signal line 21 protrudes toward the side closer to the substrate 110, forming a protrusion. As a result, static electricity will accumulate at the connection point between the first signal line 21 and the conductive pattern 11 (the portion of the first signal line 21 located within the via 105), be transmitted to the conductive pattern 11, and then be released through the conductive pattern 11, thereby dissipating the static electricity on the first signal line 21. As shown in Figure 6, the conductive pattern 11 includes at least two contact portions 1112 arranged at intervals, and the first signal line 21 is connected to at least two contact portions 1112 of the conductive pattern 11, that is, the first signal line 21 includes two positions connected to the contact portions 1112. In this way, the first signal line 21 can form two protrusions at the position where it is connected to the conductive pattern 11, which is more conducive to the transmission of static electricity to the conductive pattern 11.

[0061] The first conductive layer 10 may be any one of the multiple conductive layers included in the array substrate 100 shown in FIG3 , except for the conductive layer farthest from the substrate 110, and the second conductive layer 20 may be any conductive layer on the side of the first conductive layer 10 away from the substrate 110. For example, the second conductive layer 20 may be a film layer in the array substrate 100 used to provide signal routing, and the first conductive layer 10 may be any conductive layer on the side of the second conductive layer 20 close to the substrate 110. For example, the first conductive layer 10 may be a conductive layer adjacent to the second conductive layer 20. In this way, the depth of the via hole provided in the insulating layer between the first conductive layer 10 and the second conductive layer 20 at the connection location between the first signal line 21 and the conductive pattern 11 can be reduced, thereby reducing the difficulty of connecting the first signal line 21 to the conductive pattern 11.

[0062] For example, the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the first source-drain conductive layer SD1; alternatively, the first conductive layer 10 may be the first source-drain conductive layer SD1, and the second conductive layer 20 may be the second source-drain conductive layer SD2; alternatively, when the array substrate includes a third source-drain conductive layer, the first conductive layer 10 may be the second source-drain conductive layer SD2, and the second conductive layer 20 may be the third source-drain conductive layer. Of course, the first conductive layer 10 and the second conductive layer 20 may not be adjacent conductive layers. For example, the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the second source-drain conductive layer SD2. It is understood that the first conductive layer 10 and the second conductive layer 20 may also be other suitable combinations, and the embodiments of the present disclosure will not be listed one by one, as long as the same technical concept is adopted.

[0063] In the following embodiments of the present disclosure, the first conductive layer 10 is the first source-drain conductive layer SD1, and the second conductive layer 20 is the second source-drain conductive layer SD2. However, the embodiments of the present application are not limited thereto, as long as the same technical concept is adopted.

[0064] In some embodiments, as shown in Figures 4 and 7, the first conductive layer 10 further includes a plurality of first connection lines 12, which are arranged at intervals along the second direction Y and extend along the first direction X. The second conductive layer 20 further includes a plurality of data lines 22, each of which is electrically connected to a column of pixel circuits. The plurality of data lines 22 include a plurality of first data lines 221 and a plurality of second data lines 222. The plurality of first data lines 221 are located on either side of the plurality of second data lines 222 along the first direction X. For example, the plurality of first data lines 221 may be located in an edge region AA2 of the display area AA along the first direction X, and the plurality of second data lines 222 may be located in a central region AA1 of the display area AA along the first direction X. Each first data line 221 is connected to each first connection line 12. The plurality of first signal lines 21 included in the second conductive layer 20 include a plurality of fan-out lines 211, each of which is electrically connected to each first connection line 12. Multiple fan-out lines 211 can be located in the central area AA1 of the display area AA along the first direction X. Based on this, a first data line 221 located in the edge area AA2 of the display area AA along the first direction X is connected to the central area AA1 of the display area AA along the first direction X via a first connection line 12 and a fan-out line 211, and then leads out from the edge of the central area AA1 near the peripheral area. This arrangement of data lines 22 is also referred to as fan-out in AA (FIAA) or fan-out in panel (FIP). This arrangement helps reduce the size of the peripheral area along the second direction Y, thereby reducing the bezel width of the array substrate 100 and facilitating a narrow bezel for the display device 1000. The fan-out line 211 is located in the central area AA1 of the display area AA and is not used to transmit data signals to the pixel circuits in the central area AA1. In other words, the fan-out line 211 is electrically insulated from the pixel circuits located on the side of the fan-out line 211 near the substrate 110.

[0065] In related art, fan-out lines 211 are formed on a single film layer and are not connected to any other structures within the display area AA except the first connection lines 12. This results in a lack of a path for dissipating static electricity. Furthermore, fan-out lines 211 extend between sub-pixels and need to avoid certain conductive structures in the pixel circuitry, resulting in a specific pattern shape, such as corners or protrusions. Static electricity can accumulate at the corners or protrusions of fan-out lines 211. For these reasons, static electricity easily accumulates on the fan-out lines, resulting in lower reliability of the array substrate.

[0066] Referring to Figures 5 and 6 , in an embodiment of the present disclosure, to address the aforementioned issues, the plurality of conductive patterns 11 include a plurality of first conductive patterns 111. A fan-out line 211 is electrically connected to at least one of the first conductive patterns 111. Furthermore, a protrusion protruding toward the side closer to the substrate 110 is formed at the location where the fan-out line 211 connects to the first conductive pattern 111. Consequently, if static electricity is generated on the fan-out line 211, it is transferred toward the location where the fan-out line 211 connects to the first conductive pattern 111 and is subsequently transferred to the first conductive pattern 111. The static electricity is then discharged at the first conductive pattern 111, thereby improving the reliability of the array substrate.

[0067] In some embodiments, as shown in Figures 5 and 6, the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y. In other words, the fan-out line 2111 includes a plurality of disconnected fan-out sub-lines 2111, with an opening 2112 between two adjacent fan-out sub-lines 2111. The two ends of two adjacent fan-out sub-lines 2111, which are close to each other, are electrically connected to the same first conductive pattern 111, that is, the two adjacent fan-out sub-lines 2111 are electrically connected through one first conductive pattern 111. In this way, when the fan-out line 211 transmits current, the current can flow through each first conductive pattern 111, ensuring that static electricity on the fan-out line 211 can be transmitted to the first conductive pattern 111 and released through the first conductive pattern 111.

[0068] 5 and 6 , the first conductive pattern 111 includes an extension portion 1111 and two contact portions 1112. The extension portion 1111 extends along the second direction Y. The two contact portions 1112 are respectively connected to the two ends of the extension portion 1111 along the second direction Y. An opening 2112 is defined between two adjacent fan-out sub-lines 2111. The orthographic projection of the opening 2112 on the substrate 110 overlaps with the orthographic projection of the extension portion 1111 on the substrate 110. The two adjacent ends of the two adjacent fan-out sub-lines 2111 are electrically connected to the two contact portions 1112 of the same first conductive pattern 111. The size of the contact portion 1112 along the first direction X is larger than the size of the extension portion 1111 along the first direction X. This is beneficial to reducing the alignment accuracy requirements between the fan-out sub-line 2111 and the contact portion 1112, reducing the connection difficulty between the fan-out sub-line 2111 and the contact portion 1112, and increasing the contact area between the fan-out sub-line 2111 and the contact portion 1112, thereby reducing the resistance at the connection between the fan-out sub-line 2111 and the contact portion 1112.

[0069] In other embodiments, referring to Figures 8 and 9, the fan-out line 211 is continuous along the second direction Y, that is, there is no opening on the fan-out line 211. In this way, the fan-out line 211 is arranged in parallel with the first conductive pattern 111. The first conductive pattern 111 can not only release static electricity on the fan-out line 211, but also reduce the resistance of the fan-out line 211.

[0070] 9 , 10 , and 11 , the first conductive pattern 111 includes a plurality of contact portions 1112 and at least one extension portion 1111, which are alternately connected along the second direction Y. The dimensions of the contact portions 1112 along the first direction X are larger than those of the extension portion 1111 along the first direction X. This helps reduce the alignment accuracy requirements between the fan-out line 211 and the contact portions 1112, easing the connection difficulty between the fan-out line 211 and the contact portions 1112. It also increases the contact area between the fan-out line 211 and the contact portions 1112, thereby reducing the resistance at the connection between the fan-out line 211 and the contact portions 1112. The fan-out line 211 is electrically connected to the plurality of contact portions 1112 of the first conductive pattern 111. In other words, the fan-out line 211 includes multiple connection points with the same first conductive pattern 111. This improves the reliability and stability of the connection between the fan-out line 211 and the same first conductive pattern 111, and helps reduce the resistance of the fan-out line 211.

[0071] Exemplarily, a contact portion 1112 is provided at each end of the first conductive pattern 111 along the second direction Y, and two adjacent contact portions 1112 are connected by an extension portion 1111. For example, as shown in FIG10 , the first conductive pattern 111 includes two contact portions 1112 and one extension portion 1111; alternatively, referring to FIG11 , the first conductive pattern 111 may include three contact portions 1112 and two extension portions 1111. The first conductive pattern 111 may also include other numbers of two contact portions 1112 and extension portions 1111, as long as the same technical concept is adopted.

[0072] In some embodiments, as shown in FIG12 , a plurality of first conductive patterns 111 are arranged in a plurality of columns along a first direction X, and each column includes at least one first conductive pattern 111 arranged along a second direction Y. A fan-out line 211 is electrically connected to a plurality of first conductive patterns 111 in a column. In this way, the density of the first conductive patterns 111 connected to the fan-out line 211 can be increased, and static electricity generated at any position on the fan-out line 211 can be transmitted to the adjacent first conductive pattern 111, further improving the static discharge effect of the fan-out line 211. It can be understood that in FIG12 , in order to distinguish the first conductive pattern 111 from the second conductive pattern 112, different filling patterns are used for the two, but the two are in the same film layer and are prepared together using the same film forming process.

[0073] As shown in FIG12 , multiple first conductive patterns 111 are evenly arranged along the second direction Y, which helps improve the uniformity of the first conductive patterns 111 and the pattern uniformity of the first conductive layer 10. The arrangement density of the pixel circuits 120 is an integer multiple of the arrangement density of the first conductive patterns 111. In other words, the spacing between the first conductive patterns 111 in the second direction Y (the pitch of the first conductive patterns 111) is an integer multiple of the spacing between the pixel circuits 120 in the second direction Y (the pitch of the pixel circuits 120). That is, a first conductive pattern 111 is provided on the side away from the substrate for every integer number of pixel circuits 120. This helps improve the structural uniformity of the array substrate 100 and reduces the risk of display panel shading problems caused by differences in the distribution of the first conductive patterns 111.

[0074] 12 , the arrangement density of the pixel circuits 120 is equal to the arrangement density of the first conductive patterns 111. In this way, the pattern uniformity of the first conductive layer 10 can be maximized, and the structural uniformity of the array substrate can be maximized.

[0075] As shown in FIG7 , the array substrate 100 further includes a first power bus VSS located in the peripheral area BB. The first power bus VSS is configured to be electrically connected to the cathode of the light-emitting device 200, that is, the first power bus VSS is electrically connected to the cathode layer 203. The second conductive layer 20 includes multiple first signal lines 21, further comprising multiple first power signal lines 212. At least one end of each of the multiple first power signal lines 212 is electrically connected to the first power bus VSS along the second direction Y. The multiple first power signal lines 212 are arranged at intervals along the first direction X and extend along the second direction Y, thereby electrically connecting to the cathode layer. The multiple first power signal lines 212 can reduce the resistance of the cathode layer, thereby reducing the voltage drop across the cathode layer and improving display uniformity in the display area AA. The configuration employing the aforementioned auxiliary power lines 50 is also known as SIP (VSS in Panel) technology.

[0076] As shown in Figures 4 and 8, the plurality of conductive patterns 11 further include a plurality of second conductive patterns 112. A first power signal line 212 is electrically connected to at least one second conductive pattern 112. The first power signal line 212 protrudes toward the side closer to the substrate at the location where it connects to the second conductive pattern 112, forming a protrusion. When static electricity appears on the first power signal line 212, the static electricity accumulates at the protrusion of the first power signal line 212. In other words, the static electricity is transmitted to the connection location between the first power signal line 212 and the second conductive pattern 112, and then to the second conductive pattern 112. A sharp discharge occurs at the edge or end of the second conductive pattern 112, thereby releasing the static electricity into the insulating layer in contact with the conductive pattern 112. The static electricity charge is generally small, and the insulating layer (such as a passivation layer or a planarization layer) can absorb and release a small amount of static electricity, thereby releasing the static electricity on the first power signal line 212. It can be understood that the static electricity charge is small, and although the insulating layer is electrically insulating, it can absorb and release static electricity.

[0077] Continuing to refer to Figures 4 and 8, along the second direction Y, a first power signal line 212 is electrically connected to multiple second conductive patterns 112, and the multiple second conductive patterns 112 are evenly arranged. In this way, the density of the second conductive patterns 112 connected to the first power signal line 212 can be increased. Static electricity generated at any position on the first power signal line 212 can be transmitted to the adjacent second conductive patterns 112, further improving the static electricity release effect of the first power signal line 212.

[0078] In some embodiments, as shown in Figures 4 and 8, the plurality of conductive patterns 11 include a plurality of first conductive patterns 111 and a plurality of second conductive patterns 112. The plurality of first conductive patterns 111 have the same structure as the plurality of second conductive patterns 112, that is, the shape of the orthographic projection of the first conductive pattern 111 on the substrate is the same as the shape of the orthographic projection of the second conductive pattern 112 on the substrate, and the size of the orthographic projection of the first conductive pattern 111 on the substrate is equal to the size of the orthographic projection of the second conductive pattern 112 on the substrate. The arrangement density of the plurality of first conductive patterns 111 and the plurality of second conductive patterns 112 is the same. In this way, the structural uniformity of the first conductive layer 10 can be further improved, and the risk of image fading on the display panel can be reduced.

[0079] Of course, in other embodiments, the first conductive pattern 111 and the second conductive pattern 112 may also have differences. For example, when the first conductive pattern 111 includes two contact portions 1112, the second conductive pattern 112 may include one, three, or any other number of contact portions. The embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

[0080] In some embodiments, as shown in FIG4 , when the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y, the first power signal line 212 may also include a plurality of power sub-lines 2121 spaced apart along the second direction Y, and the structure of the fan-out sub-lines 2111 is identical to that of the power sub-lines 2121. That is, the shape and size of the orthographic projection of the fan-out sub-lines 2111 on the substrate are identical to the shape and size of the orthographic projection of the power sub-lines 2121 on the substrate. Alternatively, as shown in FIG8 , when the fan-out line 211 is continuous along the second direction, the first power signal line 212 may also be continuous along the second direction Y. This facilitates improving the structural uniformity of the second conductive layer 20.

[0081] It is understood that in some other embodiments, when the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y, the first power signal line 212 may also be continuous along the second direction Y. Alternatively, when the fan-out line 211 is continuous along the second direction, the first power signal line 212 may also include a plurality of power sub-lines spaced apart along the second direction Y. Of course, the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

[0082] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate; A plurality of pixel circuits are disposed on the substrate, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns; A first conductive layer, comprising a plurality of conductive patterns, wherein the plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and the conductive pattern comprises at least two contact portions spaced apart from each other; The second conductive layer is arranged on a side of the first conductive layer away from the substrate, and includes a plurality of first signal lines, which are arranged at intervals along a first direction and all extend along a second direction, a first signal line is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact portions of the conductive pattern; the first direction is a row direction in which the plurality of pixel circuits are arranged, and the second direction is a column direction in which the plurality of pixel circuits are arranged.

2. The array substrate according to claim 1, wherein: The first conductive layer further includes a plurality of first connection lines, which are arranged at intervals along the second direction and extend along the first direction; The second conductive layer further comprises a plurality of data lines, one data line being electrically connected to a column of pixel circuits; the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being respectively located on both sides of the plurality of second data lines; one first data line being connected to one first connecting line; The plurality of first signal lines include a plurality of fan-out lines, one fan-out line being electrically connected to one first connection line; The plurality of conductive patterns include a plurality of first conductive patterns, and the fan-out line is electrically connected to at least one of the first conductive patterns.

3. The array substrate according to claim 2, wherein: The fan-out line includes a plurality of fan-out sub-lines spaced apart along the second direction, and two ends of two adjacent fan-out sub-lines close to each other are electrically connected to the same first conductive pattern.

4. The array substrate according to claim 3, wherein: The first conductive pattern includes an extension portion and two contact portions, the extension portion extends along the second direction, the two contact portions are respectively connected to two ends of the extension portion arranged along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction; There is an opening between two adjacent fan-out sub-lines, and two ends of the two adjacent fan-out sub-lines close to each other are electrically connected to two contact portions of the same first conductive pattern respectively.

5. The array substrate according to claim 2, wherein: The fan-out line is continuous along the second direction; The first conductive pattern includes a plurality of contact portions and at least one extension portion alternately connected along the second direction, the extension portion extends along the second direction, and a size of the contact portion along the first direction is greater than a size of the extension portion along the first direction; The fan-out line is electrically connected to a plurality of contact portions of the first conductive pattern.

6. The array substrate according to claim 2, wherein: The plurality of first conductive patterns are arranged in a plurality of columns along the first direction, and one column includes at least one first conductive pattern arranged along the second direction; One fan-out line is electrically connected to a plurality of first conductive patterns in one column.

7. The array substrate according to claim 6, wherein: Along the second direction, the plurality of first conductive patterns are evenly arranged; and the arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.

8. The array substrate according to any one of claims 1 to 7, wherein: The array substrate comprises a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are arranged in the display area; The array substrate further comprises a first power bus, which is located in the peripheral area and is configured to be electrically connected to the cathode of the light emitting device; The plurality of first signal lines further include a plurality of first power signal lines, and along the second direction, at least one end of the plurality of first power signal lines is electrically connected to the first power bus; The plurality of conductive patterns further include a plurality of second conductive patterns, and one first power signal line is electrically connected to at least one second conductive pattern.

9. The array substrate according to claim 8, wherein: Along the second direction, one first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are evenly arranged.

10. The array substrate according to claim 8 or 9, wherein: The plurality of conductive patterns further include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the plurality of first conductive patterns have the same arrangement density as the plurality of second conductive patterns.

11. A display panel, comprising: The array substrate according to any one of claims 1 to 10; A plurality of light emitting devices are arranged on the array substrate, and one light emitting device is connected to one pixel circuit of the array substrate.

12. A display device, comprising: The display panel as claimed in claim 11; The driving circuit board is electrically connected to the display panel and is configured to transmit a control signal to the display panel.

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