Display substrate, display panel and display device

Abstract

A display substrate (100), a display panel and a display device. The display substrate (100) comprises a pixel array (10), a source / drain electrode layer (40), and a plurality of scan line groups (G1, G2, G3, ..., G(m-1), Gm). The source / drain electrode layer (40) comprises a plurality of data lines (S1, S2, ..., Sn) and a plurality of first touch lines (Q1, Q2, ..., Qn). The pixel array (10) comprises a plurality of pixel groups (11) arranged in a row direction, wherein each pixel group (11) comprises a first sub-pixel column (111) and a second sub-pixel column (112) adjacent to each other. The data lines (S1, S2, ..., Sn) are arranged between the first sub-pixel columns (111) and the second sub-pixel columns (112). The first touch lines (Q1, Q2, ..., Qn) are arranged between two adjacent pixel groups (11). A plurality of adjacent first touch lines (Q1, Q2,..., Qn) are connected in parallel to form a first touch coil (X1, X2, X3, ..., X(j-2), X(j-1), Xj). Each of the scan line groups (G1, G2, G3, ..., G(m-1), Gm) corresponds to one pixel row, and comprises a first scan line (G11) and a second scan line (G12) respectively arranged on two sides of the corresponding pixel row. The first scan line (G11) and the second scan line (G12) both extend in the row direction (X), the first scan line (G11) is connected to pixels located in each first sub-pixel column (111) in the corresponding pixel row, and the second scan line (G12) is connected to pixels located in each second sub-pixel column (112) in the corresponding pixel row.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] For medium and large-sized display panels, larger size and higher resolution require more IC channels. However, given the current shortage of driver ICs and rising raw material prices in the semiconductor industry, reducing the number of display driver chips is particularly important. Electromagnetic touch technology can also be applied to medium and large-sized display panels, achieving electromagnetic touch by forming a built-in electromagnetic coil.

[0003] Therefore, how to improve the display effect of the display panel while effectively realizing electromagnetic touch and reducing the semiconductor manufacturing cost has become an urgent problem to be solved.

[0004] Summary of the Invention

[0005] The present application discloses a display substrate, comprising: a substrate, a pixel array disposed on the substrate, a source-drain electrode layer, and a plurality of scan line groups, wherein the source-drain electrode layer comprises a plurality of data lines and a plurality of first touch lines;

[0006] The pixel array includes a plurality of pixel groups arranged along a row direction, each pixel group includes a first sub-pixel column and a second sub-pixel column that are adjacent to each other, the data line is arranged between the first sub-pixel column and the second sub-pixel column, and is connected to the first sub-pixel column and the second sub-pixel column, the first touch line is arranged between two adjacent pixel groups and extends along the column direction; a plurality of adjacent first touch lines are connected in parallel to form a first touch coil, and the plurality of first touch coils are arranged along the row direction;

[0007] Each of the scan line groups corresponds to a pixel row, and the scan line group includes a first scan line and a second scan line respectively arranged on both sides of the corresponding pixel row, the first scan line and the second scan line both extend along the row direction, the first scan line is connected to the pixels located in each first sub-pixel column in the corresponding pixel row, and the second scan line is connected to the pixels located in each second sub-pixel column in the corresponding pixel row.

[0008] In some embodiments, it further includes:

[0009] a gate layer, disposed on one side of the substrate, comprising the plurality of scan line groups and common electrode lines;

[0010] a gate insulating layer, disposed on a side of the gate layer away from the substrate and covering the plurality of scan line groups and the common electrode lines;

[0011] The active layer is arranged on a side of the gate insulating layer away from the substrate.

[0012] In some embodiments, further comprising:

[0013] a pixel electrode layer, disposed on a side of the gate insulating layer away from the substrate, the pixel electrode layer comprising a plurality of pixel electrodes spaced apart from each other, and the source-drain electrode layer disposed on a side of the active layer and the pixel electrode layer away from the substrate;

[0014] a first insulating layer, disposed on a side of the source / drain electrode layer away from the substrate, and covering the source / drain electrode layer and the pixel electrode layer;

[0015] a touch electrode layer, disposed on a side of the first insulating layer away from the substrate, the touch electrode layer comprising a plurality of second touch lines extending along the row direction;

[0016] a second insulating layer, disposed on a side of the touch electrode layer away from the substrate and covering the touch electrode layer;

[0017] The common electrode layer is arranged on a side of the second insulating layer away from the substrate.

[0018] In some embodiments, the source-drain electrode layer is disposed on a side of the active layer away from the substrate.

[0019] In some embodiments, further comprising:

[0020] a first insulating layer, disposed on a side of the source-drain electrode layer away from the substrate and covering the source-drain electrode layer;

[0021] The touch electrode layer is disposed on a side of the first insulating layer away from the substrate. The touch electrode layer includes a plurality of second touch lines extending along a row direction.

[0022] In some embodiments, further comprising:

[0023] a second insulating layer, disposed on a side of the touch electrode layer away from the substrate and covering the touch electrode layer;

[0024] The pixel electrode layer is arranged on a side of the second insulating layer away from the substrate, and the pixel electrode layer includes a plurality of pixel electrodes.

[0025] In some embodiments, further comprising:

[0026] a first insulating layer, disposed on a side of the source-drain electrode layer away from the substrate and covering the source-drain electrode layer;

[0027] an electrode layer, disposed on a side of the first insulating layer away from the substrate, the electrode layer comprising a plurality of pixel electrodes and a common electrode, the common electrode being disposed between adjacent pixel electrodes;

[0028] a second insulating layer, disposed on a side of the electrode layer away from the substrate and covering the pixel electrode and the common electrode;

[0029] The touch electrode layer is disposed on a side of the second insulating layer away from the substrate. The touch electrode layer includes a plurality of second touch lines extending along a row direction.

[0030] In some embodiments, within the same first touch coil, the first ends of all first touch lines are connected to one first touch connection line, and the second ends of all first touch lines are connected to one second touch connection line.

[0031] In some embodiments, the first ends of all first touch wires in all first touch coils are connected to the same first touch connection wire;

[0032] The second ends of different first touch coils are connected to different second touch connection lines.

[0033] In some embodiments, different touch connection lines are connected to different pins of the electromagnetic induction circuit board.

[0034] In some embodiments, the device further includes a plurality of second touch lines extending along the row direction;

[0035] A plurality of adjacent second touch lines are connected in parallel to form a second touch coil, and the plurality of second touch coils are arranged in sequence along a column direction;

[0036] In the same second touch coil, the first ends of all the second touch lines are connected to a third touch connection line, and the second ends of all the second touch lines are connected to a fourth touch connection line.

[0037] In some embodiments, the first ends of all second touch wires in all second touch coils are connected to the same third touch connection wire;

[0038] The second ends of different second touch coils are connected to different fourth touch connection lines.

[0039] In some embodiments, different touch connection lines are connected to different pins of the electromagnetic induction circuit board.

[0040] The present application also discloses a display panel, which includes the display substrate as described above.

[0041] The present application further discloses a display device, which includes the display panel as described above.

[0042] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0044] FIG1 is a schematic structural diagram of an embodiment of a display substrate provided by the present application;

[0045] FIG2 is a schematic diagram of a manufacturing process of an embodiment of an ADS type display substrate provided by the present application;

[0046] FIG3 is a schematic cross-sectional view of an embodiment of an ADS type display substrate provided by the present application;

[0047] FIG4 is a schematic diagram of a manufacturing process of an embodiment of a TN type display substrate provided by the present application;

[0048] FIG5 is a schematic cross-sectional view of an embodiment of a TN-type display substrate provided by the present application;

[0049] FIG6 is a schematic diagram of a manufacturing process of an embodiment of an IPS display substrate provided in the present application;

[0050] FIG7 is a schematic diagram of a cross-sectional structure along a column direction of an embodiment of an IPS display substrate provided by the present application;

[0051] FIG8 is a schematic diagram of a cross-sectional structure along a row direction of an embodiment of an IPS display substrate provided by the present application;

[0052] FIG9 is a schematic diagram of an embodiment of the connection relationship between a plurality of first touch lines in a display substrate and a circuit board provided by the present application;

[0053] FIG10 is a schematic diagram of an embodiment of the connection relationship between a plurality of second touch lines in a display substrate and a circuit board provided by the present application. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0055] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0056] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0057] Please refer to FIG1 , which shows a schematic structural diagram of an embodiment of a display substrate provided in the present application.

[0058] In this embodiment, the display substrate 100 includes a substrate (not shown in FIG1 ), a pixel array 10 formed on the substrate, a source-drain electrode layer 40, and a plurality of scan line groups G1, G2, G3, ..., G(m-1), Gm, wherein the source-drain electrode layer 40 includes a plurality of data lines S1, S2, ..., Sn and a plurality of first touch lines Q1, Q2, ..., Qn, where m and n are positive integers.

[0059] The pixel array 10 is formed by a plurality of pixels P arranged along a row direction X and a column direction Y. The pixel array 10 includes a plurality of pixel groups 11 arranged along the row direction X. Each pixel group 11 includes adjacent first and second subpixel columns 111 and 112. Data lines S1, S2, ..., Sn are disposed between the first and second subpixel columns 111 and 112. Each data line S1, S2, ..., Sn connects to two subpixel columns 111 and 112 in a pixel group 11. First touch lines Q1, Q2, ..., Qn are disposed between two adjacent pixel groups 11. The data lines S1, S2, ..., Sn and the first touch lines Q1, Q2, ..., Qn all extend along the column direction Y.

[0060] Each scan line group includes a first scan line and a second scan line, respectively, disposed on either side of each pixel row. For example, in FIG1 , scan line group G1 includes a first scan line G11 and a second scan line G12, respectively, disposed on either side of the first pixel row; scan line group G2 includes a first scan line G21 and a second scan line G22, respectively, disposed on either side of the second pixel row; scan line group G3 includes a first scan line G31 and a second scan line G32, respectively, disposed on either side of the third pixel row; scan line group G(m-1) includes a first scan line G(m-1)1 and a second scan line G(m-1)2, respectively, disposed on either side of the (m-1)th pixel row; and scan line group Gm includes a first scan line Gm1 and a second scan line Gm2, respectively, disposed on either side of the mth pixel row. The first scan lines G11, G21, G31, ..., G(m-1)1, and Gm1 extend along the row direction X of the pixel array and are respectively connected to the pixels located in the first sub-pixel columns 111 in the corresponding pixel rows. The second scan lines G12, G22, G32, ..., G(m-1)2, and Gm2 extend along the row direction X of the pixel array and are respectively connected to the pixels located in the second sub-pixel columns 112 in the corresponding pixel rows.

[0061] In some embodiments, the display substrate 100 further includes thin film transistors (not shown) corresponding one-to-one to the pixels P in the pixel array, the gate of each thin film transistor is connected to the first scan line G11, G21, G31, ..., G(m-1)1, Gm1 or the second scan line G12, G22, G32, ..., G(m-1)2, Gm2, the first electrode of each thin film transistor is connected to a data line S1, S2, ..., Sn, and the second electrode of each thin film transistor is connected to a corresponding pixel (specifically, it can be connected to the pixel electrode of the pixel).

[0062] The display substrate provided in this embodiment adopts a dual gate (one pixel row is driven by two scan lines) design, using one data line to transmit drive signals to two adjacent columns of pixels in a pixel group. This can halve the number of data lines, thereby reducing the number of IC channels. First touch lines are provided between adjacent pixel groups, so that a first touch line extending along the column direction can be provided between every two columns of pixels. This helps increase the density and number of first touch lines and reduces the resistance of the first touch lines. The first touch lines and data lines are provided on the same layer (i.e., the source and drain electrode layer) and can be manufactured using the same mask, which helps simplify the manufacturing process. In addition, the first touch lines and data lines are both provided between adjacent sub-pixel columns, eliminating the need to provide first touch lines in the pixel area. This can increase the pixel aperture ratio, improve the transmittance of the display substrate, and achieve higher image quality and display effects.

[0063] The display substrate provided in this application may be an ADS-type display substrate. The structure and manufacturing method of the ADS-type display substrate can be shown in Figures 1 to 3. Figure 1 can be regarded as a top view of an ADS-type display substrate, Figure 2 is a schematic diagram of the manufacturing process of an ADS-type display substrate, and Figure 3 is a schematic diagram of a cross-sectional structure of an ADS-type display substrate.

[0064] Please refer to Figures 2 and 3, and in combination with Figure 1 when necessary, the gate layer 22 can be set on one surface of the substrate 21 (i.e., the front side of the substrate 21). The gate layer 22 may include a plurality of scan lines 227 and common electrode lines 223 and a plurality of gates 221. The scan lines 227 and the common electrode lines 223 are spaced apart and extend in the row direction. The scan lines 227 are similar to or the same as the first scan lines G11, G21, G31, ..., G(m-1)1, Gm1 and the second scan lines G12, G22, G32, ..., G(m-1)2, Gm2 in Figure 1. The common electrode lines 223 are used to connect multiple common electrodes or all common electrodes located in another film layer. The gates 221 are connected to the corresponding scan lines 227 and cover the channel region of the active layer to control the opening and closing of the thin film transistors.

[0065] Since the common electrode lines 223 and the scan lines 227 are arranged in the same layer, they can be manufactured simultaneously during production, which helps reduce production costs. For example, a whole layer of metal material (e.g., copper, aluminum, silver, etc.) can be formed first, and then a portion of the metal material layer can be removed by etching to form a plurality of spaced scan lines 227 and one or more common electrode lines 223, thereby obtaining the gate layer 22. In some embodiments, the common electrode lines 223 can also be manufactured in a different layer from the scan lines 227. The common electrode lines 223 can be manufactured using a separate film layer.

[0066] The gate insulating layer 23 may be disposed on a side of the gate layer 22 away from the substrate 21 and cover the scan lines 227, the common electrode lines 223, and areas of the substrate 21 not covered by the scan lines 227 and the common electrode lines 223. The gate insulating layer 23 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0067] The active layer 24 can be disposed on a side of the gate insulating layer 23 away from the substrate 21. The active layer 24 can include a source region, a drain region, and a channel between the source and drain regions, for forming a thin film transistor. The active layer 24 can be made of single crystal silicon, polycrystalline silicon, or oxide, among others.

[0068] The pixel electrode layer 25 can be disposed on a side of the gate insulating layer 23 away from the substrate 21. The pixel electrode layer 25 can be spaced apart from the active layer 24. The pixel electrode layer 25 can include a plurality of pixel electrodes spaced apart from each other, each corresponding to a sub-pixel. The pixel electrode layer 25 can be made of a transparent metal, such as ITO (indium tin oxide).

[0069] The source-drain electrode layer 26 may be disposed on a side of the active layer 24 and the pixel electrode layer 25 away from the substrate 21. The source-drain electrode layer 26 may include a plurality of data lines (not shown in FIG3 , see FIG1 ), each of which extends in the column direction. The data lines cover the surface of the active layer and may be connected to the drain region of the active layer. The source-drain electrode layer 26 may also include a plurality of first touch lines (not shown in the figure), each of which extends in the column direction. The plurality of data lines and the plurality of first touch lines are alternately arranged in the row direction. The source-drain electrode layer 26 is similar to or identical to the source-drain electrode layer 40 in FIG1 . The data lines are similar to or identical to the data lines S1, S2, …, Sn in FIG1 . The first touch lines are similar to or identical to the first touch lines Q1, Q2, …, Qn in FIG1 . The source-drain electrode layer 26 may also include multiple source electrodes 265 and multiple drain electrodes 267, one end of each source electrode 265 is connected to a data line, and the other end is connected to the source region of the active layer 24; one end of each drain electrode 267 is connected to the drain region of the active layer 24, and the other end of the drain electrode 267 is overlapped with the pixel electrode of the corresponding pixel, thereby realizing the connection between the thin film transistor and the pixel.

[0070] The first insulating layer 27 can be disposed on a side of the source / drain electrode layer 26 away from the substrate 21 and covers the source / drain electrode layer 26, the pixel electrode layer 25, and the region of the gate insulating layer 23 not covered by the source / drain electrode layer 26 or the pixel electrode layer 25. The first insulating layer 27 can be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0071] The touch electrode layer 28 can be arranged on a side of the first insulating layer 27 away from the substrate 21. The touch electrode layer 28 can include a plurality of second touch lines 282, each of which extends in the row direction. The plurality of second touch lines 282 are arranged to intersect with the plurality of first touch lines, and a touch point can be formed at the intersection of the two. The material of the touch electrode layer 28 can be a metal such as copper, aluminum, or silver. The second touch lines 282 are similar to or identical to the second touch lines R1, R2, R3, ..., Rm-1, and Rm in Figure 1. A second touch line 282 can be set between adjacent pixel rows, or a second touch line 282 can be set between every two pixel rows or more pixel rows.

[0072] The second insulating layer 285 can be disposed on a side of the touch electrode layer 28 away from the substrate 21 and covers the touch electrode layer 28 and the area of ​​the first insulating layer 27 not covered by the touch electrode layer 28. The second insulating layer 285 can be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0073] The common electrode layer 29 can be disposed on a side of the second insulating layer 285 away from the substrate 21. The common electrode layer 29 can include multiple common electrodes located within the sub-pixels. The common electrodes are slit electrodes that form a multi-dimensional electric field with the pixel electrodes. Adjacent common electrodes can be connected by common electrode lines 223. The common electrode layer 29 can be made of a transparent metal, such as ITO (indium tin oxide). The common electrode layer 29 can form an electric field with the pixel electrode layer 25 to control the brightness of each pixel.

[0074] The display substrate provided in this application may also be a TN-type display substrate. The structure and manufacturing method of the TN-type display substrate can be shown in Figures 4 and 5 as well as Figure 1. Figure 1 can be used as a top view of a TN-type display substrate, Figure 4 is a schematic diagram of the manufacturing process of a TN-type display substrate, and Figure 5 is a schematic diagram of a cross-sectional structure of a TN-type display substrate.

[0075] Referring to Figures 4 and 5, and in conjunction with Figure 1 as necessary, the gate layer 32 can be provided on one surface of the substrate 31 (i.e., the front surface of the substrate 31). The gate layer 32 may include a plurality of scan lines 321, a plurality of gates 325, and common electrode lines 323. The scan lines 321 and the common electrode lines 323 are spaced apart and extend in the row direction. The scan lines 321 are similar to or identical to the first scan lines G11, G21, G31, ..., G(m-1)1, Gm1 and the second scan lines G12, G22, G32, ..., G(m-1)2, Gm2 in Figure 1. The gates 325 are connected to the corresponding scan lines 321 for receiving electrical signals from the scan lines 321. The gates 325 correspond to the positions of the channels in the active layer and are used to turn the thin film transistors on and off. The common electrode lines 323 are used to connect multiple common electrodes or all common electrodes located in another film layer.

[0076] Since the common electrode lines 323 and the scan lines 321 are arranged in the same layer, they can be manufactured simultaneously during production, which helps reduce production costs. For example, a whole layer of metal material (e.g., copper, aluminum, silver, etc.) can be formed first, and then a portion of the metal material layer can be removed by etching to form a plurality of spaced scan lines 321 and one or more common electrode lines 323, thereby obtaining the gate layer 32. In some embodiments, the common electrode lines 323 can also be manufactured in a different layer from the scan lines 321. The common electrode lines 323 can be manufactured using a separate film layer.

[0077] The gate insulating layer 33 may be disposed on a side of the gate layer 32 away from the substrate 31 and cover the scan lines 321, the common electrode lines 323, and areas of the substrate 31 not covered by the scan lines 321 and the common electrode lines 323. The gate insulating layer 33 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0078] The active layer 34 can be disposed on a side of the gate insulating layer 33 away from the substrate 31. The active layer 34 can include a source region, a drain region, and a channel between the source and drain regions, for forming a thin film transistor. The active layer 34 can be made of single crystal silicon, polycrystalline silicon, or oxide, among others.

[0079] The source-drain electrode layer 36 may be disposed on a side of the active layer 34 away from the substrate 31. The source-drain electrode layer 36 may include a plurality of data lines (not shown in FIG5 , see FIG1 ) and a plurality of source electrodes 365 , each of which extends in the column direction. One end of the source electrode 365 is connected to a corresponding data line, and the other end covers the source region of the active layer 34 . The source-drain electrode layer 36 may also include a plurality of first touch lines (not shown in the figure), each of which extends in the column direction. The plurality of data lines and the plurality of first touch lines are alternately arranged in the row direction. The source-drain electrode layer 36 is similar to or identical to the source-drain electrode layer 40 in FIG1 . The data lines are similar to or identical to the data lines S1, S2, …, Sn in FIG1 . The first touch lines are similar to or identical to the first touch lines Q1, Q2, …, Qn in FIG1 . The source-drain electrode layer 36 may further include a drain electrode 367 . One end of the drain electrode 367 is connected to the drain region of the active layer 34 , and the other end of the drain electrode 367 is connected to the pixel electrode.

[0080] The first insulating layer 371 can be disposed on a side of the source / drain electrode layer 36 away from the substrate 31 and covers the source / drain electrode layer 36 and the region of the gate insulating layer 33 not covered by the source / drain electrode layer 36. The first insulating layer 371 can be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0081] The touch electrode layer 38 can be disposed on a side of the first insulating layer 371 away from the substrate 31. The touch electrode layer 38 can include a plurality of second touch lines 382, ​​each of which extends in the row direction. The plurality of second touch lines 382 are intersected with the plurality of first touch lines, and a touch point can be formed at the intersection of the two. The material of the touch electrode layer 38 can be a metal such as copper, aluminum, or silver. The second touch lines 382 are similar to or identical to the second touch lines R1, R2, R3, ..., Rm-1, and Rm in Figure 1. A second touch line 382 can be disposed between adjacent pixel rows, or a second touch line 382 can be disposed between every two pixel rows or more.

[0082] The second insulating layer 373 may be disposed on a side of the touch electrode layer 38 away from the substrate 31 and cover the touch electrode layer 38 and the area of ​​the first insulating layer 371 not covered by the touch electrode layer 38. The second insulating layer 373 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0083] The pixel electrode layer 39 may be disposed on a side of the second insulating layer 373 away from the substrate 31. The pixel electrode layer 35 may include a plurality of pixel electrodes spaced apart from each other, each of which corresponds to a pixel. The pixel electrode layer 35 may be made of a transparent metal, such as ITO (indium tin oxide). The pixel electrode may be connected to the drain electrode 367 via a through hole (not shown), which passes through the second insulating layer 373 and the first insulating layer 371 to expose the data line.

[0084] The display substrate provided in this application may also be an IPS-type display substrate. The structure and manufacturing method of the IPS-type display substrate may be shown in Figures 6 to 8 and Figure 1. Figure 1 may be a top view of an IPS-type display substrate, Figure 6 is a schematic diagram of the manufacturing process of an IPS-type display substrate, Figure 7 is a schematic diagram of a cross-sectional structure of an IPS-type display substrate along the column direction, and Figure 8 is a schematic diagram of a cross-sectional structure of an IPS-type display substrate along the row direction.

[0085] Referring to Figures 6 and 8, and in conjunction with Figure 1 as necessary, the gate layer 42 can be provided on one surface of the substrate 41 (i.e., the front surface of the substrate 41). The gate layer 42 may include a gate 421, a scan line 427, and a common electrode line 423. The scan line 427 is spaced apart from the common electrode line 423 and both extend in the row direction. The scan line 427 is similar to or identical to the first scan lines G11, G21, G31, ..., G(m-1)1, Gm1 and the second scan lines G12, G22, G32, ..., G(m-1)2, Gm2 in Figure 1. The common electrode line 423 is used to connect multiple common electrodes or all common electrodes located in another film layer. The gate 421 is connected to the corresponding scan line 427 for receiving an electrical signal from the scan line 427. The gate 421 corresponds to the position of the channel in the active layer and is used to turn on or off the thin film transistor.

[0086] Since the common electrode lines 423 and the scan lines 427 are arranged in the same layer, they can be manufactured simultaneously during production, which helps reduce production costs. For example, a whole layer of metal material (e.g., copper, aluminum, silver, etc.) can be formed first, and then a portion of the metal material layer can be removed by etching to form a plurality of spaced scan lines 427 and one or more common electrode lines 423, thereby obtaining the gate layer 42. In some embodiments, the common electrode lines 423 can also be manufactured in a different layer from the scan lines 427. The common electrode lines 423 can be manufactured using a separate film layer.

[0087] The gate insulating layer 43 may be disposed on a side of the gate layer 42 away from the substrate 41 and cover the scan lines 427, the common electrode lines 423, and areas of the substrate 41 not covered by the scan lines 427 and the common electrode lines 423. The gate insulating layer 43 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0088] The active layer 44 may be disposed on a side of the gate insulating layer 43 away from the substrate 41. The active layer 44 may include a source region, a drain region, and a channel between the source and drain regions to form a thin film transistor. The active layer 44 may be made of single crystal silicon or polycrystalline silicon.

[0089] The source-drain electrode layer 46 may be disposed on a side of the active layer 44 away from the substrate 41. The source-drain electrode layer 46 may include multiple data lines (not shown in Figures 7 and 8) and multiple source electrodes 462, each of which extends in the column direction. The source electrode 462 is connected to a corresponding data line and is configured to receive an electrical signal from the data line. The source electrode 462 covers a portion of the surface of the active layer 44 and is configured to connect to the source region of the active layer 44. The source-drain electrode layer 46 may also include multiple first touch lines (not shown in Figures 7 and 8), each of which extends in the column direction. The multiple data lines and the multiple first touch lines are arranged alternately in the row direction. The source-drain electrode layer 46 is similar to or identical to the source-drain electrode layer 40 in Figure 1. The data lines are similar to or identical to the data lines S1, S2, ..., Sn in Figure 1. The first touch lines are similar to or identical to the first touch lines Q1, Q2, ..., Qn in Figure 1. The source-drain electrode layer 46 may further include a plurality of drain electrodes 469 , one end of each drain electrode 469 being connected to the drain region of the active layer 44 , and the other end of the drain electrode 469 being connected to the pixel electrode 45 of the corresponding pixel, thereby realizing the connection between the thin film transistor and the pixel.

[0090] The first insulating layer 47 can be disposed on a side of the source / drain electrode layer 46 away from the substrate 41 and covers the source / drain electrode layer 46 and the region of the gate insulating layer 43 not covered by the source / drain electrode layer 46. The first insulating layer 47 can be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0091] The electrode layer 490 can be disposed on a side of the first insulating layer 47 away from the substrate 41. The electrode layer 490 includes a plurality of pixel electrodes 45. The plurality of pixel electrodes 45 are spaced apart from each other, and each pixel electrode 45 corresponds to a pixel. The electrode layer 490 also includes a common electrode 49. The common electrode 49 can be disposed between adjacent pixel electrodes 45 and is used to cooperate with the corresponding pixel electrode 45 to form an electric field that controls the pixel display. The material of the electrode layer 490 can be a transparent metal, such as ITO (indium tin oxide).

[0092] The second insulating layer 485 can be disposed on a side of the electrode layer 490 away from the substrate 41 and covers the pixel electrode 45, the common electrode 49, and the area of ​​the first insulating layer 47 not covered by the pixel electrode 45 or the common electrode 49. The second insulating layer 485 can be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0093] The touch electrode layer 48 can be arranged on a side of the second insulating layer 485 away from the substrate 41. The touch electrode layer 48 can include a plurality of second touch lines 482, each of which extends in the row direction. The plurality of second touch lines 482 are arranged to intersect with the plurality of first touch lines, and the intersections of the two can form touch points. The material of the touch electrode layer 48 can be a metal such as copper, aluminum, or silver. The second touch lines 482 are similar to or identical to the second touch lines R1, R2, R3, ..., Rm-1, and Rm in Figure 1. A second touch line 482 can be provided between adjacent pixel rows, or a second touch line 482 can be provided between every two pixel rows or more pixel rows.

[0094] Figure 9 is a schematic diagram of an embodiment of the connection relationship between multiple first touch lines within a display substrate and a circuit board provided by the present application. Referring to Figure 9 and, if necessary, in conjunction with Figure 1 , the pixels are distributed throughout the entire pixel area 85. The area between the outermost edge 83 of the display substrate and the pixel area 85 is an edge area 87. Each of the first touch lines Q1, Q2, Q3, Q4, ..., Qn-1, and Qn extends in the column direction. The multiple first touch lines Q1, Q2, Q3, Q4, ..., Qn-1, and Qn are uniformly or substantially uniformly distributed throughout the pixel area 85.

[0095] Multiple adjacent first touch lines can be connected in parallel to form a first touch coil X. Multiple first touch coils X1, X2, X3, ..., X(j-2), X(j-1), and Xj are arranged sequentially along the row direction. For example, first touch lines Q1, Q2, Q3, and Q4 are connected in parallel to form first touch coils X1, ..., and first touch lines Qn-3, Qn-2, Qn-1, and Qn are connected in parallel to form first touch coil Xj. j can be any integer. For example, k can be 36. That is, the number of first touch coil groups X can be 36.

[0096] The term "plurality" herein includes two and more than two. In some embodiments, every two first touch lines can be connected in parallel to form a first touch coil. In some embodiments, every three first touch lines can be connected in parallel to form a first touch coil. In some embodiments, every five first touch lines can be connected in parallel to form a first touch coil.

[0097] Within the same first touch coil X, one end of all first touch wires is connected to a first touch connection wire 14, and the other end of all first touch wires is connected to a second touch connection wire 143. For example, within the first touch coil X1, the first ends (upper ends in FIG. 9 ) of all first touch wires Q1, Q2, Q3, and Q4 are connected to the first touch connection wire 14, and the second ends (lower ends in FIG. 9 ) of all first touch wires Q1, Q2, Q3, and Q4 are connected to the second touch connection wire 143.

[0098] In some embodiments, the first ends of all first touch lines Q1, Q2, Q3, Q4, ..., Qn-1, Qn of all first touch coils X1, X2, X3, ..., X(j-2), X(j-1), Xj are connected to the same first touch connection line 14. Therefore, the first touch connection line 14 can be referred to as a global touch connection line 14. The second ends of different first touch coils X1, X2, X3, ..., X(j-2), X(j-1), Xj are connected to different second touch connection lines 143. Therefore, the second touch connection line 143 can be referred to as a local touch connection line 143).

[0099] The global touch connection line 14 and the multiple local touch connection lines 143 can be connected to different pins 812 of the electromagnetic induction circuit board 81. The two ends of the global touch connection line 14 can each be connected to a pin 812 of the electromagnetic induction circuit board 81 through a wire 52, and the multiple local touch connection lines 143 can be connected to other pins 812 of the electromagnetic induction circuit board 81 through other wires 53.

[0100] In some embodiments, the global touch connection lines 14 and the local touch connection lines 143 and the first touch coils X1, X2, X3, ..., X(j-2), X(j-1), and Xj can be arranged on the same layer. In some embodiments, the global touch connection lines 14 and the local touch connection lines 143 can be arranged on the same layer, but not on the same layer as the first touch coils X1, X2, X3, ..., X(j-2), X(j-1), and Xj, and they can be connected via metal vias.

[0101] In some embodiments, the global touch connection lines 14 can be disposed in the edge region 87. In some embodiments, the electromagnetic induction circuit board 81 can be disposed in the edge region 87. In some embodiments, both the global touch connection lines 14 and the local touch connection lines 143 can extend in the row direction. In some embodiments, the electromagnetic induction circuit board 81 can be a flexible printed circuit (FPC) that implements touch functionality using electromagnetic induction.

[0102] In the above embodiment, the touch connection lines 14 extending along the row direction can prevent touch voltage drift, which can easily lead to a greenish display phenomenon in which red and blue pixels appear darker and green pixels appear brighter.

[0103] FIG10 is a schematic diagram of an embodiment of the connection relationship between multiple second touch lines and a circuit board within a display substrate provided by the present application. Referring to FIG10 and, if necessary, in conjunction with FIG1 , the pixels are distributed throughout the entire pixel area 85. The area between the outermost edge 83 of the display substrate and the pixel area 85 is an edge area 87. Each second touch line R1, R2, R3, R4, …, Rm-3, Rm-2, Rm-1, and Rm extends in the row direction. The multiple second touch lines R1, R2, R3, R4, …, Rm-3, Rm-2, Rm-1, and Rm are uniformly or approximately uniformly distributed throughout the pixel area 85.

[0104] Multiple adjacent second touch lines can be connected in parallel to form a second touch coil Y. Multiple second touch coils Y1, Y2, Y3, ..., Y(k-2), Y(k-1), and Yk are arranged sequentially along the column direction. For example, second touch lines R1, R2, R3, and R4 are connected in parallel to form second touch coils Y1, ..., and second touch lines Rm-3, Rm-2, Rm-1, and Rm are connected in parallel to form second touch coil Yk. k can be any positive integer. For example, k can be 23. That is, the number of second touch coil groups can be 23.

[0105] The term "plurality" herein includes two and more than two. In some embodiments, every two second touch lines can be connected in parallel to form a second touch coil. In some embodiments, every three second touch lines can be connected in parallel to form a second touch coil. In some embodiments, every five second touch lines can be connected in parallel to form a second touch coil.

[0106] Within the same second touch coil Y, one end of all second touch lines is connected to a third touch connection line 74, and the other end of all second touch lines is connected to a fourth touch connection line 743. For example, within the second touch coil Y1, the first ends (left ends in FIG. 10 ) of all second touch lines R1, R2, R3, and R4 are connected to the third touch connection line 74, and the second ends (right ends in FIG. 10 ) of all second touch lines R1, R2, R3, and R4 are connected to the fourth touch connection line 743.

[0107] In some embodiments, the first ends of all second touch lines R1, R2, R3, R4, ..., Rm-3, Rm-2, Rm-1, and Rm of all second touch coils Y1, Y2, Y3, ..., Y(k-2), Y(k-1), and Yk are connected to the same third touch connection line 74. Therefore, the third touch connection line 74 can be referred to as a global touch connection line 74. The second ends of different second touch coils Y1, Y2, Y3, ..., Y(k-2), Y(k-1), and Yk are connected to different fourth touch connection lines 743. Therefore, the fourth touch connection line 743 can also be referred to as a local touch connection line 743.

[0108] The global touch connection line 74 and the multiple local touch connection lines 743 can be connected to different pins 812 of the electromagnetic induction circuit board 81. One end (the lower end in FIG. 10 ) of the global touch connection line 74 can be connected to a pin 812 of the electromagnetic induction circuit board 81 via a wire 52, and the multiple local touch connection lines 743 can be connected to other pins 812 of the electromagnetic induction circuit board 81 via other wires 53.

[0109] In some embodiments, the global touch connection lines 74 may be disposed in the edge region 87. In some embodiments, the electromagnetic induction circuit board 81 may be disposed in the edge region 87. In some embodiments, the global touch connection lines 74 and the local touch connection lines 743 may extend along the column direction.

[0110] In some embodiments, the global touch connection lines 74 and the local touch connection lines 743 and the second touch coils Y1, Y2, Y3, ..., Y(k-2), Y(k-1), and Yk can be arranged on the same layer. In some embodiments, the global touch connection lines 74 and the local touch connection lines 743 can be arranged on the same layer, but not on the same layer as the second touch coils Y1, Y2, Y3, ..., Y(k-2), Y(k-1), and Yk. They can be connected via metal vias.

[0111] In some embodiments, the electromagnetic induction circuit board connected to the second touch coils Y1, Y2, Y3, ..., Y(k-2), Y(k-1), and Yk and the electromagnetic induction circuit board connected to the first touch coils X1, X2, X3, ..., X(j-2), X(j-1), and Xj can be the same circuit board. They only need to be connected to different pins of the circuit board.

[0112] The present application also provides a display panel, which may include the display substrate as described above and a color filter substrate disposed opposite to the display substrate.

[0113] The present application also provides a display device, which may be a liquid crystal display device, such as a mobile phone, including the display panel described above.

[0114] It is understandable that the display device may further include a backlight source, a light guide plate, a liquid crystal layer between the display substrate and the color filter substrate, a polarizer, a protective glass and other well-known structures, which will not be described in detail here.

[0115] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0116] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0117] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A display substrate, characterized in that: include: A substrate, a pixel array disposed on the substrate, a source-drain electrode layer, and a plurality of scan line groups, wherein the source-drain electrode layer includes a plurality of data lines and a plurality of first touch control lines; The pixel array includes a plurality of pixel groups arranged along a row direction, each of the pixel groups includes a first sub-pixel column and a second sub-pixel column that are adjacent to each other, the data line is arranged between the first sub-pixel column and the second sub-pixel column, and is connected to the first sub-pixel column and the second sub-pixel column, the first touch line is arranged between two adjacent pixel groups and extends along a column direction; a plurality of adjacent first touch lines are connected in parallel to form a first touch coil, and the plurality of first touch coils are arranged along a row direction; Each of the scan line groups corresponds to a pixel row, and the scan line groups include a first scan line and a second scan line respectively arranged on both sides of the corresponding pixel row, the first scan line and the second scan line both extend along the row direction, the first scan line is connected to the pixels located in each first sub-pixel column in the corresponding pixel row, and the second scan line is connected to the pixels located in each second sub-pixel column in the corresponding pixel row.

2. The display substrate according to claim 1, characterized in that: Also includes: A gate layer, disposed on one side of the substrate, including the plurality of scanning line groups and common electrode lines; A gate insulating layer, disposed on a side of the gate layer away from the substrate, and covering the plurality of scanning line groups and the common electrode lines; The active layer is arranged on a side of the gate insulating layer away from the substrate.

3. The display substrate according to claim 2, characterized in that: Also includes: A pixel electrode layer is arranged on a side of the gate insulating layer away from the substrate, the pixel electrode layer comprises a plurality of pixel electrodes, the plurality of pixel electrodes are spaced apart from each other, and the source-drain electrode layer is arranged on a side of the active layer and the pixel electrode layer away from the substrate; The first insulating layer is arranged on a side of the source-drain electrode layer away from the substrate and covers the The source-drain electrode layer and the pixel electrode layer; A touch electrode layer, disposed on a side of the first insulating layer away from the substrate, the touch electrode layer comprising a plurality of second touch lines extending along the row direction; a second insulating layer, disposed on a side of the touch electrode layer away from the substrate and covering the touch electrode layer; The common electrode layer is arranged on a side of the second insulating layer away from the substrate.

4. The display substrate according to claim 2, characterized in that: The source-drain electrode layer is arranged on a side of the active layer away from the substrate.

5. The display substrate according to claim 4, characterized in that: Also includes: A first insulating layer, disposed on a side of the source-drain electrode layer away from the substrate, and covering the source-drain electrode layer; The touch electrode layer is disposed on a side of the first insulating layer away from the substrate. The touch electrode layer includes a plurality of second touch lines extending along a row direction.

6. The display substrate according to claim 5, characterized in that: Also includes: a second insulating layer, disposed on a side of the touch electrode layer away from the substrate and covering the touch electrode layer; The pixel electrode layer is arranged on a side of the second insulating layer away from the substrate, and the pixel electrode layer includes a plurality of pixel electrodes.

7. The display substrate according to claim 4, characterized in that: Also includes: A first insulating layer, disposed on a side of the source-drain electrode layer away from the substrate, and covering the source-drain electrode layer; an electrode layer, disposed on a side of the first insulating layer away from the substrate, the electrode layer comprising a plurality of pixel electrodes and a common electrode, the common electrode being disposed between adjacent pixel electrodes; A second insulating layer, disposed on a side of the electrode layer away from the substrate, and covering the pixel electrode and the common electrode; The touch electrode layer is disposed on a side of the second insulating layer away from the substrate. The touch electrode layer includes a plurality of second touch lines extending along a row direction.

8. The display substrate according to claim 1, characterized in that: In the same first touch control coil, the first ends of all the first touch control lines are connected to a first touch control connection line, and the second ends of all the first touch control lines are connected to a second touch control connection line.

9. The display substrate according to claim 8, characterized in that: The first ends of all the first touch control wires in all the first touch control coils are connected to the same first touch control connection wire; The second ends of different first touch coils are connected to different second touch connecting lines.

10. The display substrate according to claim 8, characterized in that: Different touch connection lines are connected to different pins of the electromagnetic induction circuit board.

11. The display substrate according to claim 1, characterized in that: Also included are a plurality of second touch control lines, wherein the second touch control lines extend along the row direction; A plurality of adjacent second touch control lines are connected in parallel to form a second touch control coil, and the plurality of second touch control coils are arranged in sequence along a column direction; In the same second touch coil, the first ends of all the second touch wires are connected to a third touch connection wire, and the second ends of all the second touch wires are connected to a fourth touch connection wire.

12. The display substrate according to claim 11, characterized in that: The first ends of all the second touch control wires in all the second touch control coils are connected to the same third touch control connection wire; The second ends of different second touch coils are connected to different fourth touch connecting lines.

13. The display substrate according to claim 11, characterized in that: Different touch connection lines are connected to different pins of the electromagnetic induction circuit board.

14. A display panel, characterized in that: Comprising the display substrate according to any one of claims 1-13.

15. A display device, characterized in that: Comprising the display panel according to claim 14.

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