Digital circuit for controlling same register with different MIPI buses, and electronic device

Abstract

Disclosed in the present invention are a digital circuit for controlling the same register with different MIPI buses, and an electronic device. The digital circuit comprises a first MIPI module, a second MIPI module and a shared register module, wherein an input end of the first MIPI module is connected to a first MIPI bus; an input end of the second MIPI module is connected to a second MIPI bus; output ends of the first MIPI module and the second MIPI module are separately connected to the shared register module by means of data buses; and a serial clock signal line in the first MIPI bus and a serial clock signal line in the second MIPI bus are separately connected to the shared register module. When different MIPI buses issue write or trigger and reset operations, the first MIPI module and / or the second MIPI module work cooperatively with the shared register module, thus realizing the control of the same register by the different MIPI buses.

Description

A digital circuit and electronic device for controlling the same register using different MIPI buses Technical Field

[0001] The present invention relates to a digital circuit in which different MIPI buses control the same register, and also relates to an electronic device including the digital circuit, belonging to the technical field of digital circuits. Background Art

[0002] With the continuous advancement of integrated circuit technology, the integration of RF front-end chips is becoming increasingly higher. The L-PAMiD (LNA - Power Amplifier Module Integrated Duplexer) is a highly integrated RF front-end chip. L-PAMiD integrates components such as a power amplifier (PA), a low-noise amplifier (LNA), a filter, an antenna switch (ASW), a multi-band switch (XSW), and duplexers / multiplexers. Its advantage is that it reduces the area and power consumption of the RF front-end.

[0003] Typically, a highly integrated RF front-end has more than two MIPI (Mobile Industry Processor Interface) buses, and integrates numerous op amps and control switch components. For flexible configuration and ease of use, some control switches can accept operation commands sent from different MIPI buses. This requires that the internal registers that control these switches can accept MIPI commands sent from different MIPI buses. According to the MIPI protocol, the internal registers of these control switches are user-defined registers (UDRs), which must respond not only to write commands, but also to MIPI commands such as trigger, reset, and mask write.

[0004] In the prior art, MIPI user-defined registers are implemented as registers in digital circuits. The level of the register's output terminal Q jumps to the level of its input terminal D on a clock edge, or is reset by a valid reset signal. This implementation is not a problem when a single bus controls the register, but when different buses control the same register, conflicts may arise due to different clock signals driving the same register. Therefore, it is necessary to provide a digital circuit that can achieve the above requirements by allowing different MIPI buses to control the same register.

[0005] Chinese invention patent application number 201810703855.9 discloses a serial communication device and method. The serial communication device includes a radio frequency front-end module and a radio frequency device. The first and second input interfaces of the radio frequency front-end module are connected to the output interface of a main control module. When the first output interface of the radio frequency front-end module is connected to the first input interface of at least one radio frequency device via a first signal bus, the second output interface of the radio frequency front-end module is connected to the second input interface of at least one radio frequency device via a second signal bus. This serial communication device can meet the needs of convenient and fast one-way communication between individual chips in the radio frequency front-end module and within individual chips.

[0006] Summary of the Invention

[0007] The primary technical problem to be solved by the present invention is to provide a digital circuit in which different MIPI buses control the same register.

[0008] Another technical problem to be solved by the present invention is to provide an electronic device including the digital circuit.

[0009] In order to achieve the above object, the present invention adopts the following technical solutions:

[0010] According to a first aspect of an embodiment of the present invention, there is provided a digital circuit for controlling the same register by different MIPI buses, comprising at least a first MIPI module, a second MIPI module and a shared register module; wherein,

[0011] The input end of the first MIPI module is connected to the first MIPI bus, and the input end of the second MIPI module is connected to the second MIPI bus; the output ends of the first MIPI module and the second MIPI module are respectively connected to the shared register module through the data bus; at the same time, the serial clock signal line in the first MIPI bus and the serial clock signal line in the second MIPI bus are respectively connected to the shared register module;

[0012] The first MIPI module and the second MIPI module are both MIPI interface modules; the shared register module is a user-defined register.

[0013] Optionally, when receiving a MIPI instruction, the first MIPI module or the second MIPI module generates a corresponding flag signal that lasts for one clock cycle and outputs it to the shared register module; the shared register module uses the flag signal to generate a single-pulse clock signal, so that the register data jumps on the rising edge of the single-pulse clock signal.

[0014] Optionally, when the first MIPI bus or the second MIPI bus performs a write operation on the shared register module, it generates an internal flag signal recording the last bus performing the write operation, so that the shared register module only responds to the trigger or reset operation issued by the bus.

[0015] Optionally, the first MIPI module is composed of a main logic circuit and a flag register group; wherein,

[0016] An input end of the main logic circuit is connected to the first MIPI bus, and an internal data line output from the main logic circuit is connected to an input end of the flag register group;

[0017] The data cache bus and register address bus output from the main logic circuit, and the flag data lines for write, trigger, and reset operations output from the flag register grouper together constitute an output data line and are connected to the shared register module;

[0018] Optionally, the shared register module is composed of a first logic gate, a second logic gate, a third logic gate, an OR logic gate and a register group; wherein the first logic gate, the second logic gate and the third logic gate are all logic combination circuits, and constitute a control logic circuit with the OR logic gate; the register group is a shared register and a register cache composed of multiple registers of the same structure.

[0019] Optionally, the first logic gate and the second logic gate are used to provide a clock signal for the register group; wherein the input ends of the first logic gate are respectively connected to the flag data bus and the register address bus in the data line output from the first MIPI module, and the serial clock signal line in the first MIPI bus; the input ends of the second logic gate are respectively connected to the flag data bus and the register address bus in the data line output from the second MIPI module, and the serial clock signal line in the second MIPI bus; the output ends of the first logic gate and the second logic gate are respectively connected to the OR logic gate, and the output end of the OR logic gate is connected to the clock end of the register group.

[0020] Optionally, the third logic gate is used to provide an input signal for the register group; wherein the input end of the third logic gate is respectively connected to the data cache bus and the flag data bus output from the first MIPI module and the second MIPI module, and the current signal bus of the register cache in the register group; the output end of the third logic gate is connected to the input end of the register group.

[0021] Optionally, the internal flag signal line of the shared register module is connected to the input ends of the first logic gate, the second logic gate and the third logic gate respectively.

[0022] Optionally, in trigger mode, when a MIPI bus writes to the shared register module, the written data first enters the register cache, and when the shared register module is triggered, the data in the register cache is called and written into the shared register.

[0023] According to a second aspect of an embodiment of the present invention, an electronic device is provided, comprising the digital circuit in which different MIPI buses control the same register.

[0024] Compared with the prior art, the digital circuit for controlling the same register by different MIPI buses provided by the present invention, when performing operations such as write, reset, and trigger on different buses, generates a flag signal and a single-pulse clock signal for the corresponding operation, and controls and manages the corresponding operation through logical operation processing. This technical solution solves the need for different MIPI buses to control the same register without affecting the function of the MIPI daughter chip, and minimizes the possibility of metastable conditions caused by competition between different buses for the control of the same register. Therefore, the digital circuit for controlling the same register by different MIPI buses provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, and excellent circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a block diagram of a digital circuit for controlling the same register using different MIPI buses provided by the present invention;

[0026] FIG2 is a block diagram of a digital circuit in which different MIPI buses control the same register in an embodiment of the present invention;

[0027] FIG3 is a circuit diagram of a first MIPI module in an embodiment of the present invention;

[0028] FIG4 is a circuit diagram of a shared register module according to an embodiment of the present invention;

[0029] FIG5 is a timing diagram of a digital circuit performing a write operation in an embodiment of the present invention.

[0030] FIG6 is a timing diagram of a digital circuit performing a trigger reset operation in an embodiment of the present invention.

[0031] FIG7 is a schematic diagram of an electronic device that uses different MIPI buses provided by the present invention to control digital circuits of the same register. DETAILED DESCRIPTION

[0032] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] As shown in Figure 1, the present invention provides a digital circuit in which different MIPI buses control the same register, which includes at least a first MIPI module 1, a second MIPI module 3 and a shared register module; wherein the input end of the first MIPI module 1 is connected to the first MIPI bus, and the input end of the second MIPI module 3 is connected to the second MIPI bus; the output ends of the first MIPI module 1 and the second MIPI module 3 are respectively connected to the shared register module through a data bus; at the same time, the serial clock signal line SCLK1 in the first MIPI bus and the serial clock signal line SCLK3 in the second MIPI bus are respectively connected to the shared register module.

[0034] The first MIPI module 1 and the second MIPI module 3 are connected to the control paths of different MIPI buses and are both MIPI interface modules with the complete sub-chip functionality specified in the MIPI protocol. The data bus at their outputs includes flags for MIPI module writes, triggers, resets, and mask writes, as well as other data.

[0035] The shared register module is a user-defined register that can respond to MIPI instructions such as write, trigger, reset, mask write, etc. As shown in Figure 2, in one embodiment of the present invention, the shared register module can also be set inside the first MIPI module or the second MIPI module.

[0036] When receiving a MIPI instruction, the first MIPI module or the second MIPI module generates a corresponding flag signal that lasts for one clock cycle and outputs it to the shared register module; the shared register module uses the flag signal to generate a single-pulse clock signal, causing the register data to jump on the rising edge of the single-pulse clock signal.

[0037] When the first MIPI bus or the second MIPI bus performs a write operation on the shared register module, it generates an internal flag signal that records the last write operation performed on the bus, so that the shared register module only responds to the trigger or reset operation issued by the bus.

[0038] As shown in Figure 3, in one embodiment of the present invention, the structural composition and working principle of the first MIPI module and the second MIPI module are exactly the same. The first MIPI module is used as an example for explanation below. The first MIPI module is composed of a main logic circuit and a flag register group; wherein, the input end of the main logic circuit is connected to the first MIPI bus, and the internal data line output from the main logic circuit is connected to the input end of the flag register group; the data cache bus and register address bus output from the main logic circuit, and the flag data lines for write operation (Write), trigger operation (Trigger), reset operation (Reset) and mask write (Mask Write) operation output from the flag register group together constitute the output data line and are connected to the shared register module; the IO (input / output) bus is also output from the main logic circuit and connected to subsequent related functional modules. Depending on the application scenario, the data line output from the flag register group may not include the flag data line for the mask write (Mask Write) operation.

[0039] The main logic circuit is used to implement the sending and receiving of MIPI data packets and the functions of the sub-chip specified in the MIPI protocol. For non-shared registers, the main logic circuit assigns values ​​to them and sends them to subsequent modules in the form of IO.

[0040] The data cache is a buffer of the serial data signal SDATA of the MIPI data packet by the main logic circuit. Its width is 8 bits and is used to directly assign values ​​to the shared register or to enable the auxiliary flag bit. The register address is the register address of the target register in the current MIPI instruction.

[0041] The flag register group is used to analyze internal data on the falling edge of the serial clock signal SCLK of the first MIPI bus and output a flag signal that lasts only one clock cycle for operations such as write or reset. The number of registers in the flag register group is the same as the number of flag signals, typically three or four flag registers.

[0042] It should be noted that the flag data lines for write, trigger, reset and mask write operations output from the flag register grouper can be either independent GPIOs or encoded bus forms.

[0043] As shown in Figure 4, in one embodiment of the present invention, a shared register module is composed of a first logic gate 1, a second logic gate 2, a third logic gate 3, an OR logic gate, and a register group. The first logic gate 1, the second logic gate 2, the third logic gate 3, and the OR logic gate constitute a control logic circuit. The first logic gate 1, the second logic gate 2, and the third logic gate 3 are each a series of logical combination circuits that implement different functions. The register group is a shared register and register cache composed of multiple registers of the same structure. When a trigger operation is performed on the register module, the data in the shared registers in the register group is updated to the data value in the register cache. It should be noted that in Figure 4, for convenience of expression, a single register symbol is used to represent the shared register and register cache.

[0044] The first logic gate 1 and the second logic gate 2 are used to provide a clock signal for the register group. The input end of the first logic gate 1 is respectively connected to the flag data bus 1 and register address bus 1 in the output data line of the first MIPI module, and the serial clock signal line SCLK1 in the first MIPI bus. The input end of the second logic gate 2 is respectively connected to the flag data bus 3 and register address bus 3 in the output data line of the second MIPI module, and the serial clock signal line SCLK3 in the second MIPI bus. The output ends of the first logic gate 1 and the second logic gate 2 are respectively connected to the OR logic gate, and the output end of the OR logic gate is connected to the clock end of the register group.

[0045] The third logic gate 3 is used to provide input signals to the register group. The inputs of the third logic gate 3 are connected to the data cache bus and flag data bus output by the first and second MIPI modules, respectively, as well as the current signal bus of the register cache in the register group. The output of the third logic gate 3 is connected to the input of the register group. The output of the shared register in the register group is transmitted to subsequent modules in IO form.

[0046] The shared register module's internal flag signal line Reg_BUS is connected to the inputs of the first logic gate 1, the second logic gate 2, and the third logic gate 3. This internal flag signal line Reg_BUS is used to record the bus that last performed a write operation on the shared register module; the shared register module only responds to trigger and reset operations issued by the bus that last performed a write operation on the register module.

[0047] The first logic gate 1 and the second logic gate 2 respectively intercept their respective serial clock signals (SCLK1 or SCLK3) using the information of the flag data bus, register address bus and internal flag signal line Reg_BUS output by their respective MIPI modules, extract a clock signal from dozens of serial clock signals in the MIPI command frame, and use the clock signal to trigger the shared register.

[0048] The third logic gate 3 generates input data to be sent to the shared register by using the information of the data cache bus, the flag data line and the internal flag signal line Reg_BUS output by the first MIPI module and the second MIPI module.

[0049] It should be noted that, in this embodiment, each shared register in the register group has only one register cache for triggering; in other embodiments of the present invention, two register caches for triggering can be configured for each shared register, so that each MIPI bus has its own register cache.

[0050] It should be noted that, in other embodiments of the present invention, the digital circuit in which different MIPI buses control the same register may also include multiple first MIPI modules, multiple second MIPI modules and multiple shared register modules; wherein, the multiple first MIPI modules and the multiple second MIPI modules are respectively connected to the control paths of different MIPI buses, and the output ends of the corresponding first MIPI modules and the second MIPI modules are respectively connected to the corresponding shared register modules through the data bus, so as to realize that different MIPI buses control multiple shared register modules.

[0051] The following describes the working principle and working mechanism of the digital circuit for controlling the same register by different MIPI buses provided by the present invention by performing write and trigger reset operations on the shared register module.

[0052] The timing coordination of the digital circuits for controlling the same register by different MIPI buses provided by the present invention when performing write operations is shown in Figure 5. In the figure, the shared register Reg6 working in non-trigger mode is taken as an example. The write instructions for different MIPI buses can be received, decoded and sent to the shared register module by the MIPI module, and the value of the shared register Reg6 will also change immediately. In addition, when a MIPI bus writes to register Reg6, the write flag BUS_Write of the MIPI module of the bus will output a pulse signal, which intercepts a single pulse clock signal Reg6_CLK from the serial clock signal SCLK of its own MIPI bus. At the same time, the internal flag signal line Reg6_BUS in the shared register module will also record the bus that last performed the write operation. The shared register data Reg6_DATA and the register buffer Reg6_BUFF jump on the rising edge of the single pulse clock signal Reg6_CLK.

[0053] For example, in Figure 5, at time a, the first MIPI bus issues a write operation instruction. The write flag bit BUS1_Write of the first MIPI bus will output a pulse signal with a width from time a to time c. This pulse signal extracts a single-pulse clock signal Reg6_CLK from the serial clock signal SCLK1 of the first MIPI bus, with a width from time b to time c. At the same time, the internal flag signal line Reg6_BUS in the shared register module will record that the first MIPI bus that performed the last write operation is BUS1. The shared register data Reg6_DATA and register buffer Reg6_BUFF jump at the rising edge of the single-pulse clock signal Reg6_CLK, that is, at time b, and the value of the shared register Reg6 also changes.

[0054] Figure 6 illustrates the timing coordination of trigger and reset operations for digital circuits using different MIPI buses to control the same register. The shared register only responds to trigger and reset operations from the bus that last wrote to the shared register. The figure uses shared register Reg6 as an example to illustrate the timing coordination of this mechanism.

[0055] In trigger mode, when the MIPI1 bus or MIPI3 bus performs a write operation on the shared register Reg6, the written data does not immediately enter the register data Reg6_DATA, but first enters the register buffer Reg6_BUFF, and then calls the write register data Reg6_DATA when Reg6 is triggered. When the MIPI1 bus or MIPI3 bus performs a write operation on the shared register Reg6, the register flag Reg6_BUS will record the MIPI bus that performed the last write operation. Reg6 only responds to trigger and reset operations issued by the MIPI bus recorded by Reg6_BUS.

[0056] For example, in Figure 6, at time b, the first MIPI bus (marked as BUS1 in the figure) performs a write operation on the shared register Reg6, and the written data AA first enters the register cache Reg6_BUFF; at the same time, the register flag Reg6_BUS records the bus BUS1 that performs the write operation.

[0057] When the first or second MIPI bus performs a write operation on the shared register Reg6, or when the bus recorded by the register flag Reg6_BUS performs a trigger and reset operation on the shared register Reg6, a corresponding flag signal with a duration of one clock cycle is generated, namely BUS1_Write, BUS1_Trigger, BUS1_Reset or BUS3_Write, BUS3_Trigger, BUS3_Reset in the figure. The shared register module uses the above flag signal to intercept a single-pulse clock signal Reg6_CLK from the corresponding serial clock signal SCLK. The register values ​​of the register data Reg6_DATA and the register buffer Reg6_BUFF both jump on the rising edge of the clock signal Reg6_CLK.

[0058] For example, in FIG6 , at time b and time e of the rising edge of the clock signal Reg6_CLK, the register buffer Reg6_BUFF and the register data Reg6_DATA jump successively.

[0059] The above describes in detail the composition structure and working principle of the digital circuit for controlling the same register by different MIPI buses provided by the present invention. Based on the above-mentioned digital circuit for controlling the same register by different MIPI buses, an embodiment of the present invention further provides an electronic device, which includes the above-mentioned digital circuit for controlling the same register by different MIPI buses, and the digital circuit is an important component of the radio frequency communication component, and is used to realize the communication control in the transmission and / or reception related components. The electronic device mentioned here refers to a computer device that can be used in a mobile environment and supports multiple communication standards such as GSM, EDGE, CDMA, TD_SCDMA, WCDMA, TDD_LTE, FDD_LTE, NR, etc., including mobile phones, laptops, tablet computers, car computers, etc. In addition, the technical solution provided by the present invention is also applicable to other occasions where radio frequency integrated circuits are applied, such as communication base stations, smart connected cars, etc.

[0060] As shown in Figure 7, the electronic device includes at least a processor, a memory and a communication component, and may further include a sensor component, a power component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, communication component, sensor component, power component, multimedia component and input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. can all be implemented using general components and are not specifically described here.

[0061] In summary, compared with the prior art, the digital circuit for controlling the same register by different MIPI buses provided by the present invention, when performing operations such as writing, resetting, and triggering on different buses, generates a flag signal and a single-pulse clock signal for the corresponding operation, and controls and manages the corresponding operation through logical operation processing. This technical solution solves the need for different MIPI buses to control the same register without affecting the function of the MIPI sub-chip, and minimizes the possibility of metastable conditions caused by competition between different buses for the control of the same register. Therefore, the digital circuit for controlling the same register by different MIPI buses provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, and excellent circuit performance.

[0062] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0063] The above describes in detail the digital circuit and electronic device for controlling the same register using different MIPI buses provided by the present invention. For those skilled in the art, any obvious modification made to the present invention without departing from the essence of the present invention will constitute an infringement of the patent rights of the present invention and will result in corresponding legal liability.

Claims

1. A digital circuit for controlling the same register by different MIPI buses, characterized in that At least includes a first MIPI module, a second MIPI module and a shared register module; wherein, The input end of the first MIPI module is connected to the first MIPI bus, and the input end of the second MIPI module is connected to the second MIPI bus; the output ends of the first MIPI module and the second MIPI module are respectively connected to the common register module through the data bus; at the same time, the serial clock signal line in the first MIPI bus and the serial clock signal line in the second MIPI bus are respectively connected to the common register module; The first MIPI module and the second MIPI module are both MIPI interface modules; the shared register module is a user-defined register.

2. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 1, characterized in that: When receiving a MIPI instruction, the first MIPI module or the second MIPI module generates a corresponding flag signal that lasts for one clock cycle and outputs it to the shared register module; the shared register module uses the flag signal to generate a single-pulse clock signal, so that the register data jumps on the rising edge of the single-pulse clock signal.

3. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 1, characterized in that: When the first MIPI bus or the second MIPI bus performs a write operation on the shared register module, it generates an internal flag signal recording the last bus performing the write operation, so that the shared register module only responds to the trigger or reset operation issued by the bus.

4. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 1, characterized in that: The first MIPI module is composed of a main logic circuit and a flag register group; wherein, An input end of the main logic circuit is connected to the first MIPI bus, and an internal data line output from the main logic circuit is connected to an input end of the flag register group; The data cache bus and register address bus output from the main logic circuit, and the flag data line of write, trigger, and reset operations output from the flag register grouper together form an output data line, and are connected to the common register module; 5. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 1, characterized in that: The shared register module is composed of a first logic gate, a second logic gate, a third logic gate, or a logic gate and a register group; wherein the first logic gate, the second logic gate and the third logic gate are all logic combination circuits, and together with the or logic gate constitute a control logic circuit; the register group is a shared register and a register cache composed of multiple registers of the same structure.

6. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 5, characterized in that: The first logic gate and the second logic gate are used to provide a clock signal for the register group; wherein, the input end of the first logic gate is respectively connected to the flag data bus and the register address bus in the data line output from the first MIPI module, and the serial clock signal line in the first MIPI bus; the input end of the second logic gate is respectively connected to the flag data bus and the register address bus in the data line output from the second MIPI module, and the serial clock signal line in the second MIPI bus; the output ends of the first logic gate and the second logic gate are respectively connected to the OR logic gate, and the output end of the OR logic gate is connected to the clock end of the register group.

7. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 5, characterized in that: The third logic gate is used to provide an input signal to the register group; wherein the third logic gate The input ends of the gate are respectively connected to the data cache bus and the flag data bus output from the first MIPI module and the second MIPI module, and the current signal bus of the register cache in the register group; the output end of the third logic gate is connected to the input end of the register group.

8. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 5, characterized in that: The internal flag signal line of the shared register module is connected to the input ends of the first logic gate, the second logic gate and the third logic gate respectively.

9. The digital circuit for controlling the same register by different MIPI buses as claimed in claim 1, characterized in that: In the trigger mode, when a MIPI bus writes to the shared register module, the written data first enters the register cache, and when the shared register module is triggered, the data in the register cache is called and written into the shared register.

10. An electronic device, characterized in that A digital circuit comprising different MIPI buses controlling the same register as described in any one of claims 1 to 9.

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