Memory array, electronic device, and operation method for memory array

Abstract

At least one embodiment of the present disclosure provides a memory array, an electronic device, and an operation method for a memory array. The memory array comprises a plurality of non-volatile static memory storage units, a plurality of power lines, and a plurality of ground lines. The plurality of non-volatile static memory storage units are arranged into a plurality of rows and a plurality of columns and are configured to perform data storage and data backup and recovery. The plurality of power lines are configured to provide the plurality of non-volatile static memory storage units with a first power supply voltage, the plurality of power lines each being electrically connected to a corresponding column of storage units in a first direction, and the plurality of power lines being shorted in a second direction. The plurality of ground lines are configured to provide the plurality of non-volatile static memory storage units with a second power supply voltage, the plurality of ground lines each being electrically connected to a corresponding column of storage units in the first direction, and the plurality of ground lines being shorted in the second direction. According to the described memory array, when data recovery is performed in one row of storage units at the same time, the voltages of the power lines can be kept stable.

Description

Memory array, electronic device, and memory array operating method

[0001] This application claims priority to Chinese Patent Application No. 202311595782.3 filed on November 27, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a memory array, an electronic device, and a method for operating the memory array. Background Art

[0003] When a memory array performs data operations, a conductive path from the power supply to the ground may be formed in the memory cells. If the same power line in the memory array is simultaneously connected to multiple memory cells that need to perform data operations simultaneously, this may cause excessive power current and insufficient power supply capacity during the data operations, which may in turn cause the data operations to fail. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a memory array, which includes: a plurality of non-volatile static memory storage cells arranged in multiple rows and columns and configured to perform data storage and data backup and recovery; a plurality of power lines configured to provide a first power supply voltage to the plurality of non-volatile static memory storage cells, wherein the plurality of power lines are electrically connected to corresponding storage cell columns in a first direction, and the plurality of power lines are short-circuited in a second direction, and the first direction is different from the second direction; and a plurality of ground lines configured to provide a second power supply voltage to the plurality of non-volatile static memory storage cells, wherein the plurality of ground lines are electrically connected to corresponding storage cell columns in the first direction, and the plurality of ground lines are short-circuited in the second direction.

[0005] For example, a memory array provided in some embodiments of the present disclosure further includes: a plurality of bit lines, respectively electrically connected to the corresponding columns of the non-volatile static memory storage cells in the first direction to transmit data signals; a plurality of first control lines, respectively electrically connected to the corresponding rows of the non-volatile static memory storage cells in the second direction to transmit first control signals; and a plurality of word lines, respectively electrically connected to the corresponding rows of the non-volatile static memory storage cells in the second direction to transmit word line signals.

[0006] For example, in a memory array provided in some embodiments of the present disclosure, each of the multiple non-volatile static memory storage units includes a volatile storage sub-unit and a non-volatile storage sub-unit; the volatile storage sub-unit is configured to transfer the stored first data and / or second data to the non-volatile storage sub-unit for the data backup, or receive the third data and / or fourth data transmitted by the non-volatile storage sub-unit for the data recovery; the non-volatile storage sub-unit is configured to transfer the stored third data and / or fourth data to the volatile storage sub-unit for the data recovery, or receive the first data and / or second data transmitted by the volatile storage sub-unit for the data backup.

[0007] For example, in a memory array provided in some embodiments of the present disclosure, the non-volatile storage sub-unit includes a first non-volatile storage device, a second non-volatile storage device, a first switching transistor, and a second switching transistor; the first non-volatile storage device is connected to the volatile storage sub-unit via the first switching transistor; and the second non-volatile storage device is connected to the volatile storage sub-unit via the second switching transistor.

[0008] For example, in a memory array provided in some embodiments of the present disclosure, the first non-volatile memory device is configured to store the third data; the second non-volatile memory device is configured to store the fourth data; the third data and the fourth data are configured as differential signals; the first non-volatile memory device and the second non-volatile memory device are resistive memory devices, phase change memory devices, or magnetoresistive memory devices. For example, in a memory array provided in some embodiments of the present disclosure, the plurality of first control lines are electrically connected to the gate of the first switching transistor and the gate of the second switching transistor of each memory cell in the corresponding row of the non-volatile static memory cells.

[0009] For example, in a memory array provided in some embodiments of the present disclosure, for each column of non-volatile static memory storage cells, the multiple bit lines include a first bit line and a second bit line, the first bit line is electrically connected to the first non-volatile memory device of each storage cell in each column of non-volatile static memory storage cells, and the second bit line is electrically connected to the second non-volatile memory device of each storage cell in each column of non-volatile static memory storage cells.

[0010] For example, in a memory array provided in some embodiments of the present disclosure, the volatile storage sub-unit is a static random access memory unit.

[0011] For example, in a memory array provided in some embodiments of the present disclosure, the static random access memory cell includes a first inverter, a second inverter, a first access transistor and a second access transistor; the first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage cell in which they are located; the output end of the first inverter is connected to the input end of the second inverter, and the input end of the first inverter is connected to the output end of the second inverter; the first source and drain of the first access transistor are connected to the output end of the first inverter; and the first source and drain of the second access transistor are connected to the output end of the second inverter.

[0012] For example, in a memory array provided in some embodiments of the present disclosure, for each column of non-volatile static memory storage cells, the multiple bit lines include a first bit line and a second bit line, the first bit line is electrically connected to the second source and drain of the first access transistor of each storage cell in each column of non-volatile static memory storage cells, and the second bit line is electrically connected to the second source and drain of the second access transistor of each storage cell in each column of non-volatile static memory storage cells.

[0013] For example, in a memory array provided by some embodiments of the present disclosure, the first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage unit through a power switch component.

[0014] For example, in a memory array provided in some embodiments of the present disclosure, the power switch component includes a third switching transistor and a fourth switching transistor, the first inverter is electrically connected to the power line via the third switching transistor, and the second inverter is electrically connected to the power line via the fourth switching transistor; or, the power switch component includes a third switching transistor, and the first inverter and the second inverter are electrically connected to the power line via the third switching transistor.

[0015] For example, a memory array provided in some embodiments of the present disclosure also includes: multiple second control lines, which are electrically connected to the power switch component of each memory cell in the corresponding non-volatile static memory storage cell row in the second direction to transmit a second control signal, and the second control signal is used to control the switching state of the power switch component.

[0016] For example, in a memory array provided by some embodiments of the present disclosure, the multiple word lines are electrically connected to the gate of the first access transistor and the gate of the second access transistor of each memory cell in the corresponding nonvolatile static memory cell row.

[0017] For example, in a memory array provided in some embodiments of the present disclosure, the plurality of word lines are also electrically connected to the corresponding power switch components to transmit a second control signal, and the second control signal is used to control the switching state of the power switch components.

[0018] For example, in a memory array provided in some embodiments of the present disclosure, the multiple power lines are short-circuited at one or both ends of the memory array in the second direction; and / or the multiple ground lines are short-circuited at one or both ends of the memory array in the second direction.

[0019] Some embodiments of the present disclosure provide an electronic device, which includes the memory array described in any of the above embodiments.

[0020] Some embodiments of the present disclosure provide a method for operating a memory array, which is used for the memory array described in any of the above embodiments. The method includes: selecting the i-th row of non-volatile static memory storage cells in the memory array; and performing data backup or data recovery on the i-th row of non-volatile static memory storage cells according to a control signal, where I is a positive integer.

[0021] For example, in a memory array operation method provided in some embodiments of the present disclosure, multiple rows or all non-volatile static memory storage cells in the memory array are selected; data backup or data recovery is performed on the selected multiple rows or all non-volatile static memory storage cells according to control signals in the same operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0023] FIG1 is a schematic structural diagram of a 6T-SRAM;

[0024] FIG2 is a schematic diagram of a combination of a volatile storage sub-unit and a non-volatile storage sub-unit;

[0025] FIG3 is a schematic diagram of a storage array provided by at least one embodiment of the present disclosure;

[0026] FIG4 is a schematic structural diagram of a non-volatile static RAM (NVSRAM) storage unit provided by at least one embodiment of the present disclosure;

[0027] FIG5 is a schematic diagram of an NVSRAM storage cell provided by at least one embodiment of the present disclosure;

[0028] FIG6 is a schematic diagram of another NVSRAM storage cell provided by at least one embodiment of the present disclosure;

[0029] FIG7 is a timing diagram of a data backup operation performed by an NVSRAM storage unit according to at least one embodiment of the present disclosure;

[0030] FIG8 is a timing diagram of a data recovery operation performed by an NVSRAM storage unit according to at least one embodiment of the present disclosure;

[0031] FIG9 is a schematic flow chart of a method for operating a storage array according to at least one embodiment of the present disclosure;

[0032] FIG10 is a schematic diagram of a flow chart of a SET operation and a RESET operation when backing up data on a storage array according to at least one embodiment of the present disclosure;

[0033] FIG11 is a schematic diagram of a flow chart of simultaneously performing a SET operation and a RESET operation when backing up data on a storage array according to at least one embodiment of the present disclosure;

[0034] FIG12 is a flowchart of a method for performing data backup on a storage array using separate row-by-row operations of RESET and SET, provided by at least one embodiment of the present disclosure;

[0035] FIG13 is a flowchart of a method for performing data backup on a storage array using separate RESET and SET operations on the entire chip, provided by at least one embodiment of the present disclosure;

[0036] FIG14 is a flow chart of a data backup method for performing row-by-row operations on a storage array using RESET and SET operations simultaneously, provided by at least one embodiment of the present disclosure; and

[0037] FIG15 is a flowchart illustrating a method of recovering data from a storage array according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings. The specific embodiments and drawings described herein are only intended to explain the present disclosure and are not intended to limit the disclosed embodiments. Unless otherwise specified, the various embodiments of the present disclosure and the various features therein may be combined with each other. For ease of description, the drawings of the embodiments of the present disclosure only show the parts relevant to the embodiments of the present disclosure, while parts not relevant to the embodiments of the present disclosure are not shown in the drawings. Each unit and module involved in the embodiments of the present disclosure may correspond to only one physical structure, or may be composed of multiple physical structures, or multiple units and modules may be integrated into one physical structure. Unless otherwise specified, the functions and steps marked in the flowcharts and block diagrams of the embodiments of the present disclosure may occur in an order different from that marked in the drawings. The flowcharts and block diagrams of the embodiments of the present disclosure illustrate the possible architectures, functions, and operations of the systems, devices, equipment, and methods according to the various embodiments of the present disclosure. Each box in the flowchart or block diagram may represent a unit, module, program segment, or code, which contains executable instructions for implementing the specified functions. Furthermore, each block in the block diagrams and flowcharts, or a combination of blocks, may be implemented by a hardware-based system that implements the specified functions, or by a combination of hardware and computer instructions.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0040] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0041] Memory is a crucial component of computer architecture, used to store programs, data, and other information. Basic memory can be categorized into volatile and non-volatile memory based on the characteristics of the storage medium. Volatile memory is memory whose stored data is lost upon power failure, while non-volatile memory is memory whose stored data is not lost upon power failure. Generally, volatile memory operates quickly, while non-volatile memory offers a longer retention period.

[0042] For example, volatile memory can be DRAM (dynamic random access memory) or SRAM (static random access memory). For example, DRAM can use one transistor and one capacitor to store one bit of data, and the data stored in DRAM needs to be updated periodically; SRAM can use multiple transistors to store one bit of data, and the stored data can be permanently stored as long as the SRAM remains powered.

[0043] For example, SRAM can also have multiple types, such as 6T-SRAM (i.e., six-transistor type SRAM), 7T-SRAM (i.e., seven-transistor type SRAM), 8T-SRAM (i.e., eight-transistor type SRAM), and other multi-transistor type SRAM.

[0044] FIG1 is a schematic diagram of an exemplary structure of a 6T-SRAM memory cell.

[0045] As shown in Figure 1, the 6T-SRAM memory cell includes transistors P0, P1, N0, N1, N2, and N3, as well as bit lines BL, BLN, WL, power supply line CVDD, and ground line VSS for operating the memory cell. The memory cell has storage nodes Q and QN, where N represents an NMOS (N-metal-oxide-semiconductor) transistor and P represents a PMOS (P-type metal-oxide-semiconductor) transistor. Bit lines BL and BLN are used for reading and writing data, while word line WL controls read and write operations. Transistors P0 and N0 form one inverter, while transistors P1 and N1 form another inverter. The two inverters are cross-connected to provide storage nodes Q and QN. The SRAM memory cell has a bistable structure. When the storage node Q is at a high level, the storage node QN is at a low level, and the stored data can be selected as "1". Correspondingly, when the storage node Q is at a low level, the storage node QN is at a high level, and the stored data can be selected as "0". Transistor N2 and transistor N3 are controlled by the word line WL to turn on or off the storage unit.

[0046] The SRAM memory cell can have three states: data retention, read, and write. In the data retention state, the word line WL remains low, transistors N2 and N3 are turned off, and the two sets of inverters are isolated from the corresponding bit lines and maintain their original states.

[0047] During a read operation, assuming the stored data is 1, the storage node Q is high and the storage node QN is low. First, the bit lines BL and BLN are precharged to a high potential. Then, the word line WL is set to a high level, turning on transistors N2 and N3. Since the storage node QN is low, transistor P0 is turned on, connecting the bit line BL to the power supply line CVDD through transistors N2 and P0. The voltage level of the bit line BL (high) and the storage state of the storage node Q (high) remain unchanged. The high voltage level of the storage node Q turns on transistor N1, connecting the bit line BLN to the ground line VSS through transistors N3 and N1. The bit line BLN discharges, lowering its voltage level, but the storage state of the storage node QN (low) remains unchanged. Therefore, by reading the voltage difference between the bit lines BL and BLN (the difference is positive), it can be determined that the memory cell currently stores "1".

[0048] Assuming the stored data is 0, the storage node Q is low and the storage node QN is high. First, the bit lines BL and BLN are precharged to a high potential. Then, the word line WL is set to a high level, turning on transistors N2 and N3. Since the storage node QN is high, transistor N0 is turned on, and bit line BL is connected to ground line VSS through transistors N2 and N0. Bit line BL discharges, lowering its voltage, but the storage state of storage node Q (low) remains unchanged. The low voltage of storage node Q turns on transistor P1, connecting bit line BLN to power line CVDD through transistors N3 and P1. The voltage level of bit line BLN (high) and the storage state of storage node QN (high) remain unchanged. Therefore, by reading the voltage difference between bit lines BL and BLN (the difference is negative), it can be determined that the memory cell currently stores "0".

[0049] During a write operation, the written state needs to be loaded onto bit lines BL and BLN to modify the levels of storage nodes Q and QN in the memory cell. For example, if data 1 is to be written, storage node Q needs to be set to a high level, and storage node QN needs to be correspondingly set to a low level. At this time, bit line BL is set to a high level, bit line BLN is set to a low level, and then word line WL is set to a high level, turning on transistors N2 and N3. The high level of bit line BL sets storage node Q to a high level, and the low level of bit line BLN sets storage node QN to a low level. As a result, transistors P0 and N1 are turned on, while transistors N0 and P1 are turned off. As a result, power line CVDD maintains storage node Q at a high level through transistor P0, and ground line VSS maintains storage node QN at a low level through transistor N1, thereby achieving the writing of data 1 and the continuous storage of data 1 in the absence of power failure.

[0050] For example, if data 0 is to be written, the storage node Q needs to be driven low, and correspondingly, the storage node QN needs to be driven low. At this point, the bit line BL is set low, the bit line BLN is set high, and then the word line WL is set high, turning on transistors N2 and N3. The low level of bit line BL sets the storage node Q low, while the high level of bit line BLN sets the storage node QN high. As a result, transistors N0 and P1 are turned on, while transistors P0 and N1 are turned off. Consequently, the power line CVDD maintains the storage node QN at a high level via transistor P1, and the ground line VSS maintains the storage node Q at a low level via transistor N0. This achieves the writing of data 0 and the continuous storage of data 0 even when power is not turned off.

[0051] For example, non-volatile memory can include RRAM (Resistive Random Access Memory), PRAM (Phase-Change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), and flash memory. RRAM and PRAM store data by changing their resistance. For example, RRAM utilizes the ability of thin-film materials to switch between different resistance states—high resistance (HRS) and low resistance (LRS)—under different applied voltage conditions to achieve data storage. These high and low states represent logical "1" and "0," enabling data storage and maintaining data retention even after power is removed. The process of RRAM transitioning from a high resistance state (HRS) to a low resistance state (LRS) is called a SET process, also known as a set process. The transition from a low resistance state to a high resistance state is called a RESET process, also known as a reset process.

[0052] Typically, non-volatile memory includes a non-volatile memory device and one or more switching transistors. The switching transistor can be a transistor or a combination of multiple transistors that can control the on and off of current. Non-volatile memory typically operates slowly and requires a large operating current or voltage.

[0053] As mentioned above, SRAM (Static Random Access Memory) is a volatile memory that loses data after a power outage. Therefore, a constant power supply is required to maintain the SRAM's data storage, which consumes a considerable amount of energy and is not conducive to low-power system design. On the other hand, non-volatile memory typically operates at a relatively slow speed and requires a relatively large operating current or voltage. Therefore, non-volatile static random access memory (NVSRAM) has been proposed. This combines the advantages of both types of memory, integrating non-volatile memory (NVM) with SRAM memory and using the non-volatile memory to back up the data stored in the SRAM. This not only retains the high-speed operation advantage of SRAM, but also enables data to be stored in the non-volatile memory after a power outage and restored to the SRAM after power is restored, thereby achieving low-power processor design. It is an ideal memory for future mobile terminals, personal computers, and servers.

[0054] FIG2 is a schematic diagram of a non-volatile static random access memory (NVSRAM) cell obtained by combining a volatile memory sub-cell with a non-volatile memory sub-cell, wherein the volatile memory sub-cell is the same 6T-SRAM as shown in FIG1 , and the non-volatile memory sub-cell includes a resistive random access memory (RRAM) device R, a resistive random access memory device RN, a transistor N4, and a transistor N5. The non-volatile memory sub-cell is differentially connected to the volatile memory sub-cell, with the RRAM device R connected to a storage node Q via transistor N4, and the RRAM device RN connected to a storage node QN via transistor N5. The gates of transistors N4 and N5 are connected to a control line CWLN, which controls the switching states of transistors N4 and N5. For example, a state where the resistance of the RRAM device R is greater than the resistance of the RRAM device RN is set as data "1", and vice versa.

[0055] In other embodiments, in addition to differential connection to the volatile memory sub-unit, the non-volatile memory sub-unit may also be connected in a single-ended manner, for example, including only the resistive random access memory device R and the transistor N4. Furthermore, in addition to using RRAM in the non-volatile memory sub-unit, a phase-change random access memory (PRAM) may also be used.

[0056] In current NVSRAM storage arrays, power lines run along the rows and are electrically connected to the storage cells in that row. Storage cells in the same row are connected to the same power line. In this case, when data is recovered simultaneously from an entire row of storage cells, the total current of the power line is the sum of the power currents of the entire row of storage cells. Excessive current can easily lead to insufficient power supply capacity, unstable or reduced power supply voltage, and data recovery failure.

[0057] To address at least the aforementioned issues, at least one embodiment of the present disclosure provides a memory array comprising: a plurality of non-volatile static RAM (NVSRAM) memory cells, a plurality of power lines, and a plurality of ground lines. The plurality of NVSRAM memory cells are arranged in a plurality of rows and columns and are configured to perform data storage, data backup, and data recovery; the plurality of power lines are configured to provide a first power supply voltage to the plurality of NVSRAM memory cells, wherein the plurality of power lines are electrically connected to corresponding memory cell columns in a first direction, and the plurality of power lines are short-circuited in a second direction, the first direction being different from the second direction; and the plurality of ground lines are configured to provide a second power supply voltage to the plurality of NVSRAM memory cells, wherein the plurality of ground lines are electrically connected to corresponding memory cell columns in the first direction, and the plurality of ground lines are short-circuited in the second direction.

[0058] In the structure of the memory array provided in the above-mentioned embodiments of the present disclosure, when data is recovered simultaneously in a row of memory cells, the current of each power line in the first direction is only the power current of one memory cell, and the current of each ground line in the first direction is only the ground current of one memory cell. Therefore, the total current on the power line and the ground line is low, the power supply voltage and the ground line voltage remain stable, and the success rate of data recovery can be improved.

[0059] FIG3 is a schematic diagram of a memory array provided by at least one embodiment of the present disclosure.

[0060] As shown in Figure 3, the memory array includes multiple NVSRAM memory cells arranged in m rows and n columns, n power lines (CVDD), and n ground lines (VSS). Each power line (CVDD) is electrically connected to a column of NVSRAM memory cells, and all power lines (CVDD) are short-circuited in the row direction. Each ground line is electrically connected to a column of NVSRAM memory cells, and all ground lines (VSS) are short-circuited in the row direction. Therefore, when data is recovered simultaneously from a row of memory cells, the current flowing through each power line (CVDD) in the first direction only accounts for the power supply current of a single memory cell. This reduces the total current flowing through the power line (CVDD), stabilizes the power supply voltage, and improves the success rate of data recovery. For example, the first direction is the column direction, and the second direction is the row direction.

[0061] The memory array further includes a plurality of bit lines, a plurality of first control lines CWLN, and a plurality of word lines WL. The plurality of bit lines include a plurality of first bit lines BL and a plurality of second bit lines BLN. Each pair of bit lines BL and BLN is electrically connected to a corresponding NVSRAM memory cell column in a first direction to transmit a data signal, which is used to control the volatile memory sub-cells and non-volatile memory sub-cells in the NVSRAM memory cell (see below). The plurality of first control lines CWLN are electrically connected to a corresponding NVSRAM memory cell row in a second direction to transmit a first control signal, for example, the first control signal is used to control the non-volatile memory sub-cells in the NVSRAM memory cell (see below). The plurality of word lines WL are electrically connected to a corresponding NVSRAM memory cell row in the second direction to transmit a word line signal, which is used to control the volatile memory sub-cells in the NVSRAM memory cell (see below).

[0062] In Figure 3, WLi represents the i-th word line, for example, WL1 represents the first word line; CWLNi represents the i-th first control line, for example, CWLN1 represents the first first control line; BLi and BLNi represent the i-th first bit line and the i-th second bit line, respectively, for example, BL1 and BLN1 represent the first first bit line and the first second bit line, respectively; NVSRAMij represents the i-th row and j-th column NVSRAM storage cell, for example, NVSRAM11 represents the first row and first column NVSRAM storage cell, wherein i and j are positive integers, 1≤i≤m, 1≤j≤n; in the memory array, by controlling the voltages on the first bit line BL, the second bit line BLN, the first control line CWLN and the word line WL, the state of each device on the NVSRAM storage cell can be controlled.

[0063] In this embodiment, multiple power lines CVDD can be short-circuited in the row direction, for example, at one or both ends of the memory array, and multiple ground lines VSS can be short-circuited in the row direction, for example, at one or both ends of the memory array. Short-circuiting the power lines CVDD and the ground lines VSS at both ends of the memory array can prevent data backup and recovery failures in the memory array when a fault occurs in one of the shorting lines.

[0064] For example, Figure 4 is a schematic diagram of the structure of an NVSRAM storage unit according to at least one embodiment of the present disclosure. As shown in Figure 4, in one example, each of the multiple NVSRAM storage units includes a volatile storage subunit and a non-volatile storage subunit; the volatile storage subunit is configured to transfer stored first data and / or second data to the non-volatile storage subunit for data backup, or receive third data and / or fourth data transmitted by the non-volatile storage subunit for data recovery; and the non-volatile storage subunit is configured to transfer stored third data and / or fourth data to the volatile storage subunit for data recovery, or receive first data and / or second data transmitted by the volatile storage subunit for data backup.

[0065] For example, the third data and / or fourth data may be the first data and / or second data in the volatile memory device obtained by the non-volatile memory device through data backup, or may be data inherent in the non-volatile memory device or data stored in the non-volatile memory device through other means.

[0066] For example, in one example, the volatile memory sub-unit is a static random access memory (SRAM) unit, and the SRAM unit may be a 6T-SRAM, a 7T-SRAM, or another SRAM structure capable of implementing a static random access memory function.

[0067] For example, in one example, the non-volatile memory sub-cell may include an RRAM and a switch transistor, wherein the RRAM is electrically connected to the volatile memory sub-cell through the switch transistor.

[0068] For example, FIG5 is a schematic diagram of an NVSRAM storage unit provided by at least one embodiment of the present disclosure.

[0069] As shown in Figure 5, the non-volatile storage sub-unit of the NVSRAM storage unit includes a first non-volatile storage device R, a second non-volatile storage device RN, a first switching transistor N4 and a second switching transistor N5; the first non-volatile storage device R is connected to the volatile storage sub-unit via the first switching transistor N4; the second non-volatile storage device RN is connected to the volatile storage sub-unit via the second switching transistor N5.

[0070] The static random access memory cell of the NVSRAM memory cell includes a first inverter V1, a second inverter V2, a first access transistor N2, and a second access transistor N3; the first inverter V1 and the second inverter V2 are connected between a power line CVDD and a ground line VSS corresponding to the NVSRAM memory cell; the output end of the first inverter V1 is connected to the input end of the second inverter V2, and the input end of the first inverter V1 is connected to the output end of the second inverter V2; the first access transistor N2 is connected to the output end of the first inverter V1; and the second access transistor N3 is connected to the output end of the second inverter V2.

[0071] For example, the static random access memory cell is a 6T-SRAM, and the first inverter V1 and the second inverter V2 are connected between the power line CVDD and the ground line VSS corresponding to the NVSRAM memory cell through a power switch component.

[0072] The power switch assembly includes a third switch transistor P2 and a fourth switch transistor P3. The first inverter V1 is electrically connected to the power line CVDD via the third switch transistor P2. The second inverter V2 is electrically connected to the power line CVDD via the fourth switch transistor P3.

[0073] The first inverter V1 includes a transistor P0 and a transistor N0, the second inverter V2 includes a transistor P1 and a transistor N1, the gate of the third switch transistor P2 is connected to the gate of the fourth switch transistor P3, and is connected to the second control line RECP, the sources of the third switch transistor P2 and the fourth switch transistor P3 are connected to the power line CVDD, the drain of the third switch transistor P2 is connected to the source of the transistor P0, and the drain of the fourth switch transistor P3 is connected to the drain of the transistor P1; the second control line RECP is connected to the gate of the transistor in the power switch component, and can be connected to the word line WL at the same time, or it can provide voltage to the power switch component alone.

[0074] The storage nodes of the 6T-SRAM include storage nodes Q and QN. The voltages of the storage nodes Q and QN can be read to obtain the first data and / or second data stored in the static random access memory cell. For example, the first data is stored in the storage node Q, and the second data is stored in the storage node QN. For example, assuming that the stored data is 1, the storage node Q is at a high level and the storage node QN is at a low level. The bit lines BL and BLN are first precharged to a high potential, and then the word line WL is set to a high level, so that transistors N2 and N3 are turned on. Since the storage node QN is at a low level, transistor P0 is turned on. The bit line BL is connected to the power line CVDD through transistors N2 and P0. The level of the bit line BL (high level) and the storage state of the storage node Q (high level) remain unchanged. The high level of the storage node Q turns on transistor N1, and the bit line BLN is connected to the ground line VSS through transistors N3 and N1. The bit line BLN discharges and the level decreases, but the storage state of the storage node QN (low level) remains unchanged. Therefore, by reading the voltage difference between the bit lines BL and BLN (the difference is positive), it can be known that the memory cell currently stores "1".

[0075] Since the SRAM cell is a bistable structure, the storage nodes Q and QN are clamped to each other, so their voltage levels are not easy to change, which also leads to a low success rate of data recovery under power. By switching the switching state of the power switch component, the conductive channel between the volatile storage sub-unit and the power line can be closed during data recovery, and the timing of power off and power on can be freely controlled during data recovery, thereby improving the success rate of data recovery.

[0076] In the above-described 6T-SRAM, the gates of transistors P0 and N0 are connected to serve as the input of a first inverter V1, the gates of transistors P1 and N1 are connected to serve as the input of a second inverter V2, the drains of transistors P0 and N0 are connected to storage node Q, serving as the output of the first inverter V1, and the drains of transistors P1 and N1 are connected to storage node QN, serving as the output of the second inverter V2. The source of the first access transistor N2 is connected to storage node Q, and the source of the second access transistor is connected to storage node QN.

[0077] For example, the first non-volatile memory device R and the second non-volatile memory device RN can be configured to be connected to the storage node of the volatile memory sub-unit in a single-ended or differential connection manner. As described above, for example, the first non-volatile memory device R and the second non-volatile memory device RN can be resistive memory devices, or can be non-volatile memory devices such as phase change memory devices, magnetoresistive memory devices, etc. with variable resistance characteristics. For example, each resistive random access memory device includes a resistive memory layer sandwiched between two electrodes (e.g., an upper electrode and a lower electrode), and the resistance of the resistive memory layer is changed by applying an operating voltage to the two electrodes.

[0078] For example, the first non-volatile memory device R and the second non-volatile memory device RN are resistive random access memory devices, and the first non-volatile memory device R stores third data, and the second non-volatile memory device RN stores fourth data, and the third data and the fourth data are configured as differential signals. The lower electrode of the memory device R is connected to the drain of the first switching transistor N4, and the lower electrode of the memory device RN is connected to the drain of the second switching transistor N5. The source of the first switching transistor N4 is connected to the storage node Q, and the source of the second switching transistor N5 is connected to the storage node QN.

[0079] For example, when the voltage difference between the two ends of the first non-volatile memory device R or the second non-volatile memory device RN is greater than the operation threshold voltage of the first non-volatile memory device R or the second non-volatile memory device RN, the resistance state of the first non-volatile memory device R or the second non-volatile memory device RN is changed according to whether the voltage between the two ends of the first non-volatile memory device R and the second non-volatile memory device RN is a set voltage or a reset voltage. For example, the set voltage is a positive voltage, that is, the voltage of the first non-volatile memory device R or the second non-volatile memory device RN close to the bit line is greater than the voltage of the end close to the storage node; the reset voltage is a reverse voltage, that is, the voltage of the first non-volatile memory device R or the second non-volatile memory device RN close to the bit line is less than the voltage of the end close to the storage node. When the voltage across the first non-volatile memory device R or the second non-volatile memory device RN is a reset voltage to perform a RESET operation, the first non-volatile memory device R or the second non-volatile memory device RN changes to a high-resistance state; when the voltage across the first non-volatile memory device R or the second non-volatile memory device RN is a set voltage to perform a SET operation, the first non-volatile memory device R or the second non-volatile memory device RN changes to a low-resistance state; when the voltage difference across the first non-volatile memory device R or the second non-volatile memory device RN is 0 or less than the operation threshold voltage, the resistance state of the first non-volatile memory device R or the second non-volatile memory device RN does not change, and the resistive memory stores data in the form of a resistance state.

[0080] When the forward voltage difference between the upper and lower electrodes of the storage device R or RN is large, R or RN turns into a low resistance state; when the reverse voltage difference between the upper and lower electrodes of the storage device R or RN is large, R or RN turns into a high resistance state; when the voltage difference between the upper and lower electrodes of the storage device R or RN is 0 or less than the operating threshold voltage, the resistance state of the storage device R or RN does not change, and the resistive memory stores data in the form of a resistance state.

[0081] For example, in one embodiment, multiple first control lines CWLN are electrically connected to the first switch transistor N4 and the second switch transistor N5 of each memory cell in a corresponding NVSRAM memory cell row. The first control line CWLN is connected to the gate of the first switch transistor N4 and the gate of the second switch transistor N5. By controlling the voltage of the first control line CWLN, the switching state of the first switch transistor N4 and the second switch transistor N5 can be controlled. When the voltage of the first control line CWLN meets the conduction condition of the first switch transistor N4 and the second switch transistor N5, the first switch transistor N4 and the second switch transistor N5 are turned on; otherwise, the first switch transistor N4 and the second switch transistor N5 are turned off. When the first switch transistor N4 and the second switch transistor N5 are turned on, the storage node can be connected to the non-volatile memory device. For example, the first data and / or second data stored in the storage node can be transferred to the non-volatile memory sub-unit, or the third data and / or fourth data in the non-volatile memory sub-unit can be transferred to the storage node.

[0082] For example, in one example, for each column of NVSRAM memory cells, a first bit line BL is electrically connected to the first access transistor N2 of each memory cell in each column of NVSRAM memory cells, and a second bit line BLN is electrically connected to the second access transistor N3 of each memory cell in each column of NVSRAM memory cells. Furthermore, the first bit line BL is electrically connected to the first nonvolatile memory device R of each memory cell in each column of NVSRAM memory cells, and the second bit line BLN is electrically connected to the second nonvolatile memory device RN of each memory cell in each column of NVSRAM memory cells. Thus, the bit lines BL and BLN can be used to operate both SRAM memory cells and nonvolatile memory devices.

[0083] For example, in one embodiment, multiple word lines WL are electrically connected to the first access transistor N2 and the second access transistor N3 of each memory cell in a corresponding NVSRAM memory cell row. The word line WL is connected to the gates of the first access transistor N2 and the second access transistor N3. By controlling the voltage of the word line WL, the conduction state of the first access transistor N2 and the second access transistor N3 can be controlled. When the voltage of the word line WL meets the conduction condition of the first access transistor N2 and the second access transistor N3, the first access transistor N2 and the second access transistor N3 are turned on; otherwise, the first access transistor N2 and the second access transistor N3 are turned off.

[0084] FIG. 6 is a schematic diagram of another NVSRAM memory cell according to at least one embodiment of the present disclosure.

[0085] Compared to Figure 5 , the power switch component of the NVSRAM memory cell shown in Figure 6 includes a third switching transistor P2. The first inverter V1 and the second inverter V2 are electrically connected to the power line via the third switching transistor P2. The connection method of the remaining components is the same as that of the NVSRAM memory cell shown in Figure 5 . In this case, the source of the third switching transistor P2 is connected to the power line CVDD, the drain is connected to the sources of transistors P0 and P1, and the gate is connected to the second control line RECP. The second control line RECP is used to transmit a second control signal to control the switching state of the third switching transistor P2.

[0086] The memory array of NVSRAM memory cells shown in FIG6 further includes a plurality of second control lines RECP, each electrically connected in a second direction to the power switch component of each memory cell in a corresponding row of NVSRAM memory cells to transmit a second control signal. The second control lines RECP are connected to the gates of transistors in the power switch components and can be connected to word lines WL or independently provide voltage to the power switch components.

[0087] The process of performing data backup and data recovery for the NVSRAM storage unit shown in FIG5 can be as follows:

[0088] The data backup operation is divided into SET and RESET operations on the non-volatile memory device: according to the data of the storage node in the volatile storage sub-unit, one of the non-volatile memory devices is selected to perform the SET operation, and the other is selected to perform the RESET operation.

[0089] For example, if the data stored in the volatile storage subunit is 0, the storage node Q is at a low level and the storage node QN is at a high level. At this time, a SET operation is performed on the nonvolatile storage device R and a RESET operation is performed on the nonvolatile storage device RN.

[0090] FIG. 7 is a timing diagram of the data backup operation performed by the NVSRAM storage unit shown in FIG. 5 .

[0091] During a SET operation (on the right side of the figure), the voltage of power line CVDD is set to voltage VDD, the voltage of word line WL is set to VSS, the voltage of first control line CWLN is set to voltage VDD, and the voltages of first bit line BL and second bit line BLN are set to voltage VSET (i.e., the voltage for performing the SET operation). At this time, storage node Q is at a low level (i.e., VSS), and the first switch transistor N4 is turned on. The voltage difference VR across non-volatile memory device R is VSET and is greater than the SET operation threshold voltage. Therefore, a SET operation is performed on non-volatile memory device R, turning it into a low-resistance state. Storage node QN is at a high level (i.e., VDD), the second switch transistor N5 is turned off, and the voltage difference VR across non-volatile memory device RN is zero. Therefore, no operation is performed on non-volatile memory device RN, and its resistance value remains unchanged.

[0092] During a RESET operation (left side of the figure), the voltage of power line CVDD is set to VRST (i.e., the voltage for performing the RESET operation), the voltage of word line WL is set to VSS, the voltage of first control line CWLN is set to VDDH, and the voltages of first and second bit lines BL and BLN are set to VSS, where VDDH is greater than or equal to VDD. At this time, storage node Q is at a low level (i.e., VSS), the first switch transistor N4 is turned on, the voltage difference VR across non-volatile memory device R is zero, and the resistance state of non-volatile memory device R remains unchanged. Storage node QN is at a high level (i.e., VRST), the second switch transistor N5 is turned on, and the voltage difference VR across non-volatile memory device RN is the lower value between VRST and VDDH-VTN, where VTN is the threshold voltage of second switch transistor N5. By presetting VRST and VDDH so that both VRST and VDDH-VTN are greater than the reverse threshold voltage required for the RESET operation, the RESET operation is performed on non-volatile memory device RN, placing it in a high-impedance state.

[0093] The process of performing data backup and data recovery on the NVSRAM storage unit shown in FIG6 is the same as the process of performing data backup on the NVSRAM storage unit shown in FIG5 , and will not be described in detail here.

[0094] FIG. 8 is a timing diagram of a data recovery operation performed by the NVSRAM storage unit shown in FIG. 5 .

[0095] The data recovery operation restores the data stored in the non-volatile memory devices R and RN (in a differential manner) to the SRAM device, restores the storage nodes corresponding to the high-resistance side of the non-volatile memory devices R and RN to a high level, and restores the storage nodes corresponding to the low-resistance side to a low level.

[0096] The data recovery operation of the NVSRAM storage unit shown in Figure 5 is divided into the following three stages:

[0097] Phase 1: Set the voltage of the power line CVDD to voltage VDD, the voltage of the word line WL to voltage VDD, the voltage of the first control line CWLN to voltage VDD, and the voltage of the first bit line BL and the second bit line BLN to voltage VSS. At this time, the third switch transistor P2 and the fourth switch transistor P3 are turned off, cutting off the power supply of the SRAM memory cell, thereby destroying the bistable state of the SRAM memory cell. The voltage of the storage node Q is discharged to voltage VSS through the first switch transistor N4 and the transistor N2, and the voltage of the storage node QN is discharged to voltage VSS through the second switch transistor N5 and the transistor N3.

[0098] Phase 2: Set the voltage of the power line CVDD to voltage VDD, the voltage of the word line WL to voltage VSS, the voltage of the first control line CWLN to voltage VDD, the voltage of the first bit line BL and the second bit line BLN to voltage VSS. At this time, the first switch transistor N4 and the second switch transistor N5 as well as the third switch transistor P2 and the fourth switch transistor P3 are all in the on state, and a conduction path is formed from the power line CVDD through the third switch transistor P2, the transistor P0, the transistor N4, the first non-volatile memory device R to the first bit line BL, and a conduction path is formed from the power line CVDD through the fourth switch transistor P3, transistor P1, second switching transistor N5, second non-volatile memory device RN to second bit line BLN form a conduction path, the circuit generates current, and the voltage of storage nodes Q and QN increases. Due to the different resistance values ​​of the non-volatile memory devices on both sides, the voltage on the high-resistance side increases faster, and the voltage on the low-resistance side increases slower, resulting in a voltage difference ΔVQ between storage nodes Q and QN. The positive feedback effect of the cross-coupled inverter in the volatile memory sub-unit is amplified, and the voltages of storage nodes Q and QN are pulled to VDD and VSS, respectively. The data is restored from the non-volatile memory sub-unit to the SRAM memory unit.

[0099] In the third stage, the power line CVDD voltage is set to voltage VDD, the word line WL voltage is set to voltage VSS, the first control line CWLN voltage is set to voltage VSS, the first bit line BL and the second bit line BLN voltage are set to voltage VDD, the first switch transistor N4 and the second switch transistor N5 are turned off, the first access transistor N2 and the second access transistor N3 are turned off, and the data recovery operation is completed.

[0100] The timing diagram of the data recovery operation of the NVSRAM storage unit shown in FIG6 is the same as FIG8 . The data recovery operation of the NVSRAM storage unit shown in FIG6 is divided into the following three stages:

[0101] Phase 1: Set the voltage of the power line CVDD to voltage VDD, the voltage of the word line WL to voltage VDD, the voltage of the first control line CWLN to voltage VDD, and the voltage of the first bit line BL and the second bit line BLN to voltage VSS. At this time, the third switch transistor P2 is turned off, cutting off the power supply of the volatile storage sub-unit, destroying the bistable state of the SRAM storage unit, and the voltage of the storage node Q is discharged to voltage VSS through the first switch transistor N4 and transistor N2. The voltage of the storage node QN is discharged to voltage VSS through the second switch transistor N5 and transistor N3.

[0102] Phase 2: Set the voltage of the power line CVDD to VDD, the voltage of the word line WL to VSS, the voltage of the first control line CWLN to VDD, and the voltage of the first bit line BL and the second bit line BLN to VSS. At this time, the first switch transistor N4, the second switch transistor N5, and the third switch transistor P2 are in the on state, and a conduction path is formed from the power line CVDD through the third switch transistor P2, the transistor P0, the transistor N4, the first non-volatile memory device R to the first bit line BL, and a conduction path is formed from the power line CVDD through the third switch transistor P2, the transistor P0, the transistor N4, the first non-volatile memory device R to the first bit line BL. A conductive path is formed between the body transistor P1, the second switching transistor N5, the second non-volatile memory device RN, and the second bit line BLN. The voltages of the storage nodes Q and QN increase. Due to the different resistance values ​​of the non-volatile memory devices on both sides, the voltage on the high-resistance side increases faster, while the voltage on the low-resistance side increases slower. This generates a voltage difference ΔVQ between the storage nodes Q and QN. This voltage difference is amplified by the positive feedback effect of the cross-coupled inverters in the volatile memory sub-unit, and the voltages of the storage nodes Q and QN are pulled to voltages VDD and VSS, respectively. The data is restored from the non-volatile memory sub-unit to the volatile memory sub-unit.

[0103] In the third stage, the power line CVDD voltage is set to voltage VDD, the word line WL voltage is set to voltage VSS, the first control line CWLN voltage is set to voltage VSS, the first bit line BL and the second bit line BLN voltage are set to voltage VDD, the first switch transistor N4 and the second switch transistor N5 are turned off, the first access transistor N2 and the second access transistor N3 are turned off, and the data recovery operation is completed.

[0104] Since the SRAM memory cell has a bistable structure, during the data recovery operation, if the connection between the SRAM memory cell and the power line is not cut off, a small voltage difference will make it difficult to change the storage state of the SRAM memory cell. By cutting off the power supply of the volatile memory sub-cell through the power switch component, the bistable storage state of the SRAM is destroyed, which can improve the success rate of data recovery.

[0105] At least one embodiment of the present disclosure further provides an electronic device, which includes any one of the storage arrays described in any of the above embodiments. The electronic device can be, for example, any product or component such as a storage device, a computer, etc. that includes the storage array or is used in conjunction with the storage array. For the technical effects of the electronic device, reference can be made to the technical effects of the storage array described in the above embodiments, which will not be elaborated here.

[0106] At least one embodiment of the present disclosure provides an operation method for a storage array, which can be used, for example, for the storage arrays in any of the above embodiments. Taking the storage array shown in FIG. 3 as an example for introduction, the NVSRAM storage units in the storage array are shown in FIG. 5.

[0107] FIG. 9 is a flowchart of the operation method for the storage array provided in at least one of the above embodiments of the present disclosure.

[0108] As shown in FIG. 9, the operation method of the storage array includes the following steps:

[0109] Step S101: Select the i-th row of NVSRAM storage units in the memory array.

[0110] Step S102: The i-th row of NVSRAM storage units performs data backup or data recovery according to a control signal, where i is a positive integer and 1 ≤ i ≤ m.

[0111] In the above embodiment, the data read / write operations on the storage array with a scale of m rows and n columns as shown in FIG. 3 are the same as those on the storage array based on the SRAM storage units in FIG. 1, and will not be specifically described.

[0112] For example, it is possible to select the i-th row to the (i + k - 1)-th row to perform operations simultaneously, where i and k are positive integers, 1 ≤ i ≤ m, 1 ≤ k ≤ m, and 1 ≤ (i + k - 1) ≤ m. When k = 1, select 1 row to perform data backup or data recovery operations; when 1 < k < m, select multiple rows to perform data backup or data recovery operations simultaneously; when i = 1 and k = m, perform data backup or data recovery operations on all rows of the m-row array simultaneously.

[0113] In the embodiments of the present disclosure, for example, the data backup operation can be performed with the word as the smallest unit, or with the row as the smallest unit; for example, the data recovery operation is performed with the row as the smallest unit. Performing the operation with the word as the smallest unit means that when operating on the non-volatile storage sub-units each time, all the non-volatile storage sub-units in one selected word or multiple selected words are operated simultaneously. Performing the operation with the row as the smallest unit means that when operating on the non-volatile storage sub-units each time, all the non-volatile storage sub-units in one selected row or multiple selected rows of storage units are operated simultaneously. Taking the operation with the row as the smallest unit as an example, the operation methods of data backup and data recovery are introduced.

[0114] In at least one embodiment of the present disclosure, in a method for operating a memory array, for example, multiple rows or all non-volatile static memory cells in the memory array are sequentially or simultaneously selected; then, data backup or data recovery is performed on the selected multiple rows or all non-volatile static memory cells in the same operation according to a control signal, for example, the same operation is an operation step performed according to the same control signal. When performing a data backup operation, two data backup operation methods can be used depending on whether a SET operation and a RESET operation are performed simultaneously:

[0115] The first method is a two-step data backup operation method, that is, the SET operation and RESET operation in the data backup operation are divided into two steps. There is no requirement for the operation order of the SET operation or the RESET operation. The RESET operation can be performed first and then the SET operation, or the SET operation can be performed first and then the RESET operation.

[0116] FIG. 10 is a schematic diagram of a process for performing a two-step data backup operation on a storage array according to at least one embodiment of the present disclosure.

[0117] As shown in FIG10 , the unit operation steps of performing a RESET operation first and then a SET operation are as follows:

[0118] Step S001: Perform RESET operation on all selected cells;

[0119] Step S002: Perform SET operation on all selected cells.

[0120] The dual-step data backup method requires no additional data readout control or other external data interaction control, resulting in a simple circuit structure and easy and convenient operation. This method can perform data backup operations in word or row units, and can simultaneously perform data backup operations on multiple rows or all rows of an entire array.

[0121] FIG11 is a schematic diagram of a process of performing a single-step data backup operation on a storage array according to at least one embodiment of the present disclosure. In this process, a SET operation and a RESET operation are performed simultaneously.

[0122] As shown in Figure 11, the second method is a single-step data backup operation method, the steps are as follows:

[0123] Step S011: reading the data stored in the SRAM of the selected unit;

[0124] Step S012: setting the bit line to output a corresponding voltage according to the read data;

[0125] The bit line voltage on the side of the corresponding storage node "0" is VSET, and the bit line voltage on the side of the storage node "1" is 0;

[0126] Step S013: all selected cells perform RESET and SET operations simultaneously.

[0127] In the above embodiment, when performing a single-step data backup operation on NVSRAM storage cells, the data of the storage nodes in the SRAM of all selected NVSRAM storage cells is read. The bit lines are then set to output corresponding voltages based on the read data. The voltage of the bit line corresponding to the low-voltage storage node is set to VSET, and the voltage of the bit line corresponding to the high-voltage storage node is set to 0. Then, the bit lines BL and BLN output corresponding voltages, and all selected cells simultaneously perform RESET and SET operations. The non-volatile memory device on the low-voltage storage node performs the SET operation, while the non-volatile memory device on the high-voltage storage node performs the RESET operation. Performing the SET and RESET operations simultaneously can increase the operating speed of the array. The single-step data backup operation method can perform data backup operations in word units or in row units. However, when operating in row units, data backup operations can only be performed on a row at a time.

[0128] For a two-step data backup operation or a data recovery operation, the row operation timing of the storage array can be divided into two methods according to different row operation timings.

[0129] Method 1 is a row-by-row operation. During an array operation, after completing a single operation on all cells in the currently selected row or rows, a single operation is performed on the next row or rows. A single operation can include a data backup operation or a data recovery operation. In the data backup and data recovery operations, the sequence number (i) or row number (k) of the selected row can be the same or different.

[0130] Method 2 is a full-slice operation, wherein the first step is first performed on the entire slice in a row-by-row operation mode, and then the second step is performed on the entire slice in a row-by-row operation mode.

[0131] For a single-step data backup operation, the row operation sequence of the storage array adopts a row-by-row operation, and at most only one row of storage cells is selected at a time for the data backup operation.

[0132] FIG. 12 is a flow chart illustrating a dual-step data backup operation on a storage array using a row-by-row operation method according to at least one embodiment of the present disclosure.

[0133] As shown in FIG12 , the steps of the operation method are as follows:

[0134] The first step is to select rows from i to i+k-1;

[0135] In the second step, perform the RESET operation on the selected k rows simultaneously;

[0136] In the third step, perform the SET operation on the selected k rows simultaneously;

[0137] In the fourth step, determine whether all data backup is completed. If not, update i to i + k and return to the first step; if so, end this process.

[0138] Where i and k are positive integers, 1 ≤ i ≤ m, 1 ≤ k ≤ m, and 1 ≤ (i + k - 1) ≤ m. When k = 1, select 1 row for data backup or data recovery operation; when 1 < k < m, select multiple rows for data backup or data recovery operation simultaneously; when i = 1 and k = m, perform data backup or data recovery operation on all rows of the m - row array simultaneously. In actual operation, i is usually initialized with the value 1, that is, start the operation from the first row of the array, or it can be other values, that is, start the operation from any row in the array; when the data backup operation on the m - th row is completed, the whole process ends. When using this operation method for data backup, no additional data reading control and other external data interaction controls are required, the circuit structure is simple, it does not occupy the data bus, and the operation is simple and convenient.

[0139] FIG. 13 is a schematic flow chart of a method for separately performing full - chip RESET and SET operations on a storage array for data backup according to at least one embodiment of the present disclosure.

[0140] As shown in FIG. 13, the steps of this operation method are as follows:

[0141] In the first step, select the i - th to the (i + k - 1) - th rows;

[0142] In the second step, perform the RESET operation on the selected k rows simultaneously;

[0143] In the third step, determine whether all rows are RESET. If so, proceed to the fourth step; otherwise, update i to i + k and return to the first step;

[0144] In the fourth step, select the x - th to the (x + y - 1) - th rows;

[0145] In the fifth step, perform the SET operation on the selected y rows simultaneously;

[0146] In the sixth step, determine whether all rows are SET. If so, the data backup operation ends; otherwise, update x to x + y and return to the fourth step.

[0147] Where i and k are positive integers, 1≤i≤m, 1≤k≤m, and 1≤(i+k-1)≤m; x and y are positive integers, 1≤x≤m, 1≤y≤m, and 1≤(x+y-1)≤m; i and x can be the same or different; k and y can be the same or different. In this operation method, since SET and RESET operations are performed on the entire chip, the voltage transitions of the power supply line CVDD, the first bit line BL, and the second bit line BLN are performed only once after the SET or RESET operation for the entire array is completed. This reduces the frequency of voltage transitions and lowers the dynamic power consumption of the circuit.

[0148] FIG. 14 is a flow chart illustrating a single-step data backup operation on a storage array using a row-by-row operation method according to at least one embodiment of the present disclosure.

[0149] As shown in FIG14 , the steps of the data backup method are as follows:

[0150] The first step is to select the i-th row;

[0151] The second step is to read the i-th row of data;

[0152] The third step is to encode the bit lines according to the read data;

[0153] Step 4: Perform both RESET and SET operations on the selected row i.

[0154] Step 5: Determine whether the data backup is complete. If so, the data backup operation ends, i is incremented by 1, and the process returns to step 1.

[0155] When backing up data using the single-step data backup operation method, the RESET operation and the SET operation are performed simultaneously, thereby improving the speed of data backup.

[0156] For example, in the above embodiment, the data recovery operation adopts a row-by-row operation method.

[0157] FIG15 is a flow chart of a method for recovering data from a storage array according to at least one embodiment of the present disclosure. As shown in FIG15 , the steps of the data recovery method are as follows:

[0158] The first step is to select rows i to i+k-1;

[0159] The second step is to perform data recovery operations on the selected k rows simultaneously;

[0160] The third step is to determine whether the data recovery is complete. If not, update i to be equal to i+k and return to the first step; if yes, end the data recovery operation.

[0161] At least one embodiment of the present disclosure provides a storage array, an electronic device, and a method for operating a storage array. The power lines of all NVSRAM storage cells in the same column are connected and routed along the column direction of the array. The power lines of all columns are short-circuited along the row direction of the array. When data is recovered simultaneously for an entire row of storage cells, the current flowing through each column-direction power line is only the power supply current of one NVSRAM storage cell. This reduces the total current on the power lines, maintains a stable power supply voltage, and improves the success rate of data recovery.

[0162] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A memory array, comprising: a plurality of non-volatile static memory storage cells arranged in a plurality of rows and columns and configured to perform data storage and data backup and recovery; A plurality of power lines configured to provide a first power supply voltage to the plurality of nonvolatile static memory storage cells, wherein the plurality of power lines are electrically connected to corresponding storage cell columns in a first direction, respectively, and the plurality of power lines are short-circuited in a second direction, and the first direction is different from the second direction; A plurality of ground lines are configured to provide a second power supply voltage to the plurality of nonvolatile static memory storage cells, wherein the plurality of ground lines are electrically connected to corresponding storage cell columns in the first direction respectively, and the plurality of ground lines are short-circuited in the second direction.

2. The memory array of claim 1 , further comprising: a plurality of bit lines, respectively electrically connected to corresponding columns of storage cells of the nonvolatile static memory in the first direction to transmit data signals; a plurality of first control lines, respectively electrically connected to corresponding rows of the nonvolatile static memory cells in the second direction to transmit a first control signal; A plurality of word lines are electrically connected to corresponding nonvolatile static memory storage unit rows in the second direction to transmit word line signals.

3. The memory array according to claim 2, wherein: Each of the plurality of non-volatile static memory storage units includes a volatile storage sub-unit and a non-volatile storage sub-unit; The volatile storage subunit is configured to transfer the stored first data and / or second data to the non-volatile storage subunit to perform the data backup, or receive the third data and / or fourth data transmitted by the non-volatile storage subunit to perform the data recovery; The non-volatile storage subunit is configured to transfer the stored third data and / or fourth data to the volatile storage subunit for data recovery, or receive the first data and / or second data transmitted by the volatile storage subunit for data backup.

4. The memory array according to claim 3, wherein: The nonvolatile storage subunit includes a first nonvolatile storage device, a second nonvolatile storage device, a first switch transistor and a second switch transistor; The first non-volatile memory device is connected to the volatile memory subunit via the first switch transistor; The second non-volatile memory device is connected to the volatile memory sub-unit via the second switch transistor.

5. The memory array according to claim 4, wherein: The first non-volatile memory device is configured to store the third data; The second non-volatile memory device is configured to store the fourth data; The third data and the fourth data are configured as differential signals; The first nonvolatile memory device and the second nonvolatile memory device are resistive memory devices, phase change memory devices, or magnetoresistive memory devices.

6. The memory array according to claim 4 or 5, wherein: The plurality of first control lines are electrically connected to a gate of a first switch transistor and a gate of a second switch transistor of each memory cell in a corresponding row of nonvolatile static memory cells.

7. The memory array according to any one of claims 4 to 6, wherein: For each column of non-volatile static memory cells, the plurality of bit lines include a first bit line and a second bit line, The first bit line is electrically connected to the first non-volatile memory device of each memory cell in each column of the non-volatile static memory memory cells. The second bit line is electrically connected to the second non-volatile memory device of each memory cell in each column of the non-volatile static memory memory cells.

8. The memory array according to any one of claims 3 to 7, wherein: The volatile storage subunit is a static random access storage unit.

9. The memory array according to claim 8, wherein: The static random access memory cell includes a first inverter, a second inverter, a first access transistor and a second access transistor; The first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage unit; The output end of the first inverter is connected to the input end of the second inverter, and the input end of the first inverter is connected to the output end of the second inverter; A first source and drain of the first access transistor are connected to an output terminal of the first inverter; A first source and a drain of the second access transistor are connected to an output terminal of the second inverter.

10. The memory array of claim 9, wherein: For each column of non-volatile static memory cells, the plurality of bit lines include a first bit line and a second bit line, The first bit line is electrically connected to the second source and drain of the first access transistor of each memory cell in each column of the non-volatile static memory memory cells. The second bit line is electrically connected to the second source and drain of the second access transistor of each memory cell in each column of the non-volatile static memory cells.

11. The memory array according to claim 9 or 10, wherein: The first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage unit through a power switch component.

12. The memory array of claim 11, wherein: The power switch component includes a third switch transistor and a fourth switch transistor, the first inverter is electrically connected to the power line via the third switch transistor, and the second inverter is electrically connected to the power line via the fourth switch transistor; or, The power switch component includes a third switch transistor, and the first inverter and the second inverter are electrically connected to the power line via the third switch transistor.

13. The memory array of claim 12, further comprising: a plurality of second control lines, respectively electrically connected to the power switch components of each storage unit of the corresponding non-volatile static memory storage unit row in the second direction to transmit a second control signal, The second control signal is used to control the switching state of the power switch component.

14. The memory array according to any one of claims 9 to 13, wherein: The plurality of word lines are electrically connected to a gate of a first access transistor and a gate of a second access transistor of each memory cell in a corresponding nonvolatile static memory cell row.

15. The memory array of claim 14, wherein: The plurality of word lines are also electrically connected to the corresponding power switch components to transmit a second control signal. The second control signal is used to control the switching state of the power switch component.

16. The memory array according to any one of claims 1 to 15, wherein: The plurality of power lines are short-circuited at one or both ends of the memory array in the second direction; and / or The plurality of ground lines are short-circuited at one or both ends of the memory array in the second direction.

17. An electronic device comprising the memory array according to any one of claims 1 to 16.

18. A method for operating the memory array according to any one of claims 1 to 16, comprising: Selecting an i-th row of non-volatile static memory cells in the memory array; Performing data backup or data recovery on the non-volatile static memory storage units in the i-th row according to the control signal, Wherein, i is a positive integer.

19. The method for operating a memory array according to claim 18, wherein: selecting a plurality of rows or all of the non-volatile static memory cells in the memory array; Data backup or data recovery is performed on the selected multiple rows or all non-volatile static memory storage cells according to the control signal in the same operation.

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