Multi-layer chip stacking package structure and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductor device manufacturing, and provides a multi-layer chip stacking package structure and a manufacturing method therefor, and an electronic device. The multi-layer chip stacking package structure comprises a first substrate, a first redistribution layer, a second substrate, and a second redistribution layer; a first device is arranged in the first substrate, and the first redistribution layer is arranged on one side of the first substrate; a second device is arranged in the second substrate, and the second redistribution layer is arranged on one side of the second substrate; and the side of the first substrate away from the first redistribution layer is in bonding connection with the side of the second substrate away from the second redistribution layer. When the multi-layer chip stacking package structure is manufactured, before the first substrate and the second substrate are bonded, the redistribution layers can be manufactured on the two substrates, respectively, and the technological processes of the two redistribution layers do not affect each other, so that the risks of warping and layering of the package structure can be weakened.

Description

Multi-layer chip stacking packaging structure and preparation method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 5, 2023, with application number 202311665382.5 and invention name “Multi-layer chip stacking packaging structure and its preparation method, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor device manufacturing technology, and in particular to a multi-layer chip stacking packaging structure, an electronic device comprising the multi-layer chip stacking packaging structure, and a method for preparing the multi-layer chip stacking packaging structure. Background Art

[0003] Driven by the high-speed, high-performance, and miniaturization of electronic products, modules are moving towards high-density miniaturization to achieve high-density and high-performance packaging. This miniaturization requires higher-density fan-out packaging with multi-layer stacking. At this point, warping and delamination become more prominent, becoming bottlenecks.

[0004] As shown in Figure 1, a multi-layer chip stacking package structure is shown. In the middle layer containing devices 1, 2, 3, and 4, redistribution layers (RDLs) are provided on both the upper and lower sides. During the preparation of each RDL, the photoresist undergoes multiple temperature shocks during curing. For example, when each RDL contains four layers of metal traces, the structure shown in Figure 1 will experience at least eight temperature shocks during curing. This can easily lead to warping and delamination, and may even damage the performance of the devices in the middle layer.

[0005] Summary of the Invention

[0006] The present application provides a multi-layer chip stacking packaging structure, an electronic device including the multi-layer chip stacking packaging structure, and a method for preparing the multi-layer chip stacking packaging structure. The purpose is to reduce warping and delamination and improve the performance of the multi-layer stacking packaging structure.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] On the one hand, the present application provides a multi-layer chip stacking packaging structure.

[0009] The multi-layer chip stacking packaging structure includes: a first substrate, a first redistribution layer, a second substrate and a second redistribution layer; a first device is arranged in the first substrate, and the first redistribution layer is arranged on one side of the first substrate; a second device is arranged in the second substrate, and the second redistribution layer is arranged on one side of the second substrate; a side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

[0010] When preparing the multi-layer chip stacking packaging structure provided in the present application, a first redistribution layer can be set on one side of the first substrate, and a second redistribution layer can be set on one side of the second substrate, and then the first substrate containing the first redistribution layer can be bonded together with the second substrate containing the second redistribution layer. Compared with preparing a redistribution layer on one side of a substrate and then preparing another redistribution layer on the other side, the present application can reduce the impact of multiple high-temperature shocks when preparing the redistribution layer. For example, in the present application, since the redistribution layers can be prepared on the two substrates respectively before the first substrate and the second substrate are bonded, the process steps of the two redistribution layers do not affect each other, thereby reducing the risk of warping and delamination of the packaging structure, reducing the risk of damage to the device, and improving the performance of the entire packaging structure. Furthermore, the first device and the second device of the present application are basically located in the middle of the entire packaging structure. During the preparation process, these devices are at greater risk of warping. However, the present application sets the first device and the second device in the substrate. Since the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the device are basically close, compared with using a plastic encapsulation material with a larger thermal expansion coefficient to encapsulate the device, the present application uses a substrate with a smaller difference in thermal expansion coefficient to encapsulate the device, which can suppress the degree of warping of the device and can also suppress the risk of delamination between the substrate and the device.

[0011] In one achievable manner, the first device has a first pattern layer on a side facing the second substrate; the second substrate has a first side facing the first substrate, the first side and the first device form a cavity; and the first pattern layer is located in the cavity.

[0012] In the example of this application, the first device can be a cavity-type device. Since the second substrate and the cavity-type device form a cavity, the pattern layer of the cavity-type device is set in the cavity. This application can omit the cover structure of the cavity-type device and use the second substrate as the cover of the cavity-type device, thereby simplifying the packaging structure and eliminating the assembly process of the cover.

[0013] In one feasible manner, the first device and the second device are arranged face to face, and the first device and the second device enclose a cavity; the first device has a first pattern layer on a side facing the second substrate; the second device has a second pattern layer on a side facing the first substrate; and the first pattern layer and the second pattern layer are both located in the cavity.

[0014] In this example, the first device and the second device can both be cavity-type devices. The two devices arranged face to face form a cavity, and the pattern layers of the two devices are arranged in the cavity, that is, the second device is used as a cover for the first device, and the first device is used as a cover for the second device.

[0015] In one achievable manner, the first component includes at least one of a filter and a multiplexer.

[0016] In one achievable manner, the first device and the second device are arranged face to face, with the pattern layer of the first device facing the pattern layer of the second device; the pattern layer of the first device is bonded to the pattern layer of the second device.

[0017] When the pattern layers of two devices disposed face to face are arranged relative to each other, a bonding structure between the two substrates can be used to electrically connect the pattern layers of the two devices.

[0018] In one achievable manner, the first device includes at least one of a filter and a multiplexer, and the second device includes an integrated passive device (IPD). In this way, the filter and the IPD are integrated to realize a multifunctional device.

[0019] In one achievable manner, the pattern layer of the first device faces the second substrate; along the thickness direction of the first device, a conductive via is provided in the first device, and the conductive via electrically connects the first redistribution layer and the pattern layer of the first device.

[0020] The device can be interconnected with the first redistribution layer by using conductive vias.

[0021] In one feasible method, a third device is provided on the side of the first redistribution layer facing away from the first substrate; the pattern layer of the first device faces the first redistribution layer, and the pattern layer of the third device faces the first redistribution layer; the pattern layer of the first device and the pattern layer of the third device are both electrically connected to the first redistribution layer.

[0022] In one feasible method, a fourth device is provided on the side of the second redistribution layer facing away from the second substrate; the pattern layer of the second device faces the second redistribution layer, and the pattern layer of the fourth device faces the second redistribution layer; the pattern layer of the second device and the pattern layer of the fourth device are both electrically connected to the second redistribution layer.

[0023] The first redistribution layer can be used to interconnect the first device and the third device, and the second redistribution layer can be used to interconnect the second device and the fourth device, shortening the interconnection path between the first device and the third device, and shortening the interconnection path between the second device and the fourth device.

[0024] In one achievable method, a first package is provided on the side of the first redistribution layer facing away from the first substrate, and the third device is located in the first package; a second package is provided on the side of the second redistribution layer facing away from the second substrate, and the fourth device is located in the second package.

[0025] The first package body is used to protect the third device, and the second package body is used to protect the fourth device.

[0026] In one achievable manner, the thermal expansion coefficient of the first substrate or the second substrate is 2 ppm / K-3 ppm / K. The thermal expansion coefficient of the first substrate or the second substrate may be equal to 2 ppm / K or equal to 3 ppm / K.

[0027] In one achievable manner, the material of the first substrate or the second substrate may be at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, and a glass substrate.

[0028] In another aspect, the present application further provides a method for preparing a multi-layer chip stacking package structure, the method comprising:

[0029] A first redistribution layer is formed on one side of a first substrate, wherein a first device is provided in the first substrate;

[0030] A second redistribution layer is formed on one side of a second substrate, wherein a second device is provided in the second substrate;

[0031] The side of the first substrate facing away from the first redistribution layer is bonded to the side of the second substrate facing away from the second redistribution layer.

[0032] When using the method provided in this application to produce a double-sided redistribution layer, a redistribution layer is formed on one side of one substrate, and another redistribution layer is formed on the side of another substrate. The two substrates carrying the redistribution layers are then bonded together to form a stacked structure of double-sided redistribution layers. Compared to forming redistribution layers on both sides of a single substrate, the method provided in this application can reduce the number of temperature shocks during photoresist curing, reduce the degree of damage to the device, and also weaken warping and delamination.

[0033] In one achievable manner, before forming the first redistribution layer on one side of the first substrate, the preparation method further includes:

[0034] A first groove is opened in the first substrate, and a first device is set in the first groove, with the pattern layer of the first device facing away from the opening of the first groove. After the first substrate and the second substrate are bonded, the pattern layer of the first device is located in the cavity surrounded by the first device and the second substrate.

[0035] In the method of the example of the present application, the first device may be a cavity-type device, and using the second substrate as a cover of the cavity device can simplify the entire packaging structure and the process steps.

[0036] In one achievable manner, before forming the first redistribution layer on one side of the first substrate and before forming the second redistribution layer on one side of the second substrate, the preparation method further includes:

[0037] A first groove is opened in the first substrate, and a first device is disposed in the first groove, with the pattern layer of the first device facing away from the opening of the first groove;

[0038] A second groove is formed in the second substrate, and a second device is disposed in the second groove, with the pattern layer of the second device facing away from the opening of the second groove;

[0039] Bonding the first substrate to the second substrate includes:

[0040] The pattern layer of the first device and the pattern layer of the second device are arranged face to face, the first device and the second device surround a cavity, and the pattern layer of the first device and the pattern layer of the second device are both located in the cavity.

[0041] In this example, the first device and the second device may both be cavity-type devices, the first device disposed face to face serves as a cover for the second device, and the second device serves as a cover for the first device.

[0042] In one possible implementation, after the first substrate and the second substrate are bonded, the preparation method further includes:

[0043] Disposing a third device on a side of the first redistribution layer facing away from the first substrate;

[0044] A fourth device is arranged on a side of the second redistribution layer facing away from the second substrate.

[0045] This can produce a four-layer stacked packaging structure, further improving the integration density.

[0046] On the other hand, the present application provides an electronic device, which may include a circuit board and a multi-layer chip stacking packaging structure of any of the above implementations.

[0047] Since the electronic device includes a multi-layer chip stacking packaging structure in any of the above-mentioned implementation methods, when a double-sided redistribution layer of the multi-layer chip stacking packaging structure is prepared, the risk of warping and delamination of the packaging structure can be reduced, and the risk of damage to the device can also be reduced, thereby improving the performance of the entire packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a schematic structural diagram of a multi-layer chip stacking packaging structure in the prior art;

[0049] FIG2 is a schematic diagram of a partial structure of an electronic device provided in an embodiment of the present application;

[0050] FIG3 is a schematic structural diagram of a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0051] 4A, 4B and 4C are schematic structural diagrams of a redistribution layer formed on a substrate according to an embodiment of the present application;

[0052] 5A, 5B and 5C are schematic structural diagrams of another redistribution layer fabricated on another substrate according to an embodiment of the present application;

[0053] FIG6 is a schematic structural diagram of a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0054] FIG7 is an enlarged view of point A in FIG6 ;

[0055] FIG8 is a schematic structural diagram of a cavity-type device provided in an embodiment of the present application;

[0056] FIG9 is a schematic diagram of a partial structure of a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0057] FIG10 is a schematic diagram of a partial structure of a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0058] FIG11 is a schematic diagram of a partial structure of a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0059] FIG12 is a schematic structural diagram of a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0060] FIG13 is a process flow chart of a method for preparing a multi-layer chip stacking package structure provided in an embodiment of the present application;

[0061] 14A to 14N are cross-sectional views of corresponding process structures after completion of each step in a method for manufacturing a multi-layer chip stacking packaging structure provided by an embodiment of the present application.

[0062] Reference numerals:

[0063] 100-Multi-layer chip stacking package structure; 200-Control circuit; 300-Circuit board;

[0064] 1-base;

[0065] 2- pattern layer;

[0066] 3- lid;

[0067] 4- Cavity. DETAILED DESCRIPTION

[0068] The present invention provides an electronic device, which may include a mobile phone, a tablet computer, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, a drone, or other terminal devices, or may also be a base station, a television, a router, a car, or other devices. The present invention does not impose any particular restrictions on the specific form of the electronic device.

[0069] Figure 2 exemplarily illustrates a partial structural diagram of an electronic device. The electronic device may include a circuit board 300. In this example, the circuit board 300 may be a printed circuit board (PCB). Electronic components may be disposed on the circuit board 300. For example, a chip package structure may be disposed on the circuit board 300.

[0070] In order to achieve high-density and high-performance packaging, a multi-layer chip stacking packaging structure 100 may be provided on the circuit board 300 , and more devices may be integrated using the multi-layer stacking structure.

[0071] As shown in FIG. 2 , a control circuit 200 may also be provided on the circuit board 300 , and the multi-layer chip stack package structure 100 is electrically connected to the control circuit 200 to control the circuits in the multi-layer chip stack package structure 100 .

[0072] As shown in FIG3 , FIG3 is a structural diagram of a multi-layer chip stack package structure 100 provided in an embodiment of the present application. The multi-layer chip stack package structure 100 includes a first substrate, in which at least one device is disposed. For example, the first substrate may be provided with devices 11, 12, and 13 shown in FIG3 .

[0073] In some examples, in order to achieve interconnection between devices in the first substrate, a first redistribution layer RDL is provided on one side of the first substrate. For example, the first redistribution layer RDL can achieve interconnection between devices 11, 12 and 13.

[0074] The multi-layer chip stack package structure 100 further includes a second substrate, on which at least one device is disposed. For example, the second substrate may include the device 21, the device 22, and the device 23 shown in FIG3. To enable interconnection between the devices 21, 22, and 23, a second redistribution layer (RDL) is disposed on one side of the second substrate.

[0075] As shown in FIG3 , in the example of the present application, a side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer through a bonding process.

[0076] Figure 3 can be understood as: the first substrate has a first side surface and a second side surface back to back, and a first redistribution layer is provided on the first side surface of the first substrate; the second substrate has a first side surface and a second side surface back to back, and a second redistribution layer is provided on the first side surface of the second substrate; the second side surface of the first substrate is bonded to the second side surface of the second substrate by bonding.

[0077] In some examples, as shown in Figure 3, a first conductive via can be provided in the first substrate, the first conductive via passes through the first substrate along the thickness direction of the first substrate, and is electrically connected to the first redistribution layer; a second conductive via is provided in the second substrate, the second conductive via passes through the second substrate along the thickness direction of the second substrate, and is electrically connected to the second redistribution layer.

[0078] The first and second conductive vias, which are arranged opposite each other, can be electrically connected via a bonding layer between the two substrates. This allows interconnection between the first and second redistribution layers. In some examples, this allows devices in the first substrate to communicate with devices in the second substrate.

[0079] As shown in Figure 3 , the device disposed on the first substrate or the second substrate can be an active device or a passive device, such as a passive filter or an integrated passive device (IPD). Alternatively, the device can be a plurality of bare chips stacked three-dimensionally. This application does not impose any particular restrictions on the type or structure of the device.

[0080] The first substrate or the second substrate in the examples of the present application can be at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, or a glass substrate. Alternatively, it can be a multi-layer substrate, such as a silicon-on-insulator (SOI) substrate or a piezoelectric-on-insulator (POI) substrate.

[0081] FIG. 4A , FIG. 4B , and FIG. 4C , and FIG. 5A , FIG. 5B , and FIG. 5C exemplarily illustrate a possible preparation process of the structure shown in FIG. 3 .

[0082] As shown in FIG4A , at least one device is fabricated in a first substrate, such as device 11 , device 12 , and device 13 .

[0083] And, a blind first conductive via is formed in the first substrate, that is, the first conductive via does not penetrate the first substrate.

[0084] As shown in FIG4B , a first redistribution layer is formed on one side of the first substrate. For example, the metal wiring of the first redistribution layer can be at least four layers, or the metal wiring can be less than four layers.

[0085] As shown in FIG4C , the back surface of the first substrate is thinned to expose the end surface of the first conductive via.

[0086] As shown in FIG5A , at least one device is fabricated in the second substrate, such as device 21, device 22, and device 23. A blind second conductive via is also fabricated in the second substrate, i.e., the second conductive via does not penetrate the second substrate.

[0087] As shown in FIG5B , a second redistribution layer is formed on one side of the second substrate. For example, the number of metal traces in the second redistribution layer can be the same as that of the first redistribution layer in FIG4B , or can be different.

[0088] As shown in FIG5C , the back surface of the second substrate is thinned to expose the end surface of the second conductive via.

[0089] The structure shown in FIG3 can be obtained by bonding the structure shown in FIG4C and the structure shown in FIG5C using a wafer bonding process. The bonding process can be understood as a method of combining two wafers, or two structures made of other materials, through chemical and physical reactions.

[0090] Based on the preparation process of the above example, it is known that: after the redistribution layers are respectively prepared on two substrates, the wafer bonding process is used to bond the substrates integrated with the redistribution layers to obtain a double-sided redistribution layer structure. The preparation process of the first redistribution layer and the preparation process of the second redistribution layer are independent of each other and will not affect each other. For example, when the first redistribution layer and the second redistribution layer respectively include four layers of metal wiring, compared with the redistribution layers with four layers of metal wiring prepared on both sides of a substrate, the number of temperature shocks of the photoresist curing in the present application can be halved, reducing the probability of damage to the device, and significantly reducing the risk of warping and delamination, thereby improving the performance of the entire multi-layer chip stacking packaging structure.

[0091] In some examples, when the number of metal routing layers in the redistribution layer is greater than or equal to 4 layers, for example, greater than 5 layers of metal routing, the temperature shock of photoresist curing is more obvious. By using the methods shown in Figures 4A to 4C and Figures 5A to 5C of the examples of this application, the warping and delamination phenomena are more significantly weakened, thereby protecting the performance of the device.

[0092] Returning to FIG. 3 , in some examples, devices may be disposed above the first redistribution layer and below the second redistribution layer. The devices located in the first substrate and the second substrate are basically located in the middle layer of the entire packaging structure, and the risk of warping in the middle layer is greater.

[0093] However, this application places the first device in a first substrate and the second device in a second substrate, effectively encapsulating the devices with the substrates. The coefficient of thermal expansion (CTE) of either the first or second substrate in this application's examples can be 2ppm / k-3ppm / k. Therefore, the CTE of the substrate is substantially close to that of the devices. Encapsulating the devices with substrates having a smaller CTE difference can suppress warping of the first and second devices and reduce the risk of delamination between the substrate and the devices.

[0094] In some technologies, the first and second devices in the middle layer shown in Figure 3 can be encapsulated using a molding compound. This molding compound has a high coefficient of thermal expansion (CTE), for example, greater than or equal to 10 ppm / K, significantly different from the CTE of the devices, which can easily cause device warping. Furthermore, during the molding process, the liquid molding compound can easily impact the devices, causing them to drift. This makes it difficult to control the precision of the redistribution layer when it is subsequently fabricated, and can even affect the electrical connection between the redistribution layer and the devices.

[0095] In the example of this application, grooves can be opened in the first substrate and the second substrate, and the devices can be embedded in the grooves. The process is simple and the above-mentioned device drift and the difficulty of the redistribution layer preparation process will basically not occur.

[0096] Figure 6 is a structural diagram of another multi-layer chip stacking package structure provided in an embodiment of the present application, and Figure 7 is an enlarged view of point A in Figure 6. In conjunction with Figures 6 and 7, some devices disposed in the first substrate may be cavity-type devices. For example, device 13 disposed in the first substrate is a cavity-type device.

[0097] The structure of the cavity type device may be the structure shown in FIG8 . The cavity type device includes a substrate 1 , and a pattern layer 2 is provided on one side of the substrate 1 .

[0098] The cavity-type device further includes a packaging structure, such as a cover 3 . The cover 3 is buckled with the substrate 1 to accommodate the pattern layer 2 in the formed cavity 4 to protect the pattern layer 2 .

[0099] 6 and 7 , when the device 13 disposed in the first substrate is a cavity-type device, the pattern layer in the cavity-type device may face the second substrate, and the side of the second substrate facing the first substrate and the cavity-type device form a cavity, in which the pattern layer is located.

[0100] It can be understood that the present application can utilize the second substrate as the cover of the cavity-type device, thus omitting the cover structure, simplifying the packaging structure, and simplifying the process.

[0101] 6 and 7 illustrate that a cavity-type device is disposed in the first substrate. In other examples, a cavity-type device may be disposed in the first substrate and a cavity-type device may also be disposed in the second substrate.

[0102] For example, as shown in Figure 9, device 13 located in the first substrate and device 23 located in the second substrate are both cavity-type devices. The patterned layer of device 13 faces device 23, and the patterned layer of device 23 faces device 13. That is, device 13 and device 23 are arranged opposite each other, and the face-to-face devices 13 and 23 enclose a cavity. The patterned layers of device 13 and device 23 are located within the cavity they enclose. In other words, device 13 and device 23 act as lids for each other, with device 23 acting as a lid for device 13 and vice versa.

[0103] In some examples, devices located in the first substrate can be interconnected with devices located in the second substrate. For example, Figure 10 illustrates one electrical connection method. A third conductive via can be provided in device 13 located in the first substrate, electrically connecting the patterned layer of device 13 to the first redistribution layer located on one side of the first substrate. A fourth conductive via can be provided in device 23 located in the second substrate, electrically connecting the patterned layer of device 23 to the second redistribution layer located on one side of the second substrate. In this way, device 13 and device 23 can be interconnected using the conductive vias and the redistribution layer.

[0104] For example, when the device 13 and the device 23 are both filters, the filter device 13 and the filter device 23 can be connected in parallel or in series to realize a multiplex filter.

[0105] Figure 11 illustrates another electrical connection method in an embodiment of the present application. The patterned layer of device 13 located on the first substrate faces the second substrate, while the patterned layer of device 23 located on the second substrate faces the first substrate. The two patterned layers are interconnected using a bonding structure located between the first and second substrates. This shortens the interconnection path and improves device performance.

[0106] For example, the device 13 may be a filter, and the device 23 may be an integrated passive device IPD. The filter and the integrated passive device IPD are electrically connected to achieve integration of multifunctional devices.

[0107] In one implementation, as shown in FIG. 11 , a third conductive via may be provided in the device 13 , and the third conductive via electrically connects the pattern layer of the device 13 and the first redistribution layer.

[0108] Figure 12 is a structural diagram of another multi-layer chip stacking package structure provided in an embodiment of the present application. Compared to Figure 6 above, in this exemplary structure, at least one device is disposed on the side of the first redistribution layer facing away from the first substrate. For example, devices 31, 32, and 33 may be disposed on the first redistribution layer.

[0109] In order to protect the devices 31, 32 and 33, a first package body may be provided, and the first package body covers the devices 31, 32 and 33. The first package body may be made of a plastic packaging material.

[0110] Continuing with FIG12 , at least one device is disposed on the side of the second redistribution layer facing away from the second substrate. For example, device 41 may be disposed on the second redistribution layer. A second package may also be provided to cover device 41 to protect it or provide electromagnetic shielding. The second package may be made of a plastic encapsulation material.

[0111] The multi-layer chip stacking packaging structure of FIG12 of the example of the present application includes four device layers, which can achieve high-density integration of devices, so that the packaging structure meets the requirements of high-density miniaturization design.

[0112] In some examples, as shown in FIG12 , devices disposed on both sides of the first redistribution layer can be interconnected. For example, device 11 can be interconnected with at least one of device 31, device 32, and device 33. The pattern layer of device 11 can face the first redistribution layer, and the pattern layer of device 11 is electrically connected to the first redistribution layer. The pattern layers of devices 31, 32, and 33 can face the first redistribution layer, and the pattern layers of devices 31, 32, and 33 are electrically connected to the first redistribution layer. Thus, the first redistribution layer can be used to interconnect devices 11, 31, 32, and 33.

[0113] In other examples, as shown in FIG12 , devices disposed on both sides of the second redistribution layer can be interconnected. For example, at least one of device 21 and device 22 can be interconnected with device 41. The patterned layers of devices 21 and 22 can face the second redistribution layer, and the patterned layers of devices 21 and 22 are electrically connected to the second redistribution layer. The patterned layer of device 41 can face the second redistribution layer, and the patterned layer of device 41 is electrically connected to the second redistribution layer. Thus, the second redistribution layer can be used to interconnect devices 21, 22, and 41.

[0114] This means that the devices in the middle layer (devices located in the first and second substrates) can be partially interconnected upward and partially interconnected downward. The devices in the middle layer can be arranged vertically based on their respective functions, shortening the interconnection distance between the middle layer devices and the devices above and below them.

[0115] In the multi-layer chip stacking package structure shown in FIG12 , devices 31 , 32 and 33 are packaged in a first package, and device 41 is packaged in a second package. In some examples, the first package and the second package may be made of plastic.

[0116] Before using plastic packaging material to encapsulate devices 31, device 32 and device 33, devices 31, device 32 and device 33 can be connected to the first redistribution layer through a welding process. When these devices are then encapsulated using liquid plastic packaging material, the liquid plastic packaging material will basically not cause these devices to drift and will basically not affect the electrical connection between the devices and the redistribution layer.

[0117] In multi-layer chip stacking packaging, device heat dissipation is also a technical challenge. To improve heat dissipation, as shown in Figure 12, high-power, heat-dissipating devices can be placed in the upper and lower layers—for example, within the first package or the second package. This shortens the heat dissipation path and improves device heat dissipation efficiency.

[0118] In order to connect the multi-layer chip stacking packaging structure shown in Figure 12 to the circuit board, a connection structure can be set. As shown in Figure 12, it can be set on a connecting pin, one end of the connecting pin is electrically connected to the second redistribution layer, and the other end can be electrically connected to the circuit board, so that the multi-layer chip stacking packaging structure can communicate with other devices on the circuit board.

[0119] The present application also provides a method for preparing a multi-layer chip stacking package structure. FIG13 exemplarily shows a flowchart of preparing a multi-layer chip stacking package structure. The method includes:

[0120] S1: A first redistribution layer is formed on one side of a first substrate, wherein a first device is provided in the first substrate.

[0121] S2: A second redistribution layer is formed on one side of a second substrate, and a second device is provided in the second substrate.

[0122] S3: bonding a side of the first substrate facing away from the first redistribution layer to a side of the second substrate facing away from the second redistribution layer.

[0123] In the above-mentioned example method, before the first substrate and the second substrate are bonded, redistribution layers are first prepared on the first substrate and the second substrate respectively, and the two redistribution layers are arranged on different substrates instead of being integrated on one substrate. This can weaken the effects caused by the preparation of the redistribution layers, such as warping and delamination, or the degree of damage to the device.

[0124] The following describes in detail a method for preparing a multi-layer chip stacking packaging structure with reference to the accompanying drawings.

[0125] As shown in FIG14A , a groove is formed in the first substrate. The groove may not pass through two opposite surfaces of the first substrate.

[0126] The material of the first substrate in the example of the present application can be a semiconductor substrate, such as a silicon substrate, or a glass substrate.

[0127] 14A , a first conductive via is provided in the first substrate. The first conductive via may not pass through two opposite surfaces of the first substrate.

[0128] As shown in Figure 14B , the devices are placed in the grooves opened in Figure 14A . For example, in Figure 14B , device 11 , device 12 , and device 13 are placed in corresponding grooves, respectively.

[0129] In FIG. 14B , the pattern layers of the exemplary devices 11 and 12 are both facing upward, and the pattern layer of the device 13 is facing the bottom of the groove. The device 13 may be a cavity-type device.

[0130] In some scenarios, the orientation of the device pattern layer can be set according to the device interconnection method.

[0131] The number of devices disposed in the first substrate may be one or more.

[0132] As shown in FIG14C , a first redistribution layer is formed on one side of the first substrate, wherein the first redistribution layer can be interconnected with the devices 11 and 12 and can be interconnected with the first conductive via.

[0133] In some examples, the metal routing in the first redistribution layer can be 4 layers, 5 layers, or even more layers.

[0134] As shown in FIG14D , the structure obtained in FIG14C is temporarily bonded to a carrier.

[0135] As shown in FIG14E , the back surface of the first substrate is thinned so that the end surface of the first conductive via is exposed.

[0136] When the pattern layer of the device disposed in the first substrate is away from the first redistribution layer, the pattern layer of the device needs to be exposed when the first substrate is thinned. For example, as shown in FIG14E , the pattern layer of the cavity device needs to be exposed.

[0137] As shown in FIG14F , a groove is formed in the second substrate. The groove may not pass through the two opposite surfaces of the second substrate.

[0138] The material of the second substrate in the example of the present application can be the same as that of the first substrate, for example, it can be a silicon substrate or a glass substrate.

[0139] 14F , a second conductive via is provided in the second substrate. The second conductive via may not pass through two opposite surfaces of the second substrate.

[0140] As shown in Figure 14G , the devices are placed in the grooves opened in Figure 14F . For example, in Figure 14F , device 21 , device 22 , and device 23 are placed in corresponding grooves, respectively.

[0141] In FIG. 14G , the pattern layers of the exemplary devices 21 , 22 , and 23 are all facing upward.

[0142] The number of devices disposed in the second substrate may be one or more.

[0143] As shown in FIG14H , a second redistribution layer is formed on one side of the second substrate, wherein the second redistribution layer can be interconnected with devices 21 , 22 , and 12 ; and the second redistribution layer can be interconnected with the second conductive via.

[0144] In some examples, the metal routing in the second redistribution layer can be 4, 5, or even more layers, or less than 4 layers.

[0145] As shown in FIG14I , the structure obtained in FIG14H is temporarily bonded to a carrier.

[0146] As shown in FIG14J , the back surface of the second substrate is thinned so that the end surface of the second conductive via is exposed.

[0147] As shown in FIG14K , a wafer bonding process is used to bond the substrates shown in FIG14D and FIG14J , so that the first substrate and the second substrate are bonded together to obtain the multi-layer chip stacking structure shown in FIG14L .

[0148] In some optional processes, an anodic bonding process or a hybrid bonding process may be used to bond the first substrate and the second substrate.

[0149] In some processes, before wafer bonding the first substrate and the second substrate, the carrier bonded to the first substrate and the carrier bonded to the second substrate may be removed.

[0150] As shown in Figures 14C and 14H above, when preparing a multi-layer chip stacking packaging structure with a double-sided redistribution layer, the redistribution layer is first prepared on different substrates, and then the substrates with the redistribution layer are bonded and connected to realize a double-sided redistribution layer structure.

[0151] The preparation of double-sided redistribution layers will not affect each other, which can reduce the number of temperature shocks of photoresist curing, thereby reducing the risk of delamination or warping.

[0152] As shown in FIG14M , the multi-layer chip stack structure shown in FIG14L is temporarily bonded to a carrier, and devices are arranged on a side of the first redistribution layer away from the first substrate. For example, devices 31 , 32 and 33 may be arranged.

[0153] The pattern layers of devices 31 , 32 and 33 may all face the first redistribution layer to achieve interconnection with the first redistribution layer.

[0154] The device disposed on the first redistribution layer may be packaged to obtain a first package body as shown in FIG. 14M .

[0155] In some processes, such as FIG. 14M , a temporary bonding carrier may not be required.

[0156] As shown in FIG. 14N , the carrier in FIG. 14M is removed, and a device is disposed on a side of the second redistribution layer away from the second substrate. For example, device 41 may be disposed.

[0157] The devices disposed on the second redistribution layer may be packaged to obtain a second package body as shown in FIG. 14N .

[0158] Furthermore, a connecting pin may be manufactured, the connecting pin penetrating the second package body and interconnected with the second redistribution layer.

[0159] The pattern layers of the device 41 may all face the second redistribution layer and be interconnected with the second redistribution layer.

[0160] The four-layer stacked package structure as shown in FIG14N can be placed on a circuit board and electrically connected to the circuit board using connecting pins.

[0161] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0162] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A multi-layer chip stacking packaging structure, characterized in that: include: a first substrate, wherein a first device is disposed in the first substrate; A first redistribution layer is disposed on one side of the first substrate; a second substrate, wherein a second device is disposed in the second substrate; A second redistribution layer is disposed on one side of the second substrate; A side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

2. The multi-layer chip stacking package structure according to claim 1, characterized in that: The first device has a first pattern layer on a side facing the second substrate; The second substrate has a first side surface facing the first substrate, and the first side surface and the first device form a cavity; The first pattern layer is located in the cavity.

3. The multi-layer chip stacking package structure according to claim 1, characterized in that: The first device and the second device are arranged face to face, and the first device and the second device enclose a cavity; The first device has a first pattern layer on a side facing the second substrate; The second device has a second pattern layer on a side facing the first substrate; The first pattern layer and the second pattern layer are both located in the cavity.

4. The multi-layer chip stacking packaging structure according to claim 2 or 3, characterized in that: The first device includes at least one of a filter and a multiplexer.

5. The multi-layer chip stacking package structure according to claim 1, characterized in that: The first device and the second device are arranged face to face, and the pattern layer of the first device faces the pattern layer of the second device; The pattern layer of the first device is bonded to the pattern layer of the second device.

6. The multi-layer chip stacking packaging structure according to any one of claims 1 to 5, characterized in that: The pattern layer of the first device faces the second substrate; A conductive through hole is disposed in the first device along a thickness direction of the first device, and the conductive through hole electrically connects the first redistribution layer and the pattern layer of the first device.

7. The multi-layer chip stacking package structure according to claim 1, characterized in that: A third device is disposed on a side of the first redistribution layer facing away from the first substrate; The pattern layer of the first device faces the first redistribution layer, and the pattern layer of the third device faces the first redistribution layer; The pattern layer of the first device and the pattern layer of the third device are both electrically connected to the first redistribution layer.

8. The multi-layer chip stacking package structure according to claim 7, characterized in that: A fourth device is disposed on a side of the second redistribution layer facing away from the second substrate; The pattern layer of the second device faces the second redistribution layer, and the pattern layer of the fourth device faces the second redistribution layer; The pattern layer of the second device and the pattern layer of the fourth device are both electrically connected to the second redistribution layer.

9. The multi-layer chip stacking package structure according to claim 8, characterized in that: A first package is provided on the side of the first redistribution layer facing away from the first substrate, and the third device is located in the first package; a second package is provided on the side of the second redistribution layer facing away from the second substrate, and the fourth device is located in the second package.

10. A method for preparing a multi-layer chip stacking packaging structure, characterized in that: The preparation method comprises: A first redistribution layer is formed on one side of a first substrate, wherein a first device is disposed in the first substrate; Producing a second redistribution layer on one side of a second substrate, wherein a second device is disposed in the second substrate; A side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

11. The method for preparing a multi-layer chip stacking package structure according to claim 10, characterized in that: Before forming the first redistribution layer on one side of the first substrate, the preparation method further includes: A first groove is opened in the first substrate, and the first device is set in the first groove, with the pattern layer of the first device facing away from the opening of the first groove. After the first substrate and the second substrate are bonded, the pattern layer of the first device is located in a cavity surrounded by the first device and the second substrate.

12. The method for preparing a multi-layer chip stacking package structure according to claim 10, characterized in that: Before forming the first redistribution layer on one side of the first substrate and before forming the second redistribution layer on one side of the second substrate, the preparation method further includes: Opening a first groove in the first substrate, disposing the first device in the first groove, with the pattern layer of the first device facing away from the opening of the first groove; Opening a second groove in the second substrate, disposing the second device in the second groove, with the pattern layer of the second device facing away from the opening of the second groove; The bonding of the first substrate and the second substrate comprises: The pattern layer of the first device and the pattern layer of the second device are arranged face to face, the first device and the second device surround a cavity, and the pattern layer of the first device and the pattern layer of the second device are both located in the cavity.

13. The method for preparing a multi-layer chip stacking packaging structure according to any one of claims 10 to 12, characterized in that: After the first substrate and the second substrate are bonded, the preparation method further includes: Disposing a third device on a side of the first redistribution layer away from the first substrate; A fourth device is disposed on a side of the second redistribution layer facing away from the second substrate.

14. An electronic device, characterized in that: include: Circuit boards; The multi-layer chip stacking packaging structure as described in any one of claims 1-9, wherein the multi-layer chip stacking packaging structure is arranged on the circuit board.

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