Shift register and driving method therefor, gate driving circuit, and display device

Abstract

Disclosed are a shift register and a driving method therefor, a gate driving circuit, and a display device. The shift register comprises: an input sub-circuit; a first control sub-circuit configured to transmit a signal of a first clock signal end to a second node in response to control of a first node and transmit a first level signal of a first level end to the second node in response to control of the first clock signal end; a second control sub-circuit configured to transmit a second level signal to the first node in response to control of the second node and a second clock signal end; a first output sub-circuit configured to transmit the first level signal of the first level end to an output end in response to the control of the first node; a second output sub-circuit configured to connect a second level end and the output end in response to control of the first node, the second node, and the second clock signal end; and a first leakage prevention sub-circuit configured to provide the first level signal for the second node at least when the first level signal is provided at the input end.

Description

Shift register and driving method thereof, gate driving circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology.

[0003] A shift register circuit composed of thin film transistors (TFTs) is integrated on an array substrate of a display substrate using GOA technology to form a scan drive for the display substrate. Summary of the Invention

[0004] In a first aspect, the present disclosure provides a shift register, comprising:

[0005] an input subcircuit configured to transmit an input signal at the input terminal to the first node in response to control of the first clock signal terminal;

[0006] a first control subcircuit configured to transmit the signal of the first clock signal terminal to the second node in response to control of the first node; and transmit the first level signal of the first level terminal to the second node in response to control of the first clock signal terminal;

[0007] a second control subcircuit configured to transmit the second level signal of the second level terminal to the first node in response to control of the second node and the second clock signal terminal;

[0008] a first output sub-circuit configured to transmit the first-level signal at the first-level end to the output end of the shift register in response to control of the first node;

[0009] a second output sub-circuit configured to connect the second level terminal to the output terminal in response to control of the first node, the second node and the second clock signal terminal;

[0010] a first leakage-proof electronic circuit configured to provide the first-level signal to the second node at least when the first-level signal is provided at the input terminal;

[0011] The first node is a connection node between the input sub-circuit, the first control sub-circuit, and the second control sub-circuit, and the second node is a connection node between the first control sub-circuit and the second control sub-circuit.

[0012] In some embodiments, the first leakage-proof electronic circuit comprises:

[0013] A twelfth transistor, wherein the control electrode and the first electrode of the twelfth transistor are both electrically connected to the first level end, and the second electrode of the twelfth transistor is electrically connected to the second node.

[0014] In some embodiments, the first leakage-proof electronic circuit comprises:

[0015] an eleventh transistor, wherein a control electrode of the eleventh transistor is electrically connected to the input terminal, and a first electrode of the eleventh transistor is electrically connected to the first level terminal;

[0016] A twelfth transistor, wherein the control electrode of the twelfth transistor is electrically connected to the second electrode of the eleventh transistor, the first electrode of the twelfth transistor is electrically connected to the first level end, and the second electrode of the twelfth transistor is electrically connected to the second node.

[0017] In some embodiments, the second control subcircuit includes:

[0018] a fourteenth transistor, wherein a control electrode of the fourteenth transistor is electrically connected to the second node, and a first electrode of the fourteenth transistor is electrically connected to the second level end;

[0019] a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second node, and a first electrode of the seventh transistor and a second electrode of the fourteenth transistor are connected to a sixth node;

[0020] a second transistor, wherein a control electrode of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the second transistor is electrically connected to the first node;

[0021] The shift register further includes a second anti-leakage electronic circuit configured to transmit the first level signal to the sixth node in response to at least control of the first node.

[0022] In some embodiments, the second leakage-proof electronic circuit comprises:

[0023] A fifteenth transistor, wherein the control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode is electrically connected to the first level end, and the second electrode is electrically connected to the sixth node.

[0024] In some embodiments, the first leakage prevention electronic circuit and the second leakage prevention electronic circuit are connected to a seventh node, and the first leakage prevention electronic circuit is further configured to transmit the first level signal to the seventh node in response to the input signal;

[0025] The second leakage-proof electronic circuit comprises:

[0026] a thirteenth transistor, having a control electrode electrically connected to the seventh node, a first electrode electrically connected to the second level end, and a second electrode electrically connected to the sixth node directly or via a fourth capacitor;

[0027] A fifteenth transistor has a control electrode electrically connected to the first node, a first electrode electrically connected to the first level end, and a second electrode electrically connected to the sixth node.

[0028] In some embodiments, the input sub-circuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

[0029] In some embodiments, the first control subcircuit includes:

[0030] a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first node, a first electrode is electrically connected to the first clock signal terminal, and a second electrode is electrically connected to the second node;

[0031] A sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first clock signal end, a first electrode is electrically connected to the first level end, and a second electrode is electrically connected to the second node.

[0032] In some embodiments, the first output sub-circuit includes:

[0033] a third transistor, wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode is electrically connected to the first level end, and a second electrode is electrically connected to the output end;

[0034] A third capacitor, wherein two ends of the third capacitor are electrically connected to the first node and the second clock signal end respectively.

[0035] In some embodiments, the second output subcircuit includes: a first output control unit, a second output control unit, and an output unit; the first output control unit and the second output control unit are connected to a fourth node, and the second output control unit and the output unit are connected to a fifth node;

[0036] The first output control unit is configured to transmit the signal of the second clock signal terminal to the fourth node in response to control of the second node;

[0037] The second output control unit is configured to transmit the signal of the fourth node to the fifth node in response to the control of the second clock signal terminal; and transmit the second level signal to the fifth node in response to the control of the first node;

[0038] The output unit is configured to transmit the first level signal to the output terminal in response to control of the fifth node.

[0039] In some embodiments, the first output control unit includes:

[0040] an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the second node, a first electrode is electrically connected to the second clock signal terminal, and a second electrode is electrically connected to the fourth node;

[0041] A second capacitor, wherein two ends of the second capacitor are electrically connected to the second node and the fourth node respectively.

[0042] In some embodiments, the second output control unit includes:

[0043] a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the second clock signal terminal, a first electrode of the ninth transistor is electrically connected to the fourth node, and a second electrode of the ninth transistor is electrically connected to the fifth node;

[0044] A tenth transistor, wherein a control electrode of the tenth transistor is electrically connected to the first node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the fifth node.

[0045] In some embodiments, the output unit includes:

[0046] a first capacitor, wherein two ends of the first capacitor are electrically connected to the second level end and the fifth node respectively;

[0047] A fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the fifth node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the output end.

[0048] In a second aspect, the present disclosure further provides a driving method for the shift register as described above, comprising:

[0049] In the first stage, the input terminal and the first clock signal terminal both provide a first-level signal, the second clock signal terminal provides a second-level signal, the input subcircuit transmits the signal from the input terminal to the first node, and the first output subcircuit disconnects the output terminal from the first-level terminal; the first control subcircuit and the first leakage prevention electronic circuit provide a first-level signal to the second node, the second output subcircuit maintains the disconnection state between the second-level terminal and the output terminal; and the output terminal continues to output the first-level signal of the previous stage;

[0050] In the second stage, the input terminal and the first clock signal terminal both provide a second-level signal, the second clock signal terminal provides a first-level signal, the second control subcircuit transmits the second-level signal of the second-level terminal to the first node, and the second output subcircuit transmits the second-level signal of the second signal terminal to the output terminal;

[0051] In the third stage, the input terminal and the second clock signal terminal both provide a second level signal, the first clock signal terminal provides a first level signal, the first control subcircuit transmits the first level signal of the first level terminal to the second node, and the second output subcircuit maintains a conductive state between the second level terminal and the output terminal;

[0052] In a fourth stage, the input terminal and the second clock signal terminal both provide first-level signals, the first clock signal terminal provides a second-level signal, the second control subcircuit transmits the second-level signal from the second-level terminal to the first node, and the first leakage prevention electronic circuit provides the first-level signal to the second node; the second output subcircuit transmits the second-level signal from the second signal terminal to the output terminal;

[0053] In the fifth stage, the input end and the first clock signal end both provide a first level signal, the second clock signal end provides a second level signal, the input sub-circuit transmits the first level signal of the input end to the first node, the first leakage prevention electronic circuit provides the first level signal to the second node, the second output sub-circuit disconnects the output end from the second level end; and the first output sub-circuit transmits the first level signal of the first level signal end to the output end.

[0054] In a third aspect, the present disclosure further provides a gate driving circuit comprising a plurality of cascaded shift registers as described above.

[0055] In a fourth aspect, the present disclosure further provides a display device comprising the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0057] FIG1 is a schematic diagram of a shift register provided in some embodiments.

[0058] FIG2 is a driving timing diagram of the shift register shown in FIG1 in a normal state.

[0059] FIG3 is a schematic structural diagram of a shift register provided in some embodiments of the present disclosure.

[0060] FIG4 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0061] FIG5 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0062] FIG6 is an operation timing diagram of the shift register shown in FIG5 .

[0063] FIG7 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0064] FIG8 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0065] FIG9 is a schematic diagram of a driving method of a shift register provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0066] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0067] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0068] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0069] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, to distinguish the source and drain of the transistor, one of the electrodes is referred to as the first electrode, the other electrode is referred to as the second electrode, and the gate is referred to as the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. The following embodiments are described using N-type transistors. When an N-type transistor is used, the first electrode is the source of the N-type transistor and the second electrode is the drain of the N-type transistor. When the gate input is high, the source and drain are conductive, while the P-type is the opposite. It is conceivable that the use of P-type transistors is something that a person skilled in the art can easily come up with without creative effort, and therefore it is also within the scope of protection of the embodiments of the present disclosure. In addition, according to the material of the active layer in the transistor, transistors can be divided into types such as oxide thin-film transistors and low-temperature polysilicon thin-film transistors. Generally, oxide thin-film transistors are N-type transistors, and low-temperature polysilicon thin-film transistors are P-type transistors.

[0070] In the present disclosure, "first-level signal" / "first-level potential" refers to a signal / potential that can control the conduction of a transistor after being input to the control electrode of a transistor, and "second-level signal" refers to a signal / potential that can control the cutoff of a transistor after being input to the control electrode of a transistor. In some embodiments, the first-level signal can be a high-level signal, and the first-level potential is a high-level potential; the second-level signal can be a low-level signal, and the second-level potential is a low-level potential; in other embodiments, the first-level signal is a low-level signal, and the first-level potential is a low-level potential; the second-level signal is a high-level signal, and the second-level potential is a high-level potential. For an N-type transistor, the first-level signal is a high-level signal, and the first-level potential is a high-level potential; the second-level signal is a low-level signal, and the second-level potential is a low-level potential. For a P-type transistor, the first-level signal is a low-level signal, and the first-level potential is a low-level potential; the second-level signal is a high-level signal, and the second-level potential is a high-level potential.

[0071] In the display substrate, a plurality of gate lines and a plurality of data lines intersect in the display area to define a plurality of pixels. A pixel circuit and a light-emitting device are provided in each pixel. The working phases of the pixel circuit include a data writing phase and a light-emitting phase. In the data writing phase, the pixel circuit responds to the scanning signal on the gate line to write the data voltage and the threshold voltage into the storage capacitor, thereby performing threshold compensation; in the light-emitting phase, the pixel circuit responds to the light-emitting control signal on the light-emitting control line to provide a driving current for the light-emitting device. Among them, the structure of the above-mentioned light-emitting device includes multiple types, which can be selected and set according to actual needs. For example, the above-mentioned light-emitting device can be an OLED (Organic Light-Emitting Diode), a quantum dot light-emitting diode (QLED) or a micro light-emitting diode (Micro LED).

[0072] The peripheral area of ​​the display substrate is provided with multiple gate drive circuits, each of which includes multiple cascaded shift registers. For example, the peripheral area is provided with a first gate drive circuit and a second gate drive circuit. The first gate drive circuit includes multiple cascaded first shift registers, which are connected to the gate lines and sequentially provide scanning signals to the multiple gate lines. The second gate drive circuit includes multiple cascaded second shift registers, which are connected to the light control lines and sequentially provide light control signals to the multiple light control lines.

[0073] FIG1 is a schematic diagram of a shift register provided in some embodiments. As shown in FIG1 , the shift register includes an input subcircuit 10 , a first control subcircuit 20 , a second control subcircuit 30 , a first output subcircuit 40 , and a second output subcircuit 50 .

[0074] The input sub-circuit 10 is electrically connected to the shift register input terminal EIN, the first node n1, and the first clock signal terminal CLK, and is configured to transmit the input signal at the input terminal EIN to the first node n1 in response to the control of the first clock signal terminal CLK. The first control sub-circuit 20 is electrically connected to the first node n1, the second node n2, the first clock signal terminal CLK, and the first level terminal V1, and is configured to transmit the signal at the first clock signal terminal CLK to the second node n2 in response to the control of the first node n1; and to transmit the first level signal at the first level terminal V1 to the second node n2 in response to the control of the first clock signal terminal CLK. The second control sub-circuit 30 is connected to the second node n2, the second clock signal terminal CKB, and the second level terminal V2, and is configured to transmit the second level signal at the second level terminal V2 to the first node n1 in response to the control of the second node n2 and the second clock signal terminal CKB. The first output sub-circuit 40 is electrically connected to the first level terminal V1, the first node n1, and the output terminal EOUT of the shift register, and is configured to transmit the first level signal of the first level terminal V1 to the output terminal EOUT of the shift register in response to the control of the first node n1. The second output sub-circuit 50 is electrically connected to the first node n1, the second node n2, the second clock signal terminal CKB, the second level terminal V2, and the output terminal EOUT, and is configured to connect the second level terminal V2 to the output terminal EOUT in response to the control of the first node n1, the second node n2, and the second clock signal terminal CKB. Optionally, the second output sub-circuit 50 connects the second level terminal V2 to the output terminal EOUT in response to the second level signal of the first node n1, the first level signal of the second node n2 and the first level signal of the second clock signal terminal CKB; and maintains the on-off state of the second level terminal V2 and the output terminal EOUT in response to the second level signal of the first node n1, the first level signal of the second node n2 and the second level signal of the second clock signal terminal CKB; and disconnects the second level terminal V2 from the output terminal EOUT in response to the first level signal of the first node n1 and the second level signal of the second node n2.

[0075] In one example, the first control subcircuit 20 may specifically include a fifth transistor M5 and a sixth transistor M6. The control electrode of the fifth transistor M5 is electrically connected to the first node n1, the first electrode is electrically connected to the first clock signal terminal CLK, and the second electrode is electrically connected to the second node n2. The control electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLK, the first electrode is electrically connected to the first level terminal V1, and the second electrode is electrically connected to the second node n2. The second control subcircuit 30 may specifically include a seventh transistor M7 and a second transistor M2. The control electrode of the seventh transistor M7 is electrically connected to the second node n2, the first electrode is electrically connected to the second level terminal V2, and the second electrode is connected to the first electrode of the second transistor M2 and the third node n3. The control electrode of the second transistor M2 is electrically connected to the second clock signal terminal CKB, and the second electrode is electrically connected to the first node n1.

[0076] FIG2 is a driving timing diagram of the shift register shown in FIG1 under normal conditions. This embodiment is described by taking each transistor as an N-type transistor, the first level signal as a high level signal, and the second level signal as a low level signal as an example. As shown in FIG2 , in the first stage t1, the input terminal EIN and the second clock signal terminal CKB both provide a second level signal, and the first clock signal terminal CLK provides a first level signal. At this time, the sixth transistor M6 is turned on, thereby transmitting the first level signal of the first level terminal V1 to the second node n2. In addition, the first transistor M1 is turned on, thereby transmitting the second level signal of the input terminal EIN to the first node n1, thereby controlling the third transistor M3 to be turned off. The second output subcircuit 50 maintains the disconnection state between the second level terminal V2 and the output terminal EOUT. The output terminal EOUT continues to output the first level signal of the previous stage.

[0077] During the second phase t2, the input terminal EIN and the first clock signal terminal CLK both provide a second-level signal, and the second clock signal terminal CKB provides a first-level signal. At this point, the second control sub-circuit 30 transmits the second-level signal from the second-level terminal V2 to the first node n1, causing the first output sub-circuit 40 to disconnect the first-level terminal V1 from the output terminal EOUT. The fifth transistor M5 and the sixth transistor M6 in the first control sub-circuit 20 are both turned off, and the second node n2 remains at the first-level potential. The second output sub-circuit 50 connects the second-level terminal V2 to the output terminal EOUT, causing the output terminal EOUT to output the second-level signal.

[0078] In the third phase t3, both the input terminal EIN and the second clock signal terminal CKB provide a second-level signal, and the first clock signal terminal CLK provides a first-level signal. At this point, the input sub-circuit 10 transmits the second-level signal from the input terminal EIN to the first node n1, causing the first output sub-circuit 40 to disconnect the first-level terminal V1 from the output terminal EOUT. The sixth transistor M6 of the first control sub-circuit 20 is turned on, thereby transmitting the first-level signal from the first-level terminal V1 to the second node n2. The second output sub-circuit 50 maintains the conductive state between the second-level terminal V2 and the output terminal EOUT in response to the second-level signal from the first node n1, the first-level signal from the second node n2, and the second-level signal from the second clock signal terminal CKB.

[0079] In the fourth stage t4, the input terminal EIN and the second clock signal terminal CKB both provide first level signals, and the first clock signal terminal CLK provides second level signals. The operation process of this stage is the same as that of the second stage.

[0080] In the fifth phase t5, the input terminal EIN and the first clock signal terminal CLK both provide a first-level signal, and the second clock signal terminal CKB provides a second-level signal. The input sub-circuit 10 transmits the first-level signal from the input terminal EIN to the first node n1, thereby causing the first output sub-circuit 40 to connect the first-level terminal V1 to the output terminal EOUT, and the output terminal EOUT outputs the first-level signal. In addition, the fifth transistor M5 and the sixth transistor M6 of the first control sub-circuit 20 are turned on, thereby transmitting the first-level terminal V1 and the first-level signal from the first clock signal terminal CLK to the second node n2. In response to the first-level signal from the first node n1, the second output sub-circuit 50 disconnects the second-level terminal V2 from the output terminal EOUT.

[0081] In the sixth phase t6, both the input terminal EIN and the second clock signal terminal CKB provide first-level signals, and the second clock signal terminal CKB provides a first-level signal. At this point, the input sub-circuit 10 disconnects the first node n1 from the input terminal EIN, maintaining the first-level potential of the previous phase. The first output sub-circuit 40 maintains the connection between the output terminal EOUT and the first-level potential terminal V1. Furthermore, the fifth transistor M5 turns on, transmitting the second-level potential of the first clock signal terminal CLK to the second node n2. In response to the first-level potential of the first node n1, the second output sub-circuit 50 disconnects the second-level potential terminal V2 from the output terminal EOUT.

[0082] Optionally, the working process of the shift register also includes between the third stage t3 and the fourth stage t4: a first holding stage t31 and a second holding stage t32, wherein the signal timing of the shift register in the first holding stage t31 is the same as that in the second stage t2, and the signal timing of the second holding stage t32 is the same as that in the third stage t3, which will not be repeated here.

[0083] During the operation of the shift register, when the transistors do not leak, the shift register can operate normally. However, when the transistors leak, the normal output of the shift register cannot be guaranteed. For example, if the threshold voltage Vth of the fifth transistor M5 is greater than 0, when the signals of the first node n1 and the first clock signal terminal CLK are both second-level signals, the voltage difference Vgs between the control electrode and the first electrode of the fifth transistor M5 is less than the threshold voltage, so the fifth transistor M5 is turned off. If the threshold voltage of the fifth transistor M5 shifts to less than 0, when the signals of the first node n1 and the first clock signal terminal CLK are both second-level signals, the fifth transistor M5 cannot be turned off, resulting in leakage of the second node n2; when the second node n2 drops to the second-level potential, the output terminal EOUT continues to output the first-level signal. Similarly, when the threshold voltages of the transistors in the input sub-circuit 10 and the second control sub-circuit 30 shift to less than 0, leakage will occur at the third node n3. In this case, the second-level signal output by the output terminal EOUT is normal, but when the signal of the first clock signal terminal CLK changes, the signal of the output terminal EOUT will also fluctuate.

[0084] FIG3 is a schematic diagram of the structure of a shift register provided in some embodiments of the present disclosure. As shown in FIG3 , the shift register includes an input subcircuit 10, a first control subcircuit 20, a second control subcircuit 30, a first output subcircuit 40, a second output subcircuit 50, and a first anti-leakage electronic circuit 60. The input subcircuit 10, the first control subcircuit 20, and the second control subcircuit 30 are connected to a first node n1; the first control subcircuit 20, the second control subcircuit 30, and the first anti-leakage electronic circuit 60 are connected to a second node n2.

[0085] The input sub-circuit 10 is configured to transmit an input signal from the input terminal EIN to the first node n1 in response to control of the first clock signal terminal CLK. The first control sub-circuit 20 is configured to transmit the signal from the first clock signal terminal CLK to the second node n2 in response to control of the first node n1; and to transmit the first-level signal from the first level terminal V1 to the second node n2 in response to control of the first clock signal terminal CLK. The second control sub-circuit 30 is configured to transmit the second-level signal from the second level terminal V2 to the first node n1 in response to control of the second node n2 and the second clock signal terminal CKB. The first output sub-circuit 40 is configured to transmit the first-level signal from the first level terminal V1 to the output terminal EOUT of the shift register in response to control of the first node n1. The second output sub-circuit 50 is configured to connect the second level terminal V2 to the output terminal EOUT in response to control of the first node n1, the second node n2, and the second clock signal terminal CKB. The second output sub-circuit 50 is configured to connect the second level terminal V2 and the output terminal EOUT in response to the second level signal of the first node n1, the first level signal of the second node n2, and the first level signal of the second clock signal terminal CKB; maintain the conductive state between the second level terminal V2 and the output terminal EOUT in response to the second level signal of the first node n1, the first level signal of the second node n2, and the second level signal of the second clock signal terminal CKB; and disconnect the output terminal EOUT from the second level terminal V2 in response to the first level signal of the first node n1 and the second level signal of the second node n2. The first leakage prevention electronic circuit 60 is configured to provide a first level signal to the second node n2 at least when the input terminal EIN provides a first level signal.

[0086] Compared with the shift register shown in Figure 1, the shift register in Figure 2 also includes a first leakage prevention electronic circuit 60, and the first leakage prevention electronic circuit 60 provides a first level signal to the second node n2 at least when the input terminal EIN provides a first level signal, thereby preventing the potential of the second node n2 from decreasing due to leakage of the transistor in the second control sub-circuit 30, thereby reducing or preventing output abnormalities caused by the potential of the second node n2.

[0087] FIG4 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure. As shown in FIG4 , the second control subcircuit 30 of the shift register includes a fourteenth transistor M14, a seventh transistor M7, and a second transistor M2. The control electrode of the fourteenth transistor M14 is electrically connected to the second node n2, and the first electrode of the fourteenth transistor M14 is electrically connected to the second level terminal V2. The control electrode of the seventh transistor M7 is electrically connected to the second node n2, and the first electrode of the seventh transistor M7 and the second electrode of the fourteenth transistor M14 are connected to the sixth node n6. The control electrode of the second transistor M2 is electrically connected to the second clock signal terminal CKB, the first electrode of the second transistor M2 and the second electrode of the seventh transistor M7 are connected to the third node n3, and the second electrode of the second transistor M2 is electrically connected to the first node n1. When the second node n2 is at a first level and the second clock signal terminal CKB provides a first level signal, the fourteenth transistor M14, the seventh transistor M7, and the second transistor M2 are turned on, thereby transmitting the second level signal from the second level terminal V2 to the first node n1.

[0088] As shown in Figure 4, the shift register also includes a second leakage prevention electronic circuit 70, which is electrically connected to the sixth node n6 and the first node n1, and is configured to transmit the first level signal to the sixth node n6 in response to at least the control of the first node n1, so as to reduce the voltage between the control electrode and the second electrode of the fourteenth transistor M14 and the voltage between the control electrode and the first electrode of the seventh transistor M7, thereby reducing the leakage of the transistor between the first node n1 and the second level end V2 due to the threshold voltage offset, which is beneficial to maintaining the voltage of the third node n3 and reducing the output abnormality of the third node n3 caused by leakage.

[0089] FIG5 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure. The shift register illustrated in FIG5 is a specific implementation of FIG4 . As shown in FIG5 , the input subcircuit 10 includes a first transistor M1. The control electrode of the first transistor M1 is electrically connected to the first clock signal terminal CLK, the first electrode is electrically connected to the input terminal EIN, and the second electrode is electrically connected to the first node n1. When the first clock signal terminal CLK provides a first level signal, the first transistor M1 is turned on, thereby transmitting the signal at the input terminal EIN to the first node n1.

[0090] As shown in FIG5 , the first control subcircuit 20 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 has a control electrode electrically connected to the first node n1, a first electrode electrically connected to the first clock signal terminal CLK, and a second electrode electrically connected to the second node n2. The sixth transistor M6 has a control electrode electrically connected to the first clock signal terminal CLK, a first electrode electrically connected to the first level terminal V1, and a second electrode electrically connected to the second node n2. When the first node n1 is at a first level, the fifth transistor M5 is turned on, thereby transmitting the signal from the first clock signal terminal CLK to the second node n2. When the first clock signal terminal CLK provides a first level signal, the sixth transistor M6 is turned on, thereby transmitting the signal from the first level terminal V1 to the second node n2.

[0091] The second control subcircuit 30 includes a fourteenth transistor M14, a seventh transistor M7, and a second transistor M2. The control electrode of the fourteenth transistor M14 is electrically connected to the second node n2, and the first electrode of the fourteenth transistor M14 is electrically connected to the second level terminal V2. The control electrode of the seventh transistor M7 is electrically connected to the second node n2, and the first electrode of the seventh transistor M7 and the second electrode of the fourteenth transistor M14 are connected to the sixth node n6. The control electrode of the second transistor M2 is electrically connected to the second clock signal terminal CKB, the first electrode of the second transistor M2 is electrically connected to the second electrode of the seventh transistor M7, and the second electrode of the second transistor M2 is electrically connected to the first node n1. When the second node n2 is at the first level and the second clock signal terminal CKB provides a first level signal, the fourteenth transistor M14, the seventh transistor M7, and the second transistor M2 are turned on, thereby transmitting the second level signal from the second level terminal V2 to the first node n1.

[0092] The first output sub-circuit 40 includes a third transistor M3 and a third capacitor C3. The control electrode of the third transistor M3 is electrically connected to the first node n1, the first electrode is electrically connected to the first level terminal V1, and the second electrode is electrically connected to the output terminal EOUT. The terminals of the third capacitor C3 are electrically connected to the first node n1 and the second clock signal terminal CKB, respectively. When the first node n1 is at a first level, the third transistor M3 is turned on, thereby transmitting the first level signal of the first level terminal V1 to the output terminal EOUT. Furthermore, when the first node n1 is in a floating state, the voltage stabilizing effect of the third capacitor C3 allows the first node n1 to maintain the voltage at the previous stage.

[0093] The second output sub-circuit 50 includes a first output control unit 51, a second output control unit 52, and an output unit 53. The first and second output control units 51 and 52 are connected to a fourth node n4, while the second and output units 52 and 53 are connected to a fifth node n5. The first output control unit 51 is configured to transmit the signal of the second clock signal terminal CKB to the fourth node n4 in response to control of the second node n2. The second output control unit 52 is configured to transmit the signal of the fourth node n4 to the fifth node n5 in response to control of the second clock signal terminal CKB; and to transmit a second-level signal to the fifth node n5 in response to control of the first node n1. The output unit 53 is configured to transmit a first-level signal to the output terminal EOUT in response to control of the fifth node n5.

[0094] Specifically, the first output control unit 51 can be configured to transmit the signal of the second clock signal terminal CKB to the fourth node n4 in response to a first-level signal at the second node n2; disconnect the second clock signal terminal CKB from the fourth node n4 in response to a second-level signal at the second node n2; and maintain the voltage between the second node n2 and the fourth node n4 unchanged when the second node n2 is floating. The second output control unit 52 can be configured to connect the fourth node n4 to the fifth node n5 in response to a first-level signal at the second clock signal terminal CKB; and connect the fifth node n5 to the second level terminal V2 in response to a first-level signal at the first node n1. The output unit 53 can be configured to transmit the second-level signal of the second level terminal V2 to the output terminal EOUT in response to a first-level signal at the fifth node n5; and maintain the voltage between the second level terminal V2 and the fifth node n5 unchanged when the fifth node n5 is floating.

[0095] As shown in FIG5 , the first output control unit 51 may include an eighth transistor M8 and a second capacitor C2. The eighth transistor M8 has a control electrode electrically connected to the second node n2, a first electrode electrically connected to the second clock signal terminal CKB, and a second electrode electrically connected to the fourth node n4. The second capacitor C2 has two terminals electrically connected to the second node n2 and the fourth node n4, respectively. When the second node n2 is at a first potential level, the eighth transistor M8 is turned on, thereby transmitting the signal from the second clock signal terminal CKB to the fourth node n4. When the second node n2 is in a floating state, the voltage between the second node n2 and the fourth node n4 remains unchanged due to the bootstrapping effect of the second capacitor C2.

[0096] As shown in FIG5 , the second output control unit 52 includes a ninth transistor M9 and a tenth transistor M10. The ninth transistor M9 has a control electrode electrically connected to the second clock signal terminal CKB, a first electrode electrically connected to the fourth node n4, and a second electrode electrically connected to the fifth node n5. The tenth transistor M10 has a control electrode electrically connected to the first node n1, a first electrode electrically connected to the second level terminal V2, and a second electrode electrically connected to the fifth node n5. When the second clock signal terminal CKB provides a first level signal, the ninth transistor M9 turns on, thereby electrically connecting the fourth node n4 to the fifth node n5. When the first node n1 is at a first level, the tenth transistor M10 turns on, thereby electrically connecting the second level terminal V2 to the fifth node n5.

[0097] As shown in FIG5 , the output unit 53 includes a first capacitor C1 and a fourth transistor M4. The two ends of the first capacitor C1 are electrically connected to the second level terminal V2 and the fifth node n5, respectively. The control electrode of the fourth transistor M4 is electrically connected to the fifth node n5, the first electrode is electrically connected to the second level terminal V2, and the second electrode is electrically connected to the output terminal EOUT. When the fifth node n5 is at a first level, the fourth transistor M4 is turned on, thereby transmitting the second level signal of the second level terminal V2 to the output terminal EOUT. When the fifth node n5 is at a second level, the fourth transistor M4 disconnects the second level terminal V2 from the output terminal EOUT. When the fifth node n5 is floating, the voltage stabilization effect of the first capacitor C1 allows the fifth node n5 to maintain the voltage of the previous stage.

[0098] As shown in FIG5 , the first leakage prevention circuit 60 includes a twelfth transistor M12. The control electrode and the first electrode of the twelfth transistor M12 are both electrically connected to the first level terminal V1, and the second electrode of the twelfth transistor M12 is electrically connected to the second node n2. At this time, the twelfth transistor M12 is in a continuously on state, thereby continuously supplying power to the second node n2.

[0099] As shown in FIG5 , the second leakage prevention circuit 70 includes a fifteenth transistor M15. The control electrode of the fifteenth transistor M15 is electrically connected to the first node n1, the first electrode of the fifteenth transistor M15 is electrically connected to the first level terminal V1, and the second electrode of the fifteenth transistor M15 is electrically connected to the sixth node n6. When the first node n1 is at a first level, the fifteenth transistor M15 transmits the first level signal of the first level terminal V1 to the sixth node n6. When the first node n1 is at a second level, the fifteenth transistor M15 disconnects the first level terminal V1 from the sixth node n6.

[0100] FIG6 is an operating timing diagram of the shift register shown in FIG5 . The operating process of the shift register in the embodiment of the present disclosure is described below in conjunction with FIG5 and FIG6 . The description is given using an example in which each transistor in the shift register is an N-type transistor. In this case, a high-level signal serves as a first-level signal, and a low-level signal serves as a second-level signal.

[0101] In the first phase t1, both the input terminal EIN and the second clock signal terminal CKB provide low-level signals, while the first clock signal terminal CLK provides a high-level signal. At this point, the first transistor M1 turns on, transmitting the low-level signal from the input terminal EIN to the first node n1, thereby controlling the third transistor M3, the fifth transistor M5, and the fifteenth transistor M15 to turn off. Furthermore, the sixth transistor M6 and the twelfth transistor M12 turn on, transmitting the high-level signal from the first level terminal V1 to the second node n2. Because the second node n2 receives a high-level signal, the seventh transistor M7, the fourteenth transistor M14, and the eighth transistor M8 turn on, transmitting the low-level signal from the second clock signal terminal CKB to the fourth node n4 via the eighth transistor M8. Simultaneously, the ninth transistor M9 and the tenth transistor M10 turn off, the fifth node n5 maintains the low-level potential from the previous phase, and the fourth transistor M4 remains disconnected from the previous phase. Since there is no discharge path at the output terminal EOUT, the high-level signal from the previous phase is maintained.

[0102] In the second phase t2, the input terminal EIN and the first clock signal terminal CLK both provide low-level signals, and the second clock signal terminal CKB provides a high-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off. Under the voltage regulation effect of the third capacitor C3, the first node n1 maintains a low-level potential, thereby controlling the third transistor M3, the fifth transistor M5, and the fifteenth transistor M15 to be turned off. The twelfth transistor M12 is turned on, causing the second node n2 to be at a high-level potential, thereby controlling the fourteenth transistor M14, the seventh transistor M7, and the eighth transistor M8 to be turned on. In addition, the second transistor M2 is turned on, thereby transmitting the low-level signal of the second level terminal V2 to the first node n1, and the tenth transistor M10 is turned off. The high-level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8, and since the ninth transistor M9 is turned on under the control of the high-level signal provided by the second clock signal terminal CKB, the fifth node n5 receives the high-level signal of the fourth node n4, thereby controlling the fourth transistor M4 to be turned on, and the low-level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0103] In the third phase t3, the input terminal EIN and the second clock signal terminal CKB provide low-level signals, while the first clock signal terminal CLK provides a high-level signal. At this point, the first transistor M1 turns on, transmitting the low-level signal from the input terminal EIN to the first node n1, thereby controlling the third transistor M3, the fifth transistor M5, and the tenth transistor M10 to remain off. Simultaneously, the sixth transistor M6 and the twelfth transistor M12 turn on, causing the second node n2 to receive a high-level signal, which controls the seventh transistor M7, the fourteenth transistor M14, and the eighth transistor M8 to turn on. Because the eighth transistor M8 turns on, the low-level signal from the second clock signal terminal CKB is transmitted to the fourth node n4. The second transistor M2 and the ninth transistor M9 are turned off under the control of the low-level signal from the second clock signal terminal CKB. The fifth node n5 maintains the high-level potential from the previous phase due to the energy storage of the first capacitor C1, thereby keeping the fourth transistor M4 on and transmitting the second-level signal from the second level terminal V2 to the output terminal EOUT.

[0104] In the fourth phase t4, the input terminal EIN and the second clock signal terminal CKB both provide high-level signals, and the first clock signal terminal CLK provides a low-level signal. At this time, the on-off state of each transistor and the potential of each node are the same as in the second phase t2, and are not further described here.

[0105] During the fifth phase t5, both the input terminal EIN and the first clock signal terminal CLK provide high-level signals, while the second clock signal terminal CKB provides a low-level signal. At this point, the first transistor M1 turns on, transmitting the high-level signal from the input terminal EIN to the first node n1. This in turn controls the conduction of the fifteenth transistor M15 and the third transistor M3, transmitting the first-level signal from the first level terminal V1 to the output terminal EOUT via the third transistor M3. Simultaneously, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 turn on. Therefore, during the fifth phase t5, the second node n2 receives a high-level signal. During the interval t5-1 following the fifth phase t5, the discharge of the second node n2 by the fifth transistor M5 causes the second node n2 to drop to a low-level potential. When the second node n2 is at a high level, the seventh transistor M7, the fourteenth transistor M14, and the eighth transistor M8 are turned on, and the low-level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8; the sixth node n6 and the third node n3 are turned on; when the second node n2 is at a low level potential, the seventh transistor M7, the fourteenth transistor M14, and the eighth transistor M8 are turned off. If the threshold voltages of the fourteenth transistor M14 and the fifteenth transistor M15 are equal, the voltage of the sixth node n6 = (V1-V2) / 2; if the threshold voltages of the fourteenth transistor M14 and the fifteenth transistor M15 are different, the voltage of the sixth node n6 is close to the voltage of the level terminal connected to the one with the smaller threshold voltage of the fourteenth transistor M14 or the fifteenth transistor M15.

[0106] In addition, in the fifth stage t5 and the interval stage t5-1, since the second clock signal terminal CKB provides a low-level signal, the second transistor M2 and the ninth transistor M9 are turned off. Since the first node n1 receives a high-level signal, the tenth transistor M10 is turned on, thereby transmitting the low-level signal of the second clock signal terminal V2 to the fifth node n5, thereby keeping the fourth transistor M4 in the off state.

[0107] In the sixth phase t6, the input terminal EIN and the second clock signal terminal CKB provide high-level signals, and the first clock signal terminal CLK provides a low-level signal. At this point, the first transistor M1 is turned off, and the first node n1 maintains a high-level potential due to the energy storage of the third capacitor C3. This controls the third transistor M3 to turn on, and the first-level signal of the first level terminal V1 is transmitted to the output terminal EOUT, thereby further increasing the potential of the first node n1. Simultaneously, the sixth transistor M6 is turned off, and the fifth transistor M5 is turned on, allowing the second node n2 to continue to be discharged, lowering its potential. This in turn causes the seventh transistor M7, the fourteenth transistor M14, and the eighth transistor M8 to turn off. Because the first node n1 is at a high-level potential, the fifteenth transistor M15 is turned on, raising the potential of the sixth node n6. Furthermore, because the second clock signal terminal CKB provides a high-level signal, the second transistor M2 and the ninth transistor M9 are turned on. Since the first node n1 is at a high level potential, the tenth transistor M10 is turned on, thereby transmitting the low level signal of the second level terminal V2 to the fifth node n5, thereby keeping the fourth transistor M4 in the off state.

[0108] There may also be a first holding stage t31 and a second holding stage t32 between the third stage t3 and the fourth stage t4. In the first holding stage t31, the on-off state of each transistor and the potential of each node are the same as those in the second stage t2; in the second holding stage t32, the on-off state of each transistor and the potential of each node are the same as those in the third stage t3.

[0109] FIG7 is a schematic diagram of a shift register provided in other embodiments of the present disclosure. FIG7 is another specific implementation of the shift register shown in FIG4 . The shift register shown in FIG7 is similar to FIG5 , except that the specific structures of the first anti-leakage electronic circuit 60 and the second anti-leakage electronic circuit 70 are different. In FIG7 , the first anti-leakage electronic circuit 60 and the second anti-leakage electronic circuit 70 are connected to the seventh node n7. The first anti-leakage electronic circuit 60 is further configured to transmit a first-level signal to the seventh node n7 in response to an input signal. The first anti-leakage electronic circuit 60 includes an eleventh transistor M11 and a twelfth transistor M12. The control electrode of the eleventh transistor M11 is electrically connected to the input terminal EIN, and the first electrode of the eleventh transistor M11 is electrically connected to the first level terminal V1. The control electrode of the twelfth transistor M12 is electrically connected to the second electrode of the eleventh transistor M11, the first electrode of the twelfth transistor M12 is electrically connected to the first level terminal V1, and the second electrode of the twelfth transistor M12 is electrically connected to the second node n2. When the input terminal EIN provides a first level signal, the eleventh transistor M11 and the twelfth transistor M12 are turned on, thereby supplying power to the second node n2.

[0110] As shown in FIG7 , the second leakage prevention circuit 70 includes a thirteenth transistor M13 and a fifteenth transistor M15. The thirteenth transistor M13 has a control electrode electrically connected to the seventh node n7, a first electrode electrically connected to the second level terminal V2, and a second electrode electrically connected to the sixth node n6. The fifteenth transistor M15 has a control electrode electrically connected to the first node n1, a first electrode electrically connected to the first level terminal V1, and a second electrode electrically connected to the sixth node n6.

[0111] The operating timing of the shift register shown in Figure 7 is the same as that of Figure 6. In the first phase t1, both the input terminal EIN and the second clock signal terminal CKB provide low-level signals, while the first clock signal terminal CLK provides a high-level signal. At this point, the first transistor M1 turns on, transmitting the low-level signal from the input terminal EIN to the first node n1, thereby controlling the third transistor M3, the fifth transistor M5, and the fifteenth transistor M15 to turn off. Furthermore, the sixth transistor M6 turns on, transmitting the high-level signal from the first level terminal V1 to the second node n2. Because the second node n2 receives a high-level signal, the seventh transistor M7, the fourteenth transistor M14, and the eighth transistor M8 turn on, transmitting the low-level signal from the second clock signal terminal CKB to the fourth node n4 via the eighth transistor M8. Simultaneously, the ninth transistor M9 and the tenth transistor M10 turn off, the fifth node n5 maintains the low-level potential from the previous phase, and the fourth transistor M4 remains disconnected from the previous phase. Since there is no discharge path at the output terminal EOUT, the high-level signal from the previous phase is maintained.

[0112] In the second phase t2, the input terminal EIN and the first clock signal terminal CLK both provide low-level signals, and the second clock signal terminal CKB provides a high-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off. Under the voltage stabilization effect of the third capacitor C3, the first node n1 maintains a low-level potential, thereby controlling the third transistor M3, the fifth transistor M5, and the fifteenth transistor M15 to be turned off. Under the energy storage effect of the second capacitor C2, the second node n2 maintains a high-level potential, thereby controlling the fourteenth transistor M14, the seventh transistor M7, and the eighth transistor M8 to be turned on. In addition, the second transistor M2 is turned on, thereby transmitting the low-level signal of the second level terminal V2 to the first node n1, and the tenth transistor M10 is turned off. The high-level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8, and since the ninth transistor M9 is turned on under the control of the high-level signal provided by the second clock signal terminal CKB, the fifth node n5 receives the high-level signal of the fourth node n4, thereby controlling the fourth transistor M4 to be turned on, and the low-level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0113] In the third phase t3, the input terminal EIN and the second clock signal terminal CKB provide a low-level signal, and the first clock signal terminal CLK provides a high-level signal. At this time, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are all turned off, and the conduction states of the remaining transistors are the same as those of the transistors in the third phase t3 in FIG5 . This description will not be repeated here.

[0114] In the fourth phase t4, the input terminal EIN and the second clock signal terminal CKB both provide high-level signals, and the first clock signal terminal CLK provides a low-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off. Under the voltage regulation effect of the third capacitor C3, the first node n1 maintains a low-level potential, thereby controlling the third transistor M3, the fifth transistor M5, and the fifteenth transistor M15 to be turned off. At the same time, the eleventh transistor M11 and the twelfth transistor M12 are turned on, thereby transmitting the high-level signal of the first level terminal V1 to the second node n2, thereby controlling the fourteenth transistor M14, the seventh transistor M7, and the eighth transistor M8 to be turned on. In addition, the thirteenth transistor M13 and the second transistor M2 are turned on, thereby transmitting the low-level signal of the second level terminal V2 to the sixth node n6, the third node n3, and the first node n1. The tenth transistor M10 and the fifteenth transistor M15 are turned off. The high-level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8, and since the ninth transistor M9 is turned on under the control of the high-level signal provided by the second clock signal terminal CKB, the fifth node n5 receives the high-level signal of the fourth node n4, thereby controlling the fourth transistor M4 to be turned on, and the low-level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0115] In the fifth phase t5, the input terminal EIN and the first clock signal terminal CLK both provide high-level signals, and the second clock signal terminal CKB provides a low-level signal. In this phase, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are all turned on. The on-off states of the remaining transistors and the voltages of the nodes are described in conjunction with FIG. 5 and are not further described here.

[0116] In the sixth phase t6, the input terminal EIN and the second clock signal terminal CKB provide a high-level signal, and the first clock signal terminal CLK provides a low-level signal. At this time, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are turned on. The on-off states of the remaining transistors and the voltages of the nodes are described in FIG5 and are not repeated here.

[0117] There may also be a first holding stage t31 and a second holding stage t32 between the third stage t3 and the fourth stage t4. In the first holding stage t31, the on-off state of each transistor and the potential of each node are the same as those in the second stage t2; in the second holding stage t32, the on-off state of each transistor and the potential of each node are the same as those in the third stage t3.

[0118] FIG8 is a schematic diagram of a shift register provided in other embodiments of the present disclosure. FIG8 is another specific implementation of the shift register shown in FIG4 . The shift register shown in FIG8 is similar to FIG7 , except that, in FIG8 , the thirteenth transistor M13 is electrically connected to the sixth node n6 via the fourth capacitor C4. Providing the fourth capacitor C4 between the sixth node n6 and the thirteenth transistor M13 helps maintain the potential of the sixth node n6, thereby preventing leakage of the seventh transistor M7 and the fourteenth transistor M14 to the sixth node n6 when a large negative offset occurs. The shift register in FIG8 operates in the same manner as the shift register in FIG7 , and will not be described in detail here.

[0119] The present disclosure also provides a method for driving a shift register. FIG9 is a schematic diagram of a method for driving a shift register provided in some embodiments of the present disclosure. As shown in FIG9 , the driving method includes:

[0120] In the first stage, the input end and the first clock signal end both provide a first-level signal, the second clock signal provides a second-level signal, the input sub-circuit transmits the signal from the input end to the first node, and the first output sub-circuit disconnects the output end from the first-level end; the first control sub-circuit and the first leakage-proof electronic circuit provide a first-level signal to the second node, and the second output sub-circuit maintains the disconnection state between the second-level end and the output end; the output end continues to output the first-level signal of the previous stage.

[0121] In the second stage, the input end and the first clock signal end both provide second-level signals, the second clock signal end provides a first-level signal, the second control subcircuit transmits the second-level signal of the second-level end to the first node, and the second output subcircuit transmits the second-level signal of the second signal end to the output end.

[0122] In the third stage, the input terminal and the second clock signal terminal both provide a second level signal, the first clock signal terminal provides a first level signal, the first control subcircuit transmits the first level signal of the first level terminal to the second node, and the second output subcircuit maintains a conductive state between the second level terminal and the output terminal.

[0123] In the fourth stage, the input end and the second clock signal end both provide a first level signal, the first clock signal end provides a second level signal, the second control subcircuit transmits the second level signal of the second level end to the first node, and the first leakage prevention electronic circuit provides the first level signal to the second node; the second output subcircuit transmits the second level signal of the second signal end to the output end.

[0124] In the fifth stage, the input terminal and the first clock signal terminal both provide a first-level signal, the second clock signal terminal provides a second-level signal, the input sub-circuit transmits the first-level signal of the input terminal to the first node, the first leakage-proof electronic circuit provides the first-level signal to the second node, the second output sub-circuit disconnects the output terminal from the second-level terminal; and the first output sub-circuit transmits the first-level signal of the first-level signal terminal to the output terminal.

[0125] The working process of the shift register is specifically described above and will not be repeated here.

[0126] The present disclosure also provides a gate drive circuit comprising a plurality of cascaded shift registers, wherein each shift register is the shift register in the above embodiment, wherein in two adjacent stages of shift registers, the output end of the upper stage shift register is electrically connected to the input end of the lower stage shift register.

[0127] An embodiment of the present disclosure further provides a display device, which includes the above-mentioned gate driving circuit.

[0128] In some embodiments, the display device is an OLED display device, which includes a display substrate, the display substrate including a base substrate and a plurality of pixel units disposed on the base substrate, each pixel unit including a light-emitting device and a pixel circuit electrically connected to the light-emitting device, and the plurality of pixel circuits can be arranged in an array, with each row of pixel circuits electrically connected to a gate line and a light-emitting control line to receive a scanning signal from the gate line and a light-emitting control signal from the light-emitting control line. The gate drive circuit in the above embodiment can be disposed on the base substrate and sequentially provide light-emitting control signals to the plurality of light-emitting control lines.

[0129] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, comprising: an input subcircuit configured to transmit an input signal at the input terminal to the first node in response to control of the first clock signal terminal; A first control subcircuit is configured to transmit the signal of the first clock signal terminal to the second node in response to the control of the first node; and transmitting the first level signal of the first level terminal to the second node in response to the control of the first clock signal terminal; a second control subcircuit configured to transmit the second level signal of the second level terminal to the first node in response to control of the second node and the second clock signal terminal; a first output sub-circuit configured to transmit the first level signal at the first level end to the output end of the shift register in response to control of the first node; A second output sub-circuit, configured to connect the second level terminal to the output terminal in response to control of the first node, the second node and the second clock signal terminal; a first leakage-proof electronic circuit configured to provide the first level signal to the second node at least when the first level signal is provided at the input terminal; The first node is a connection node between the input sub-circuit, the first control sub-circuit and the second control sub-circuit, and the second node is a connection node between the first control sub-circuit and the second control sub-circuit.

2. The shift register according to claim 1, wherein: The first leakage-proof electronic circuit comprises: A twelfth transistor, wherein the control electrode and the first electrode of the twelfth transistor are both electrically connected to the first level end, and the second electrode of the twelfth transistor is electrically connected to the second node.

3. The shift register according to claim 1, wherein: The first leakage-proof electronic circuit comprises: an eleventh transistor, a control electrode of the eleventh transistor being electrically connected to the input terminal, and a first electrode of the eleventh transistor being electrically connected to the first level terminal; A twelfth transistor, wherein a control electrode of the twelfth transistor is electrically connected to the second electrode of the eleventh transistor, a first electrode of the twelfth transistor is electrically connected to the first level end, and a second electrode of the twelfth transistor is electrically connected to the second node.

4. The shift register according to claim 1, wherein: The second control subcircuit comprises: a fourteenth transistor, wherein a control electrode of the fourteenth transistor is electrically connected to the second node, and a first electrode of the fourteenth transistor is electrically connected to the second level end; a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second node, and a first electrode of the seventh transistor and a second electrode of the fourteenth transistor are connected to a sixth node; a second transistor, wherein a control electrode of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the second transistor is electrically connected to the first node; The shift register further includes a second leakage prevention electronic circuit configured to transmit the first level signal to the sixth node in response to at least control of the first node.

5. The shift register according to claim 4, wherein: The second leakage-proof electronic circuit comprises: A fifteenth transistor, wherein the control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode is electrically connected to the first level end, and the second electrode is electrically connected to the sixth node.

6. The shift register according to claim 4, wherein: The first leakage prevention electronic circuit and the second leakage prevention electronic circuit are connected to a seventh node, and the first leakage prevention electronic circuit is further configured to transmit the first level signal to the seventh node in response to the input signal; The second leakage-proof electronic circuit comprises: a thirteenth transistor, a control electrode of which is electrically connected to the seventh node, a first electrode of which is electrically connected to the second level end, and a second electrode of which is directly electrically connected to the sixth node or electrically connected to the sixth node through a fourth capacitor; A fifteenth transistor has a control electrode electrically connected to the first node, a first electrode electrically connected to the first level end, and a second electrode electrically connected to the sixth node.

7. The shift register according to any one of claims 1 to 6, wherein: The input subcircuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

8. The shift register according to any one of claims 1 to 6, wherein: The first control subcircuit comprises: a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node; A sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first clock signal end, a first electrode is electrically connected to the first level end, and a second electrode is electrically connected to the second node.

9. The shift register according to any one of claims 1 to 6, wherein: The first output sub-circuit comprises: a third transistor, wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first level end, and a second electrode of the third transistor is electrically connected to the output end; A third capacitor, wherein two ends of the third capacitor are electrically connected to the first node and the second clock signal end respectively.

10. The shift register according to any one of claims 1 to 6, wherein: The second output subcircuit comprises: a first output control unit, a second output control unit and an output unit; the first output control unit and the second output control unit are connected to a fourth node, and the second output control unit and the output unit are connected to a fifth node; The first output control unit is configured to transmit the signal of the second clock signal terminal to the fourth node in response to the control of the second node; The second output control unit is configured to transmit the signal of the fourth node to the fifth node in response to the control of the second clock signal terminal; and transmit the second level signal to the fifth node in response to the control of the first node; The output unit is configured to transmit the first level signal to the output terminal in response to control of the fifth node.

11. The shift register according to claim 10, wherein: The first output control unit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the second node, a first electrode is electrically connected to the second clock signal terminal, and a second electrode is electrically connected to the fourth node; A second capacitor, wherein two ends of the second capacitor are electrically connected to the second node and the fourth node respectively.

12. The shift register according to claim 10, wherein: The second output control unit comprises: a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the second clock signal terminal, a first electrode of the ninth transistor is electrically connected to the fourth node, and a second electrode of the ninth transistor is electrically connected to the fifth node; A tenth transistor, wherein a control electrode of the tenth transistor is electrically connected to the first node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the fifth node.

13. The shift register according to claim 10, wherein: The output unit comprises: a first capacitor, wherein two ends of the first capacitor are electrically connected to the second level end and the fifth node respectively; A fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the fifth node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the output end.

14. A method for driving a shift register according to any one of claims 1 to 13, comprising: In the first stage, the input terminal and the first clock signal terminal both provide a first level signal, the second clock signal terminal provides a second level signal, the input subcircuit transmits the signal of the input terminal to the first node, and the first output subcircuit disconnects the output terminal from the first level terminal; The first control subcircuit and the first anti-leakage electronic circuit provide a first level signal for the second node, and the second output subcircuit maintains a disconnection state between the second level terminal and the output terminal; The output end keeps outputting the first level signal of the previous stage; In the second stage, the input terminal and the first clock signal terminal both provide a second level signal, the second clock signal terminal provides a first level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the second output subcircuit transmits the second level signal of the second signal terminal to the output terminal; In the third stage, the input terminal and the second clock signal terminal both provide a second level signal, the first clock signal terminal provides a first level signal, the first control subcircuit transmits the first level signal of the first level terminal to the second node, and the second output subcircuit maintains a conductive state between the second level terminal and the output terminal; In the fourth stage, the input terminal and the second clock signal terminal both provide a first level signal, the first clock signal terminal provides a second level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the first anti-leakage electronic circuit provides the first level signal to the second node; The second output subcircuit transmits the second level signal of the second signal terminal to the output terminal; In the fifth stage, the input terminal and the first clock signal terminal both provide a first level signal, the second clock signal terminal provides a second level signal, the input subcircuit transmits the first level signal of the input terminal to the first node, the first anti-leakage electronic circuit provides the first level signal for the second node, and the second output subcircuit disconnects the output terminal from the second level terminal; The first output sub-circuit transmits the first level signal of the first level signal terminal to the output terminal.

15. A gate driving circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 13.

16. A display device comprising the gate driving circuit according to claim 15.

Images