Brain simulation processing method and apparatus, electronic device and computer readable storage medium

Abstract

The present disclosure provides a brain simulation processing method and apparatus, an electronic device and a computer readable storage medium. The method comprises: on the basis of firing index information of first neurons in a first neuron cluster that generate firing, determining synaptic information of the first neurons from a synapse lookup table, wherein the synaptic information comprises synaptic weights of the first neurons and labels of second neurons, the synapse lookup table comprises multiple sets of synaptic information, each set of synaptic information comprises the synaptic weights and labels of neurons in a second neuron cluster, and the firing index information comprises at least an index address and a firing quantity for the synapse lookup table; and on the basis of the synaptic information of the first neurons received by the second neurons in the second neuron cluster, determining a firing result of the second neuron cluster.

Description

Brain simulation processing method and device, electronic device, and computer-readable storage medium Technical Field

[0001] The embodiments of the present disclosure relate to the field of computer technology, and in particular to a brain simulation processing method and device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the continuous development of artificial intelligence (AI) technology, especially deep learning technology, deep neural network models have been widely used in multiple fields. However, the scale of deep neural network models is also increasing, which makes many deep neural networks difficult to deploy and implement on some storage-constrained embedded devices. Summary of the Invention

[0003] The present disclosure provides a brain simulation processing method and device based on a many-core system, a processing core, an electronic device, and a computer-readable storage medium.

[0004] In a first aspect, the present disclosure provides a brain simulation processing method, wherein a neural network for brain simulation includes multiple neuron clusters, each neuron cluster includes multiple neurons, and the connections between the neurons are characterized by synaptic weights. The method comprises: determining synaptic information of the first neuron from a synaptic lookup table based on firing index information of a first neuron in a first neuron cluster that generates a firing, the synaptic information including at least the synaptic weight of the first neuron and the label of a second neuron in a second neuron cluster that is a firing target of the first neuron;

[0005] The first neuron cluster is any neuron cluster of the neural network, the second neuron cluster is a subsequent neuron cluster of the first neuron cluster, the synaptic lookup table includes multiple sets of synaptic information, each set of synaptic information includes at least a synaptic weight and a label of a neuron in the second neuron cluster, and the issuance index information includes at least an index address for the synaptic lookup table and a issuance quantity;

[0006] The firing result of the second neuron cluster is determined according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster.

[0007] In a second aspect, the present disclosure provides a brain simulation processing device, wherein a neural network for brain simulation includes multiple neuron clusters, each neuron cluster includes multiple neurons, and the connections between the neurons are characterized by synaptic weights; the device includes:

[0008] a synaptic information search module configured to determine synaptic information of the first neuron from a synaptic lookup table based on the firing index information of the first neuron that generates a firing in the first neuron cluster, the synaptic information including at least a synaptic weight of the first neuron and an index of a second neuron in the second neuron cluster that is a firing target of the first neuron;

[0009] The first neuron cluster is any neuron cluster of the neural network, the second neuron cluster is a subsequent neuron cluster of the first neuron cluster, the synaptic lookup table includes multiple sets of synaptic information, each set of synaptic information includes at least a synaptic weight and a label of a neuron in the second neuron cluster, and the issuance index information includes at least an index address for the synaptic lookup table and a issuance quantity;

[0010] The emission result determination module is configured to determine the emission result of the second neuron cluster according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster.

[0011] In a third aspect, the present disclosure provides an electronic device comprising: a plurality of processing cores; and an on-chip network configured to exchange data between the plurality of processing cores and external data; wherein one or more instructions are stored in one or more processing cores, and the one or more instructions are executed by one or more processing cores, so that the one or more processing cores can execute the above-mentioned brain simulation processing method.

[0012] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned brain simulation processing method when executed by a processor / processing core.

[0013] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned brain simulation processing method.

[0014] The embodiments provided by the present disclosure are provided with a lookup table including multiple sets of synaptic information, which can generate the index of the neuron that fires in the front neuron cluster in brain simulation, and find the synaptic information including synaptic weights and post-neuron labels from the lookup table; the neurons of the post-neuron cluster determine the firing results based on the synaptic information, so that only a small amount of synaptic information is stored to realize brain simulation of large-scale neural networks, significantly reducing the amount of stored data and improving computing efficiency.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0017] FIG1 is a schematic diagram of connections between neuron clusters according to an embodiment of the present disclosure;

[0018] FIG2 is a flow chart of a brain simulation processing method provided by an embodiment of the present disclosure;

[0019] FIG3 is a schematic diagram of a many-core system implementation of a brain simulation processing method provided by an embodiment of the present disclosure;

[0020] FIG4 is a block diagram of a brain simulation processing device provided by an embodiment of the present disclosure;

[0021] FIG5 is a block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] To enable those skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0023] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0024] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, features, wholes, steps, operations, elements and / or components are specified to exist, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof are not excluded. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0027] In some possible implementations, brain simulation processing can be performed through a neural network to achieve corresponding processing tasks. The neural network can be, for example, a spiking neural network (SNN) or an artificial neural network (ANN); the corresponding processing tasks can be, for example, image processing tasks, text processing tasks, audio processing tasks, etc. This disclosure does not limit the specific network type of the neural network or the specific task type of the processing task.

[0028] The neural network may include multiple neurons, and the connections between neurons are characterized by synaptic weights. The synaptic weight between unconnected neurons is 0, and the synaptic weight between connected neurons is greater than 0. The value of the synaptic weight represents the strength of the connection between neurons, for example, a number between 0 and 1. The present disclosure does not limit the specific value of the synaptic weight.

[0029] In some possible implementations, a multi-cluster model of a neural network can be constructed, that is, neurons in the neural network are divided into multiple neuron clusters, each neuron cluster including one or more neurons. Neuron clusters can be divided, for example, based on the number of connections between neurons, connection strength, connection density, etc. This disclosure does not limit the specific method of dividing neuron clusters.

[0030] In some possible implementations, the connections between neuron clusters have a front-to-back relationship. In brain simulation, the front neuron cluster will send information to the back neuron cluster. Assume that the synaptic information between neuron cluster A (front neuron cluster, number of neurons K) and neuron cluster B (back neuron cluster, number of neurons Q) is available (W, P, D, L). K Represented by . Where L is a scalar, and W, P, and D are vectors of length L. There are K sets of synaptic information, each of which corresponds to the information of all synapses connected to a neuron in the pre-neuron cluster. That is, each neuron in the neuron cluster A has a set of synaptic information.

[0031] In some possible implementations, each set of synaptic information includes the number of connections L, synaptic weight W, post-neuron label P, and synaptic delay information D. The number of connections L represents the number of post-neurons connected to the pre-neuron, and L is a scalar. For example, L=3 means that the pre-neuron is connected to three post-neurons. The synaptic weight W represents the weights of the L synapses of the pre-neuron, that is, the synaptic connection strength, and is a vector of length L, which can also be expressed as W1×L The post-neuron label P represents the labels of the L post-neurons connected to the pre-neuron, which is a vector of length L and can also be expressed as P 1× L The synaptic delay information D represents the delay information of the L synapses of the preneuron, which is a vector of length L and can also be expressed as D 1×L It can also be understood that each set of synaptic information includes L triplets, each triplet is the information of a synapse, including synaptic weight, post-neuron label, and synaptic delay information, that is, (Wi, Pi, Di), 0≤i≤L-1.

[0032] FIG1 is a schematic diagram of the connection between neuron clusters provided by an embodiment of the present disclosure. As shown in FIG1 , the number of front neurons of the front neuron cluster A is K=5, the number of back neurons of the back neuron cluster B is Q=6, and the number of connections L0~L4 of the front neurons A0~A4 of the front neuron cluster A are 3, 2, 2, 2, and 5 respectively; 1 represents firing, and 0 represents no firing; a black dot at the intersection represents a synaptic connection, and no black dot represents no synaptic connection. Based on the firing status of the front neurons A0~A4 and the corresponding groups of synaptic information, the firing information received by the back neurons B0~B5 within d time delays can be determined, that is, the current value I of each group in FIG1 0,0 ~I 5,0 , I 0,1 ~I 5,1 ,…,I 0,d-1 ~I 5,d-1 ; We can then calculate the firing results of the back neurons B0-B5 at each time step (or time beat). For example, if the number of connections L0 of the front neuron A0 is 3, it has three synapses (W0, P0, D0), (W1, P1, D1), and (W2, P2, D2). According to the situation in Figure 1, the back neurons are labeled P0 = 1, P1 = 3, and P2 = 4. Here, 0 ≤ Di ≤ d-1, 0 ≤ Pi ≤ Q-1, and d is the maximum number of time steps of synaptic delay.

[0033] It should be understood that those skilled in the art may set the specific content of a set of synaptic information according to actual conditions, and a set of synaptic information may also include other information, which is not limited in this disclosure.

[0034] In related technologies, the connection relationship between neurons, namely synaptic information, needs to be constructed before brain simulation. This information includes the labels of the connected post-neurons, synaptic weights, synaptic delay information, etc., so that synaptic information can be read and synaptic calculations can be performed during the brain simulation. Each pre-neuron must store synaptic information, which takes up a large amount of storage space. When the scale of synaptic information is large, the on-chip storage space is insufficient and it can only be stored in off-chip storage space (such as DDR memory). Reading synaptic information takes up a lot of time, affecting the speed of brain simulation and limiting the scale of brain simulation.

[0035] According to an embodiment of the present disclosure, a brain simulation processing method is provided, which can pre-store a small amount of synaptic information (synaptic weights, post-neuron labels, synaptic delay information, etc.) in an on-chip storage space as a lookup table LUT, and generate a starting address for reading the lookup table through a preset generation seed, so that only a small amount of synaptic information needs to be stored (usually placed on the chip), and there is no need to additionally generate or read synaptic information from outside the chip, thereby significantly improving computing efficiency.

[0036] The brain simulation processing method according to the embodiments of the present disclosure is applicable to the following application scenarios: in a neural network used for brain simulation, the distribution information of a small number of synapses is consistent or substantially consistent with the distribution information of all stored synapses, and only the statistical characteristics of neuronal synapses rather than the individual characteristics of synapses are of interest. For example, only the firing efficiency characteristics of a large number of simulated neurons are of interest rather than the firing / synaptic changes of individual neurons. It should be understood that those skilled in the art can set the application scenarios of the embodiments of the present disclosure according to actual circumstances, and the present disclosure does not limit this.

[0037] The brain simulation processing method according to the embodiment of the present disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The method can be implemented by a processor calling computer-readable program instructions stored in a memory. Alternatively, the method can be executed by a server.

[0038] In some possible implementations, the brain simulation processing method according to the embodiment of the present disclosure can be applied to a many-core system, that is, a neural network for brain simulation is run through a many-core system. The many-core system may include one or more neuromorphic chips, the neuromorphic chip includes multiple processing cores arranged in a full crossbar array (crossbar) manner and an on-chip network, the processing core is configured to perform corresponding processing tasks according to instructions / instruction streams, and the on-chip network is configured to exchange data between multiple processing cores and external data. Among them, the internal storage space of the processing core may include at least one of the following: storage space within the core, on-chip storage space corresponding to the processing core, and the internal storage space of the processing core is configured to store processing instructions, synaptic information, etc., so that the processing core processes the input data of the corresponding neuron / neuron cluster.

[0039] FIG2 is a flow chart of a brain simulation processing method provided by an embodiment of the present disclosure. Referring to FIG2 , the method includes:

[0040] In step S21, based on the firing index information of the first neuron that generates a firing in the first neuron cluster, synaptic information of the first neuron is determined from a synaptic lookup table, where the synaptic information includes at least the synaptic weight of the first neuron and the label of the second neuron in the second neuron cluster that is the firing target of the first neuron;

[0041] The first neuron cluster is any neuron cluster of the neural network, the second neuron cluster is a subsequent neuron cluster of the first neuron cluster, the synaptic lookup table includes multiple sets of synaptic information, each set of synaptic information includes at least a synaptic weight and a label of a neuron in the second neuron cluster, and the issuance index information includes at least an index address for the synaptic lookup table and a issuance quantity;

[0042] In step S22 , the firing result of the second neuron cluster is determined according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster.

[0043] For example, the neurons of a neural network can be pre-divided into multiple neuron clusters, and the forward and backward connections between the neuron clusters can be determined. For any neuron cluster in the neural network (hereinafter referred to as the first neuron cluster), the neuron cluster following the first neuron cluster can be referred to as the second neuron cluster. During the brain simulation process, the neurons in the first neuron cluster will send information to the neurons in the second neuron cluster.

[0044] In some possible implementations, a certain amount of synaptic information for the first and second neuron clusters can be pre-generated and stored on-chip or off-chip as a synaptic lookup table (LUT). The synaptic lookup table includes multiple sets of synaptic information, each set of synaptic information including at least synaptic weights and the labels of neurons in the second neuron cluster. Each set of synaptic information may also include synaptic delay information, etc., which is not limited in this disclosure.

[0045] In an example, when the synaptic information includes synaptic weight, label, and synaptic delay information, the synaptic lookup table may be as shown in Table 1:

[0046] Table 1

[0047] As shown in Table 1, the synaptic lookup table includes R groups of synaptic information (R ≥ Q), where Q is the number of neurons in the second neuron cluster. Each group of synaptic information has three values: synaptic weight W, post-neuron label P, and synaptic delay information D, denoted as (Wj, Pj, Dj), 0≤j≤R-1. Among them, the values ​​of W, P, and D must satisfy the statistical information of the synaptic distribution. For example, the synaptic weight W satisfies the normal distribution N(μ,σ 2); the neuron label P usually satisfies the uniform distribution u(0, Q-1); and D satisfies the exponential distribution exp(p). Thus, the R sets of synaptic information can be considered as R samples that satisfy these distributions. This disclosure does not impose any restrictions on the distribution of synaptic information.

[0048] In some possible implementations, a release index information may be stored for each anterior neuron in the first neuron cluster as an anterior neuron-specific information. The release index information may include an index address C for the synaptic lookup table and a release quantity L. The index address C indicates the location from which reading begins in the synaptic lookup table, and the release quantity L indicates the number of groups of synaptic information to be read. The index address C may be a random value between (0, R-1) that satisfies a uniform distribution. The release index information may also include other content. The present disclosure does not limit the specific content of the release index information, the specific distribution of the index address C, and the release quantity L.

[0049] Among them, the synaptic information needs to be read and calculated only when the current neuron releases information, otherwise it does not need to be read and calculated. In this way, for the same pre-neuron, the synaptic information read each time it releases is unchanged. That is, the synaptic information is static. When the input of different simulation time beats is consistent, the output current value (synaptic integration result) is also consistent. In addition, the synaptic information corresponding to different neurons may overlap, so it can be understood as the sharing of neuronal synaptic information. However, due to the different index addresses at the beginning of reading and the different number of releases, the synaptic information of each neuron is still different, meeting the preset distribution law and being static.

[0050] In this way, the consistency of brain simulation results can be improved and the accuracy of brain simulation can be improved.

[0051] In some possible implementations, at any time beat in the brain simulation processing, for the first neuron cluster and the second neuron cluster, the neuron that generates the discharge in the first neuron cluster (hereinafter referred to as the first neuron) can be determined in step S21, and the synaptic information of the first neuron can be determined from the synaptic lookup table based on the discharge index information of the first neuron.

[0052] In some possible implementations, for any first neuron, when the emission index information includes an index address C and an emission quantity L, the first reading position in the synaptic lookup table can be determined based on the index address C, and the number of reading groups can be determined based on the emission quantity L, and L groups of synaptic information are read starting from the index address C as the synaptic information of the first neuron.

[0053] For example, if the index address C1 of the first neuron A1 is 2 and the number of emissions L1 is 3, then reading starts from position 2 (W2, P2, D2) in the synaptic lookup table of Table 1, and a total of three sets of synaptic information are read: (W2, P2, D2), (W3, P3, D3), and (W3, P4, D4), thereby obtaining the synaptic information of the first neuron A1.

[0054] In some possible implementations, if C+L>R, then after reading the tail of the synaptic lookup table, the synaptic information can be returned to the beginning of the synaptic lookup table to continue reading. This process is called a ring buffer. That is, when an address greater than R is read in the synaptic lookup table, such as address C+L, the synaptic information actually read is located at (C+L) in the synaptic lookup table. modR Position, modR means modulo R.

[0055] In this way, by reading each first neuron that generates a discharge, the synaptic information of each first neuron can be obtained.

[0056] In some possible implementations, after obtaining the synaptic information of each first neuron in the first neuron cluster, in step S22, the synaptic information received by each second neuron in the second neuron cluster can be determined based on the label of the second neuron serving as the firing target of the first neuron in the synaptic information of each first neuron. That is, the synaptic information received by each second neuron can be determined based on the neuron label P in each set of synaptic information of the first neurons.

[0057] In some possible implementations, for any second neuron in the second neuron cluster, synaptic integration processing can be performed on the second neuron based on the synaptic information of each first neuron emitted to the second neuron to obtain the synaptic integration result of the second neuron (i.e., integrated current). If the synaptic information only includes the synaptic weight W and the post-neuron label P, the synaptic integration is directly performed based on each synaptic weight W to obtain the synaptic integration result; if the synaptic information also includes synaptic delay information, the emission time beat of the corresponding first neuron is determined based on the synaptic delay information of each first neuron; based on the emission situation determined by the previous historical time beat and the emission situation of the current time beat, the synaptic weight W of each first neuron emitted at the current time beat is determined, and the synaptic integration is performed based on each synaptic weight W to obtain the synaptic integration result. The present disclosure does not limit the specific processing method of synaptic integration.

[0058] In this way, each second neuron in the second neuron cluster is processed to obtain the firing result of the second neuron cluster. Based on the firing result of the second neuron cluster, the subsequent neuron cluster of the second neuron cluster can be processed using the processing method of steps S21-S22. Furthermore, the above processing is performed on all neuron clusters in the neural network to obtain the brain simulation processing result of the neural network at the current time beat. After processing multiple time beats, the final brain simulation processing result of the neural network can be obtained.

[0059] According to an embodiment of the present disclosure, a lookup table containing multiple sets of synaptic information is provided. In brain simulation, synaptic information can be retrieved from the lookup table based on the index of the neuron that generated the firing in the anterior neuron cluster. Neurons in the posterior neuron cluster then determine the firing result based on this synaptic information. This sharing of synaptic information allows for large-scale neural network simulations using only a small amount of synaptic information, significantly reducing the amount of stored data. Furthermore, synaptic information can be stored on-chip, eliminating the need to read it off-chip, significantly improving computational efficiency.

[0060] The following describes the brain simulation processing method according to an embodiment of the present disclosure.

[0061] As previously described, for the first neuron cluster (front neuron cluster) and the second neuron cluster (back neuron cluster) of the neural network, a certain amount of synaptic information can be pre-generated and stored on-chip or off-chip as a synaptic lookup table LUT1. The synaptic lookup table includes multiple sets of synaptic information, each set of synaptic information including at least a synaptic weight and the label of a neuron in the second neuron cluster.

[0062] In some possible implementations, the method is applied to an electronic device, and the synaptic lookup table is stored in the internal storage space of the electronic device. In other words, the synaptic lookup table can be stored in the internal storage space of the electronic device to reduce the amount of data handled during processing and increase the read speed to improve computing efficiency.

[0063] In the example, when the electronic device is a conventional terminal or server, the internal storage space may be the memory of the terminal or server; when the electronic device is a many-core system including one or more neuromorphic chips, the internal storage space may include at least one of the following: storage space within the core, on-chip storage space corresponding to the processing core, and the present disclosure does not impose any restrictions on this.

[0064] In some possible implementations, at any time beat in the brain simulation process, for the first neuron cluster and the second neuron cluster, the first neuron that generates a discharge in the first neuron cluster can be determined in step S21, and the synaptic information of the first neuron can be determined from the synaptic lookup table based on the discharge index information of the first neuron.

[0065] In some possible implementations, when the issuance index information includes the index address C and the issuance quantity L, step S21 may include:

[0066] For any first neuron, determining a reading start address of the first neuron in the synaptic lookup table according to the index address of the emission index information of the first neuron;

[0067] According to the number of synaptic information groups in the synaptic lookup table, at least one group of synaptic information corresponding to the number of issuances is read from the synaptic lookup table starting from a reading start address to obtain synaptic information of the first neuron.

[0068] That is to say, for any first neuron, if the issuance index information only includes the index address C and the issuance quantity L, the reading start address of the first neuron in the synapse lookup table can be determined based on the index address C; then, based on the total number of synapse information groups R in the synapse lookup table, the synapse information is read starting from the reading start address.

[0069] In some possible implementations, if the read start address C + the number of releases L ≤ R, then L sets of synaptic information are sequentially read starting from the read start address C, and these L sets of synaptic information are used as the synaptic information of the first neuron. As shown in Table 1, for example, if the index address C1 of the first neuron A1 is 2 and the number of releases L1 is 3, then the reading starts at position 2 (W2, P2, D2) in the synaptic lookup table of Table 1, and a total of three sets of synaptic information are read: (W2, P2, D2), (W3, P3, D3), and (W3, P4, D4), thereby obtaining the synaptic information of the first neuron A1.

[0070] In some possible implementations, if the read start address C + the issuance quantity L > R, then (RC) groups of synaptic information are read sequentially starting from the read start address C, reaching the end of the synaptic lookup table; then returning to the first position of the synaptic lookup table, the (C + LR) groups of synaptic information are continued to be read, and L groups of synaptic information are obtained, and the L groups of synaptic information are used as the synaptic information of the first neuron.

[0071] In this way, the synaptic information of the first neuron that generates the firing can be read without having to store all the synaptic information, thereby reducing the amount of stored data and improving the scale and computational efficiency of the simulation.

[0072] In some possible implementations, the sequential reading of L sets of synaptic information for a first neuron starting at starting address C may still result in a high degree of overlap with the synaptic information read from other first neurons. In this case, other information may be added to the distribution index information to increase the randomness of the read synaptic information and reduce the overlap of synaptic information from different first neurons.

[0073] In some possible implementations, the distributed index information may also include label offset information Poffset (abbreviated as Po). Specifically, the distributed index information is (C, L, Po). The label offset information is used to compensate for the labels of the read synaptic information. The specific value of the label offset information Po for each neuron in the first neuron cluster is random and remains static after the value is determined. This disclosure does not limit the specific distribution pattern of the label offset information Po.

[0074] In some possible implementations, when the issued index information also includes label compensation information, step S21 may include:

[0075] For any first neuron, determining a reading start address of the first neuron in the synaptic lookup table according to the index address of the emission index information of the first neuron;

[0076] Reading at least one set of synapse information corresponding to the number of synapses issued, starting from a read start address, in a synapse lookup table;

[0077] Determine the compensated label of the second neuron according to the label of the second neuron in the synaptic information and the label compensation information, and update the synaptic information;

[0078] Synaptic information of the first neuron is determined according to the updated at least one set of synaptic information.

[0079] For example, for any first neuron, the reading start address of the first neuron in the synapse lookup table is determined according to the index address C of the first neuron; then, according to the total number of synapse information groups R in the synapse lookup table, the synapse information is read starting from the reading start address.

[0080] In some possible implementations, L groups of synaptic information can be read sequentially from the synaptic lookup table starting from the read start address; if the read position exceeds the number R of synaptic information groups in the synaptic lookup table, then after reading the tail of the synaptic lookup table, the read is returned to the beginning of the synaptic lookup table to continue reading, thereby obtaining L groups of synaptic information.

[0081] In some possible implementations, let the label of the second neuron in the L group of synaptic information be P LUT , then the label is compensated according to the label compensation information Po of the first neuron to obtain the compensated label P of the second neuron real . It can be expressed as: P real =(Po+P LUT ) modR , modR represents the modulus of R, which is used to ensure that the output P is within the range of the label of the second neuron in the synaptic lookup table.

[0082] For example, if the label P1 in a set of synaptic information (W1, P1, D1) is 12 and the label offset is 2, then the label is incremented by 2 to 14, resulting in the updated set of synaptic information (W1, 14, D1). Subsequent distribution and calculations are based on this synaptic information. In other words, the information originally intended for distribution to the neuron labeled 12 is instead distributed to the neuron labeled 14, thereby increasing the randomness of the distribution target and the randomness of information such as the synaptic weights in the synaptic information.

[0083] In some possible implementations, the label P of the compensated second neuron may be used. real To update the labels in the L groups of synaptic information, the updated L groups of synaptic information are obtained as the synaptic information of the first neuron for subsequent processing.

[0084] In this way, the randomness of the read synaptic information can be improved, and the overlap of the synaptic information of each first neuron can be reduced, thereby improving the processing effect of brain simulation.

[0085] In some possible implementations, the distribution index information may further include a reading interval S, i.e., the distribution index information is (C, L, S). The reading interval is used to represent the address interval between each set of synaptic information read. Where S ≥ 1, the specific value of the reading interval S for each neuron in the first neuron cluster is random and remains static after the value is determined. This disclosure does not limit the specific distribution pattern of the reading interval S.

[0086] In some possible implementations, when the issuing index information also includes a reading interval, step S21 may include:

[0087] For any first neuron, determining a reading start address of the first neuron in the synaptic lookup table according to the index address of the emission index information of the first neuron;

[0088] According to the reading interval, at least one set of synaptic information corresponding to the number of synapses is read from the synaptic lookup table starting from the reading start address to obtain the synaptic information of the first neuron.

[0089] For example, for any first neuron, the reading start address of the first neuron in the synapse lookup table is determined according to the index address C of the first neuron; then, according to the total number of synapse information groups R in the synapse lookup table, the synapse information is read starting from the reading start address.

[0090] In some possible implementations, L sets of synaptic information can be sequentially read from the synaptic lookup table starting at a read start address C with a read interval S. Specifically, the synaptic information sets at addresses C, C+S, C+2S, ..., C+(L-1)S are read in sequence. If the read position exceeds the number of synaptic information sets R in the synaptic lookup table, after reading the end of the synaptic lookup table, the read sequence returns to the beginning of the table and continues, obtaining the L sets of synaptic information. For example, if C=1, S=2, and L=3 for a first neuron, then the three sets of synaptic information (W1, P1, D1), (W3, P3, D3), and (W5, P5, D5)) are read as the synaptic information for the first neuron.

[0091] In this way, the randomness of the read synaptic information can be improved, and the overlap of the synaptic information of the first neuron can be reduced, thereby improving the processing effect of brain simulation.

[0092] In some possible implementations, the release index information may also include label offset information Po and a reading interval S, that is, the release index information is (C, L, Po, S). Similarly, in step S21, for any first neuron, the reading start address of the first neuron in the synapse lookup table is determined based on the index address C of the first neuron; then, based on the total number of synapse information groups R in the synapse lookup table, synapse information is read starting from the reading start address.

[0093] In some possible implementations, starting from the read start address C, L groups of synaptic information can be sequentially read from the synaptic lookup table at a read interval S, that is, the groups of synaptic information at addresses C, C+S, C+2S, ..., C+(L-1)S are read in sequence; if the read position exceeds the number of synaptic information groups R in the synaptic lookup table, then after reading the tail of the synaptic lookup table, the read is returned to the first position of the synaptic lookup table to continue reading, thereby obtaining L groups of synaptic information; then, the labels of the L groups of synaptic information are compensated according to the label compensation information Po of the first neuron, and the compensated label P is used. real To update the labels in the L groups of synaptic information, the updated L groups of synaptic information are obtained as the synaptic information of the first neuron.

[0094] In this way, the randomness of the read synaptic information can be further improved, and the overlap of the synaptic information of the first neuron can be further reduced.

[0095] In some possible implementations, the number of groups R of synaptic information in the synaptic lookup table may be increased to further reduce the overlap of synaptic information of the first neuron. The present disclosure does not limit the specific technical means used to reduce the overlap of synaptic information.

[0096] In some possible implementations, a neuron cluster may be connected to multiple subsequent neuron clusters, to which information is distributed during brain simulation. This means that a first neuron cluster corresponds to multiple second neuron clusters. If there are multiple second neuron clusters, and the distribution of neurons in these clusters varies, a synaptic lookup table and specific information about neurons in the first neuron cluster (i.e., distribution index information) must be generated for each second neuron cluster separately. This allows the distribution information to be input to each second neuron cluster separately, and the subsequent synaptic integration process also needs to traverse each second neuron cluster.

[0097] In some possible implementations, multiple second neuron clusters can share a synaptic lookup table, but the connection rules between the front neuron cluster and the back neuron cluster need to meet certain common conditions. For example, there are neuron clusters A, B, and E, where neuron cluster A is the front neuron cluster, and neuron clusters B and E are the back neuron clusters of A. The connection between the neuron clusters is represented by C AB 、C AE , connect C AB Satisfaction: W AB ~Normal distribution N(μ AB ,σ 2 AB ), D AB ~Exponential distribution exp(p), P AB ~Uniform distribution u(0,Q AB -1); and connect C AE Satisfaction: W AE ~Normal distribution N(μ AE ,σ 2 AE ), D AE ~Exponential distribution exp(p), P AE ~Uniform distribution u(0,Q AE -1); that is, if D distribution is consistent, W satisfies normal distribution (can also be Gaussian distribution), and P satisfies uniform distribution, then it is considered that the common conditions are met and a synaptic lookup table (W~N(0,1), P~u(0,1)) can be shared, but the read synaptic information needs to be converted.

[0098] In some possible implementations, synaptic conversion information for each second neuron cluster may be set so as to convert the read initial synaptic information during processing. The synaptic conversion information is used to represent the mapping relationship between the initial synaptic information and the converted target synaptic information. For example, the synaptic conversion information of the second neuron cluster B includes μ AB , σ AB , Q AB wait.

[0099] In some possible implementations, when multiple second neuron clusters share one synapse lookup table, step S21 may include:

[0100] determining, from a synaptic lookup table, initial synaptic information of the first neuron according to the firing index information of the first neuron that generates a firing in the first neuron cluster, the initial synaptic information including an initial weight of the first neuron and an initial label of a second neuron that is a firing target of the first neuron;

[0101] For any second neuron cluster, the initial synaptic information of the first neuron is converted according to the synaptic conversion information of the second neuron cluster to obtain the target synaptic information of the first neuron for the second neuron cluster. The synaptic conversion information is used to characterize the mapping relationship between the initial synaptic information and the target synaptic information.

[0102] For example, at any time beat in the brain simulation process, for the first neuron that generates a discharge in the first neuron cluster, the reading start address of the first neuron in the synaptic lookup table can be determined based on the index address in the discharge index information of the first neuron; then, based on the total number of synaptic information groups R in the synaptic lookup table, L groups of synaptic information corresponding to the number of discharges are read starting from the reading start address as the initial synaptic information of the first neuron.

[0103] In some possible implementations, for any second neuron cluster, the initial synaptic information of the first neuron can be converted according to the synaptic conversion information of the second neuron cluster to obtain the target synaptic information of the first neuron for the second neuron cluster. For example, a set of synaptic information read is (W, P, D), and the synaptic conversion information of the second neuron cluster B includes μ AB , σ AB , Q AB , then: W AB =W×σ 2 AB +μ AB ;P AB =P×Q AB ;D AB =D (1)

[0104] After conversion by formula (1), a set of target synaptic information (W) of the first neuron to the second neuron cluster B can be obtained. AB 、P AB 、D AB ).

[0105] Similarly, the synaptic conversion information of the second neuron cluster E includes μ AE , σ AE , Q AE , then: W AE =W×σ2 AE +μ AE ;P AE =P×Q AE ;D AE =D (2)

[0106] After conversion by formula (2), a set of target synaptic information (W) of the first neuron to the second neuron cluster E can be obtained. AE 、P AE 、D AE ).

[0107] In this way, by converting the initial synaptic information of each first neuron respectively, the target synaptic information of each first neuron for each second neuron cluster can be obtained, so that subsequent processing can be performed respectively according to the target synaptic information.

[0108] In this way, the synaptic lookup tables of multiple post-neuron clusters can be shared, further reducing the amount of stored synaptic information and improving computing efficiency.

[0109] In some possible implementations, if a neuron has multiple ion channels, each channel can be considered to correspond to a post-neuron, and multiple channels can correspond to multiple post-neurons. In this case, synaptic conversion information for the second neuron cluster can be set to convert the read initial synaptic information during processing. This synaptic conversion information can be, for example, the number Q of neurons in the second neuron cluster.

[0110] In some possible implementations, at any time beat in the brain simulation process, for the first neuron that generates a discharge in the first neuron cluster, the reading start address of the first neuron in the synaptic lookup table can be determined based on the index address in the discharge index information of the first neuron; then, based on the total number R of synaptic information groups in the synaptic lookup table, L groups of synaptic information corresponding to the number of discharges are read starting from the reading start address as the initial synaptic information of the first neuron.

[0111] In some possible implementations, the initial synaptic information of the first neuron can be converted according to the synaptic conversion information Q of the second neuron cluster. Assume that a set of synaptic information read is (W, P, D), the second neuron cluster has F channels, and for the channel numbered f (0≤f≤F-1), there are P f =P+f×Q, and obtain a set of target synaptic information (W, P f , D). In this way, by converting each channel separately, the target synaptic information of the first neuron for each channel of the second neuron cluster can be obtained.

[0112] In this way, multi-channel processing can be achieved, further reducing the amount of stored synaptic information data.

[0113] In order to further reduce the amount of synaptic information that needs to be stored, improvements can be made based on the above solution, such as sharing the index address in the emission index information of the first neuron, sharing the synaptic weight in the synaptic lookup table, and sharing the synaptic delay information.

[0114] In some possible implementations, the firing index information includes the neuron number, firing quantity, and initial index address of the first neuron cluster. That is, the entire first neuron cluster shares a single initial index address, and the index addresses of the individual neurons in the first neuron cluster are not completely random. For the first neuron that generates a firing, the index address of the first neuron can be calculated based on its number, initial index address, and other information.

[0115] In this case, step S21 may include:

[0116] For any first neuron in the first neuron cluster that generates a firing, determining the total number of firings of a plurality of neurons preceding the first neuron according to the label of the first neuron;

[0117] Determine the index address of the first neuron based on the initial index address and the total number of neurons emitted;

[0118] According to the index address and the number of firings of the first neuron, the synaptic information of the first neuron is determined from the synaptic lookup table.

[0119] For example, before searching the synaptic lookup table, the index address of the first neuron can be determined first. For any first neuron that generates a firing, the total number of firings of the multiple neurons before the first neuron can be determined based on the number of the first neuron. For example, if the number of the first neuron is n, and the number of neurons before the first neuron is 0 to n-1, and the firing numbers are L0, L1, ..., Ln-1 respectively, then the total number of firings is L 总 =L0+L1+…+Ln-1.

[0120] In some possible implementations, the index address of the first neuron can be determined based on the initial index address and the total number of neurons emitted. For example, the initial index address is C0, and the total number of neurons emitted is L. 总 =L0+L1+…+Ln-1, then the index address of the first neuron numbered n is Cn=C0+L 总 .

[0121] In some possible implementations, based on the index address of the first neuron n, the reading start address of the first neuron in the synaptic lookup table can be determined; then, based on the total number of synaptic information groups R in the synaptic lookup table, the synaptic information is read starting from the reading start address; and the read Ln groups of synaptic information are used as the synaptic information of the first neuron.

[0122] In this way, the index address can be shared, further reducing the amount of synaptic information that needs to be stored.

[0123] In some possible implementations, weight sharing can be implemented in the synaptic lookup table, that is, multiple labels P reuse a set of weights W. In this case, the synaptic lookup table includes a weight sub-table and a label sub-table. The weight sub-table includes multiple sets of synaptic sub-information, and the label sub-table includes the labels of neurons in the second neuron cluster. The synaptic sub-information includes at least synaptic weights and may also include synaptic delay information, etc., which is not limited in this disclosure.

[0124] In an example, when the synapse sub-information includes synapse weight and synapse delay information, the weight sub-table and the label sub-table may be shown in Table 2 and Table 3, respectively:

[0125] Table 2 Weight subtable

[0126] Table 3 Label subtable

[0127] The weight sub-table and the label sub-table can logically form the corresponding relationship shown in Table 4 below:

[0128] Table 4

[0129] It can be seen that the use of this weight sharing method can further reduce the amount of stored synaptic information.

[0130] In some possible implementations, the number of synapse sub-information groups G in the weight sub-table is less than the number of labels R in the label sub-table. The number of synapse sub-information groups G can also be referred to as the macro variable Wrap. R can be an integer multiple of G. For example, in Tables 2 and 3, G = 3 and R = 9, where the number of labels R is 3 times the number of synapse sub-information groups G. R can also be a non-integer multiple of G, such as 2.5 times, though this disclosure is not limited thereto.

[0131] In some possible implementations, when the synaptic lookup table includes a weight sub-table and a label sub-table, step S21 may include: for any first neuron, determining a first read start address of the first neuron in the weight sub-table based on the index address of the first neuron and the number of synaptic sub-information groups in the weight sub-table; determining a second read start address of the first neuron in the label sub-table based on the index address of the first neuron and the number of labels in the label sub-table; reading the synaptic sub-information and labels corresponding to the number of releases from the weight sub-table and the label sub-table respectively based on the number of synaptic sub-information groups and the first read start address in the weight sub-table and the number of labels and the second read start address in the label sub-table, to obtain the synaptic information of the first neuron.

[0132] For example, for any first neuron, if the synapse lookup table includes a weight sub-table and a label sub-table, information can be read from the two sub-tables respectively.

[0133] In some possible implementations, for the weight sub-table, the first read start address of the first neuron in the weight sub-table can be determined based on the index address C and the number of synaptic sub-information groups G. If the index address C ≤ G, the first read start address is address C; if the index address C > G, the first read start address is the address modulo G, expressed as C modG The first read start address can also be uniformly expressed as C modG .

[0134] In some possible implementations, starting from the first read start address, L groups of synapse sub-information can be read from the weight sub-table. modG +L≤G, then directly read the L group of synaptic sub-information; if C modG +L>G, after reading the tail of the weight sub-table, it can return to the first position of the weight sub-table and continue reading, and read L groups of synaptic sub-information, wherein the read Lth group of synaptic sub-information can be expressed as (C modG +L) modG .

[0135] In some possible implementations, for the label subtable, the second read start address of the first neuron in the label subtable can be determined based on the index address C and the number of labels in the label subtable R. In this case, C ≤ R, and the second read start address is address C.

[0136] In some possible implementations, L labels may be read from the label subtable starting from the second read start address C. If C + L ≤ R, L labels are read directly. If C + L > R, after reading the end of the label subtable, the read may be continued to the beginning of the label subtable until L labels are read.

[0137] In some possible implementations, L sets of synapse sub-information can be combined with the synapse sub-information and labels at corresponding positions in the L labels to obtain L sets of synapse information as the synapse information of the first neuron. In this way, the synapse information of each first neuron that generates a firing signal can be obtained by reading the synapse information of each first neuron.

[0138] In this way, synaptic weights can be shared, further reducing the amount of synaptic information data that needs to be stored, allowing corresponding electronic devices to support brain simulation of larger-scale neural networks, thereby raising the upper limit of brain simulation.

[0139] In some possible implementations, after obtaining the synaptic information of each first neuron in the first neuron cluster in step S21, the synaptic information received by each second neuron in the second neuron cluster can be determined in step S22 based on the label of the second neuron serving as the firing target of the first neuron in the synaptic information of each first neuron. That is, the synaptic information received by each second neuron is determined based on the neuron label P in each set of synaptic information of the first neurons. Furthermore, in step S22, corresponding processing is performed based on the synaptic information of each first neuron received by each second neuron in the second neuron cluster.

[0140] In some possible implementations, step S22 may include:

[0141] For any second neuron, synaptic integration processing is performed on the second neuron based on the synaptic information of the first neuron that emits to the second neuron to obtain the synaptic integration result of the second neuron; when the synaptic integration result meets the emission condition, the second neuron is determined to be the neuron that generates emission in the second neuron cluster; based on the neurons that generate emission in the second neuron cluster, the emission result of the second neuron cluster is determined.

[0142] For example, for any second neuron in the second neuron cluster, synaptic integration processing can be performed on the second neuron based on the synaptic information of each first neuron emitted to the second neuron to obtain the synaptic integration result of the second neuron (i.e., the total integrated current I). The present disclosure does not limit the specific processing method of synaptic integration.

[0143] In some possible implementations, when the synaptic information only includes the synaptic weight W and the label P, the synaptic integration result can be expressed as I(P)+=W, which means that the integral current is calculated separately according to each synaptic weight W received by the second neuron P, and each integral current is summed to obtain the synaptic integration result of the second neuron P.

[0144] In some possible implementations, synaptic information includes, in addition to the synaptic weight W and the label P, synaptic delay information, which characterizes the delay between the firing of the preceding neuron and the subsequent neuron. For example, a synaptic delay of 3 indicates that the subsequent neuron receives the firing information at time t3, three time ticks after time tick t0 of the preceding neuron. This means that the subsequent neuron performs synaptic integration at time t3.

[0145] In some possible implementations, when the synaptic information includes synaptic delay information, the step of performing synaptic integration processing on the second neuron according to the synaptic information of each first neuron emitted to the second neuron in step S22 may include:

[0146] According to the synaptic delay information of the first neuron that emits to the second neuron, the first neuron that emits to the second neuron at the current time beat is determined; according to the synaptic weight of the first neuron that emits to the second neuron at the current time beat, a synaptic integration process is performed on the second neuron to obtain a synaptic integration result of the second neuron.

[0147] For example, for any second neuron, if the synaptic information also includes synaptic delay information, the firing time of the corresponding first neuron can be determined based on the synaptic delay information of each first neuron that fires to the second neuron. For example, if the synaptic delay information obtained for a first neuron is 3 at the current time t0, the firing time is t3. The synaptic weight of the first neuron can be cached first, and the synaptic integration can be performed at the subsequent time t3.

[0148] Then, based on the firing status determined by the previous historical time beat and the firing status of the current time beat, the first neurons that fire to the second neuron at the current time beat are determined; a synaptic integration is performed based on the synaptic weight W of each first neuron to obtain a synaptic integration result. This disclosure does not limit the specific processing method of the synaptic integration.

[0149] Among them, the synaptic integration result can be expressed as I(P, D) += W, which means that the integral current is calculated separately according to the synaptic weight W of each neuron received by the second neuron P at the current time beat D, and each integral current is summed to obtain the synaptic integration result of the second neuron P.

[0150] Incorporating synaptic delay processing into brain simulation can make brain simulation closer to the actual processing process and improve the accuracy of brain simulation.

[0151] In some possible implementations, if the synaptic integration result of the second neuron P meets the firing condition, such as reaching the firing current threshold, the second neuron P is determined to be a neuron that generates firing in the second neuron cluster, and needs to be fired to the neurons in the neuron cluster after the second neuron cluster; conversely, if the synaptic integration result of the second neuron P does not meet the firing condition, it is determined that the second neuron P does not generate firing.

[0152] In some possible implementations, the above-mentioned processing may be performed on each second neuron in the second neuron cluster respectively, so as to determine each neuron in the second neuron cluster that generates a firing, and obtain the firing result of the second neuron cluster.

[0153] In this way, the result of the subsequent neuron cluster firing can be determined, thereby realizing the processing process of the subsequent neuron cluster at the current time beat.

[0154] In some possible implementations, based on the firing results of the second neuron cluster, the processing method of steps S21-S22 can be used to process the subsequent neuron clusters of the second neuron cluster. Furthermore, the above processing is performed on all neuron clusters in the neural network to obtain the brain simulation processing results of the neural network at the current time beat. After processing multiple time beats, the final brain simulation processing results of the neural network can be obtained.

[0155] In some possible implementations, the brain simulation processing method according to an embodiment of the present disclosure may be applied to a multi-core system comprising a plurality of processing cores. Each neuron cluster of a neural network corresponds to at least one processing core. In related art, synaptic information is completely stored, and it is necessary to read synaptic information from the complete information storage area of ​​the multi-core system (usually an external storage space), which reduces processing efficiency and occupies a large amount of storage space. According to an embodiment of the present disclosure, the synaptic lookup table may be stored in an internal storage space, that is, including at least one of the following: a storage space within a processing core, and an on-chip storage space corresponding to the processing core.

[0156] In some possible implementations, each neuron cluster corresponds to at least one of the multiple processing cores, which stores a synaptic lookup table for the corresponding neuron cluster. At each tick during the brain simulation, the corresponding processing core reads and integrates the synaptic lookup table for its own neuron cluster, thereby implementing the brain simulation process.

[0157] Figure 3 is a schematic diagram of a multi-core system implementation of a brain simulation processing method provided by an embodiment of the present disclosure. As shown in Figure 3, processing cores 1, 2, and 3 each correspond to a neuron cluster, and the neurons in each neuron cluster are represented in the form of a Cij array. The neurons in the neuron cluster corresponding to processing core 1 include C11, C21, C31, C41, C12, C22, and C32; the neurons in the neuron cluster corresponding to processing core 2 include C23 and C43; and the neurons in the neuron cluster corresponding to processing core 3 include C44 and C34.

[0158] In this example, each processing core has an input buffer and an output buffer. The input buffer is configured to cache release information transmitted by other processing cores, and the output buffer is configured to cache release information to be transmitted to other processing cores. For example, processing core 1 has input buffers S1, S2, S3, and S4, and output buffers S1 and S2; processing core 2 has input buffers S2 and S4, and output buffer S3; and processing core 3 has input buffers S4, S3, and output buffer S4. The input buffers correspond to the rows of the neuron array, and the output buffers correspond to the columns of the neuron array. This disclosure does not limit the specific arrangement of the input and output buffers.

[0159] In this example, the arrows in Figure 3 represent routing relationships. After completing processing at each time tick, each processing core caches the emission information in its corresponding output buffer. Furthermore, as indicated by the routing relationship, the emission information is transmitted via the on-chip network to the designated input buffer of the designated processing core. For example, the emission information of neurons C12, C22, and C32 in processing core 1 is cached in output buffer S2 and then transmitted from output buffer S2 to input buffers S2 of processing core 1 and S2 of processing core 2.

[0160] In some possible implementations, when implemented by a processing core of a many-core system, the second neuron cluster corresponds to a target processing core among multiple processing cores, and the target processing core stores a synaptic lookup table corresponding to the first neuron cluster and the second neuron cluster, as well as the emission index information of each neuron of the first neuron cluster.

[0161] In some possible implementations, before step S21, the brain simulation processing method according to an embodiment of the present disclosure may further include: determining firing index information of the first neuron that generates the firing according to the firing result of the first neuron cluster to the second neuron cluster received by the input buffer of the target processing core;

[0162] For example, at any time beat (current time beat) in brain simulation processing, the firing result obtained by the processing core corresponding to the first neuron cluster read and integrated in the previous time beat will be transmitted to the input buffer of the target processing core through its output buffer routing; after the input buffer of the target processing core receives the firing result, at the current time beat, the target processing core can read the firing index information of the first neuron that generated the firing from the internal storage space, including the index address C and the firing quantity L, etc.

[0163] In some possible implementations, in step S21, the target processing core reads the synaptic information of each first neuron from a synaptic lookup table in the target processing core's internal storage space based on the firing index information of each first neuron. In step S22, the target processing core determines the synaptic information received by each second neuron in the second neuron cluster based on the second neuron label in the synaptic information of each first neuron. Furthermore, for any second neuron, synaptic integration processing can be performed on the second neuron based on the synaptic information of each first neuron fired to the second neuron at the current time beat, obtaining a synaptic integration result for the second neuron at the current time beat. If the synaptic integration result meets the firing condition, the firing is performed. In this way, the target processing core processes each second neuron in the second neuron cluster to obtain the firing result of the second neuron cluster.

[0164] In some possible implementations, after step S22, the brain simulation processing method according to the embodiment of the present disclosure may also include: placing the emission results of the second neuron cluster into the output buffer of the target processing core, and transmitting it to the input buffer of the processing core corresponding to the subsequent neuron cluster of the second neuron cluster through the on-chip network of the many-core system.

[0165] That is to say, the target processing core can cache the emission results of the second neuron cluster to the output buffer of the target processing core, and transmit it to the input buffer of the processing core corresponding to the subsequent neuron cluster of the second neuron cluster through the on-chip network of the many-core system, so that the processing core can read and integrate the emission results in the next time beat to realize the brain simulation processing process.

[0166] In the example, the emission information of neurons C12, C22, and C32 of processing core 1 in the previous time is cached in its output buffer S2, and transmitted from output buffer S2 to input buffer S2 of processing core 1 and input buffer S2 of processing core 2; similarly, the emission information of neurons C44 and C34 of processing core 3 in the previous time is cached in its output buffer S4, and transmitted from output buffer S4 to input buffer S4 of processing core 1 and input buffer S4 of processing core 2.

[0167] In the example, at the current time beat, processing core 2 determines the pre-neuron for release based on the release information of input buffers S2 and S4, and reads the release index information of the pre-neuron from the internal storage space of processing core 2; based on the release index information, reads the synaptic information of each pre-neuron from the synaptic lookup table in the internal storage space of processing core 2; determines the synaptic information received by neurons C23 and C43 based on the neuron label in the synaptic information of each pre-neuron; and performs synaptic integration processing respectively to obtain the synaptic integration results of neurons C23 and C43 at the current time beat. If the synaptic integration results meet the release conditions, they are released, thereby obtaining the release result of processing core 2.

[0168] In the example, the emission result of processing core 2 is cached in its output buffer S3, and transmitted from the output buffer S3 to the input buffer S3 of processing core 1 and the input buffer S3 of processing core 3, so that processing cores 1 and 3 read and integrate the emission result in the next time beat to realize the brain simulation processing process.

[0169] In this way, on the one hand, the amount of stored data can be significantly reduced, so that synaptic information can be placed on the chip, improving processing efficiency; on the other hand, each processing core can perform its own lookup table reading and integration process, realizing parallel processing between cores, thereby realizing multi-core acceleration of brain simulation processing and further improving processing efficiency.

[0170] In the related art, the synaptic information required by each processing core needs to be transferred from the interface of the external storage space (such as the DDR interface), which is serial and cannot be parallelized, resulting in low processing efficiency.

[0171] According to the brain simulation processing method of the embodiment of the present disclosure, due to the use of the lookup table LUT method, the amount of stored data can be very small compared to the full storage implementation scheme, for example, only 1 / 100 of the original data size can work; and the amount of neuron-specific information (i.e., the release index information) is related to the number of front neurons N, which is O(N), that is, it is positively correlated with the number of front neurons N. The data amount of the related technology is O(N 2 ), which is positively correlated with the square of the number of neurons N. Therefore, embodiments of the present disclosure can significantly reduce storage overhead. Furthermore, the upper limit of the network size that can be stored is determined by the size of the neuron-specific information, i.e., whether this information can be stored. Other neuron parameters and state value overhead must also be considered.

[0172] In this example, it is assumed that the effective internal storage space of the electronic device is 100MB (10 8B), the synaptic weight W in each synaptic information occupies 2B, the synaptic delay information D occupies 1B, and the post-neuron label P occupies 3B, a total of 6B / each synaptic information; assuming that each pre-neuron is connected to an average of 1000 synapses, then in the full storage solution in the related art, the number of pre-neurons that can be stored is 10 8 / (6×1000)≈1.66×10 4 Using the solution of the embodiment of the present disclosure, the size of the LUT is selected as R=10 5 , then the number of stored front neurons is calculated as: 6×10 5 +x×(3(address C)+2(issued quantity L)+1(reading interval S))≤10 8 (3)

[0173] In formula (3), the storage of address C requires 3B, the storage of the issuance quantity L requires 2B, and the storage of the reading interval S requires 1B. According to formula (3), we can get x≤1656.66×10 4 It can be seen that the efficiency is improved by about 1000 times compared with the full storage solution in the related art.

[0174] According to the brain simulation processing method of the embodiment of the present disclosure, synaptic information sharing is achieved by pre-storing a small amount of synaptic information as a lookup table LUT, so that only a small amount of synaptic information needs to be stored (usually can be placed in the on-chip storage space, which is faster), and there is no need to additionally generate or read synaptic information from outside the chip, so that brain simulation of large-scale neural networks can be achieved, thereby significantly reducing the amount of stored data, and can simulate brain simulations of a network scale far larger than the fully stored neural network (larger).

[0175] According to the brain simulation processing method of the embodiment of the present disclosure, synaptic information needs to be read and calculated only when the preneuron releases information, otherwise it does not need to be read and calculated; for the same preneuron, the synaptic information read each time it releases is unchanged, that is, the synaptic information is static. When the inputs of different simulation time beats are consistent, the output current value (synaptic integration result) is also consistent, thereby improving the consistency of brain simulation results and improving the accuracy of brain simulation.

[0176] According to the brain simulation processing method of the embodiment of the present disclosure, there is no restriction on the distribution method of synaptic information, and it can support various weight distribution methods. Compared with the method of fully storing or generating weights online, it has higher flexibility and adaptability; and according to the embodiment of the present disclosure, the size of the synaptic lookup table can be dynamically conditioned, so that lookup tables of any size can be adapted to the application network; and according to the embodiment of the present disclosure, it also supports multi-core system simulation and neuromorphic chip implementation, realizes parallel processing between cores, thereby realizing multi-core acceleration of brain simulation processing, and further improving processing efficiency.

[0177] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0178] In addition, the present disclosure also provides a brain simulation processing device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any brain simulation processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method section and will not be repeated here.

[0179] FIG4 is a block diagram of a brain emulation processing device provided by an embodiment of the present disclosure. Referring to FIG4 , an embodiment of the present disclosure provides a brain emulation processing device, wherein a neural network configured to simulate a brain includes multiple neuron clusters, each of which includes multiple neurons, and the connections between neurons are characterized by synaptic weights. The device includes:

[0180] a synaptic information search module 41 configured to determine synaptic information of the first neuron from a synaptic lookup table based on the firing index information of the first neuron that generates a firing in the first neuron cluster, the synaptic information including at least the synaptic weight of the first neuron and the label of a second neuron in the second neuron cluster that is the firing target of the first neuron;

[0181] The first neuron cluster is any neuron cluster of the neural network, the second neuron cluster is a subsequent neuron cluster of the first neuron cluster, the synaptic lookup table includes multiple sets of synaptic information, each set of synaptic information includes at least a synaptic weight and a label of a neuron in the second neuron cluster, and the issuance index information includes at least an index address for the synaptic lookup table and a issuance quantity;

[0182] The emission result determination module 42 is configured to determine the emission result of the second neuron cluster according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster.

[0183] In some possible implementations, the synaptic information search module 41 is configured to: for any first neuron, determine the reading start address of the first neuron in the synaptic lookup table based on the index address of the emission index information of the first neuron; and read at least one group of synaptic information corresponding to the emission number starting from the reading start address in the synaptic lookup table based on the number of synaptic information groups in the synaptic lookup table to obtain the synaptic information of the first neuron.

[0184] In some possible implementations, the issuance index information also includes label compensation information, and the synaptic information search module 41 is configured to: for any first neuron, determine the reading start address of the first neuron in the synaptic lookup table based on the index address of the issuance index information of the first neuron; read at least one set of synaptic information corresponding to the issuance quantity starting from the reading start address in the synaptic lookup table; determine the compensated label of the second neuron based on the label of the second neuron in the synaptic information and the label compensation information, and update the synaptic information; determine the synaptic information of the first neuron based on the updated at least one set of synaptic information.

[0185] In some possible implementations, the issuance index information also includes a reading interval, and the synaptic information search module 41 is configured to: for any first neuron, determine the reading start address of the first neuron in the synaptic lookup table based on the index address of the issuance index information of the first neuron; and read at least one set of synaptic information corresponding to the issuance quantity starting from the reading start address in the synaptic lookup table based on the reading interval to obtain the synaptic information of the first neuron.

[0186] In some possible implementations, there are multiple second neuron clusters, and the multiple second neuron clusters share a synaptic lookup table. The synaptic information lookup module 41 is configured to: determine the initial synaptic information of the first neuron from the synaptic lookup table based on the release index information of the first neuron that generates the release in the first neuron cluster, the initial synaptic information including the initial weight of the first neuron and the initial label of the second neuron that is the release target of the first neuron; for any second neuron cluster, convert the initial synaptic information of the first neuron based on the synaptic conversion information of the second neuron cluster to obtain the target synaptic information of the first neuron for the second neuron cluster, and the synaptic conversion information is configured to characterize the mapping relationship between the initial synaptic information and the target synaptic information.

[0187] In some possible implementations, the emission index information includes the label, emission quantity and initial index address of the neurons in the first neuron cluster, and the synapse information search module 41 is configured to: for any first neuron that generates emission in the first neuron cluster, determine the total emission quantity of multiple neurons before the first neuron according to the label of the first neuron; determine the index address of the first neuron according to the initial index address and the total emission quantity; and determine the synapse information of the first neuron from the synapse lookup table according to the index address and emission quantity of the first neuron.

[0188] In some possible implementations, the synaptic lookup table includes a weight sub-table and a label sub-table, the weight sub-table includes multiple groups of synaptic sub-information, the label sub-table includes the labels of neurons in the second neuron cluster, the number of synaptic sub-information groups in the weight sub-table is less than the number of labels in the label sub-table, and the synaptic information lookup module 41 is configured to: for any first neuron, determine the first reading start address of the first neuron in the weight sub-table according to the index address of the first neuron and the number of synaptic sub-information groups in the weight sub-table; determine the second reading start address of the first neuron in the label sub-table according to the index address of the first neuron and the number of labels in the label sub-table; read the synaptic sub-information and labels corresponding to the number of discharges from the weight sub-table and the label sub-table respectively according to the number of synaptic sub-information groups and the first reading start address in the weight sub-table, and the number of labels and the second reading start address in the label sub-table, to obtain the synaptic information of the first neuron.

[0189] In some possible implementations, the emission result determination module 42 is configured to: for any second neuron, perform synaptic integration processing on the second neuron based on the synaptic information of the first neuron that emits to the second neuron, to obtain the synaptic integration result of the second neuron; when the synaptic integration result meets the emission condition, determine that the second neuron is the neuron that generates emission in the second neuron cluster; and determine the emission result of the second neuron cluster based on the neuron that generates emission in the second neuron cluster.

[0190] In some possible implementations, each set of synaptic information also includes synaptic delay information, and the emission result determination module 42 is configured to: determine the first neuron that emits to the second neuron at the current time beat based on the synaptic delay information of the first neuron that emits to the second neuron; and perform synaptic integration processing on the second neuron based on the synaptic weight of the first neuron that emits to the second neuron at the current time beat to obtain a synaptic integration result of the second neuron.

[0191] In some possible implementations, the apparatus is applied to an electronic device, and the synapse lookup table is stored in an internal storage space of the electronic device.

[0192] In some possible implementations, the apparatus is applied to a many-core system, the many-core system including a plurality of processing cores, the second neuron cluster corresponds to a target processing core among the plurality of processing cores, and the target processing core stores a synaptic lookup table;

[0193] Before the synaptic information search module 41, the device also includes: an index determination module, which is configured to determine the emission index information of the first neuron that generates the emission based on the emission result of the first neuron cluster for the second neuron cluster received by the input buffer of the target processing core; after the emission result determination module 42, the device also includes: an output buffer module, which is configured to place the emission result of the second neuron cluster into the output buffer of the target processing core, and transmit it to the input buffer of the processing core corresponding to the neuron cluster after the second neuron cluster through the on-chip network of the many-core system.

[0194] FIG5 is a block diagram of an electronic device provided in accordance with an embodiment of the present disclosure. Referring to FIG5 , an embodiment of the present disclosure provides an electronic device comprising a plurality of processing cores 1001 and an on-chip network 1002, wherein the plurality of processing cores 1001 are connected to the on-chip network 1002, and the on-chip network 1002 is configured to exchange data between the plurality of processing cores and external data. One or more processing cores 1001 store one or more instructions, which are executed by the one or more processing cores 1001 to enable the one or more processing cores 1001 to perform the above-described brain simulation processing method.

[0195] In some embodiments, the electronic device may be a brain-inspired chip. Because brain-inspired chips employ vectorized computing and require the use of external memory, such as Double Data Rate (DDR) synchronous dynamic random access memory, to load parameters such as weight information of the neural network model, the disclosed embodiments utilize batch processing for higher computational efficiency.

[0196] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor / processing core, implements the above-described brain simulation processing method. The computer-readable storage medium may be volatile or non-volatile computer-readable storage medium.

[0197] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned brain simulation processing method.

[0198] It will be understood by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium).

[0199] As is well known to those skilled in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically contains computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0200] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0201] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0202] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0203] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0204] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0205] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0206] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions configured to realize the logical function of the specification. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a special hardware-based system that performs the function or action of the specification, or can be implemented by a combination of special hardware and computer instructions.

[0207] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A brain simulation processing method, wherein: The neural network for brain simulation includes a plurality of neuron clusters, wherein the neuron clusters include a plurality of neurons, and the connections between the neurons are characterized by synaptic weights; the method includes: Determine synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster, wherein the synaptic information includes at least a synaptic weight of the first neuron and a label of a second neuron in the second neuron cluster that is a firing target of the first neuron; Wherein, the first neuron cluster is any neuron cluster of the neural network, the second neuron cluster is a post-neuron cluster of the first neuron cluster, the synapse lookup table includes multiple groups of synapse information, each group of synapse information includes at least a synapse weight and a label of a neuron in the second neuron cluster, and the issuance index information includes at least an index address and a issuance quantity for the synapse lookup table; The firing result of the second neuron cluster is determined according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster.

2. The method according to claim 1, wherein: The step of determining the synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster includes: For any first neuron, determining a reading start address of the first neuron in the synapse lookup table according to an index address of the release index information of the first neuron; According to the number of synaptic information groups in the synaptic lookup table, at least one group of synaptic information corresponding to the issuance quantity starting from the read start address is read in the synaptic lookup table to obtain the synaptic information of the first neuron.

3. The method according to claim 1, wherein: The issuing index information also includes label compensation information, The step of determining the synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster includes: For any first neuron, determining a reading start address of the first neuron in the synapse lookup table according to an index address of the release index information of the first neuron; Reading at least one set of synapse information corresponding to the issuance quantity starting from the read start address in the synapse lookup table; Determine the label of the second neuron after compensation according to the label of the second neuron in the synaptic information and the label compensation information, and update the synaptic information; The synaptic information of the first neuron is determined according to the updated at least one set of synaptic information.

4. The method according to claim 1, wherein: The issuing index information also includes a reading interval, The step of determining the synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster includes: For any first neuron, determining a reading start address of the first neuron in the synapse lookup table according to an index address of the release index information of the first neuron; According to the reading interval, at least one set of synaptic information corresponding to the issuance quantity starting from the reading start address is read in the synaptic lookup table to obtain the synaptic information of the first neuron.

5. The method according to claim 1, wherein: There are multiple second neuron clusters, and the multiple second neuron clusters share the synapse lookup table. The step of determining the synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster includes: Determining initial synaptic information of a first neuron in a first neuron cluster from a synaptic lookup table according to the firing index information of the first neuron generating the firing, the initial synaptic information including an initial weight of the first neuron and an initial label of a second neuron that is a firing target of the first neuron; For any second neuron cluster, the initial synaptic information of the first neuron is converted according to the synaptic conversion information of the second neuron cluster to obtain the target synaptic information of the first neuron for the second neuron cluster, and the synaptic conversion information is used to characterize the mapping relationship between the initial synaptic information and the target synaptic information.

6. The method according to claim 1, wherein: The issuing index information includes the number of neurons of the first neuron cluster, the issuing quantity and the initial index address, The step of determining the synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster includes: For any first neuron in the first neuron cluster that generates firing, determine the total number of firings of a plurality of neurons preceding the first neuron according to the label of the first neuron; Determining the index address of the first neuron according to the initial index address and the total number of issuances; According to the index address and the emission quantity of the first neuron, the synaptic information of the first neuron is determined from the synaptic lookup table.

7. The method according to claim 1, wherein: The synapse lookup table includes a weight sub-table and a label sub-table, wherein the weight sub-table includes multiple groups of synapse sub-information, and the label sub-table includes the labels of neurons in the second neuron cluster, and the number of synapse sub-information groups in the weight sub-table is less than the number of labels in the label sub-table, The step of determining the synaptic information of the first neuron from a synaptic lookup table according to the firing index information of the first neuron that generates firing in the first neuron cluster includes: For any first neuron, determining a first read start address of the first neuron in the weight subtable according to the index address of the first neuron and the number of synapse sub-information groups in the weight subtable; Determine a second read start address of the first neuron in the label subtable according to the index address of the first neuron and the number of labels in the label subtable; According to the number of synaptic sub-information groups in the weight sub-table and the first read start address, the number of labels in the label sub-table and the second read start address, the synaptic sub-information and labels corresponding to the number of releases are read from the weight sub-table and the label sub-table respectively to obtain the synaptic information of the first neuron.

8. The method according to claim 1, wherein: The determining the emission result of the second neuron cluster according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster includes: For any second neuron, according to the synaptic information of the first neuron emitted to the second neuron, perform synaptic integration processing on the second neuron to obtain a synaptic integration result of the second neuron; When the synaptic integration result satisfies the firing condition, determining the second neuron as a neuron in the second neuron cluster that generates firing; The firing result of the second neuron cluster is determined according to the neurons that generate firing in the second neuron cluster.

9. The method according to claim 8, wherein: Each set of synaptic information also includes synaptic delay information. The step of performing synaptic integration processing on the second neuron according to the synaptic information of the first neuron emitted to the second neuron to obtain the synaptic integration result of the second neuron includes: Determine the first neuron that emits to the second neuron at the current time according to the synaptic delay information of the first neuron that emits to the second neuron; According to the synaptic weight of the first neuron that is emitted to the second neuron at the current time, synaptic integration processing is performed on the second neuron to obtain a synaptic integration result of the second neuron.

10. The method according to any one of claims 1 to 9, wherein: The method is applied to an electronic device, and the synapse lookup table is stored in an internal storage space of the electronic device.

11. The method according to claim 8, wherein: The method is applied to a many-core system, the many-core system includes a plurality of processing cores, the second neuron cluster corresponds to a target processing core among the plurality of processing cores, and the synapse lookup table is stored in the target processing core; Before determining the synaptic information of the first neuron from the synaptic lookup table, the method further includes: Determine, according to the firing result of the first neuron cluster to the second neuron cluster received by the input buffer of the target processing core, firing index information of the first neuron that generates the firing; After determining the firing result of the second neuron cluster, the method further includes: The emission result of the second neuron cluster is placed in the output buffer of the target processing core, and transmitted to the input buffer of the processing core corresponding to the subsequent neuron cluster of the second neuron cluster through the on-chip network of the many-core system.

12. A brain simulation processing device, wherein: The neural network for brain simulation includes a plurality of neuron clusters, wherein the neuron clusters include a plurality of neurons, and the connections between the neurons are characterized by synaptic weights. The device includes: a synaptic information search module, configured to determine synaptic information of the first neuron from a synaptic search table according to the firing index information of the first neuron that generates firing in the first neuron cluster, wherein the synaptic information at least includes a synaptic weight of the first neuron and a label of a second neuron in the second neuron cluster that is a firing target of the first neuron; Wherein, the first neuron cluster is any neuron cluster of the neural network, the second neuron cluster is a post-neuron cluster of the first neuron cluster, the synapse lookup table includes multiple groups of synapse information, each group of synapse information includes at least a synapse weight and a label of a neuron in the second neuron cluster, and the issuance index information includes at least an index address and a issuance quantity for the synapse lookup table; The emission result determination module is configured to determine the emission result of the second neuron cluster according to the synaptic information of the first neuron received by the second neuron of the second neuron cluster.

13. An electronic device, wherein: include: Multiple processing cores; as well as An on-chip network is configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the brain simulation processing method as described in any one of claims 1-11.

14. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the computer program implements the brain simulation processing method according to any one of claims 1 to 11.

15. A computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, wherein: When the computer readable code is executed in a processor of an electronic device, the processor in the electronic device executes the brain simulation processing method according to any one of claims 1 to 11.

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