Memory management method and apparatus, and storage system and computer-readable medium

Abstract

A memory management method and apparatus, and a storage system and a computer-readable medium, which relate to the technical field of mobile terminals. The method comprises: determining a target pre-erasing mode from an automatic mode and an active mode (S201), wherein in the automatic mode, a memory automatically executes a pre-erasing operation, and in the active mode, the memory executes the pre-erasing operation on the basis of an instruction sent by a host; and executing the pre-erasing operation on the memory on the basis of the target pre-erasing mode (S202). For a mode in which the memory automatically performs pre-erasing and a mode in which pre-erasing is triggered by the host, the method can freely select one of the automatic mode and the active mode to execute the pre-erasing operation, so that the setting of the pre-erasing operation is more rational.

Description

Memory management method, device, storage system and computer-readable medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application with application number 202311672217.2 filed with the Chinese Patent Office on December 6, 2023, entitled “Memory Management Method, Device, Storage System and Computer-Readable Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of mobile terminal technology, and more specifically, to a memory management method, device, storage system, and computer-readable medium. Background Art

[0004] Currently, in flash memory, especially NAND type flash memory, a pre-erase operation is usually required. Usually, when the current block of such memory is full and the data is switched to a new block, the new block must be erased before data is written. Summary of the Invention

[0005] The present application proposes a memory management method, device, storage system and computer-readable medium to improve the above-mentioned defects.

[0006] In a first aspect, the present application provides a memory management method, which is applied to a host of a storage system, wherein the storage system also includes the memory, and the host is connected to the memory, and the method includes: determining a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; and performing a pre-erase operation on the memory based on the target pre-erase mode.

[0007] In a second aspect, the present application further provides a memory management device, applied to a host of a storage system, the storage system also including the memory, the host being connected to the memory, the device comprising: a determination unit and an erasing unit. The determination unit is configured to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host. The erasing unit is configured to perform a pre-erase operation on the memory based on the target pre-erase mode.

[0008] In a third aspect, the present application also provides a storage system, comprising: a host; a memory; the host is connected to the memory, and the host is used to execute the above method.

[0009] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] FIG1 shows a schematic diagram of a storage system provided by an embodiment of the present application;

[0012] FIG2 shows a flow chart of a memory management method according to an embodiment of the present application;

[0013] FIG3 shows a schematic diagram of the interaction between the automatic mode and the active mode provided by another embodiment of the present application;

[0014] FIG4 is a schematic diagram showing the effects of the automatic mode and the active mode provided by another embodiment of the present application;

[0015] FIG5 shows a schematic diagram of the format of a UPIP provided in an embodiment of the present application;

[0016] FIG6 shows a schematic diagram of an EHS field provided in an embodiment of the present application;

[0017] FIG7 shows a flow chart of a memory management method provided by another embodiment of the present application;

[0018] FIG8 shows a schematic diagram of step S780 in FIG7 ;

[0019] FIG9 shows a module block diagram of a memory management device provided by an embodiment of the present application;

[0020] FIG10 shows a storage unit for storing or carrying program codes for implementing the method according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0022] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0023] Currently, flash memory, particularly NAND flash memory, often requires a pre-erase operation. Typically, in host systems using universal flash storage (UFS) as a storage device, the UFS firmware manages the media (NAND flash) in units of virtual blocks (VBs). When a UFS device switches to a new block after the current block is full, it first erases the new block (in milliseconds) before writing data (program). This is because erased media has poor stability and cannot be used for data writing after a certain period of time.

[0024] A pre-erase operation is the process of erasing the block containing the data to be written before a write operation is performed on flash memory. This process is typically managed and executed by a controller. In NAND flash memory, data can only be erased and written in blocks. Therefore, if new data is to be written to a block that already contains old data, the entire block must be erased before the write operation can be performed. This leads to an operation process known as "erase-write." The purpose of the pre-erase operation is to erase the block containing data before the actual write operation to reduce write latency. This eliminates the need for the controller to perform an erase operation during the actual write operation, thereby speeding up write operations and reducing potential errors. In practical applications, the pre-erase operation for flash memory is typically managed and executed by the controller. When the controller receives a write request, it checks whether the block containing the data has been erased. If the block has not been erased, the controller automatically performs an erase operation before proceeding with the write operation.

[0025] Due to the erase-before-write strategy described above, flash memory devices (such as UFS devices) experience periods of time, typically milliseconds, when writes are not possible under high write pressure. Therefore, pre-erasing some blocks and reducing the time required for UFS block switching significantly improves device write performance while minimizing the maximum latency caused by the erase operation during block switching.

[0026] However, the inventors found in their research that current pre-erase schemes generally have the following disadvantages:

[0027] 1) Relatively Fixed Pre-erase Capacity Threshold: In current device-independent pre-erase schemes, the pre-erase capacity is determined by the device itself, and pre-erases to the set threshold during idle time. To maximize performance gains, the threshold should be as high as possible; however, considering stability and the lack of free blocks, the threshold cannot be set too high. Therefore, the device selects a threshold that strikes a balance between benefit and risk. This relatively fixed threshold cannot adapt to changes in host write activity.

[0028] 2) Stability risk of pre-erased blocks: Currently, the device cannot detect host write actions, and the pre-erase threshold is relatively fixed, so there will always be some pre-erased blocks in the device. If the host does not write for a period of time, the pre-erased blocks are prone to stability risks.

[0029] Therefore, it is extremely important to set a reasonable pre-erase strategy.

[0030] In order to overcome the above-mentioned defects, an embodiment of the present application provides a memory management method that can adaptively adjust the pre-erase mode in combination with the actual data writing situation of the electronic device.

[0031] It should be noted that the memory management method provided in the embodiment of the present application is applied to a system composed of a host using a flash memory. As shown in Figure 1, the storage system 10 includes a host 100 and a memory 200, and the host 100 is connected to the memory 200. Exemplarily, the host 100 can be an electronic device, which can be a device capable of running applications such as a smartphone, a tablet computer, an e-book, etc. In the embodiment of the present application, the host 100 is a smartphone. The memory 200 can be the above-mentioned flash memory, for example, the memory 200 is a UFS.

[0032] It is understandable that the memory 200 can be a built-in memory of the host 100, that is, the memory 200 can be integrated into the motherboard of the host 100 and used as the ROM of the mobile phone to store the operating system, application programs and user data. In addition, the memory 200 can be an external memory of the host 100, that is, a peripheral device belonging to the host 100. For example, taking the memory 200 as UFS as an example, the host 100 and the memory 200 are connected through a USB interface. Of course, the UFS storage device can also be designed as a pluggable memory card, similar to a traditional SD card or microSD card. In this way, the user can insert the UFS storage device into the USB interface of the mobile phone and perform data transmission and access through the USB interface. In the embodiment of the present application, there is no limitation on whether the memory 200 is an external memory or a built-in memory of the host 100, and the host is used to execute the following embodiments.

[0033] Please refer to Figure 2. The method is applied to the above-mentioned host. For ease of description, the following embodiment takes the memory as UFS as an example. Of course, the memory can also be of other types and is not limited to this. The method includes: S201 to S202.

[0034] S201: Determine a target pre-erase mode in the automatic mode and the active mode.

[0035] As an implementation method, the host can generally use two pre-erase modes, namely automatic mode and active mode. Among them, the automatic mode is Auto mode. In Auto mode, the UFS will automatically perform a pre-erase operation. When the host sends a write command, the UFS device will automatically detect the status of the target physical block and perform an erase operation when necessary. In this mode, the host does not need to explicitly send a pre-erase command, and the erase operation is handled by the UFS device itself. The active mode is Host Trigger mode. In Host Trigger mode, the host needs to explicitly send a pre-erase command to trigger the erase operation. After the host sends the pre-erase command, the UFS device will perform the erase operation according to the requirements of the command. In this mode, the host can more accurately control when to perform the erase operation. That is, in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on the instruction sent by the host.

[0036] Please refer to Figure 3, which shows the difference between automatic mode and active mode. In automatic mode, the host sends the first erase command, i.e., Write (10) EHS: open auto pre erase. The storage device responds to the first erase command and enters automatic mode. In automatic mode, 2GB of free physical blocks are pre-erased to obtain 2GB of pre-erased blocks. Then, the host performs a write operation using the pre-erased blocks, i.e., Write cmds, use pre erase blocks. The memory detects that the pre-erased blocks are being used and automatically pre-erases 2GB of free physical blocks again. This continues in this order until the automatic mode is turned off, i.e., Write (10) EHS: close auto pre erase. As can be seen from Figure 3, in active mode, each pre-erase operation is actively triggered by the host. Specifically, it can be actively triggered based on the return information of the memory, which will be described in detail later.

[0037] Specifically, the beneficial effects of the automatic mode and the active mode are shown in FIG4 .

[0038] It can be seen that in active mode (host trigger mode), the pre-erase amount is fully controllable by the host, which can effectively prevent the stability risks caused by the retention of pre-erased blocks. However, the IO coverage is lower than that in automatic mode (auto mode). This is mainly because the host trigger mode triggers pre-erase after a large number of write IOs (write operations), which has a certain lag and cannot guarantee that all IOs will benefit from the pre-erase. Based on the aforementioned conditions for sending the second erase operation, it can be seen that the second erase instruction is only sent when it is determined that the write rate is greater than the current first specified threshold. Therefore, multiple write operations may have been executed before the write rate reaches the first specified threshold. As shown in Figure 4, in active mode, write operations within the time period filled with diagonal lines cannot benefit from the pre-erase.

[0039] The auto mode has a higher io coverage rate, but it is not fully controllable by the host. If it is always on, erase blocks may remain unused, causing stability issues. Therefore, in scenarios where there is a large amount of sequential writes, the auto mode can be enabled to maximize the pre-erase benefit of the write operation. The io coverage rate refers to the ratio of the time period during which the write operation benefits from the pre-erase benefit to the entire write operation time period. The pre-erase benefit refers to the ability of the write operation to use the pre-erase block.

[0040] In the present application, based on the characteristics of the aforementioned active mode and automatic mode, a mode may be selected from the automatic mode and the active mode as a target pre-erase mode based on actual needs, so as to perform a pre-erase operation.

[0041] As an implementation method, the embodiment of the present application can determine the target pre-erase mode based on the application scenario of the storage system. For example, the application scenario can be a scenario of writing data to the UFS of the storage system. As mentioned above, the purpose of the pre-erase operation is to erase the data in the storage device before writing new data to ensure the stability and security of data writing. Therefore, for different data write amounts, there should be different requirements for the capacity of the physical block of the pre-erase operation. In order to make the pre-erase operation more reasonable, it is necessary to determine the current data writing situation of the storage system, that is, the application scenario, before determining the pre-erase operation mode.

[0042] As an implementation method, the application scenario can reflect the amount of data written to the storage system currently or in a certain time period in the future (i.e., the target time period). Therefore, multiple scenarios can be pre-set, and the amount of data written to each scenario is different. Among them, the amount of data written represents the amount of data written that may occur in the scenario. For example, it can be the maximum amount of data written in the scenario, that is, it can be the historical peak value of the amount of data written in the scenario, or it can be the historical average value of the amount of data written in the scenario. Therefore, for different scenarios, it can be determined by analyzing the amount of data written to the UFS of the storage system in the historical time period before the current moment, and by counting the amount of data written to the UFS in the historical time period, the data range of the data write amount corresponding to the current historical time period can be determined. Based on the scenarios corresponding to the pre-set different data ranges, the current application scenario can be determined.

[0043] As an implementation manner, after the application scenario is determined, a target pre-erasure mode is determined in the automatic mode and the active mode based on the application scenario.

[0044] In the embodiments of the present application, the application scenarios of the storage system can be divided into a first scenario and a second scenario, wherein the data write volume of the first scenario is greater than the data write volume of the second scenario. It should be noted that the preset data write volume represents the data write capacity corresponding to the scenario, that is, it is an estimate of the maximum data write volume in the scenario.

[0045] It can be understood that in the embodiments of the present application, the first scenario is a scenario in which a large amount of data is written compared to the second scenario. That is, in the first scenario, the storage system may have the possibility of writing a large amount of data sequentially into the memory, while in the second scenario, the amount of data written into the memory is often smaller.

[0046] As another implementation, the target pre-erase mode can also be determined by the application running on the host. For example, the application currently running on the host is determined, and based on the currently running application, the target pre-erase mode is determined between the automatic mode and the active mode. Since different applications have different requirements for the number of writes and the write rate, different applications may have different requirements for the automatic mode and the active mode. Therefore, the modes corresponding to different applications can be pre-set to obtain a mode correspondence relationship. Based on this mode correspondence relationship, it can be determined whether the current application should use the active mode or the automatic mode. The details will be explained in the subsequent embodiments.

[0047] In an embodiment of the present application, the different pre-erase modes correspond to different pre-erase strategies, which may specify the timing of the pre-erase operation, the capacity of the pre-erase block, etc., wherein the pre-erase block refers to the physical block in the memory on which the pre-erase operation is performed, and the capacity of the pre-erase block may refer to the number of physical blocks of a specified capacity in the memory on which the pre-erase operation is performed.

[0048] Therefore, through the above correspondence, the pre-erasing mode corresponding to the current application scenario of the storage system can be determined as the target pre-erasing mode for the memory.

[0049] S202: Perform a pre-erase operation on the memory based on the target pre-erase mode.

[0050] As previously mentioned, different pre-erase modes specify pre-erase policies, including the timing of pre-erase, the capacity of pre-erase blocks, and the entity that performs the pre-erase operation. After determining the target pre-erase mode corresponding to the current application scenario of the storage system, a pre-erase operation is performed on the memory based on the target pre-erase policy corresponding to the target pre-erase mode. Subsequent embodiments will explain different pre-erase operations based on different pre-erase modes.

[0051] It should be noted that after determining the target pre-erase mode, a pre-erase instruction corresponding to the target pre-erase mode can be determined and the pre-erase instruction can be sent to the memory so that the memory performs a pre-erase operation based on the pre-erase instruction. In the embodiment of the present application, the host can send the pre-erase instruction to the memory in three ways.

[0052] In the first method, the pre-erase command is added to a preset field of a specified instruction to be sent to the memory to obtain a target instruction; the target instruction is sent to the memory, causing the memory to perform a pre-erase operation based on the pre-erase command. The specified instruction to be sent to the memory may be a write or read instruction, i.e., a WRITE / READ command, that the host currently needs to send to the memory. The preset field may be the EHS field or other field of the specified instruction.

[0053] In an embodiment of the present application, the designated instruction is a read or write instruction in a UFS Protocol Information Unit (UPIU), and the preset field is an extra header segment (EHS). The format of the UPIU is shown in FIG5 , and it can be seen that the UPIU includes an EHS field, wherein the definition of the EHS field in the UPIU is shown in FIG6 . It can be seen that the type, parameters, and specific content of a specific instruction can be defined in the EHS, so that a pre-erase command can be added to the EHS.

[0054] It can be understood that UPIU is the basic protocol used for communication in UFS. It is a standard command format used for control and data transmission between UFS devices, and includes commands and data structures used for communication. UPIU contains various commands for reading and writing, status information, error codes, etc., as well as some additional header information, such as Extra Header Segment (EHS). Among them, EHS is part of UPIU, which contains extended header information for carrying some additional control information or metadata. EHS can be used to transmit some auxiliary information specific to commands or data transmission to support more complex operations or provide additional contextual information.

[0055] For example, the identifier of the pre-erase command can be determined first, and then the EHS data structure can be configured. According to the definition in the UFS specification, the data structure of the pre-erase command to be added to the EHS needs to be determined. This may include the command type, command parameters, length field, etc. The data structure and identifier of the pre-erase command are then encapsulated in the EHS field of the UPIU. It should be noted that the EHS field is an extension of the aforementioned specified instruction.

[0056] In addition, the memory needs to be adaptively configured so that after receiving the specified instruction, it can parse the EHS field of the instruction, obtain the pre-erase command, and execute the pre-erase command when the execution conditions are met. The implementation method of the execution conditions can be referred to in subsequent embodiments and will not be repeated here.

[0057] Therefore, by adding the pre-erase command in the preset field of the specified instruction to be sent to the memory, the pre-erase command is also included in the specified instruction to be sent to the memory, so that there is no need to send a pre-erase command separately in addition to the specified instruction. In other words, there is no need to generate additional interaction due to sending a pre-erase command separately, which can prevent the real-time performance of the user from being affected.

[0058] The second method is to obtain the pre-erase command corresponding to the target pre-erase mode, generate a pre-erase instruction based on the pre-erase command in the UPIU protocol, and send the pre-erase instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase instruction. Exemplarily, by creating an erase command (Erase Command) data packet, encapsulating the Erase Command into the UPIU, configuring the UPIU header information, and sending the UPIU, the UPIU instruction (i.e., the pre-erase instruction) containing the erase command is sent to the UFS device to trigger the pre-erase operation. For example, a separate UPIU is used to issue a pre-erase instruction, such as using the WRITE BUFFER command to define a pre-erase vendor command. Among them, the WRITE BUFFER command may include the following functions: write data: this command can instruct the storage device to receive a certain amount of data and write this data into the device's buffer; buffer management: the WRITE BUFFER command may involve the management of the device's internal buffer, including clearing, refreshing or allocating buffer operations; data transfer preparation: some storage devices may use the WRITE BUFFER command to prepare for data transfer so that data can be effectively transferred to a specific location in the memory. For example, according to the UFS memory specification, a specific vendor command is defined using the WRITE BUFFER command to perform an erase operation. The specific vendor command structure and content need to be constructed according to the specification document of the UFS memory. In the vendor command, command codes and parameters can be defined to instruct the memory to perform an erase operation. Send the Vendor Command, that is, send the constructed vendor command to the UFS memory using UPIU.

[0059] It should be noted that the difference between the second method and the first method is that in the first method, the host sends a specified instruction, and the preset field of the specified instruction contains a pre-erase command. The pre-erase command serves as extended information of the specified instruction in the preset field. For example, if the specified instruction is a write instruction of the UPIU protocol, then the pre-erase command belongs to the extended content of the write instruction. The host sends a specified instruction to the memory, and the memory obtains the pre-erase command by parsing the content of the preset field of the specified instruction. At the same time, the memory responds to the specified instruction and performs the operation corresponding to the specified instruction. For example, if the specified instruction is a write instruction, the memory will simultaneously respond to the write instruction to perform a write operation and respond to the pre-erase command to perform a pre-erase operation. In the second method, the pre-erase instruction sent by the host is a pre-erase instruction directly defined by the UPIU protocol. Therefore, the memory receives the instruction and responds to the pre-erase instruction to perform a pre-erase operation.

[0060] The third method is to obtain the pre-erase command corresponding to the target pre-erase mode and issue the pre-erase command through a preset request such as a query request or a task management request. The query request (i.e., the first request) is used to query the properties and status of the memory, while the task management request (i.e., the second request) can be used to manage and control the execution of tasks in the memory. In other words, the pre-erase command can be added to the preset request, and then the preset request is sent to the memory, so that the memory performs the pre-erase operation based on the pre-erase command in the preset request.

[0061] It should be noted that, in the above three methods, the embodiment of the present application can select any one method to send the pre-erase command. However, considering reducing the interactive impact on the memory, in the embodiment of the present application, the pre-erase command corresponding to the target pre-erase mode is sent through the first method.

[0062] Therefore, the embodiment of the present application can determine the pre-erase mode for the memory based on the current data writing situation of the storage system, so that the pre-erase operation of the memory can be combined with the application scenario of the storage system, thereby making the pre-erase operation more in line with the current data writing requirements of the storage system, and making the setting of the pre-erase operation more reasonable.

[0063] Please refer to Figure 7. The method is applied to the above-mentioned host. For ease of description, the following embodiment takes the memory as UFS as an example. Of course, the memory can also be of other types and is not limited to this. The method includes: S710 to S780.

[0064] S710: Determine the application program currently running on the host.

[0065] As mentioned above, the target pre-erase mode can be determined by the application program running on the host. Therefore, in the embodiment of the present application, the application program running on the host is first determined.

[0066] As an implementation method, taking the host as a smartphone as an example, the running application can be an application running in the foreground and / or background of the smartphone. In the embodiment of the present application, the running application can be an active application, and the active application can refer to an application that has run in the foreground within the current time period and is currently running in the foreground or background, or an application that has written data to the memory within the current time period, or an application that is currently running in the foreground, or an application that is currently reading and / or writing data.

[0067] Active applications are applications that have run in the foreground within the current time period and are currently running in the foreground or background. The current time period can be a specified time period before the current moment. Active applications can include applications currently running in the foreground and applications that have switched from the foreground to the background during the current time period. In other words, considering that applications that the user recently switched to the background may be switched to the foreground again, all applications that have run in the foreground within the current time period are considered active applications, that is, the aforementioned running applications.

[0068] In the case where the active application is an application that has written data to the memory within the current time period and is currently running in the foreground or background, the electronic device determines the application currently running in the foreground or background of the electronic device as an alternative application, and then searches for an application that has written data to the memory within the current time period from the alternative application as the active application, that is, the aforementioned running application. Among them, the application that has written data to the memory can be further defined as the amount of data written to the memory is greater than the specified amount of data. Therefore, among the various applications currently running in the foreground and background of the electronic device, the application that has written data recently can be regarded as the active application, that is, the application currently running by the host.

[0069] In an embodiment of the present application, the active application refers to the application currently running in the foreground of the electronic device, that is, to determine the implementation method of the application currently running on the host, determine the application currently running in the foreground of the host, that is, the application currently running in the foreground of the electronic device.

[0070] S720: Determine whether a specified application exists in the running applications.

[0071] As an implementation method, the designated application may be an application in an application list, and the application list may be an application that has been pre-counted to have a large number of sequential write operations. For example, when a game application performs an installation package installation operation or a version update operation, there are a large number of sequential write operations. A large number of sequential write operations refers to the continuous execution of write operations within a preset time period and the amount of data written is greater than the preset data amount. It is understandable that the applications in the application list can be manually added or determined by the host based on whether there are a large number of sequential write operations for each application within the statistical period. The specific details are not limited here.

[0072] Therefore, after the host determines the currently running application, it uses the currently running application as the active application and compares it with each designated application in the application list to determine whether there is an application that is identical to the designated application. Assuming that the currently running application is the application currently running in the foreground, it determines whether the application is a designated application in the application list. If so, the process proceeds to S730; otherwise, the process proceeds to S750.

[0073] As an implementation method, if a designated application exists among the running applications, then the application scenario in which the target pre-erase mode is determined to be the automatic mode host is the first scenario; if the designated application does not exist among the running applications, then the application scenario in which the target pre-erase mode is determined to be the active mode host is the second scenario. In an embodiment of the present application, the two application scenarios of the designated application existing among the running applications and the designated application not existing among the running applications can be named as the first scenario and the second scenario, respectively. It is understandable that in some embodiments, the first scenario and the second scenario may not be set. When it is determined that a designated application exists among the running applications, the target pre-erase mode is directly determined to be the automatic mode, and when it is determined that a designated application does not exist among the running applications, the target pre-erase mode is directly determined to be the active mode. By adopting the first scenario and the second scenario, it is more convenient to describe the active mode scenario and the automatic mode scenario.

[0074] S730: Determine that the application scenario of the host is the first scenario.

[0075] That is, when it is determined that the designated application exists among the running applications, the application scenario of the host is determined to be the first scenario.

[0076] As previously mentioned, the application scenario may include a first scenario and a second scenario, with the first scenario having a greater data write volume than the second scenario. Each designated application within the application list is a predetermined application that undergoes a large number of sequential write operations. Therefore, when the designated application is running, it is likely to perform a large number of sequential write operations. Therefore, the application scenario in which the designated application is running is defined as the first scenario, and the application scenario in which the designated application is not running is correspondingly defined as the second scenario. This aligns with the assumption that the first scenario has a greater data write volume than the second scenario.

[0077] S740: Determine that the target pre-erase mode for the memory is the automatic mode.

[0078] If the application scenario is the first scenario, the target pre-erase mode for the memory is determined to be the automatic mode, that is, for application scenarios with a large number of sequential writes, an application list is pre-set and the automatic mode is enabled during the activities of these applications.

[0079] S750: Send a first erase instruction to the memory to trigger the memory to enter an automatic mode.

[0080] The pre-erase instruction corresponding to the automatic mode is the first erase instruction, which is used to trigger the memory to enter the automatic mode. It is understood that the first erase instruction can be sent in any of the three aforementioned ways. In the embodiment of the present application, the first erase instruction can be sent in the first way.

[0081] As an implementation, the memory corresponds to a device management unit, which can be a controller within the memory. Furthermore, in a host system using universal flash storage (UFS) as a storage device, the UFS firmware manages the medium (NAND flash) using virtual blocks (VBs). In UFS, the storage area is divided into multiple physical blocks, each containing multiple sectors, typically 512 bytes or 4KB in size. Virtual blocks are a logical mapping layer built on top of physical blocks, combining multiple physical blocks into a single logical block and assigning a virtual address to the logical block. Virtual block mapping enables more efficient data reading, writing, and management. For example, in UFS, if a bad block occurs, the virtual block can automatically remove the block from the logical block and migrate the data to other available physical blocks, thereby ensuring data integrity and reliability. Furthermore, virtual blocks enable UFS's high-speed random read and write operations, as well as optimization and support for the TRIM command.

[0082] It is understood that in UFS storage, pre-erase operations are typically performed by a controller within the storage, namely the aforementioned device management unit. For example, the UFS controller within the storage is responsible for managing and executing erase operations. The storage controller can use VB to search for free physical blocks to perform erase operations.

[0083] For example, sending a first erase instruction to the memory to trigger the memory to enter the automatic mode may be implemented as follows:

[0084] In the automatic mode, a first erase command is sent to the memory; the memory erases free physical blocks of a first capacity within the memory as pre-erase blocks. If the amount of data written to the pre-erase blocks is detected to be greater than a threshold, the memory erases free physical blocks of the first capacity within the memory as pre-erase blocks again, continuing until the automatic mode ends. The first capacity may be a pre-erase capacity specified by the host and included in the first erase command. In other words, the host triggers the memory to automatically trigger a pre-erase operation and reserve pre-erase physical space of the first capacity, i.e., pre-erase blocks. A free physical block refers to a storage block on a storage medium (such as a solid-state drive or flash memory) that has not been used or allocated to any data. A physical block is the smallest writable unit of a storage medium and typically has a fixed size. In a storage device, physical blocks are organized into contiguous blocks for storing data. When data is deleted or moved, the corresponding physical block becomes a free physical block and can be reused to store new data. Therefore, the capacity of a pre-erase block typically refers to the number of physical blocks on which the pre-erase operation is performed.

[0085] That is, in automatic mode, the host turns on the pre-erase of the memory's Auto mode through the first erase command, and specifies the pre-erase capacity (i.e., the first capacity) and the VB usage mode. The UFS device will automatically pre-erase to the first capacity after idle time for read and / or write operations. The VB usage mode will be described in the subsequent content. When the pre-erased blocks are consumed by write operations, the device automatically pre-erases based on its own idle time and replenishes the pre-erased blocks to the set capacity. When the host issues a command to turn off the Auto mode, the device stops automatic pre-erasing. The pre-erased blocks will gradually be consumed by subsequent writes.

[0086] Therefore, the host can specify the following in the pre-erase command: a) Pre-erase mode: automatic mode (Auto mode) or active mode (Host trigger mode); b) VB usage mode: including the currently commonly used NAND flash SLC / TLC / QLC modes, including but not limited to the media usage mode of new media such as MRAM / PCM / XL-Flash; c) Capacity configuration: the host can configure the pre-erase capacity size within a certain range.

[0087] S760: Determine that the application scenario of the host is the second scenario.

[0088] That is, when it is determined that the designated application does not exist in the running applications, the application scenario of the host is determined to be the second scenario.

[0089] S770: Determine that the target pre-erase mode for the memory is an active mode.

[0090] The implementation of the second scenario and the active mode can refer to the above content.

[0091] S780: Send a second erase instruction to the memory, instructing the memory to perform a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space.

[0092] In the active mode, a second erase instruction is sent to the memory, instructing the memory to perform a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space. That is, in the active mode, the host specifies the capacity of the pre-erase space as the second capacity, and the memory erases the free physical blocks of the second capacity to obtain a pre-erase space of the second capacity, i.e., a pre-erase block. Therefore, when the host detects that the specified application is active at the application layer, it determines that the application scenario is the first scenario and sends an instruction to start the automatic mode, i.e., the open auto pre-erase instruction, to the driver layer. Then, the driver layer sends a pre-erase command to start the auto mode, i.e., the first erase instruction, to the memory. For example, the driver layer uses the EHS field of the write(10) command to send a pre-erase command to start the auto mode, i.e., the first erase instruction is sent to the memory using the first method mentioned above. Wherein, write(10) is a write command, and "(10)" represents that this is a 10-byte write command for writing data.

[0093] It should be noted that in automatic mode, the host needs to determine whether automatic mode has ended. If so, the host needs to send a first shutdown instruction to the memory, which is used to terminate automatic mode. Determining whether automatic mode has ended can include returning to execute the application currently running on the host. The termination of automatic mode can include entering active mode or transitioning to neither active mode nor automatic mode, for example, when no application is currently running. Similarly, active mode can also determine whether active mode has ended in this manner.

[0094] In addition, since NAND flash has different usage modes for a physical block, namely SLC / MLC / TLC / QLC modes, and the number of bits that can be stored in each minimum unit in different modes is different, usually the storage bit number of the minimum unit corresponding to SLC / MLC / TLC / QLC is 1bit / 2bit / 3bit / 4bit respectively. Therefore, in the case of a pre-erase operation on the memory, while sending the pre-erase instruction corresponding to the target pre-erase mode, the usage mode corresponding to the pre-erase operation is also sent, so that the memory performs the pre-erase operation in this usage mode. In other words, the host can specify the usage mode of the pre-erase VB.

[0095] As an implementation manner, in different usage modes, the prerequisites for the memory to respond to the pre-erase instruction and perform the pre-erase operation are different.

[0096] For example, if the VB usage mode specified by the host for this pre-erase operation is SLC (Single-Level Cell) mode, the prerequisite for the memory to respond to the pre-erase instruction is that the memory's write booster (WB) buffer is available. That is, when WB available buffer size! = 0, that is, the WB buffer is not empty, the SLC mode pre-erase operation issued by the host can be executed by the memory. If the memory's WB buffer is not available, then if the memory capacity is insufficient, the memory will return a failure message to the host, and the host will know through this failure message that this pre-erase operation cannot be successfully executed.

[0097] It is understood that SLC mode is a memory operation mode in UFS devices that uses a higher cell density (i.e., each storage cell stores one bit) to achieve greater capacity and provide faster data transfer speeds. In SLC mode, UFS devices typically have a dedicated WB (Write Booster) buffer. The WB buffer is typically a high-speed storage area used to temporarily store write data from the host system so that it can be written to the UFS device's storage medium in batches at the appropriate time.

[0098] When the host system needs to perform a write operation, the data is first written to the WB buffer of the UFS device. However, before performing an erase operation, the UFS device must ensure that all data in the WB buffer has been written to the storage medium to avoid data loss or inconsistency. Therefore, in SLC mode, the UFS device usually checks whether the WB buffer is empty before performing an erase operation. If the WB buffer still contains data to be written, the UFS device will first organize the data reasonably and write it to the memory in batches before performing the erase operation. Therefore, when the WB buffer is not empty, a failure message is returned and the host needs to send the pre-erase command again.

[0099] In addition, if the host specifies the usage mode for this pre-erase operation as TLC or QLC mode, the memory's response to the pre-erase instruction is conditional on the number of free physical blocks currently meeting a preset requirement. The preset requirement may be that the number of free physical blocks is greater than a first number, where the first number can be set based on actual usage requirements. If the number of free physical blocks is less than or equal to the first number, it indicates that the memory has insufficient free physical blocks. Therefore, if the memory determines that the number of free physical blocks currently is less than or equal to the first number, it returns a failure message to the host.

[0100] It should be noted that when the application currently running on the electronic device is not a specified application, this means that the current application scenario does not involve the writing of a large amount of data, that is, there is no large amount of sequential writing. This means that there may be an operation to write data at present, but the amount of data written is not large. It also means that the current scenario may be data writing or the data written is very small. Therefore, it is necessary to use the write rate to determine whether the amount of data written is not large. Therefore, as shown in Figure 8, S780 may include: S781 to S789.

[0101] S781: In the active mode, obtain the current write rate of the memory.

[0102] It should be noted that the current write rate is the write rate within the preset time length corresponding to the current moment, that is, the write rate can be the amount of data written to the memory within the preset time length corresponding to the current moment. Therefore, an implementation method for obtaining the current write rate of the memory can be to obtain the number of specified write commands sent to the memory within the preset time length corresponding to the current moment, and use the number as the write rate, wherein the specified write command is used to write a data block of a specified data size. For example, the specified data size is 512KB. Typically, for larger data write operations, the block layer of the operating system is usually cut to adapt it to the characteristics of the underlying storage device. In current storage devices, data read and write operations are performed in blocks, and the block size can be configured according to the specific storage device and file system. Common block sizes are 512KB, 1KB, 2KB, 4KB, etc. In the embodiment of the present application, the size of the data block is 512KB, so the specified write command is used to write a 512KB data block. Therefore, the number of data blocks written can measure the amount of data written within a period of time. Since the specified write command is used to write data blocks of a specified data size, the number of specified write commands can reflect the amount of data written. Therefore, the number of specified write commands sent to the memory within the preset time length corresponding to the current moment is used as the write rate. For example, if the preset time length is 100ms, the write rate is represented by the number n of 512KB chunksize write commands within 100ms, where chunksize refers to the parameter used to control the block size or buffer size of data write operations.

[0103] It can be understood that the preset time length corresponding to the current moment is the corresponding time period, which can be named the current time period. The time length of the current time period is the preset time length, and the end moment of the current time period is the current moment. Therefore, if the current moment changes, although the preset time length is the same, the current time period is still different.

[0104] S782: Obtain the current first specified threshold.

[0105] The first specified threshold is used to determine whether the active mode is required to trigger a pre-erase operation at the current write rate. The first specified threshold can be variable, and the method of varying it will be described later. Because the first specified threshold is variable, the current first specified threshold must be obtained before each determination of whether the write rate is greater than the current first specified threshold.

[0106] S783: Determine whether the write rate is greater than a current first specified threshold.

[0107] S784: Send the second erase instruction to the memory.

[0108] If the write rate is greater than the current first specified threshold, execute S784. If the write rate is less than or equal to the current first specified threshold, return to execute S781. Of course, you can also return to execute the step of determining the application program running on the host and subsequent steps.

[0109] It should be noted that the method of sending the second erase instruction to the memory can refer to the above description and will not be repeated here.

[0110] S785: Obtain response information returned by the memory in response to the second erase instruction currently sent.

[0111] In the embodiment of the present application, after the memory receives the first erase instruction or the second erase instruction, it will send a reply message to the host, and the reply message may include a failure message, a success message, a first message, and a second message. Among them, the failure message (fail) indicates that the memory cannot perform the pre-erase operation this time, such as the command requires the pre-erase VB of the SLC mode, but the WB buffer is 0, or there are insufficient empty blocks, etc. The implementation method of the memory sending the failure message (fail) can refer to the aforementioned embodiment and will not be repeated here. In the case that the memory successfully performs the pre-erase operation, it will send a success message (Success) to the host, and Success indicates that the pre-erase of the set capacity corresponding to the pre-erase operation has been completed. For example, the first erase instruction is used to instruct the memory to automatically erase the free physical blocks of the first capacity, that is, each pre-erase operation can obtain the pre-erase block of the first capacity; the second erase instruction is used to instruct the memory to obtain the pre-erase block of the second capacity, so after the memory successfully pre-erase the corresponding capacity, it will return a success message.

[0112] As an implementation method, when the host determines that the current write rate is greater than the current first specified threshold, the host sends a second erase instruction to the memory. After receiving the second erase instruction, the memory determines whether the current remaining capacity of the pre-erase space obtained by the last pre-erase operation is lower than the second specified threshold. If it is lower than the second specified threshold, the first information is returned; if it is greater than or equal to the second specified threshold, the second information is returned. When the first information or the second information is returned this time, the pre-erase operation is performed based on the second erase instruction. The last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time. The first information and the second information reflect the efficiency of issuing the second erase instruction this time.

[0113] It can be understood that the first information, "efficient," indicates that the current remaining capacity of the pre-erase space obtained from the previous pre-erase operation on the memory is less than a second specified threshold, and the second information, "inefficient," indicates that the current remaining capacity of the pre-erase space obtained from the previous pre-erase operation on the memory is greater than or equal to the second specified threshold. It can be seen that after receiving the first information, the host can determine that the capacity of the pre-erase space obtained from the previous pre-erase operation on the memory is insufficient, i.e., there is insufficient space available for writing data. Therefore, the host returns the first information to notify the host that the pre-erase blocks obtained from the current pre-erase operation are more efficiently utilized, i.e., the efficiency of issuing the second erase command is relatively high. Similarly, after receiving the second information, the host can determine that the capacity of the pre-erase space obtained from the previous pre-erase operation on the memory is still sufficient, i.e., there is still some space left unwritten. Therefore, the host returns the second information to notify the host that the pre-erase blocks obtained from the current pre-erase operation are less efficiently utilized, i.e., the efficiency of issuing the second erase command is relatively low.

[0114] S786: Determine whether the reply message is the first message or the second message.

[0115] S787: Increase the first specified threshold.

[0116] S788: Reduce the first specified threshold.

[0117] As mentioned above, the premise for sending the second erase instruction to the memory is to determine that the current mode is active and that the current write rate of the memory is greater than the current first specified threshold. Therefore, by changing the first specified threshold, the frequency of sending the second erase instruction to the memory can be adjusted, that is, the host can be helped to dynamically adjust the frequency of issuing pre-erase. It can be seen that if the first specified threshold is increased this time, then the next time when the write rate is used to determine whether to issue the second erase instruction, the write rate needs to be higher in order to meet the condition that the next write rate is greater than the first specified threshold used next time. In other words, the write operation needs to be more active in order to send the second erase instruction. To a certain extent, the frequency of issuing the second erase instruction can be reduced. Similarly, if the first specified threshold is lowered this time, then the next time when the write rate is used to determine whether to issue the second erase instruction, the write rate can be lowered in order to meet the condition that the next write rate is greater than the first specified threshold used next time. In other words, it is easier to trigger the sending of the second erase instruction, which can increase the frequency of issuing the second erase instruction.

[0118] Therefore, it is determined whether the reply information is the first information or the second information. If it is the first information, the first specified threshold is reduced; if it is the second information, the first specified threshold is increased.

[0119] S789: Waiting for the data of this pre-erase to be written.

[0120] After returning the first or second information, the memory performs a pre-erase operation and waits for data to be written to the pre-erase block. It should be noted that if the active mode has not ended, that is, if the application scenario is still the second scenario, the process returns to the step of obtaining the current write rate of the memory and subsequent steps. In other words, the write rate detection continues, and the first specified threshold used next time is the first specified threshold adjusted based on the first or second information.

[0121] As an implementation method, the first specified threshold has an initial value. When the current active mode ends or the next active mode begins, the first specified threshold will be initialized, that is, set to the initial value. In addition, the first specified threshold also has an upper limit value and a lower limit value, so that the first specified threshold will not increase or decrease blindly. Therefore, the implementation method of reducing the first specified threshold if the reply information is the first information is as follows: if the reply information is the first information, determine whether the current first specified threshold is less than or equal to the lower limit value; if it is less than or equal to the lower limit value, maintain the first specified threshold as the lower limit value; if it is greater than the lower limit value, reduce the first specified threshold. Similarly, if the reply information is the second information, the implementation method of increasing the first specified threshold may be as follows: if the reply information is the second information, determine whether the current first specified threshold is greater than or equal to the upper limit value; if it is greater than or equal to the upper limit value, maintain the first specified threshold as the upper limit value; if it is less than the upper limit value, increase the first specified threshold.

[0122] Therefore, in the first scenario, that is, when there are a large number of write operations, the automatic mode is used so that the memory can automatically perform the pre-erase operation in a timely manner based on the current idle physical state, avoiding the host's active triggering of the pre-erase operation in a delayed manner. In the absence of a large number of write operations, the active mode can be used to avoid the long-term existence of pre-erase blocks in the memory, which may lead to stability risks.

[0123] Therefore, by detecting the running designated application, it can be determined whether to enter the active mode or the automatic mode, so that in a scenario with a large amount of sequential writes, the pre-erase benefit of the write operation can be increased by using the automatic mode.

[0124] Please refer to FIG. 9 , which shows a structural block diagram of a memory management device 900 provided in an embodiment of the present application. The device may include: a determination unit 901 and an erasing unit 902 .

[0125] The determination unit 901 is used to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host.

[0126] Furthermore, the determining unit 901 is further configured to determine an application program currently running on the host; and determine a target pre-erase mode in the automatic mode and the active mode based on the application program currently running.

[0127] Furthermore, the determination unit 901 is also used to determine that if there is a specified application among the running applications, the application scenario in which the target pre-erase mode is the automatic mode host is the first scenario; if there is no specified application among the running applications, the application scenario in which the target pre-erase mode is the active mode host is the second scenario.

[0128] The erasing unit 903 is configured to perform a pre-erasing operation on the memory based on the target pre-erasing mode.

[0129] Furthermore, the erasing unit 903 is also used to send a first erasing instruction to the memory to trigger the memory to enter an automatic mode, wherein, in the automatic mode, the memory automatically performs a pre-erase operation on the free physical blocks in the memory to obtain a pre-erase space.

[0130] Furthermore, the erasing unit 903 is further configured to send a second erasing instruction to the memory in the active mode, instructing the memory to perform a pre-erasing operation on the free physical blocks in the memory to obtain a pre-erasing space.

[0131] Furthermore, the erasing unit 903 is further configured to obtain a current write rate of the memory in the active mode; and send the second erasing instruction to the memory if the write rate is greater than a current first specified threshold.

[0132] Furthermore, the erasing unit 903 is also used to obtain the number of specified write commands sent to the memory within a preset time length corresponding to the current moment, and use the number as the write rate, wherein the specified write command is used to write a data block of a specified data size.

[0133] Furthermore, the erasing unit 903 is also used to obtain the reply information returned by the memory for the second erase instruction currently sent after sending the erase instruction to the memory if the write rate is greater than the specified threshold; if the reply information is the first information, the first specified threshold is reduced, wherein the first information is used to indicate that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is lower than the second specified threshold, wherein the last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time; if the reply information is the second information, the first specified threshold is increased, wherein the second information is used to indicate that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is higher than or equal to the second specified threshold; if the application scenario is still the second scenario, return to execute the step of obtaining the current write rate of the memory and subsequent steps.

[0134] Furthermore, the erasing unit 903 is also used to obtain a pre-erase command corresponding to the target pre-erase mode; add the pre-erase command in a preset field of the specified instruction to be sent to the memory to obtain a target instruction; and send the target instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase command.

[0135] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0136] In several embodiments provided in this application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0137] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0138] Please refer to Figure 10, which shows a block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 1000 stores program code, which can be called by a processor to execute the method described in the above method embodiment.

[0139] The computer-readable medium 1000 can be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable medium 1000 includes a non-transitory computer-readable storage medium. The computer-readable medium 1000 has storage space for program code 1010 for executing any of the method steps described above. These program codes can be read from or written to one or more computer program products. The program code 1010 can be compressed, for example, in a suitable form.

[0140] In summary, the memory management method, device, storage system, and computer-readable medium provided in this application determine an application scenario of the storage system, and based on the application scenario, determine a target pre-erase mode for the memory from among multiple preset pre-erase modes; and perform a pre-erase operation on the memory based on the target pre-erase mode. Therefore, the pre-erase mode for the memory can be determined based on the current data writing status of the storage system, allowing the pre-erase operation of the memory to be combined with the application scenario of the storage system, thereby making the pre-erase operation more consistent with the current data writing requirements of the storage system and making the setting of the pre-erase operation more reasonable.

[0141] In addition, pre-erasing VB saves a lot of time in erasing VB during the sequential write process, improves the sequential write performance of the storage system, and reduces the delay spike (i.e., maximum delay) caused by erasing VB. The host and device are linked to each other and pre-erased on demand through scene recognition. While ensuring maximum benefits, the pre-erased blocks will not exist for a long time, which improves the stability risk of the existing solution. Solution 1 does not use independent commands, but uses the EHS field or reserved field of UPIU, which does not affect the user's performance.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, characterized in that: A host applied to a storage system, the storage system further comprising the storage, the host being connected to the storage, the method comprising: determining a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; A pre-erase operation is performed on the memory based on the target pre-erase pattern.

2. The method according to claim 1, characterized in that The determining of the target pre-erase mode in the automatic mode and the active mode comprises: determining an application program running on the host; A target pre-erase mode is determined in the automatic mode and the active mode based on the running application program.

3. The method according to claim 2, characterized in that The determining of the target pre-erase mode in the automatic mode and the active mode based on the running application program comprises: If there is a designated application in the running applications, determining that the target pre-erasure mode is the automatic mode; If the designated application does not exist in the running application programs, the target pre-erasing mode is determined to be the active mode.

4. The method according to claim 1, characterized in that: The determining of the target pre-erase mode in the automatic mode and the active mode comprises: Determining an application scenario of the storage system; A target pre-erasing mode is determined in the automatic mode and the active mode based on the application scenario.

5. The method according to claim 4, characterized in that The determining a target pre-erasure mode in the automatic mode and the active mode based on the application scenario includes: If the application scenario is the first scenario, determining that the target pre-erasing mode is the automatic mode; If the application scenario is the first scenario, the target pre-erasing mode is determined to be the active mode, wherein the data writing amount of the first scenario is greater than the data writing amount of the second scenario.

6. The method according to claim 1, characterized in that The target pre-erase mode is the automatic mode, and the performing a pre-erase operation on the memory based on the target pre-erase mode includes: A first erasing instruction is sent to the memory to trigger the memory to enter an automatic mode, wherein in the automatic mode, the memory automatically performs a pre-erasing operation on an idle physical block in the memory to obtain a pre-erasing space.

7. The method according to claim 1, characterized in that The target pre-erase mode is the active mode, and the performing a pre-erase operation on the memory based on the target pre-erase mode includes: In the active mode, a second erasing instruction is sent to the memory to instruct the memory to perform a pre-erasing operation on an idle physical block in the memory to obtain a pre-erasing space.

8. The method according to claim 7, characterized in that The sending a second erase instruction to the memory in the active mode comprises: In the active mode, obtaining a current write rate of the memory; If the write rate is greater than a current first specified threshold, the second erase instruction is sent to the memory.

9. The method according to claim 8, characterized in that The obtaining of the current write rate of the memory includes: The number of designated write commands sent to the memory within a preset time length corresponding to the current moment is obtained, and the number is used as the write rate, wherein the designated write command is used to write a data block of a designated data size.

10. The method according to claim 8, characterized in that If the write rate is greater than a specified threshold, after sending an erase instruction to the memory, the method further includes: Obtaining reply information returned by the memory in response to the second erase instruction currently sent; If the reply information is the first information, reducing the first specified threshold, wherein the first information is used to indicate that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is lower than the second specified threshold, wherein the last pre-erase operation refers to the pre-erase operation performed before the second erase instruction is received this time; If the reply information is second information, increasing the first specified threshold, wherein the second information is used to indicate that the current remaining capacity of the pre-erase space obtained by the last pre-erase operation of the memory is higher than or equal to the second specified threshold; If the active mode is not ended, return to execute the step of obtaining the current write rate of the memory and subsequent steps.

11. The method according to any one of claims 1 to 10, characterized in that: The performing a pre-erase operation on the memory based on the target pre-erase mode comprises: Obtaining a pre-erase command corresponding to the target pre-erase mode; Adding the pre-erase command in a preset field of a designated instruction to be sent to the memory to obtain a target instruction; The target instruction is sent to the memory to cause the memory to perform a pre-erase operation based on the pre-erase command.

12. The method according to claim 11, characterized in that The designated instruction to be sent to the memory is a write or read instruction that the host currently wants to send to the memory.

13. The method according to claim 12, characterized in that The designated instruction is a read or write instruction in a UFS protocol information unit, and the preset field is an additional header segment.

14. The method according to any one of claims 1 to 10, characterized in that: The performing a pre-erase operation on the memory based on the target pre-erase mode comprises: Obtaining a pre-erase command corresponding to the target pre-erase mode; The pre-erase command is generated into a pre-erase instruction based on the UPIU protocol; The pre-erase instruction is sent to the memory, so that the memory performs a pre-erase operation based on the pre-erase instruction.

15. The method according to any one of claims 1 to 10, characterized in that: The performing a pre-erase operation on the memory based on the target pre-erase mode comprises: Obtaining a pre-erase command corresponding to the target pre-erase mode; Adding the pre-erase command to a preset request; The preset request is sent to a memory, so that the memory performs a pre-erase operation based on the pre-erase command in the preset request.

16. The method according to claim 15, characterized in that The preset request includes a first request or a second request, wherein the first request is used to query the property and state of the memory, and the second request is used to manage and control the task execution of the memory.

17. The method according to any one of claims 1 to 16, characterized in that: The memory is a general flash memory.

18. A memory management device, characterized in that: A host applied to a storage system, the storage system further comprising the memory, the host being connected to the memory, the device comprising: a determining unit, configured to determine a target pre-erase mode in an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory, and in the active mode, the memory performs a pre-erase operation based on an instruction sent by the host; An erasing unit is used to perform a pre-erasing operation on the memory based on the target pre-erasing mode.

19. A storage system, characterized in that: include: Host; Memory; The host is connected to the memory, and the host is used to execute the method according to any one of claims 1-17.

20. A computer readable medium, characterized in that The computer-readable medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the method according to any one of claims 1 to 17.

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