Method and apparatus for use in high frequency ac power supplies

Abstract

A high frequency alternating current, HFAC, power supply system is disclosed herein. The HFAC power supply system comprises: at least two inverters configured to provide a redundancy in supply of HFAC power, wherein the at least two inverters are each coupled to provide an HFAC voltage to shared HFAC output supply connections; and a phase error controller configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference, the phase error controller comprising: a phase error detector configured to output a first intermediate signal based on the first input signal and a second intermediate signal based on the second input signal; and a differencing circuit configured to provide the phase control signal based on a difference between the first intermediate signal and the second intermediate signal; wherein the first input signal corresponds to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal corresponds to a timing of the HFAC voltage provided by a second one of the at least two inverters; wherein the phase control signal has a pulse width and a polarity, the pulse width corresponding to a magnitude of the phase difference and the polarity indicating a direction of the phase difference; the system further comprising a controller configured to control a pulse width modulation of the at least two inverters based on the phase control signal.

Description

[0001] Method and apparatus for use in high frequency AC power supplies

[0002] Field of Invention

[0003] The present invention relates to a phase error controller configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference, and to a high frequency alternating current (HFAC) power supply system comprising such a phase error controller.

[0004] Background

[0005] In high frequency alternating current (HFAC) power distribution systems, there can be difficulties in implementing redundancy for the purposes of power sharing. In a multi-inverter power distribution system, each inverter must continually adjust its own output voltage magnitude, output current magnitude, output phase and output frequency to equal the other inverters so that even power sharing is achieved. Failure to do so may result in one inverter powering the others, rather than all the inverters equally powering a load of the power distribution system. To achieve this function, there is a need for phase error control.

[0006] Phase error control for implementation of a multi-inverter high frequency power distribution system is typically performed using a multiplier circuit. However, in such circuits, the output control signal often has a highly non-linear gain response to phase error, and it also may not be clear whether one inverter is leading or lagging another. Such an approach may therefore be challenging to implement as part of a feedback control system.

[0007] Summary

[0008] Aspects of the disclosure are set out in the independent claims and optional features are set out in the dependent claims. Aspects of the disclosure may be provided in conj unction with each other and features of one aspect may be appl ied to other aspects .

[0009] An aspect of the di sclosure provides a high frequency alternating current , HFAC, power supply system compri sing : at least two inverters configured to provide a redundancy in supply of HFAC power, wherein the at least two inverters are each coupled to provide an HFAC voltage to shared HFAC output supply connections ; and a phase error control ler configured to detect a phase di fference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase di fference , the phase error controller compri sing : a phase error detector configured to output a fi rst intermediate signal based on the first input signal and a second intermediate signal based on the second input signal ; and a di fferencing circuit conf igured to provide the phase control signal based on a di f ference between the first intermediate signal and the second intermediate signal ; wherein the first input signal corresponds to a timing of the HFAC voltage provided by a fi rst one of the at least two inverters and the second input signal corresponds to a timing of the HFAC voltage provided by a second one of the at least two inverters ; wherein the phase control signal has a pul se width and a polarity, the pulse width corresponding to a magnitude of the phase dif ference and the polarity indicating a direction of the phase di fference ; the system further comprising a controller configured to control a pulse width modulation of the at least two inverters based on the phase control signal .

[0010] Additionally, the dif ferencing ci rcuit may comprise a first ampl ifier leg and a second ampli fier leg , the first and second ampl ifier legs arranged in a back-to-back configuration, wherein the first ampli fier leg i s configured to receive the first intermediate signal and output a first output signal , and the second amplifier leg is configured to receive the second intermediate signal and output a second output signal.

[0011] Additionally, the first amplifier leg may comprise at least one voltage controlled impedance, VCI, configured to be controlled by the first intermediate signal; and the second amplifier leg may comprise at least one VCI configured to be controlled by the second intermediate signal.

[0012] Additionally, the at least one VCI of the first amplifier leg may comprise two VCIs connected in series, the first output signal being output from a first node between the two VCIs of the first amplifier leg; and the at least one VCI of the second amplifier leg may comprise two VCIs connected in series, the second output signal being output from a second node between the two VCIs of the second amplifier leg.

[0013] Additionally, the phase control signal may comprise a bipolar waveform based on the first and second output signals.

[0014] Additionally, the phase control signal may comprise a differential phase control signal, the differential phase control signal corresponding to a difference between the first and second output signals .

[0015] Another aspect of the disclosure provides a phase error controller configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference, the phase error controller comprising: a phase error detector configured to output a first intermediate signal based on the first input signal and a second intermediate signal based on the second input signal; and a differencing circuit configured to provide the phase control signal based on a difference between the first intermediate signal and the second intermediate signal; wherein the phase control signal has a pulse width and a polarity, the pulse width corresponding to a magnitude of the phase difference and the polarity indicating a direction of the phase difference.

[0016] Additionally, the differencing circuit may comprise a first amplifier leg and a second amplifier leg, the first and second amplifier legs arranged in a back-to-back configuration, wherein the first amplifier leg is configured to receive the first intermediate signal and output a first output signal, and the second amplifier leg is configured to receive the second intermediate signal and output a second output signal.

[0017] Additionally, the first amplifier leg may comprise at least one voltage controlled impedance, VCI, configured to be controlled by the first intermediate signal; and the second amplifier leg may comprise at least one VCI configured to be controlled by the second intermediate signal.

[0018] Additionally, the at least one VCI of the first amplifier leg may comprise two VCIs connected in series, the first output signal being output from a first node between the two VCIs of the first amplifier leg; and the at least one VCI of the second amplifier leg may comprise two VCIs connected in series, the second output signal being output from a second node between the two VCIs of the second amplifier leg.

[0019] Additionally, the first and second nodes may be connected by a resistor.

[0020] Additionally, the two VCIs of the first amplifier leg may comprise a first complementary pair of transistors; and the two VCIs of the second amplifier leg may comprise a second complementary pair of transistors . Additionally, the transistors comprise any of: bipolar junction transistors, field effect transistors and insulated-gate bipolar transistors .

[0021] Additionally, the first amplifier leg may comprise a first biasing circuit configured to provide a DC bias to control connections of the two VCIs of the first amplifier leg to match a threshold voltage of the two VCIs of the first amplifier leg; and the second amplifier leg may comprise a second biasing circuit configured to provide a DC bias to control connections of the two VCIs of the second amplifier leg to match a threshold voltage of the two VCIs of the second amplifier leg.

[0022] Additionally, the first and second biasing circuits may be configured to reduce crossover distortions and are configured to match the threshold voltages of the VCIs so as to minimise switchon times of the VCIs.

[0023] Additionally, the first and second amplifier legs may each comprise a class AB amplifier.

[0024] Additionally, the differencing circuit may further comprise a differential amplifier configured to amplify a difference between the first and second output signals to provide the phase control signal .

[0025] Additionally, amplifying the difference between the first and second output signals to provide the phase control signal may comprise subtracting the second output signal from the first output signal and applying a gain.

[0026] Additionally, if the first input signal is leading the second input signal, the phase control signal may have a positive polarity; and if the first input signal is lagging the second input signal, the phase control signal may have a negative polarity.

[0027] Additionally, the phase error detector may be configured to compare the first input signal with the second input signal and generate an indication of the phase difference between the first and second input signals.

[0028] Additionally, the indication of the phase difference may comprise the first and second intermediate signals, wherein the first and second intermediate signals are synchronised.

[0029] Additionally, the phase error detector may comprise a first flip flop and a second flip flop.

[0030] Additionally, the first flip flop may comprise a first D flip-flop and the second flip flop may comprise a second D flip-flop.

[0031] Additionally, the first input signal may be configured as a clock signal of the first flip-flop and the second input signal may be configured as a clock signal of the second flip-flop, wherein both the first and second flip-flops share a common input and a common reset signal .

[0032] Additionally, the first flip-flop may be configured to output the value of the common input at every rising edge of the clock signal and to set the output to zero when the common reset signal is activated, the first intermediate signal comprising the output of the first flip-flop; and the second flip-flop may be configured to output the value of the common input at every rising edge of the clock signal and to set the output to zero when the common reset signal is activated, the second intermediate signal comprising the output of the second D flip-flop. Additionally, the phase control signal may have a linear relationship with the amount of phase difference between the first and second input signals.

[0033] Additionally, the phase error controller may further comprise a current gain amplifier circuit configured to enhance the phase control signal.

[0034] Additionally, the phase error controller may further comprise a low pass filter configured to remove high frequency AC voltage ripple from the phase control signal.

[0035] Another aspect of the disclosure provides a method of detecting and controlling phase error in an HFAC power supply system comprising at least two inverters configured to provide a redundancy in supply of HFAC power, wherein the at least two inverters are each coupled to provide an HFAC voltage to shared HFAC output supply connections, the method comprising: detecting, by a phase error controller, a phase difference between a first input signal and a second input signal; providing, by the phase error controller, a phase control signal based on the detected phase difference; wherein the first input signal corresponds to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal corresponds to a timing of the HFAC voltage provided by a second one of the at least two inverters; the phase control signal comprising a pulsed signal having a pulse width and a polarity, wherein the pulse width corresponds to a magnitude of the phase difference and the polarity indicates a direction of the phase difference; the method further comprising controlling, by a controller, a pulse width modulation of the at least two inverters based on the phase control signal.

[0036] Another aspect of the disclosure provides a method of detecting and controlling phase error by a phase error controller, the method comprising: detecting a phase difference between a first input signal and a second input signal; and providing a phase control signal based on the detected phase difference; the phase control signal comprising a pulsed signal having a pulse width and a polarity, wherein the pulse width corresponds to a magnitude of the phase difference and the polarity indicates a direction of the phase difference.

[0037] Brief Description of Drawings

[0038] Embodiments of the disclosure will now be described, by way of example only, with reference to the accompanying drawings.

[0039] Figure 1 shows a functional block diagram of a phase error controller .

[0040] Figure 2 shows a functional block diagram of the phase error detector from Figure 1.

[0041] Figure 3 shows a functional block diagram of the differencing circuit from Figure 1.

[0042] Figure 4 shows an electronic circuit diagram of the first and second amplifier legs from Figure 3.

[0043] Figure 5 shows a series of plots representing different signals that are fed into or output from various stages of the phase error controller from Figure 1.

[0044] Figure 6 shows a functional block diagram of a phase error controller .

[0045] Figures 7A-C show plots of phase control signal against phase error for different types of phase error controller. In the drawings like reference numerals are used to indicate like elements .

[0046] Specific Description

[0047] Figure 1 shows a functional block diagram of a phase error controller 100. The phase error controller 100 is configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference between the first input signal and the second input signal.

[0048] The phase error controller 100 comprises a phase error detector 101, into which the first input signal and the second input signal are fed. The first and second input signals may be unipolar square pulse waveforms, which may themselves be indicative of sinusoidal signals, or other types of waveform. For example, the first and second input signals may be zero crossing signals output by first and second zero crossing detectors respectfully. In such a case, the first zero crossing detector may receive a first sinusoidal signal (e.g. from an inverter) , detect zero crossings of the first sinusoidal signal and output a first zero crossing signal accordingly, which may then act as the first input signal of the phase error controller 100. Similarly, the second zero crossing detector may receive a second sinusoidal signal (e.g. from another inverter) , detect zero crossings of the second sinusoidal signal and output a second zero crossing signal accordingly, which may then act as the second input signal of the phase error controller 100.

[0049] Outputs of the phase error detector 101 may be a first intermediate signal and a second intermediate signal. The first and intermediate signals may be synchronised signals with the same frequency, but different pulse widths. The difference between the pulse widths may represent the phase difference between the first and second input signals.

[0050] The phase error detector 101 may be configured to receive the first and second input signals and generate an indication of the phase difference between the first and second input signals. In this way, the phase error detector 101 may comprise any detector suitable for performing such a function. For example, as will be described with reference to Figure 2, the phase error controller 100 may comprise a pair of flip flops configured to output the first and second intermediate signals.

[0051] The phase error controller 100 further comprises a differencing circuit 102, into which the first intermediate signal and the second intermediate signal are fed. The differencing circuit 102 is therefore connected to the phase error detector 101 in that the outputs of the phase error detector 101 act as inputs for the differencing circuit 102. A more detailed description of the differencing circuit 102 will be described with reference to Figures 3 and 4.

[0052] The differencing circuit is configured to provide a phase control signal, which may indicate a magnitude of any phase difference between the first input signal and the second input signal and a direction of any such phase difference (i.e. lead or lag) . The phase control signal may subsequently be used by other circuitry, such as a controller, which may then control a pulse width modulation of one or more inverters based on the phase control signal .

[0053] The phase control signal may have a pulse width and a polarity, the pulse width corresponding to the magnitude of the phase difference and the polarity indicating the direction of the phase difference. For example, if the first input signal is leading the second input signal, the phase control signal may have a positive polarity. If the first input signal is lagging the second input signal, the phase control signal may have a negative polarity.

[0054] In operation, the phase error detector 101 receives the first and second input signals and outputs the first and second intermediate signals. More specifically, the phase error detector 101 detects any phase difference between the first and second input signals and outputs an indication of this phase difference by way of the first and second intermediate signals - as mentioned, the difference in the pulse widths of the first and second intermediate signals represents the phase difference between the first and second input signals.

[0055] The differencing circuit 102 receives the indication of the phase difference in the form of the first and second intermediate signals and accordingly generates a phase control signal that indicates the magnitude and direction of the phase difference.

[0056] Figure 2 shows a functional block diagram of the phase error detector 101 from Figure 1. As mentioned, the phase error detector 101 may comprise a pair of flip flops. More specifically, the phase error detector 101 may comprise a first flip flop 201 configured to receive the first input signal and a second flip flop 202 configured to receive the second input signal. Both the first flip flop 201 and the second flip flop 202 may also be configured to receive a common input and a reset signal. The common input and the reset signal are the same for both the first flip flop 201 and the second flip flop 202.

[0057] The common input may be a simple signal of constant magnitude, and the reset signal may be a pulse waveform. The first flip flop 201 and the second flip flop 202 may comprise any suitable flip flop, although preferably, both the first flip flop 201 and the second flip flop 202 comprise D flip flops.

[0058] The first flip flop 201 may be configured to output the value of the common input at every rising edge of the first input signal and to reset every time the reset signal is activated (i.e. at every pulse of the reset signal) . Similarly, the second flip flop 202 may be configured to output the value of the common input at every rising edge of the second input signal and to reset every time the reset signal is activated (i.e. at every pulse of the reset signal ) .

[0059] In operation, the first flip flop 201 receives the first input signal, along with the common input set as logic high and the reset signal, with the first input signal functioning as a clock signal. At every rising edge of the clock signal, the output signal (i.e. the first intermediate signal) is set as the value of the common input at that time. At every activation of the common reset signal, the output signal is reset to zero, regardless of the value of the common input. The result of this is the first intermediate signal, which is a pulse waveform with the same frequency as the first input signal, but with a different pulse width.

[0060] The second flip flop 202 receives the second input signal, along with the common input set as logic high and the reset signal, with the second input signal functioning as a clock signal. At every rising edge of the clock signal, the output signal (i.e. the second intermediate signal) is set as the value of the common input at that time. At every activation of the common reset signal, the output signal is reset to zero, regardless of the value of the common input. The result of this is the second intermediate signal, which is a pulse waveform with the same frequency as the second input signal, but with a different pulse width. In this sense, the first and second intermediate signals are synchronised. Since both zero flip flops share a common input, the first and second intermediate signals may have the same amplitude and since both flip flops share a common reset signal, the first and second intermediate signals may have the same frequency. The differences between the two intermediate signals may be their pulse width and their phase.

[0061] The first and second intermediate signals are then fed into the differencing circuit 102, where they may be compared and the phase difference between them amplified so as to produce the phase control signal. The precise operation of the differencing circuit 102 will be described with respect to Figures 3 and 4.

[0062] Figure 3 shows a functional block diagram of the differencing circuit 102 from Figure 1. The differencing circuit 102 may comprise a first amplifier leg 301, into which the first intermediate signal is fed and from which a first output signal is output. The first amplifier leg 301 may comprise any suitable type of amplifier. For example, the first amplifier leg 301 may comprise a class AB amplifier.

[0063] The differencing circuit 102 may also comprise a second amplifier leg 302, into which the second intermediate signal is fed and from which a second output signal is output. The second amplifier leg 302 may comprise any suitable type of amplifier. For example, the second amplifier leg 302 may comprise a class AB amplifier. Preferably, the first amplifier leg 301 and the second amplifier leg 302 may comprise the same type of amplifier.

[0064] The first amplifier leg 301 and the second amplifier leg 303 may be connected such that they together form a full bridge amplifier circuit. This connection may be in the form of a resistor 303. The precise arrangements of the first amplifier leg 301 and the second amplifier leg 302 with respect to each other, as well as the elements which they comprise, wil be described in more detail with reference to Figure 4.

[0065] The differencing circuit 102 may further comprise a differential amplifier 304, into which the first output signal and the second output signal may be fed and from which the phase control signal may be fed. The differential amplifier 304 may comprise any conventional differential amplifier circuitry that is capable of amplifying a difference between two inputs.

[0066] The function of the first amplifier leg 301 and the second amplifier leg 302 may be to use electric power from a power supply to increase the amplitude of the first and second intermediate signals. Specifically, the first amplifier leg 301 and the second amplifier leg 302 may be configured to output first and second output signals that are based on the first and second intermediate signals.

[0067] Since the first amplifier leg 301 is connected to the second amplifier leg 302, the first output signal is based on both the first intermediate signal and the second crossing signal, and so is not simply an amplified version of the first intermediate signal. Similarly, the second output signal is based on both the first intermediate signal and the second intermediate signal, and so is not simply an amplified version of the second intermediate signal .

[0068] The function of the differential amplifier 304 may be to determine the difference between the first output signal and the second output signal and to output a phase control signal representative of this difference. More specifically, the differential amplifier 304 may be configured to apply a gain to this difference. In this sense, the phase control signal may comprise a differential phase control signal, the differential phase control signal corresponding to a difference between the first and second output signals.

[0069] In operation, the first amplifier leg 301 receives the first intermediate signal from the phase error detector 101 and the second amplifier leg 302 receives the second intermediate signal from the phase error detector 101. The first amplifier leg 301 and the second amplifier leg 302 work together to output a first output signal from the first amplifier leg 301 and a second output signal from the second amplifier leg 302. The nature of the first and second output signals depends on the first and second intermediate signals. The precise workings of the first amplifier leg 301 and the second amplifier leg 302 will be described in greater detail with reference to Figure 4.

[0070] The first and second output signals are then received by the differential amplifier 304, which determines the difference between the first and second output signals and amplifies this difference in the form of an outputted phase control signal. Specifically, the differential amplifier 304 may subtract the second output signal from the first output signal and apply a gain to the resulting difference, which may then be output in the form of the phase control signal.

[0071] Figure 4 shows an electronic circuit diagram of the first amplifier leg 301 and the second amplifier legs 302 from Figure 3. As mentioned, the first and second amplifier legs 301 and 302 may comprise any suitable type of amplifier. With reference now to the particular amplifier components, the first amplifier leg 301 may comprise at least one voltage controlled impedance (VCI) 401. Figure 4 shows the first amplifier leg 301 as comprising two VCIs 401, but it should be appreciated that only one VCI 401 may be present, or even more than two, depending on the type of amplifier. In the case where the first amplifier leg 301 comprises two VCIs 401, as in Figure 4, the first amplifier leg 301 may comprise a class AB amplifier.

[0072] The at least one VCI 401 may comprise at least one transistor. Any suitable type of transistor may be used, such as a bipolar junction transistor (BJT) , a field effect transistor (FET) (including MOSFET) , an insulated-gate bipolar transistor (IGPT) , or any other type .

[0073] Although different types of transistor have different terminology to describe their respective terminals, it should be appreciated that here, corresponding terms (such as gate / base, or source / collector , or drain / emitter ) are used interchangeably. The use of any one term that is typically associated with one type of transistor does not mean that another type of transistor utilising different terminology cannot be employed.

[0074] The two VCIs 401 may be connected in series and may comprise a first complementary pair of transistors. For example, if both VCIs 401 are BJTs, as shown in Figure 4, a first of the two VCIs 401 may be an NPN transistor and a second of the two VCIs 401 may be a PNP transistor. The emitter of the first of the two VCIs 401 may be connected to the emitter of the second of the two VCIs 401.

[0075] Each VCI 401 may have a threshold voltage, which is the minimum voltage required to turn the VCI 401 on and allow current to flow through the VCI 401. If the voltage applied to the gate / base of the VCI 401 is below this threshold, current may not flow. Although the term "threshold voltage" is traditionally associated with a field effect transistor, it should be appreciated that here, the term is intended to cover corresponding terms for other types of transistors, such as "turn on voltage" or the like. The first amplifier leg 301 may comprise a first node 403 located between the two VCIs 401, from which the first output signal may be output.

[0076] The first amplifier leg 301 may comprise a power supply. For example, the first amplifier leg 301 may comprise two voltage rails, with a first of the two voltage rails being a positive power supply Vdd and a second of the two voltage rails being a negative power supply Vss.

[0077] The first voltage rail may be connected to the collector of the first of the two VCIs 401 and the second voltage rail may be connected to the collector of the second of the two VCIs 401.

[0078] The first amplifier leg 301 may further comprise a first biasing circuit connected between the gates / bases of the two VCIs 401. The first biasing circuit may comprise a pair of diodes 405 connected in series. A first of the two diodes 405 may be connected to the first voltage rail and to the gate / base of the first of the two VCIs 401, whereas a second of the two diodes 405 may be connected to the gate / base of the second of the two VCIs 401 and to ground.

[0079] The first biasing circuit may further comprise a node between the two diodes 405, into which the first intermediate signal may be fed.

[0080] The first amplifier leg 301 may comprise a plurality of resistors 407. As can be seen in Figure 4, resistors 407 may be present between the first voltage rail and the first of the two VCIs 401, between the first voltage rail and the first of the two diodes 405, between the second of the two VCIs 401 and the second voltage rail, and between the second of the two diodes 405 and ground. A resistor 407 may also be present at the input of the first intermediate signal . The second amplifier leg 302 may comprise at least one voltage controlled impedance (VCI) 402. Figure 4 shows the second amplifier leg 302 as comprising two VCIs 402, but it should be appreciated that only one VCI 402 may be present, or even more than two, depending on the type of amplifier. In the case where the second amplifier leg 302 comprises two VCIs 402, as in Figure 4, the second amplifier leg 302 may comprise a class AB amplifier.

[0081] The at least one VCI 402 may comprise at least one transistor. Any suitable type of transistor may be used, such as a bipolar junction transistor (BJT) , a field effect transistor (FET) (including MOSFET) , an insulated-gate bipolar transistor (IGPT) , or any other type .

[0082] Although different types of transistor have different terminology to describe their respective terminals, it should be appreciated that here, corresponding terms (such as gate / base, or source / collector , or drain / emitter ) are used interchangeably. The use of any one term that is typically associated with one type of transistor does not mean that another type of transistor utilising different terminology cannot be employed.

[0083] The two VCIs 402 may be connected in series and may comprise a first complementary pair of transistors. For example, if both VCIs 402 are BJTs, as shown in Figure 4, a first of the two VCIs 402 may be an NPN transistor and a second of the two VCIs 402 may be a PNP transistor. The emitter of the first of the two VCIs 402 may be connected to the emitter of the second of the two VCIs 402.

[0084] Each VCI 402 may have a threshold voltage, which is the minimum voltage required to turn the VCI 402 on and allow current to flow through the VCI 402. If the voltage applied to the gate / base of the VCI 402 is below this threshold, current may not flow. Although the term "threshold voltage" is traditionally associated with a field effect transistor, it should be appreciated that here, the term is intended to cover corresponding terms for other types of transistors, such as "turn on voltage" or the like.

[0085] Preferably, the complementary pair of VCIs 402 of the second amplifier leg 302 is the same as the complementary pair of VCIs 401 of the first amplifier leg 301.

[0086] The second amplifier leg 302 may comprise a second node 404 located between the two VCIs 402, from which the second output signal may be output.

[0087] The second amplifier leg 302 may comprise a power supply. For example, the first amplifier leg 302 may comprise two voltage rails, with a first of the two voltage rails being a positive power supply Vdd and a second of the two voltage rails being a negative power supply Vss. As shown in Figure 4, the power supply of the second amplifier leg 302 may be the same power supply that is used to power the first amplifier leg 301.

[0088] The first voltage rail may be connected to the collector of the first of the two VCIs 402 and the second voltage rail may be connected to the collector of the second of the two VCIs 402.

[0089] The second amplifier leg 302 may further comprise a second biasing circuit connected between the gates / bases of the two VCIs 402. The second biasing circuit may comprise a pair of diodes 406 connected in series. A first of the two diodes 406 may be connected to the first voltage rail and to the gate / base of the first of the two VCIs 402, whereas a second of the two diodes 406 may be connected to the gate / base of the second of the two VCIs 402 and to ground. The second biasing circuit may further comprise a node between the two diodes 406, into which the second intermediate signal may be fed.

[0090] The second amplifier leg 302 may comprise a plurality of resistors 408. As can be seen in Figure 4, resistors 408 may be present between the first voltage rail and the first of the two VCIs 402, between the first voltage rail and the first of the two diodes 406, between the second of the two VCIs 402 and the second voltage rail, and between the second of the two diodes 406 and ground. A resistor 408 may also be present at the input of the second intermediate signal .

[0091] As described with reference to Figure 4, the first amplifier leg 301 and the second amplifier leg 302 may be connected by a resistor 303, thus allowing current to flow between the two amplifier legs. Specifically, the first node 403 and the second node 404 may be connected by the resistor 303, such that the resistor 303 connects the VCIs 401 of the first amplifier leg 301 with the VCIs 402 of the second amplifier leg 302.

[0092] The function of the at least one VCI 401 of the first amplifier leg 301 is to enable current to flow only under particular conditions (i.e. depending on the nature of the first intermediate signal) . Specifically, in the case where the at least one VCI 401 comprises two VCIs 401, as shown in Figure 4, one of the VCIs 401 is configured to only allow current to flow when the first intermediate signal is high, whereas the other VCI 401 is configured to only allow current to flow when the first intermediate signal is low.

[0093] Similarly, the function of the at least one VCI 402 of the second amplifier leg 302 is to enable current to flow only under particular conditions (i.e. depending on the nature of the second intermediate signal) . Specifically, in the case where the at least one VCI 402 comprises two VCIs 402, as shown in Figure 4, one of the VCIs 402 is configured to only allow current to flow when the second intermediate signal is high, whereas the other VCI 402 is configured to only allow current to flow when the second intermediate signal is low.

[0094] The function of the first biasing circuit (e.g. the pair of diodes 405) is to minimise the effects of crossover distortion. This is a common problem associated with conventional class B amplifiers, which routinely switch between transistors in use. The shape of the output waveform will have a region of zero voltage as it crosses over from one half of the waveform to the other. The reason for this is that there is a so-called "transition period" (which occurs as one transistor turns off and the other one turns on) . The small delay caused by this transition period results in both transistors being switched off for this short period of time producing a distorted waveform at the zero crossing point.

[0095] The first biasing circuit is configured to mitigate this effect by providing a DC bias to control connections of the two VCIs 401 to match the threshold voltage of the two VCIs 401. This means that each VCI 401 may conduct for more than half of the input cycle, thus avoiding the situation in which both VCIs 401 are off for a short period of time during crossover.

[0096] Similarly, the function of the second biasing circuit (e.g. the pair of diodes 406) is to minimise the effects of crossover distortion, which is described above.

[0097] The second biasing circuit is configured to mitigate this effect by providing a DC bias to control connections of the two VCIs 402 to match the threshold voltage of the two VCIs 402. This means that each VCI 402 may conduct for more than half of the input cycle, thus avoiding the situation in which both VCIs 402 are off for a short period of time during crossover.

[0098] In operation, the first amplifier leg 301 and the second amplifier leg 302 are powered by their power supplies (which as mentioned, are preferably the same power supply) . The first amplifier leg 301 receives the first intermediate signal, and the nature of the signal determines which of the two VCIs 401 will be turned on.

[0099] When the first intermediate signal is high, the first of the two VCIs 401 may turn on and the second of the two VCIs 401 may turn off (or remain off) . As previously mentioned, the first of the two VCIs 401 may be the VCI 401 closest to the Vdd power rail and the second of the two VCIs 401 may be the VCI 401 closest to the Vss power rail. When the first intermediate signal is low, the second of the two VCIs 401 may turn on and the first of the two VCIs 401 may turn off (or remain off) .

[0100] Similarly, when the second intermediate signal is high, the first of the two VCIs 402 may turn on and the second of the two VCIs 402 may turn off (or remain off) . As previously mentioned, the first of the two VCIs 402 may be the VCI 402 closest to the Vdd power rail and the second of the two VCIs 402 may be the VCI 401 closest to the Vss power rail. When the second intermediate signal is low, the second of the two VCIs 402 may turn on and the first of the two VCIs 402 may turn off (or remain off) .

[0101] As can be seen from Figure 4, this results in a number of different paths for current flow, depending on which VCIs 401 / 402 are on and which VCIs 401 / 402 are off. The outputs from the nodes 403 and 404 are therefore directly impacted by both the first intermediate signal and the second intermediate signal. If the first intermediate signal is high and the second intermediate signal is low, the first of the two VCIs 401 may turn on and the second of the VCIs 402 may turn on, with the other VCIs 401 / 402 turning or remaining off. This provides a current path through these two VCIs, and accordingly, the voltage will increase significantly at node 403. There will also be a small voltage rise at node 404.

[0102] If the first intermediate signal is low and the second intermediate signal is high, the first of the two VCIs 402 may turn on and the second of the VCIs 401 may turn on, with the other VCIs 401 / 402 turning or remaining off. This provides a current path through these two VCIs, and accordingly, the voltage will increase significantly at node 404. There will also be a small voltage rise at node 403.

[0103] If the first intermediate signal and the second intermediate signal are both high, the first of the two VCIs 401 may turn on and the first of the VCIs 402 may turn on, with the other VCIs 401 / 402 turning or remaining off. This means that there is no suitable path for current to flow between the two power supplies and accordingly the first output signal output from node 403 and the second output signal output from node 404 will be the same. Specifically, the voltage rise will be the same at both nodes 403 and 404, so the output voltage of both nodes 403 and 404 (and therefore the first and second output signals) will be the same.

[0104] If the first intermediate signal and the second intermediate signal are both low, the second of the two VCIs 401 may turn on and the second of the VCIs 402 may turn on, with the other VCIs 401 / 402 turning or remaining off. This means that there is no suitable path for current to flow between the two power supplies and accordingly the first output signal output from node 403 and the second output signal output from node 404 will be the same. Specifically, there will be no voltage rise at either node 403 and 404, so the output voltage of both nodes 403 and 404 (and therefore the first and second output signals) will be the same.

[0105] As switching occurs between the VCIs 401, the pair of diodes 405 of the first biasing circuit provide a small biasing voltage which causes both VCIs 401 to slightly conduct even if there is no input signal present. As mentioned, this causes a slight overlap in the conduction periods of the VCIs 401, meaning that crossover distortion is minimised.

[0106] Similarly, as switching occurs between the VCIs 402, the pair of diodes 406 of the second biasing circuit provide a small biasing voltage which causes both VCIs 402 to slightly conduct even if there is no input signal present. As mentioned, this causes a slight overlap in the conduction periods of the VCIs 402, meaning that crossover distortion is minimised.

[0107] The first and second intermediate signals therefore cause the VCIs 401 / 402 to switch repeatedly, thus resulting in first and second output signals being generated.

[0108] The first output signal and the second output signal are then both fed into the differential amplifier 304. The differential amplifier 304 determines the difference between the two output signals and applies a gain to this difference. For example, the differential amplifier 304 may subtract the second output signal from the first output signal and apply an appropriate gain. The resulting signal that is output is the phase control signal. The phase control signal may comprise a bipolar waveform based on the first and second output signals. Alternatively, the nodes 403 and 404 may be switched so that in the differential amplifier, the first output signal is subtracted from the second output signal, with an appropriate gain applied.

[0109] With reference to Figures 1-4, a method of detecting and controlling phase error by a phase error controller (such as phase controller 100) may comprise detecting a phase difference between a first input signal and a second input signal and providing a phase control signal based on the detected phase difference. As described, the phase control signal may comprise a pulsed signal having a pulse width and a polarity, wherein the pulse width corresponds to a magnitude of the phase difference and the polarity indicates a direction of the phase difference.

[0110] Figure 5 shows a series of plots 500 representing different signals that are fed into or output from various stages of the phase error controller 100. Specifically, the plots 500 represent the scenario in which the first input signal is leading the second input signal.

[0111] Plot 501 shows the first input signal and plot 502 shows the second input signal. As has been mentioned, the first input signal is leading the second input signal.

[0112] Plot 503 shows the first intermediate signal. Plot 504 shows the second intermediate signal

[0113] Plot 505 shows the first output signal (i.e. the signal output from the node 403 of the first amplifier leg 301) . Plot 506 shows the second output signal (i.e. from the node 404 of the second amplifier leg 302 ) .

[0114] Plot 507 shows the phase control signal output by the differential amplifier 304 of the differencing circuit 102. This phase control signal has not undergone any optional additional buffering or filtering, as will be described with reference to Figure 6.

[0115] As can be seen in Figure 5, the phase control signal 507 has a positive polarity because the first input signal 501 is leading the second input signal 502. If the first input signal 501 were to be lagging the second input signal 502, the phase control signal 507 would have a negative polarity, as has been described.

[0116] Figure 6 shows the phase error controller 100 of Figure 1, but comprising additional circuitry. For example, the phase error controller 100 may further comprise a current gain amplifier circuit 601 and a low pass filter circuit 602. Although Figure 6 shows the current gain amplifier circuit 601 and the low pass filter circuit 602 as being separate components to the phase error controller 100, it should be understood that the current gain amplifier circuit 601 and the low pass filter circuit 602 may constitute part of the phase error controller 100.

[0117] The current gain amplifier circuit 601 may be connected to the phase error controller 100. Specifically, an input of the current gain amplifier circuit 601 may be the phase control signal output by the differential amplifier 304 of the phase error controller 100, and an output of the current gain amplifier circuit 601 may be the phase control signal after the current has been amplified.

[0118] The current gain amplifier circuit 601 may comprise any suitable amplifier. For example, the current gain amplifier circuit 601 may comprise a class AB amplifier, and may be similar or substantially identical to the first amplifier leg 301 or the second amplifier leg 302. The current gain amplifier circuit 601 may therefore comprise at least one VCI . The low pass filter circuit 602 may be connected to the current gain amplifier circuit 601. Specifically, the phase control signal output by the current gain amplifier circuit 601 may be fed into the low pass filter 602, where it is low pass filtered. The phase control signal may then be output from the low pass filter 602.

[0119] The low pass filter 602 may be any suitable type of filter, such as an RC filter or a double RC filter.

[0120] The function of the current gain amplifier circuit 601 may be to enhance the phase control signal by increasing the magnitude of the current while keeping the voltage component unchanged. The function of the low pass filter 602 may be to pass signals with a frequency lower than a predetermined cutoff frequency and attenuate signals with frequencies above this cutoff frequency. More specifically, this means that the low pass filter 602 may be configured to remove any high frequency AC voltage ripple from the phase control signal.

[0121] In operation, the phase control signal is generated by the phase error controller 100, as has been described with respect to Figures 1-3. The phase control signal is then fed into the current gain amplifier circuit 601, where the magnitude of the current is amplified accordingly. The phase control signal is then fed into the low pass filter 602, where high frequency AC voltage ripple is removed from the phase control signal.

[0122] Figures 7A-C show plots of phase control signal against phase error for different types of phase error controller. Specifically, Figure 7A shows a plot 700 of the magnitude of the phase control signal (in mV) against phase error (in degrees) for a conventional multiplier-based phase error detector, whereas Figure 7B shows a plot 701 of the magnitude of the phase control signal (in mV) against phase error (in degrees) for the phase error controller 100 of the present application.

[0123] As can be seen from plot 700, the conventional multiplier approach of phase error detection and control results in a non-linear phase control signal - specifically, a parabolic curve. The plot 700 is symmetrical about the y-axis, meaning that different phase errors can produce the same phase control signal. Specifically, for a given phase error, both a lead and a lag of this magnitude will produce the same phase control signal. This means that implementing such a phase control signal as part of a practical linear feedback control system is difficult, since extra steps will be required in order to determine whether the phase difference constitutes a lead or a lag.

[0124] Plot 701, by contrast, is a linear plot, since the phase control signal has a linear relationship with the phase difference between the first and second input signals. This means that a lead of, say, 40 degrees will produce a different phase control signal to a lag of 40 degrees. From this relationship, it is therefore possible to determine both the magnitude and the direction of the phase error from the phase control signal, making it far easier to implement as part of a practical linear feedback control system.

[0125] It should be appreciated that the phase control signal voltage polarity may be flipped to suit the input interfacing needs of any feedback control system that the circuitry described above may form a part of. This can be seen in Figure 7C, which shows a plot 702 of the magnitude of the phase control signal (in mV) against phase error (in degrees) for the phase error controller 100 of the present application, but in which the phase control signal voltage polarity has been flipped. The phase error controller 100, as described with reference to any of the Figures, may form part of a high frequency alternating current (HFAC) power supply system. The HFAC power supply system comprises at least two inverters configured to provide a redundancy in supply of HFAC power and are each coupled to provide an HFAC voltage to shared HFAC output supply connections.

[0126] The HFAC power supply system also comprises a phase error controller, which as mentioned may correspond to the phase error controller 100 as described with reference to any of the Figures. The phase error controller may be configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference. As described earlier, the phase error controller may comprise a phase error detector 101) configured to output a first intermediate signal based on the first input signal and a second intermediate signal based on the second input signal. The phase error controller may further comprise a differencing circuit (such as differencing circuit 102) configured to provide the phase control signal based on a difference between the first intermediate signal and the second intermediate signal.

[0127] The first input signal may correspond to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal may correspond to a timing of the HFAC voltage provided by a second one of the at least two inverters.

[0128] As described earlier, the phase control signal may have a pulse width and a polarity, the pulse width corresponding to a magnitude of the phase difference and the polarity indicating a direction of the phase difference.

[0129] The system may also comprise a controller configured to control a pulse width modulation of the at least two inverters based on the phase control signal. This may help to keep the at least two inverters synchronised.

[0130] The system may be used in a method of detecting and controller phase error in a manner described with reference to the previous Figures .

[0131] Such a method may comprise detecting, by a phase error controller (such as phase error controller 100) , a phase difference between a first input signal and a second input signal. The method may further comprise providing, by the phase error controller, a phase control signal based on the detected phase difference. The first input signal may correspond to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal may correspond to a timing of the HFAC voltage provided by a second one of the at least two inverters. As described, the phase control signal may comprise a pulsed signal having a pulse width and a polarity, and the pulse width may correspond to a magnitude of the phase difference and the polarity may indicate a direction of the phase difference. The method may further comprise controlling, by a controller, a pulse width modulation of the at least two inverters based on the phase control signal.

[0132] Any feature of any one of the examples disclosed herein may be combined with any selected features of any of the other examples described herein. For example, features of methods may be implemented in suitably configured hardware, and the configuration of the specific hardware described herein may be employed in methods implemented using other hardware.

[0133] It will be appreciated from the discussion above that the embodiments shown in the Figures are merely exemplary, and include features which may be generalised, removed or replaced as described herein and as set out in the claims. With reference to the drawings in general , it will be appreciated that schematic functional block diagrams are used to indi cate functional ity of systems and apparatus described herein . It will be appreciated however that the functionality need not be divided in thi s way, and should not be taken to imply any particular structure of hardware other than that described and claimed below . The function of one or more of the elements shown in the drawings may be further subdivided, and / or di stributed throughout apparatus of the disclosure . In some embodiments the function of one or more element s shown in the drawings may be integrated into a single functional unit .

[0134] In some examples the functionality of the controller may be provided by a general purpose proces sor, which may be configured to perform a method according to any one o f those described herein . In some examples the controller may compri se digital logic , such as field programmable gate arrays , FPGA, application speci fic integrated circuits , ASIC , a digital signal processor , DSP , or by any other appropriate hardware . In some examples , one or more memory elements can store data and / or program instructions used to implement the operations described herein . Embodiments of the di sclosure provide tangible , non-transitory storage media compri sing program instructions operable to program a proce ssor to perform any one or more of the methods described and / or claimed herein and / or to provide data proces sing apparatus as described and / or claimed herein . The controller may compri se an analogue control circuit which provides at least a part of this control functionality . An embodiment provides an analogue control circuit conf igured to perform any one or more of the methods described herein .

[0135] The above embodiments are to be understood as illustrative examples . Further embodiments are envi saged . It i s to be understood that any feature described in relation to any one embodiment may be used alone , or in combination with other features des cribed, and may also be used in combination with one or more features of any other of the embodiment s , or any combination of any other of the embodiments . Furthermore , equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanying claims .

Claims

Claims1. A high frequency alternating current, HFAC, power supply system comprising: at least two inverters configured to provide a redundancy in supply of HFAC power, wherein the at least two inverters are each coupled to provide an HFAC voltage to shared HFAC output supply connections; and a phase error controller configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference, the phase error controller comprising: a phase error detector configured to output a first intermediate signal based on the first input signal and a second intermediate signal based on the second input signal; a differencing circuit configured to provide the phase control signal based on a difference between the first intermediate signal and the second intermediate signal; wherein the first input signal corresponds to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal corresponds to a timing of the HFAC voltage provided by a second one of the at least two inverters; wherein the phase control signal has a pulse width and a polarity, the pulse width corresponding to a magnitude of the phase difference and the polarity indicating a direction of the phase difference ; the system further comprising a controller configured to control a pulse width modulation of the at least two inverters based on the phase control signal.

2. The apparatus of claim 1, wherein the differencing circuit comprises a first amplifier leg and a second amplifier leg, the first and second amplifier legs arranged in a back-to-back configuration, wherein the first amplifier leg is configured toreceive the first intermediate signal and output a first output signal, and the second amplifier leg is configured to receive the second intermediate signal and output a second output signal.

3. The apparatus of claim 2, wherein: the first amplifier leg comprises at least one voltage controlled impedance, VCI, configured to be controlled by the first intermediate signal; and the second amplifier leg comprises at least one VCI configured to be controlled by the second intermediate signal.

4. The apparatus of claim 3, wherein: the at least one VCI of the first amplifier leg comprises two VCIs connected in series, the first output signal being output from a first node between the two VCIs of the first amplifier leg; and the at least one VCI of the second amplifier leg comprises two VCIs connected in series, the second output signal being output from a second node between the two VCIs of the second amplifier leg.

5. The apparatus of any of claims 2 to 4, wherein the phase control signal comprises a bipolar waveform based on the first and second output signals.

6. The apparatus of any of claims 2 to 5, wherein the phase control signal comprises a differential phase control signal, the differential phase control signal corresponding to a difference between the first and second output signals.

7. A phase error controller configured to detect a phase difference between a first input signal and a second input signal and to provide a phase control signal based on the detected phase difference, the phase error controller comprising:a phase error detector configured to output a first intermediate signal based on the first input signal and a second intermediate signal based on the second input signal; and a differencing circuit configured to provide the phase control signal based on a difference between the first intermediate signal and the second intermediate signal; wherein the phase control signal has a pulse width and a polarity, the pulse width corresponding to a magnitude of the phase difference and the polarity indicating a direction of the phase difference .

8. The apparatus of claim 7, wherein the differencing circuit comprises a first amplifier leg and a second amplifier leg, the first and second amplifier legs arranged in a back-to-back configuration, wherein the first amplifier leg is configured to receive the first intermediate signal and output a first output signal, and the second amplifier leg is configured to receive the second intermediate signal and output a second output signal.

9. The apparatus of claim 8, wherein: the first amplifier leg comprises at least one voltage controlled impedance, VCI, configured to be controlled by the first intermediate signal; and the second amplifier leg comprises at least one VCI configured to be controlled by the second intermediate signal.

10. The apparatus of claim 9, wherein: the at least one VCI of the first amplifier leg comprises two VCIs connected in series, the first output signal being output from a first node between the two VCIs of the first amplifier leg; and the at least one VCI of the second amplifier leg comprises two VCIs connected in series, the second output signal being output from a second node between the two VCIs of the second amplifier leg.

11. The apparatus of claim 10, wherein the first and second nodes are connected by a resistor.

12. The apparatus of claim 10 or 11, wherein: the two VCIs of the first amplifier leg comprises a first complementary pair of transistors; and the two VCIs of the second amplifier leg comprises a second complementary pair of transistors.

13. The apparatus of claim 12, wherein the transistors comprise any of: bipolar junction transistors, field effect transistors and insulated-gate bipolar transistors.

14. The apparatus of any of claims 10 to 13, wherein: the first amplifier leg comprises a first biasing circuit configured to provide a DC bias to control connections of the two VCIs of the first amplifier leg to match a threshold voltage of the two VCIs of the first amplifier leg; and the second amplifier leg comprises a second biasing circuit configured to provide a DC bias to control connections of the two VCIs of the second amplifier leg to match a threshold voltage of the two VCIs of the second amplifier leg.

15. The apparatus of claim 14, wherein the first and second biasing circuits are configured to reduce crossover distortions and are configured to match the threshold voltages of the VCIs so as to minimise switch-on times of the VCIs.

16. The apparatus of any of claims 8 to 15, wherein the first and second amplifier legs each comprise a class AB amplifier.

17. The apparatus of any of claims 8 to 16, wherein the differencing circuit further comprises a differential amplifier configured to amplify a difference between the first and second output signals to provide the phase control signal.

18. The apparatus of claim 17, wherein amplifying the difference between the first and second output signals to provide the phase control signal comprises subtracting the second output signal from the first output signal and applying a gain.

19. The apparatus of any of claims 7 to 18, wherein: if the first input signal is leading the second input signal, the phase control signal has a positive polarity; if the first input signal is lagging the second input signal, the phase control signal has a negative polarity.

20. The apparatus of any of claims 7 to 19, wherein the phase error detector is configured to compare the first input signal with the second input signal and generate an indication of the phase difference between the first and second input signals.

21. The apparatus of claim 20, wherein the indication of the phase difference comprises the first and second intermediate signals, wherein the first and second intermediate signals are synchronised.

22. The apparatus of any of claims 7 to 21, wherein the phase error detector comprises a first flip flop and a second flip flop.

23. The apparatus of claim 22, wherein the first flip comprises a first D flip-flop and the second flip flop comprises a second D flip-flop .

24. The apparatus of claim 23, wherein the first input signal is configured as a clock signal of the first flip-flop and the secondinput signal is configured as a clock signal of the second D flipflop, wherein both the first and second flip-flops share a common input and a common reset signal.

25. The apparatus of claim 24, wherein: the first flip-flop is configured to output the value of the common input at every rising edge of the clock signal and to set the output to zero when the common reset signal is activated, the first intermediate signal comprising the output of the first flipflop; and the second flip-flop is configured to output the value of the common input at every rising edge of the clock signal and to set the output to zero when the common reset signal is activated, the second intermediate signal comprising the output of the second flip-flop .

26. The apparatus of any preceding claim, wherein the phase control signal has a linear relationship with the phase difference between the first and second input signals.

27. The apparatus of any of claims 7 to 26, wherein the phase error controller further comprises a current gain amplifier circuit configured to enhance the phase control signal.

28. The apparatus of any of claims 7 to 27, wherein the phase error controller further comprises a low pass filter configured to remove high frequency AC voltage ripple from the phase control signal .

29. A method of detecting and controlling phase error in an HFAC power supply system comprising at least two inverters configured to provide a redundancy in supply of HFAC power, wherein the at least two inverters are each coupled to provide an HFAC voltage to shared HFAC output supply connections, the method comprising:detecting, by a phase error controller, a phase difference between a first input signal and a second input signal; providing, by the phase error controller, a phase control signal based on the detected phase difference; wherein the first input signal corresponds to a timing of the HFAC voltage provided by a first one of the at least two inverters and the second input signal corresponds to a timing of the HFAC voltage provided by a second one of the at least two inverters; the phase control signal comprising a pulsed signal having a pulse width and a polarity, wherein the pulse width corresponds to a magnitude of the phase difference and the polarity indicates a direction of the phase difference; the method further comprising controlling, by a controller, a pulse width modulation of the at least two inverters based on the phase control signal.

30. A method of detecting and controlling phase error by a phase error controller, the method comprising: detecting a phase difference between a first input signal and a second input signal; and providing a phase control signal based on the detected phase difference ; the phase control signal comprising a pulsed signal having a pulse width and a polarity, wherein the pulse width corresponds to a magnitude of the phase difference and the polarity indicates a direction of the phase difference.

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