Image sensor, imaging device, and image-sensor control method

Abstract

The present invention improves security in image sensors that carry out high-dynamic-range (HDR) rendering.　A vertical drive circuit drives, in row units, a plurality of effective pixels arrayed in a two-dimensional grid pattern within a pixel array section so as to output, in sequence, first and second effective pixel signals having different exposure times. A column signal processing unit reads out the first effective pixel signals within a first readout period and reads out the second effective pixel signals within a second readout period a portion of the duration of which overlaps the first readout period. A logic circuit carries out a predetermined self-diagnostic process within a predetermined period that does not correspond to any portion of the duration from the start of the first readout period to the end of the second readout period.

Description

Image sensor, imaging device, and method for controlling image sensor

[0001] The present technology relates to an image sensor, and more particularly to an image sensor that performs processing to expand a dynamic range, an imaging device, and a method for controlling the image sensor.

[0002] Conventionally, in order to expand the dynamic range, high-dynamic-range (HDR) compositing, which exposes pixels over multiple different exposure times and combines the read-out pixel signals, has been used in imaging devices and the like. When pixel signals are read row by row in this HDR compositing, a digital over lap (DOL) mode may be used in which a read-out period with a longer exposure time partially overlaps with a read-out period with a shorter exposure time. An image sensor has been proposed that performs a self-diagnosis process during a V-blank period in which no drive signal is supplied to the pixels during this DOL mode (see, for example, Patent Document 1).

[0003] JP 2018-125840 A

[0004] In the above-described conventional technology, a self-diagnosis process is performed during the V-blank period to detect a fault during imaging operation. However, in the above-described conventional technology, even if a fault occurs outside the V-blank period, the fault cannot be detected until the next V-blank period. This causes a delay in transmitting the diagnostic results from the image sensor to the outside, which may result in insufficient safety for the system including the image sensor.

[0005] This technology was developed in light of these circumstances, and aims to improve safety in image sensors that perform HDR synthesis.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof provides an image sensor and a control method thereof, the image sensor including: a vertical drive circuit that drives a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times; a column signal processing unit that reads out the first effective pixel signals within a first readout period and reads out the second effective pixel signals within a second readout period that partially overlaps with the first readout period; and a logic circuit that performs a predetermined self-diagnosis process within a predetermined period from the start of the first readout period to the end of the second readout period that does not fall within the partial period, thereby improving safety.

[0007] In this first aspect, the pixel array unit may further include a predetermined number of dummy pixels that output dummy pixel signals of a predetermined voltage, the column signal processing unit may sequentially read out the dummy pixel signals and one of the first and second effective pixel signals within the predetermined period, and the self-diagnosis processing may include processing for determining whether the dummy pixel signals are equal to an expected value, thereby providing an effect of detecting a fault in a vertical signal line or the like.

[0008] In addition, in this first aspect, the dummy pixels may include adjacent first and second dummy pixels, and the first and second dummy pixels may output first and second dummy pixel signals having different voltages, thereby providing an effect of detecting a short circuit between two adjacent columns.

[0009] In this first aspect, the column signal processing unit may include an analog-to-digital converter that converts each of the first and second effective pixel signals into a digital signal, a test pattern generation unit that generates a predetermined test pattern, a multiplexer that selects and outputs either the digital signal or the test pattern, and a latch unit that holds a signal from the multiplexer, and the self-diagnosis processing may include processing that determines whether the test pattern held in the latch unit is identical to the generated test pattern, thereby providing an effect that a failure of the latch unit or the like is detected.

[0010] In this first aspect, the latch unit may output the held signal in synchronization with a horizontal synchronization signal, and the column signal processing unit may further include a sense amplifier that amplifies the signal from the latch unit and supplies the amplified signal to the logic circuit, thereby providing an effect of detecting a failure of the sense amplifier.

[0011] In addition, in this first aspect, the logic circuit may include a first multiplexer that selects and outputs either a first digital signal or a predetermined test pattern, a second multiplexer that selects and outputs either a second digital signal or the test pattern, a first data path that processes the signal from the first multiplexer and outputs first processed data, a second data path that processes the signal from the second multiplexer and outputs second processed data, and a comparison unit that compares the first processed data with the second processed data, thereby providing the effect of detecting a fault in a circuit constituting the data path.

[0012] In addition, in the first aspect, the device may further include a temperature sensor that outputs a sensor voltage according to temperature, a selector that selects either a constant reference voltage or the sensor voltage and outputs the selected voltage as an output voltage, and an analog-to-digital converter that converts the voltage from the selector into a digital signal, and the self-diagnosis process may include a process of determining whether the digital signal corresponding to the reference voltage is an expected value, thereby providing the effect of detecting a failure in the temperature measurement unit.

[0013] In this first aspect, the pixel array unit may further include a predetermined number of identification pixels that output identification pixel signals indicating specific logical values, and the self-diagnosis process may include a process of determining whether a code obtained by arranging digital signals corresponding to the identification pixel signals in the row to be accessed is the identification code assigned to the row to be accessed, thereby providing the effect of detecting a failure in the drive line.

[0014] In this first aspect, the logic circuit may further include a self-diagnosis processing unit that performs the self-diagnosis processing within the predetermined period and outputs a diagnosis result, an image processing unit that generates RAW data by combining the first and second effective pixel signals, and a format processing unit that generates a frame including the RAW data, thereby producing an effect of capturing a frame.

[0015] In this first aspect, the format processing unit may generate the frame in which the diagnostic result is embedded, thereby providing an effect that the diagnostic result is output to the outside.

[0016] In addition, in this first aspect, the device may further include a first transmitter that transmits the frame and a second transmitter that transmits the diagnosis result, thereby providing an effect that the diagnosis result is output to the outside.

[0017] In addition, in the first aspect, a dedicated terminal for outputting the diagnostic result may be further provided, thereby providing an effect that the diagnostic result is output to the outside.

[0018] In addition, in this first aspect, the logic circuit may further perform the self-diagnosis process within a period from the end of the second read period to the start of the next first read period, thereby providing an effect of improving safety.

[0019] According to a second aspect of the present technology, there is provided an imaging device including: an image sensor including: a vertical drive circuit that drives a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times; a column signal processing unit that reads out the first effective pixel signals within a first readout period and reads out the second effective pixel signals within a second readout period that partially overlaps with the first readout period; and a logic circuit that performs a predetermined self-diagnosis process within a predetermined period from a start of the first readout period to an end of the second readout period that does not fall within the partial period; and a processing unit that processes a signal from the image sensor. This brings about an effect of improving safety of the imaging device.

[0020] 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology. FIG. 2 is a diagram showing a configuration example of a pixel array unit according to the first embodiment of the present technology. FIG. 3 is a block diagram showing a configuration example of a column signal processing unit according to the first embodiment of the present technology. FIG. 4 is a timing chart showing an example of an operation of an image sensor according to the first embodiment of the present technology. FIG. 5 is a diagram showing an example of a readout period and a shutter period according to the first embodiment of the present technology. FIG. 6 is a timing chart showing an example of an operation of an image sensor within a period from timing T1 to T3 according to the first embodiment of the present technology. FIG. 7 is a timing chart showing an example of an operation of an image sensor within a period from timing T3 to T5 according to the first embodiment of the present technology. FIG. 8 is a timing chart showing an example of an operation of an image sensor within a period from timing T5 to T7 according to the first embodiment of the present technology. FIG. 9 is a timing chart showing an example of an operation of an image sensor within a period from timing T7 to T9 according to the first embodiment of the present technology. FIG. 10 is a block diagram showing a configuration example of an image sensor according to the first embodiment of the present technology. FIG. 11 is a diagram showing an example of a frame format according to the first embodiment of the present technology. FIG. 12 is a diagram showing an example of output timing of BIST data in a comparative example. FIG. 13 is a diagram showing an example of output timing of BIST data according to the first embodiment of the present technology. FIG. 10 is a diagram showing an example of a timing chart when a frame rate is improved in the first embodiment of the present technology. FIG. 11 is a diagram showing an example of a timing chart when only long and short exposure times are set in the first embodiment of the present technology. FIG. 12 is a flowchart showing an example of an operation of an image sensor in the first embodiment of the present technology. FIG. 13 is a block diagram showing an example of a configuration of an imaging device in a first modified example of the first embodiment of the present technology. FIG. 14 is a block diagram showing an example of a configuration of an imaging device in a second modified example of the first embodiment of the present technology. FIG. 15 is a block diagram showing an example of a configuration of a column signal processing unit in the second embodiment of the present technology. FIG. 16 is a block diagram showing an example of a configuration of a latch unit in the second embodiment of the present technology. FIG. 17 is a timing chart showing an example of an operation of an image sensor in the second embodiment of the present technology. FIG. 18 is a block diagram showing an example of a configuration of a logic circuit in a third embodiment of the present technology.Fig. 10 is a block diagram showing an example configuration of an image sensor according to a fourth embodiment of the present technology. Fig. 11 is a block diagram showing an example configuration of a temperature measurement unit according to the fourth embodiment of the present technology. Fig. 12 is a block diagram showing an example configuration of a temperature measurement unit and a column signal processing unit according to the fourth embodiment of the present technology. Fig. 13 is a diagram showing an example configuration of a temperature measurement unit and a pixel array unit according to the fourth embodiment of the present technology. Fig. 14 is a diagram showing an example configuration of a pixel array unit according to a fifth embodiment of the present technology. Fig. 15 is a diagram summarizing diagnosable periods according to the first to fifth embodiments of the present technology. Fig. 16 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 17 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0021] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order: 1. First embodiment (an example of performing self-diagnosis processing within a period where readouts do not overlap) 2. Second embodiment (an example of detecting a fault in a latch unit or the like within a period where readouts do not overlap) 3. Third embodiment (an example of performing a data path test within a period where readouts do not overlap) 4. Fourth embodiment (an example of detecting a fault in a temperature measurement unit within a period where readouts do not overlap) 5. Fifth embodiment (an example of detecting a fault in a drive line and performing self-diagnosis processing within a period where readouts do not overlap) 6. Application example to a moving body

[0022] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to an embodiment of the present technology. The imaging device 100 is a device that captures image data (in other words, frames), and includes an image sensor 200 and an application processor 400.

[0023] The image sensor 200 includes a vertical drive circuit 211, a timing control unit 212, and a DAC (Digital to Analog Converter) 213. The image sensor 200 further includes a pixel array unit 214, a column signal processing unit 240, a horizontal transfer control unit 215, a logic circuit 260, and a transmission unit 291. The application processor 400 also includes a reception unit 410 and a processor 420.

[0024] In the pixel array section 214, a plurality of effective pixels 230 are arranged in a two-dimensional lattice pattern, and dummy pixels 220 are arranged for each column of the effective pixels 230.

[0025] The effective pixel 230 generates an effective pixel signal of a voltage corresponding to the amount of exposure light and outputs it to the column signal processing unit 240. The dummy pixel 220 has a DSF (Dummy Source Follower) circuit and generates a dummy pixel signal of a predetermined voltage regardless of the amount of exposure light and outputs it to the column signal processing unit 240.

[0026] The vertical drive circuit 211 drives the effective pixels 230 in the pixel array section 214 row by row to sequentially output a plurality of effective pixel signals with different exposure times. The pixel driving method will be described in detail later.

[0027] The timing control unit 212 synchronizes with the vertical synchronization signal XVS and controls the operation timing of the vertical drive circuit 211, the DAC 213, the column signal processing unit 240, the horizontal transfer control unit 215, and the logic circuit 260. For example, the timing control unit 212 generates a horizontal synchronization signal XHS by multiplying the vertical synchronization signal XVS, and uses the horizontal synchronization signal XHS to control the vertical drive circuit 211, etc.

[0028] The DAC 213 generates a sawtooth ramp signal by digital-to-analog conversion and supplies it to the column signal processing unit 240 .

[0029] The column signal processing unit 240 performs signal processing such as AD (Analog to Digital) conversion and CDS (Correlated Double Sampling) processing for each column on pixel signals from the pixel array unit 214. An ADC (Analog to Digital Converter) is arranged for each column in the column signal processing unit 240. The column signal processing unit 240 then supplies the processed digital signals to the logic circuit 260 under the control of the horizontal transfer control unit 215.

[0030] The horizontal transfer control unit 215 controls the output timing of the column signal processing unit 240 .

[0031] The logic circuit 260 performs various types of image processing on the digital signals from the column signal processing unit 240. The logic circuit 260 also performs self-diagnosis processing to detect whether or not there is a failure in the circuits within the image sensor 200. Details of the self-diagnosis processing will be described later. The logic circuit 260 supplies the frame after image processing to the transmission unit 291.

[0032] The transmitting unit 291 transmits frames to a receiving unit 410 in the application processor 400. Communication standards for the transmitting unit 291 and the receiving unit 410 include MIPI (Mobile Industry Processor Interface) and SLVS-EC (Scalable Low Voltage Signaling-Embedded Clock).

[0033] The receiving unit 410 receives frames and supplies them to the processor 420. The processor 420 performs various types of image processing on the frames, such as HDR processing and image recognition, which differ from the processing within the logic circuit 260.

[0034] 2 is a diagram showing an example of the configuration of the pixel array unit 214 according to the first embodiment of the present technology. As described above, a plurality of effective pixels 230 are arranged in a two-dimensional lattice, and dummy pixels 220 are arranged for each column of the effective pixels 230. Furthermore, within the pixel array unit 214, vertical signal lines VSL are wired along the column direction for each column.

[0035] The dummy pixel 220 includes an amplification transistor 221 and a selection transistor 222. For example, an nMOS (n-channel metal oxide semiconductor) is used as these transistors.

[0036] The amplifier transistor 221 and the select transistor 222 are connected in series between the power supply voltage and the vertical signal line VSL, with the amplifier transistor 221 acting as the power supply. A predetermined diagnostic voltage Vb1 is input to the gate of the amplifier transistor 221 from the vertical drive circuit 211. A drive signal SELd from the vertical drive circuit 211 is input to the gate of the select transistor 222. The diagnostic voltage Vb1 and the drive signal SELd are supplied via drive lines 215-1 and 216. These drive lines are arranged in the row direction.

[0037] With the above-described configuration, when the drive signal SELd is at a high level, the dummy pixel 220 outputs a dummy pixel signal Ain ｄ are supplied to the column signal processing unit 240 via the vertical signal line VSL.

[0038] A diagnostic voltage Vb1 is input to the dummy pixels 220 in odd-numbered columns, and a diagnostic voltage Vb2 is input to the dummy pixels 220 in even-numbered columns. The diagnostic voltage Vb1 is controlled to alternate between high and low levels, and the diagnostic voltage Vb2 is also controlled to alternate between high and low levels. However, the difference between the high and low levels of the diagnostic voltage Vb1 is a different value from the difference between the high and low levels of the diagnostic voltage Vb2. The diagnostic voltage Vb2 is supplied via a drive line 215-2 (not shown).

[0039] In the diagnostic process, the logic circuit 260 ｄ If the digital signal of a certain column is not the expected value, it is estimated that a break (in other words, a failure) has occurred in the vertical signal line VSL, or a failure has occurred in the ADC or latch unit 250 in that column.

[0040] Furthermore, the logic circuit 260 determines whether the digital signal corresponding to the dummy pixel signal in the nth column (n is an integer) and the digital signal corresponding to the dummy pixel signal in the n+1th column have different values. If these digital signals are identical, it is estimated that a short circuit has occurred between the nth column and the n+1th column.

[0041] Each effective pixel 230 includes a photoelectric conversion element 231, a transfer transistor 232, a reset transistor 233, a floating diffusion layer 234, an amplification transistor 235, and a selection transistor 236. The transistors in the effective pixel 230 are, for example, nMOS transistors.

[0042] The photoelectric conversion element 231 generates electric charges by photoelectric conversion of incident light. The transfer transistor 232 transfers electric charges from the photoelectric conversion element 231 to the floating diffusion layer 234 in accordance with a drive signal TRG from the vertical drive circuit 211. The reset transistor 233 initializes the floating diffusion layer 234 in accordance with a drive signal RST from the vertical drive circuit 211.

[0043] The floating diffusion layer 234 accumulates electric charges and generates a voltage according to the amount of accumulation. The amplification transistor 235 forms a source follower circuit and outputs a voltage according to the voltage of the floating diffusion layer 234 from its drain. The selection transistor 236 converts the analog signal of the voltage output from the amplification transistor 235 into an effective pixel signal Ain in accordance with a drive signal SELe from the vertical drive circuit 211. ｓ and outputs it to the vertical signal line VSL.

[0044] The drive signals RST, TRG, and SEL are transmitted via drive lines 217, 218, and 219. These drive lines are laid out in the row direction. ｄ or effective pixel signal Ain ｅ is transmitted as a pixel signal Ain through the vertical signal line VSL.

[0045] At the start of exposure, the vertical drive circuit 211 supplies high-level drive signals TRG and RST for a pulse period to initialize the effective pixels 230. This control is hereinafter referred to as "start of shutter."

[0046] Then, just before the end of exposure, the vertical drive circuit 211 supplies a high-level drive signal SEL and a high-level drive signal RST for a pulse period. ｅThe level of the effective pixel signal Ain at this time is called the reset level. Then, at the end of exposure, the vertical drive circuit 211 supplies a high-level drive signal SEL and a high-level drive signal TRG for a pulse period. ｅ The level of the signal is called the signal level.

[0047] The column signal processing unit 240 performs AD conversion on the reset level and the signal level in order, and performs CDS processing to obtain the difference between them. ｅ This is called "reading out."

[0048] Although the vertical drive circuit 211 controls the diagnostic voltages Vb1 and Vb2 to a high level and a low level, respectively, the present invention is not limited to this control. The vertical drive circuit 211 can also control the diagnostic voltages Vb1 and Vb2 to different constant voltages. In this case, the column signal processing unit 240 performs only AD conversion on the dummy pixel signals without performing CDS processing on them.

[0049] [Configuration Example of Column Signal Processing Unit] Fig. 3 is a block diagram showing a configuration example of the column signal processing unit 240 according to the first embodiment of the present technology. The column signal processing unit 240 includes a plurality of ADCs 241, a plurality of latch units 250, and a plurality of sense amplifiers 244. The ADCs 241 and the latch units 250 are arranged for each column. Furthermore, if the data size of the digital signal Dout corresponding to the pixel signal Ain is D bits (D is an integer), then D sense amplifiers 244 are arranged. In Fig. 3, only one of the D sense amplifiers 244 is shown, and the remaining sense amplifiers 244 are omitted.

[0050] The ADC 241 converts the pixel signal Ain of the corresponding column into a digital signal Dout. The ADC 241 includes a comparator 242 and a counter 243.

[0051] The comparator 242 compares the pixel signal Ain of the corresponding column with the ramp signal RMP from the DAC 213. The comparator 242 supplies the comparison result to the counter 243.

[0052] The counter 243 counts the count value over a period until the comparison result is inverted. For example, the counter 243 counts down when reading the reset level and counts up when reading the signal level. This realizes CDS processing. The counter 243 supplies a digital signal Dout indicating the count value to the latch unit 250.

[0053] Although the counter 243 performs both AD conversion and CDS processing, the present invention is not limited to this configuration. The counter 243 may perform only AD conversion, and a subsequent circuit may perform CDS processing.

[0054] As shown in the figure, an ADC made up of a comparator 242 and a counter 243 is called a single-slope ADC. Note that an ADC other than the single-slope ADC, such as a SAR ADC (Successive Approximation Register Analog to Digital Converter), can also be used.

[0055] The latch unit 250 synchronizes with the horizontal synchronization signal and holds the digital signal Dout at the end of the CDS process. The latch unit 250 supplies the held digital signal Dout to the sense amplifier 244 under the control of the horizontal transfer control unit 215.

[0056] The dth (d is an integer from 0 to D−1) sense amplifier 244 amplifies the dth bit of the digital signal Dout and supplies it to the logic circuit 260 .

[0057] If the digital signal of a certain column is not the expected value, it is estimated that a failure has occurred in that column in one of the vertical signal line VSL, the ADC 241, the latch unit 250, and the sense amplifier 244. Furthermore, if the digital signals of two adjacent columns are the same, it is estimated that a short circuit has occurred between the nth column and the (n+1)th column, or that a failure has occurred in the sense amplifier 244.

[0058] It is also possible to configure the circuit without inserting the sense amplifier 244 between the latch section 250 and the logic circuit 260 .

[0059] [Example of Operation of Image Sensor] Fig. 4 is a timing chart showing an example of operation of the image sensor 200 according to the first embodiment of the present technology. In the figure, the vertical axis indicates row addresses, and the horizontal axis indicates time. A plurality of different exposure times can be set in the image sensor 200. For example, three exposure times are set, with the longest exposure time being L, the second longest exposure time being M, and the shortest exposure time being S.

[0060] The vertical drive circuit 211 drives the rows in sequence and starts a shutter for exposure time L. This shutter is called a "long shutter." The long shutter for the first row starts at timing T0. Thin diagonal lines indicate the timing of the long shutter for each row.

[0061] The column signal processing unit 240 reads out effective pixel signals row by row from timing T1 at the end of the exposure time L of the first row to timing T5 at the end of the exposure time L of the last row. Furthermore, the vertical drive circuit 211 starts shuttering for an exposure time M for each read-out row. These readouts and shutterings are referred to as "long readout" and "middle shutter." The thick dotted diagonal lines indicate the timing of the long readout and middle shutter for each row.

[0062] The column signal processing unit 240 reads out effective pixel signals row by row from timing T2, when the exposure time M of the first row ends, to timing T6, when the exposure time M of the last row ends. The vertical drive circuit 211 also starts shuttering for an exposure time S for each read-out row. These readouts and shutters are referred to as "middle readout" and "short shutter." The dashed dotted lines indicate the timing of the middle readout and short shutter for each row.

[0063] The column signal processing unit 240 reads out effective pixel signals row by row from timing T3 at the end of the exposure time S of the first row to timing T7 at the end of the exposure time S of the last row. This readout is called "short readout." The thick diagonal lines indicate the timing of short readout for each row.

[0064] Moreover, from timing T4 to timing T8, the vertical drive circuit 211 drives the rows in order, and starts the long shutter.

[0065] Then, at timing T9 after T8, the column signal processing unit 240 performs long readout, and the vertical drive circuit 211 starts a middle shutter for each readout row. The period from timing T8 to T9 is a period during which no drive signal is supplied to each effective pixel, and is called a V blank period.

[0066] The period from timing T1 to T9 corresponds to the period of the vertical synchronization signal XVS, and this period is called a 1V period.

[0067] As shown in the figure, part of the long read period from timing T1 to timing T5 overlaps with the short read period from timing T3 to timing T7. The period from timing T3 to T5 corresponds to the overlapping period. In this way, a mode in which the read period with the longer exposure time (long read, etc.) and the read period with the shorter exposure time (short read, etc.) partially overlap is called a DOL mode.

[0068] 5 is a diagram showing an example of a readout period and a shutter period according to the first embodiment of the present technology, in which the vertical axis represents time.

[0069] As shown in the figure, long readout is performed row by row from timing T1 to timing T5, and a middle shutter is initiated. Middle readout is performed row by row from timing T2 to timing T6, and a short shutter is initiated. Short readout is performed row by row from timing T3 to timing T7. Long shutter is initiated row by row from timing T4 to timing T8. The period from timing T8 to timing T9 corresponds to a V blank period.

[0070] As shown in the figure, the period from timing T3 to T5 is a period in which the readout periods of the long readout, the medium readout, and the short readout overlap. Outside of this overlapping period, there is a period in which the ADC does not read valid pixel signals. Using this period, the logic circuit 260 performs a self-diagnosis process to detect faults in the vertical signal lines, etc. This realizes the built-in self-test (BIST) function of the image sensor 200.

[0071] Although the vertical drive circuit 211 starts the long shutter after timing T4 after the start of the short readout, the control is not limited to this. For example, the vertical drive circuit 211 can also start the long shutter during the short readout period from timing T3 to T7. In this case, the period after timing T7 becomes the V blank period.

[0072] As described in Patent Document 1, if the image sensor 200 performs self-diagnosis processing only during a V-blank period, even if a failure occurs outside the V-blank period, the detection of the failure must wait until the next V-blank period, which may delay the detection of the failure and reduce the safety of the system.

[0073] In contrast, under the control shown in the figure, the image sensor 200 performs self-diagnosis processing not only during the V-blank period but also during the period up to timing T3 and the period from timing T5 to T9. This allows the image sensor 200 to detect failures in real time, improving system safety. Furthermore, the application processor 400 can determine in real time whether or not there is a problem with the received frames.

[0074] Note that two of the readout periods of the long readout, the medium readout, and the short readout are examples of the first and second readout periods set forth in the claims. Also, the effective pixel signals read out during each of the two readout periods of the long readout, the medium readout, and the short readout are examples of the first and second effective pixel signals set forth in the claims. Also, the period from timing T1 to timing T3 and the period from timing T5 to T7 are examples of the predetermined period set forth in the claims.

[0075] Next, the operation of the image sensor 200 during the period from timing T1 to T9 in FIG. 5 will be described in detail with reference to FIGS.

[0076] 6 is a timing chart showing an example of the operation of the image sensor 200 during a period from timing T1 to T3 according to the first embodiment of the present technology. In the figure, "a" shows an example of the operation of the image sensor 200 during a period from timing T1 to T2, and "b" shows an example of the operation of the image sensor 200 during a period from timing T2 to T3.

[0077] As shown in a and b in the figure, the horizontal synchronization signal XHS falls at timings T1, t11, t12, t13, and so on.

[0078] As described above, in the DOL mode, there is a period in which the long readout, the middle readout, and the short readout overlap. Therefore, during this overlapping period, the column signal processing unit 240 performs the long readout in the 3h (h is an integer) cycle of the horizontal synchronization signal, the middle readout in the 3h+1 cycle, and the short readout in the 3h+2 cycle, for example.

[0079] During the period a in the figure, the column signal processing unit 240 performs long readout in the 3h cycle, and the vertical drive circuit 211 starts middle shuttering for the readout row in the 3h+1 cycle. "LRD" indicates long readout, and "MSH" indicates middle shuttering. For example, the column signal processing unit 240 performs long readout in the period from timing T1 to t11, and the vertical drive circuit 211 starts middle shuttering in the period from timing t11 to t12.

[0080] Here, during the 3h+1 and 3h+2 cycles (for example, from timing t11 to timing t13), no valid pixel signals are read out, and the ADC in the column signal processing unit 240 is free. Therefore, the column signal processing unit 240 reads out dummy pixel signals during this period. Also, during this period, the logic circuit 260 performs self-diagnosis processing based on the digital signal corresponding to the dummy pixel signal. "DRD" indicates reading out of the dummy pixel signal, and "T" indicates self-diagnosis processing.

[0081] Also, within the period b in the figure, the column signal processing unit 240 performs long readout in the 3h cycle and middle readout in the 3h+1 cycle. Then, the vertical drive circuit 211 starts middle shuttering in the 3h+1 cycle for rows where long readout has been performed, and starts short shuttering in the 3h+2 cycle for rows where middle readout has been performed. "MRD" indicates middle readout, and "SSH" indicates short shutter.

[0082] For example, the column signal processing unit 240 performs long readout during the period from timing T2 to t21, and middle readout during the period from timing t21 to t22. The vertical drive circuit 211 starts middle shuttering during the period from timing t21 to t22, and starts short shuttering during the period from timing t22 to t23.

[0083] During the 3h+2th cycle (for example, from timing t22 to timing t23), no valid pixel signals are read out, and the ADC in the column signal processing unit 240 is free. Therefore, the column signal processing unit 240 reads out dummy pixel signals during this period. Also, during this period, the logic circuit 260 performs self-diagnosis processing based on the digital signal corresponding to the dummy pixel signal.

[0084] 7 is a timing chart showing an example of the operation of the image sensor 200 during a period from timing T3 to T5 according to the first embodiment of the present technology. In the figure, "a" shows an example of the operation of the image sensor 200 during a period from timing T3 to T4, and "b" shows an example of the operation of the image sensor 200 during a period from timing T4 to T5.

[0085] During the period a in the figure, the column signal processing unit 240 performs long readout in the 3h cycle, middle readout in the 3h+1 cycle, and short readout in the 3h+2 cycle. "SRD" indicates short readout. The vertical drive circuit 211 then starts middle shuttering in the 3h+1 cycle for rows where long readout has been performed, and starts short shuttering in the 3h+2 cycle for rows where middle readout has been performed.

[0086] For example, the column signal processing unit 240 performs long readout during the period from timing T3 to t31, middle readout during the period from timing t31 to t32, and short readout during the period from timing t32 to t33. The vertical drive circuit 211 starts middle shuttering during the period from timing t31 to t32, and starts short shuttering during the period from timing t32 to t33.

[0087] During the period b in the figure, the column signal processing unit 240 performs long readout in the 3h cycle, middle readout in the 3h+1 cycle, and short readout in the 3h+2 cycle. The vertical drive circuit 211 then starts long shuttering in the 3h cycle for rows where short readout has been performed, and starts middle shuttering in the 3h+1 cycle for rows where long readout has been performed. The vertical drive circuit 211 also starts short shuttering in the 3h+2 cycle for rows where middle readout has been performed.

[0088] For example, the column signal processing unit 240 performs long readout during the period from timing T4 to t41, middle readout during the period from timing t41 to t42, and short readout during the period from timing t42 to t43. The vertical drive circuit 211 starts long shuttering during the period from timing T4 to t41, middle shuttering during the period from timing t41 to t42, and short shuttering during the period from timing t42 to t43.

[0089] In the periods a and b in the figure, the long read, the medium read, and the short read overlap, so there is no period when the ADC is free and the self-diagnosis process cannot be executed.

[0090] 8 is a timing chart showing an example of the operation of the image sensor 200 during a period from timing T5 to T7 according to the first embodiment of the present technology. In the figure, "a" shows an example of the operation of the image sensor 200 during a period from timing T5 to T6, and "b" shows an example of the operation of the image sensor 200 during a period from timing T6 to T7.

[0091] During the period a in the figure, the column signal processing unit 240 performs middle readout in the 3h+1th cycle and short readout in the 3h+2nd cycle. Then, the vertical drive circuit 211 starts long shuttering in the 3hth cycle for the rows where short readout was performed, and starts short shuttering in the 3h+2nd cycle for the rows where middle readout was performed.

[0092] For example, the column signal processing unit 240 performs middle readout during the period from timing t51 to t52, and performs short readout during the period from timing t52 to t53. The vertical drive circuit 211 starts long shuttering during the period from timing t5 to t51, and starts short shuttering during the period from timing t52 to t53.

[0093] During the 3hth cycle (for example, from timing T5 to timing t51), no valid pixel signals are read out, and the ADC in the column signal processing unit 240 is free. Therefore, the column signal processing unit 240 reads out dummy pixel signals during this period. Also, during this period, the logic circuit 260 performs self-diagnosis processing based on the digital signal corresponding to the dummy pixel signal.

[0094] Furthermore, within the period b in the figure, the column signal processing unit 240 performs short readout in the 3h+2 cycle, and the vertical drive circuit 211 starts long shuttering in the 3h cycle for the row where short readout was performed.

[0095] For example, the column signal processing unit 240 performs short readout during the period from timing t62 to t63, and the vertical drive circuit 211 starts long shuttering during the period from timing T6 to t61.

[0096] During the 3h and 3h+1 cycles (for example, from timing T6 to timing t62), no valid pixel signals are read out, and the ADC in the column signal processing unit 240 is free. Therefore, the column signal processing unit 240 reads out dummy pixel signals during this period. Also, during this period, the logic circuit 260 performs self-diagnosis processing based on the digital signal corresponding to the dummy pixel signal.

[0097] 9 is a timing chart showing an example of the operation of the image sensor 200 during a period from timing T7 to T9 according to the first embodiment of the present technology. In the figure, "a" shows an example of the operation of the image sensor 200 during a period from timing T7 to T8, and "b" shows an example of the operation of the image sensor 200 during a period from timing T8 to T9.

[0098] In addition, during the period a in the figure, the vertical drive circuit 211 starts the long shutter in the 3hth cycle for the row where the short readout was performed. For example, the vertical drive circuit 211 starts the long shutter in the period from timing T7 to t71.

[0099] In the V blank period b in the figure, no reading is performed and the shutter is not started.

[0100] During periods a and b in the figure, no valid pixel signals are read out over the entire period, and the ADC in the column signal processing unit 240 is free. Therefore, the column signal processing unit 240 reads out dummy pixel signals during this period. Also, during this period, the logic circuit 260 performs self-diagnosis processing based on the digital signal corresponding to the dummy pixel signal.

[0101] 10 is a block diagram showing an example of the configuration of the image sensor 200 according to the first embodiment of the present technology. The logic circuit 260 in the image sensor 200 includes a multiplexer 261, an image processing unit 270, a self-diagnosis processing unit 280, and a format processing unit 262.

[0102] As described above, the pixel array unit 214 has a plurality of effective pixels 230 arranged in a two-dimensional grid, and dummy pixels 220 arranged in columns. The vertical drive circuit 211 drives the effective pixels 230 in the pixel array unit row by row to sequentially output a plurality of effective pixel signals with different exposure times. The column signal processing unit 240 reads out these effective pixel signals and generates a digital signal Dout.

[0103] As described above, the period for reading out effective pixel signals with a longer exposure time (for example, long readout) and the period for reading out effective pixel signals with a shorter exposure time (for example, short readout) partially overlap.

[0104] If the ADC is free during a period in which readout does not overlap, the vertical drive circuit 211 drives the dummy pixel 220 to output a dummy pixel signal at a level corresponding to the diagnostic voltage. The column signal processing unit 240 reads out the dummy pixel signal and generates a digital signal Dout.

[0105] The multiplexer 261 switches the output destination of the digital signal Dout under the control of the timing control unit 212. When a valid pixel signal is read out, the multiplexer 261 supplies the digital signal Dout to the image processing unit 270. On the other hand, when a dummy pixel signal is read out, the multiplexer 261 supplies the digital signal Dout to the self-diagnosis processing unit 280.

[0106] The image processing unit 270 performs various image processing operations on the digital signal Dout corresponding to the effective pixel signal to generate RAW data. The RAW data is supplied to the format processing unit 262.

[0107] The self-diagnosis processing unit 280 performs self-diagnosis processing during periods when readout does not overlap, particularly during the periods from timing T1 to T3 and from timing T6 to T7 in FIG.

[0108] In the self-diagnosis process, it is determined for each column whether the digital signal Dout is equal to an expected value corresponding to the diagnostic voltage, and if the digital signal Dout is not equal to the expected value, a fault in the vertical signal line of that column is detected. Furthermore, if the digital signal Dout for the nth column is equal to the digital signal Dout for the (n+1)th column in the self-diagnosis process, a short circuit between the nth column and the (n+1)th column is detected.

[0109] The self-diagnosis processing unit 280 generates BIST data indicating the diagnosis results and supplies it to the format processing unit 262 .

[0110] The format processing unit 262 generates a frame containing RAW data and in which BIST data is embedded. The format processing unit 262 supplies the frame to the transmitting unit 291.

[0111] 11 is a diagram showing an example of a frame format in the first embodiment of the present technology. In the diagram, PH indicates a pixel header. FS indicates the start position of a frame. EBD indicates an embedded data area, and BIST data indicating a diagnostic result is stored in this area. EBD is provided both immediately after FS and immediately before FE, and BIST data can be stored in either area. FE indicates the end position of a frame.

[0112] Here, a configuration in which self-diagnosis is performed only during the V-blank period will be considered as a comparative example.

[0113] 12 is a diagram showing an example of the output timing of BIST data in a comparative example. For example, assume that a failure such as a break in a vertical signal line occurs between timing T5 at the end of a long read and timing T8 at the start of a V-blank period.

[0114] The image sensor of the comparative example generates RAW data by HDR synthesis after long readout, medium readout, and short readout, and outputs frame F1 including the RAW data. However, at this point, the self-diagnosis process is not executed, and therefore no BIST data is stored in frame F1.

[0115] The image sensor of the comparative example detects a failure by self-diagnosis processing within the V blank period from timing T8 to T9, and embeds BIST data in frame F2, which follows frame F1, and outputs the frame.

[0116] As illustrated in the figure, in the comparative example, even if a failure occurs during generation of frame F1, the output of BIST data notifying the failure is delayed until the next frame F2. This delay may result in insufficient safety of a system including image sensor 200. For example, when a car travels at 100 kilometers per hour, the car travels approximately 0.46 meters in 1 / 60 seconds. Therefore, when image sensor 200 is applied to a car system and used for obstacle recognition, if the period of vertical synchronization signal XVS is set to 1 / 60 seconds, a delay of one frame may cause adverse effects.

[0117] 13 is a diagram illustrating an example of output timing of BIST data according to the first embodiment of the present technology. As in the comparative example, it is assumed that a failure such as a break in a vertical signal line occurs between timing T5 at the end of a long read and timing T8 at the start of a V-blank period.

[0118] The image sensor 200 according to the first embodiment also performs self-diagnosis processing during the period from timing T5 to T8, so that the image sensor 200 can embed BIST data in the frame F1 and output it.

[0119] As shown in the figure, unlike the comparative example, the image sensor 200 of the first embodiment can detect and output the presence or absence of a fault in real time, except for the period when readouts overlap, thereby improving the safety of the system.

[0120] 14 is a diagram illustrating an example of a timing chart when the frame rate is improved according to the first embodiment of the present technology. In the comparative example, since the self-diagnosis is performed within the V-blank period, it is necessary to ensure a V-blank period that is longer than the time required for the self-diagnosis process.

[0121] In contrast, the image sensor 200 in the first embodiment performs self-diagnosis processing even outside the V-blank period, such as the period from timing T5 to T8. This allows the V-blank period to be reduced, as illustrated in the figure. For example, the image sensor 200 can start long readout and middle shutter at timing T9, immediately after timing T8, when the long shutter ends. This allows the period of the vertical synchronization signal XVS to be shortened (in other words, the frame rate to be improved).

[0122] In the first embodiment, three different exposure times are set, but four or more exposure times can also be set.

[0123] Furthermore, as shown in FIG. 15, two exposure times, a long one and a short one, can be set.

[0124] 16 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing an image of a frame is executed.

[0125] The image sensor 200 starts a long shutter and self-diagnosis process on a row-by-row basis (step S901). After the long shutter process for all rows is completed, the image sensor 200 starts a long readout and a middle shutter while continuing the self-diagnosis process (step S902). Then, the image sensor 200 starts a middle readout and a short shutter while continuing the self-diagnosis process (step S903).

[0126] Then, the image sensor 200 starts short readout and suspends the self-diagnosis process (step S904). The image sensor 200 determines whether long readout of all rows has been completed (step S905). If long readout of all rows has not been completed (step S905: No), the image sensor 200 returns to step S905.

[0127] If the long readout of all rows is completed (step S905: Yes), the image sensor 200 resumes the self-diagnosis process (step S906). The image sensor 200 determines whether the short readout of all rows is completed (step S907). If the short readout of all rows is not completed (step S907: No), the image sensor 200 returns to step S907.

[0128] When the short readout of all rows is completed (step S907: Yes), the image sensor 200 generates and outputs a frame in which the diagnosis result is embedded (step S908). After step S908, the image sensor 200 ends the operation for capturing the frame. When generating multiple frames in synchronization with the vertical synchronization signal, steps S901 to S908 are repeatedly executed in synchronization with the vertical synchronization signal.

[0129] Thus, according to the first embodiment of the present technology, the self-diagnosis processing unit 280 performs the self-diagnosis processing within a period that does not fall within an overlapping period of the readout period, thereby enabling faults to be detected in real time excluding the overlapping period, thereby improving safety.

[0130] [First Modification] In the first embodiment described above, the image sensor 200 transmits frames in which BIST data indicating the diagnostic results are embedded, but the BIST data and the frames can also be transmitted separately. The image sensor 200 in this first modification of the first embodiment differs from the first embodiment in that the image sensor 200 transmits the BIST data via a communication interface that is different from the transmission unit 291 that transmits the frames.

[0131] 17 is a block diagram showing an example configuration of an imaging device 100 according to a first modified example of the first embodiment of the present technology. The imaging device 100 according to the first modified example of the first embodiment differs from the first embodiment in that it further includes communication interfaces 292 and 430.

[0132] The communication interface 292 is arranged in the image sensor 200, and the communication interface 430 is arranged in the application processor 400. In addition, the logic circuit 260 in the first modification of the first embodiment does not embed BIST data in frames. The BIST data is supplied to the communication interface 292.

[0133] The communication interface 292 transmits the BIST data to the communication interface 430. For example, the I2C (Inter-Integrated Circuit) standard is used as the communication standard of the communication interfaces 292 and 430. The transmitting unit 291 and the communication interface 292 are examples of the first and second transmitting units set forth in the claims.

[0134] As shown in the figure, the BIST data can be transmitted in parallel with the transmission of RAW data by transmitting the BIST data via a communication interface 292 that is different from the transmission unit 291. This can further improve real-time performance.

[0135] In this way, according to the first modified example of the first embodiment of the present technology, the BIST data is transmitted by a communication interface 430 separate from the transmitting unit 291 that transmits the frames, thereby further improving real-time performance.

[0136] [Second Modification] In the first embodiment described above, the image sensor 200 transmits frames in which BIST data indicating the diagnostic results are embedded, but the BIST data and the frames can also be transmitted separately. The image sensor 200 in this second modification of the first embodiment differs from the first embodiment in that the BIST data is transmitted via a dedicated terminal.

[0137] 18 is a block diagram showing an example configuration of an imaging device 100 according to a second modified example of the first embodiment of the present technology. The imaging device 100 according to the second modified example of the first embodiment differs from the first embodiment in that it further includes dedicated terminals 293 and 440.

[0138] The dedicated terminal 293 is provided in the image sensor 200, and the dedicated terminal 440 is provided in the application processor 400. In addition, the logic circuit 260 in the second modified example of the first embodiment does not embed BIST data in frames. The BIST data is supplied to the dedicated terminal 293. The dedicated terminal 293 outputs the BIST data to the dedicated terminal 440.

[0139] As shown in the figure, the BIST data can be output in parallel with the transmission of RAW data by outputting the BIST data via a dedicated terminal 293 that is different from the transmission unit 291. This further improves real-time performance.

[0140] As described above, according to the second modification of the first embodiment of the present technology, the dedicated terminal 293 separate from the transmitting unit 291 outputs the BIST data, thereby further improving the real-time performance.

[0141] 2. Second Embodiment In the first embodiment described above, the logic circuit 260 detects failures in the vertical signal lines, the ADC 241, the latch unit 250, and the sense amplifier 244 based on dummy pixel signals, but this configuration may not be able to identify the location of the failure. For example, the logic circuit 260 may not be able to determine whether the failure is in the ADC 241 or the latch unit 250. The image sensor 200 in this second embodiment differs from the first embodiment in that a test pattern is held in the latch unit 250 and a self-diagnosis process is performed.

[0142] 19 is a block diagram showing an example of a configuration of a column signal processing unit 240 according to a second embodiment of the present technology. The column signal processing unit 240 according to the second embodiment differs from the first embodiment in that it further includes a test pattern generation unit 245 and a plurality of multiplexers 246. The multiplexers 246 are arranged for each column.

[0143] The test pattern generating unit 245 generates a predetermined test pattern and supplies it to each of the multiplexers 246. The data size of the test pattern is assumed to be the same as the digital signal Dout of each column.

[0144] The multiplexer 246 selects either the digital signal Dout of the corresponding column or the test pattern under the control of the timing control section 212 and outputs the selected signal to the latch section 250 .

[0145] 20 is a block diagram showing an example configuration of the latch unit 250 according to the second embodiment of the present technology. The latch unit 250 includes D latch circuits 251. The dth latch circuit 251 holds the dth bit of the signal from the multiplexer 246. The dth latch circuit outputs the held bit to the dth sense amplifier 244 under the control of the horizontal transfer control unit 215.

[0146] The test pattern generator 245 also sequentially supplies a pair of test patterns, one of which is the bit-by-bit inversion of the other, with the logical values ​​of odd-numbered bits (e.g., "1") being different from the logical values ​​of even-numbered bits (e.g., "0").

[0147] FIG. 21 is a timing chart showing an example of the operation of the image sensor 200 according to the second embodiment of the present technology.

[0148] The column signal processing unit 240 either reads out dummy pixel signals or latches a test pattern during a period when the ADC is idle. These operations cannot be performed simultaneously. For example, the column signal processing unit 240 reads out dummy pixel signals during the period from timing t11 to t13. Also, the column signal processing unit 240 causes the latch unit 250 to hold the test pattern during the period from timing t11 to t13.

[0149] The logic circuit 260 detects a failure in a vertical signal line or the like based on a digital signal corresponding to the dummy pixel signal. The logic circuit 260 also determines whether the test pattern held in the latch unit 250 is identical to the generated test pattern. If they are not identical, a failure in the latch unit 250 or the sense amplifier 244 is detected. If the dth bit and the d+1th bit are identical, a short circuit between the dth bit and the d+th bit is detected. If the dth bit before inversion and the dth bit after inversion are identical, a failure in the latch circuit 251 for the dth bit or the sense amplifier 244 is detected.

[0150] The logic circuit 260 can identify the location of the failure based on the dummy pixel signal and the test pattern. For example, assume that the stored test pattern is the same as the generated one, and the digital signal corresponding to the dummy pixel signal is not the expected value corresponding to the diagnostic voltage. In this case, the logic circuit 260 can determine that there is no failure in the latch unit 250 or the sense amplifier 244, but that a failure has occurred in the vertical signal line or the ADC.

[0151] The first and second modifications of the first embodiment can be applied to the second embodiment.

[0152] As described above, according to the second embodiment of the present technology, the logic circuit 260 detects a failure in the latch unit 250 and the like in addition to a failure in the VSL and the like, and therefore can identify the location of the failure.

[0153] 3. Third Embodiment In the above-described first embodiment, the logic circuit 260 detects failures in vertical signal lines and the like based on dummy pixel signals, but this configuration makes it impossible to detect failures in circuits within the logic circuit 260. The image sensor 200 in this third embodiment differs from the first embodiment in that it performs a data path test.

[0154] 22 is a block diagram showing a configuration example of a logic circuit 260 according to the third embodiment of the present technology. In the logic circuit 260 according to the third embodiment, an image processing unit 270 includes multiplexers 271 and 272, data paths 273 and 274, demultiplexers 275 and 276, and a RAW data generation unit 277. Furthermore, a self-diagnosis processing unit 280 includes a test pattern generation unit 281, a comparison unit 282, and a BIST data generation unit 283.

[0155] The test pattern generation unit 281 generates a predetermined test pattern and supplies it to the multiplexers 271 and 272. The data size of this test pattern is the same as that of the digital signal Dout from the column signal processing unit 240.

[0156] The multiplexer 271 receives the digital signal Dout1 from the column signal processing unit 240 and the test pattern. The multiplexer 271 selects either the digital signal Dout1 or the test pattern in accordance with a control signal SWa from the timing control unit 212, and supplies the selected signal to the data path 273.

[0157] The multiplexer 272 receives the digital signal Dout2 from the column signal processing unit 240 and a test pattern. The multiplexer 272 selects either the digital signal Dout2 or the test pattern in accordance with the control signal SWa and supplies the selected signal to the data path 274. The digital signals Dout1 and Dout2 are examples of the first and second digital signals set forth in the claims.

[0158] The data path 273 processes the signal from the multiplexer 271 and outputs processed data Pout1 to the demultiplexer 275. The data path 274 processes the signal from the multiplexer 272 and outputs processed data Pout2 to the demultiplexer 276. The processed data Pout1 and Pout2 are examples of the first and second processed data set forth in the claims.

[0159] The demultiplexer 275 selects either the raw data generating section 277 or the comparing section 282 as an output destination in accordance with a control signal SWb from the timing control section 212, and outputs the processed data Pout1 to that output destination.

[0160] The demultiplexer 276 selects either the raw data generating section 277 or the comparing section 282 as an output destination in accordance with the control signal SWb, and outputs the processed data Pout2 to that output destination.

[0161] The RAW data generation unit 277 generates RAW data by performing various processes such as synthesis on the processed data from the demultiplexers 275 and 276. The RAW data generation unit 277 supplies the RAW data to the format processing unit 262.

[0162] The comparison unit 282 compares the processed data Pout1 and Pout2 and supplies the comparison result to the BIST data generation unit 283. If these processed data do not match, a fault in the circuit that constitutes the data path 273 or 274 is detected.

[0163] The BIST data generating unit 283 generates BIST data including the comparison result and supplies it to the format processing unit 262 .

[0164] The timing control section 212 causes the multiplexers 271 and 272 to select the test pattern and the demultiplexers 275 and 276 to select the comparison section 282 during a period in which the ADC is not reading out valid pixel signals.

[0165] It is also possible to provide three or more data paths in the logic circuit 260 and have the self-diagnosis processing unit 280 test them.

[0166] Furthermore, in addition to testing the data paths, the logic circuit 260 can detect faults in vertical signal lines and the like based on dummy pixel signals. In this case, the self-diagnosis processing unit 280 can perform the data path test and the detection of faults in vertical signal lines and the like in parallel. The self-diagnosis processing unit 280 can also perform only the data path test without detecting faults in vertical signal lines and the like.

[0167] Moreover, the first and second modifications of the first embodiment and the second embodiment can be applied to the third embodiment.

[0168] In this way, according to the third embodiment of the present technology, the logic circuit 260 performs a data path test, and therefore, a failure in the circuit within the logic circuit 260 can be detected.

[0169] 4. Fourth Embodiment In the first embodiment described above, the logic circuit 260 detects failures in the vertical signal lines and the like based on dummy pixel signals, but if the image sensor 200 performs temperature measurement, it can also detect failures in the circuits used for that purpose. The image sensor 200 in this fourth embodiment differs from the first embodiment in that it also detects failures in the temperature measurement units.

[0170] 23 is a block diagram showing an example configuration of an image sensor 200 according to a fourth embodiment of the present technology. The image sensor 200 according to the fourth embodiment differs from the image sensor 200 according to the first embodiment in that it further includes a voltage generating unit 300 and a temperature measuring unit 310.

[0171] The voltage generating unit 300 generates a constant reference voltage that is independent of temperature and supplies it to the temperature measuring unit 310. Details of the temperature measuring unit 310 will be described later. A BGR (Band Gap Reference) circuit or the like is used as the voltage generating unit 300.

[0172] 24 is a block diagram showing an example of the configuration of the temperature measurement unit 310 according to the fourth embodiment of the present technology. The temperature measurement unit 310 includes a temperature sensor 311, a selector 312, and an ADC 313.

[0173] The temperature sensor 311 outputs a sensor voltage V ｔｅｍｐ and supplies it to the selector 312. The temperature sensor 311 may be a thermistor or a resistance temperature detector.

[0174] The selector 312 selects the reference voltage V from the voltage generating section 300 under the control of the timing control section 212. ｒｅｆ and the sensor voltage V from the temperature sensor 311 ｔｅｍｐ and outputs it to the ADC 313.

[0175] The ADC 313 converts the voltage from the selector 312 into a digital signal and supplies it to the self-diagnosis processing unit 280 .

[0176] The timing control unit 212 controls the selector 312 to select the reference voltage V ｒｅｆ Select the desired option.

[0177] The self-diagnosis processing unit 280 is configured such that the selector 312 selects the sensor voltage V ｔｅｍｐDuring the period when the temperature measurement unit 310 is selected, the digital signal from the temperature measurement unit 310 is supplied as is to the format processing unit 262. This digital signal is embedded in a frame and output to the outside. Note that the image sensor 200 can also output the digital signal to the outside via a communication interface different from the frame.

[0178] Also, the selector 312 selects the reference voltage V ｒｅｆ During the period when the temperature measurement unit 310 is selected, the self-diagnosis processing unit 280 detects that the digital signal from the temperature measurement unit 310 is equal to or exceeds the reference voltage V ｒｅｆ If the digital signal is not the expected value, a failure of the temperature measurement unit 310 is detected. The self-diagnosis processing unit 280 generates BIST data including the diagnosis result of the temperature measurement unit 310 and supplies it to the format processing unit 262.

[0179] The self-diagnosis processing unit 280 can detect failures in vertical signal lines, etc., based on dummy pixel signals, in addition to detecting failures in the temperature measurement unit 310. In this case, the self-diagnosis processing unit 280 can detect failures in vertical signal lines, etc., and failures in the temperature measurement unit 310 in parallel. The self-diagnosis processing unit 280 can also detect failures in the temperature measurement unit 310 only, without detecting failures in vertical signal lines, etc.

[0180] Furthermore, although the ADC 313 for temperature measurement and the ADC 241 for each column for readout are arranged separately, the present invention is not limited to this configuration.

[0181] As illustrated in FIGS. 25 and 26 , a portion of the ADC 241 can be shared by the temperature measurement unit 310 and the column signal processing unit 240. In this case, the ADC 313 is eliminated. In the example of FIG. 25 , a selector 247 is added to the column signal processing unit 240, which selects either the vertical signal line or the voltage from the selector 312 under the control of the timing control unit 212 and outputs the signal to the ADC 241. In the example of FIG. 26 , a selector 247 is added to the pixel array unit, which selects either the drive signal from the drive line 216 or the voltage from the selector 312 and supplies the signal to the gate of the amplification transistor 222. In FIG. 26 , the selector 227 can also be disposed in a stage preceding the amplification transistor 236.

[0182] Moreover, the first and second modifications of the first embodiment, the second embodiment, and the third embodiment can be applied to the fourth embodiment.

[0183] As described above, according to the fourth embodiment of the present technology, the self-diagnosis processing unit 280 detects whether or not there is a malfunction in the temperature measurement unit 310, thereby improving safety when performing temperature measurement.

[0184] 5. Fifth Embodiment In the first embodiment described above, the logic circuit 260 detects failures in vertical signal lines, etc., based on dummy pixel signals, but this configuration does not allow detection of breaks in drive lines that transmit pixel drive signals. The image sensor 200 in this fifth embodiment differs from the first embodiment in that it detects breaks in drive lines.

[0185] 27 is a diagram showing a configuration example of a pixel array unit 214 according to a fifth embodiment of the present technology. The pixel array unit 214 according to the fifth embodiment differs from that according to the first embodiment in that a predetermined number of ID (IDentification) pixels 320 and a predetermined number of ID pixels 330 are further arranged.

[0186] The ID pixels 320 and 330 generate identification pixel signals indicating specific logical values ​​in response to a drive signal from the vertical drive circuit 211. The ID pixel 320 generates an identification pixel signal indicating a logical value of "1," and the ID pixel 330 generates an identification pixel signal indicating a logical value of "0."

[0187] The ID pixel 320 includes, for example, a transfer transistor 321 , a reset transistor 322 , a floating diffusion layer 323 , an amplification transistor 324 , and a selection transistor 325 .

[0188] The transfer transistor 321 opens and closes a path between a node of a constant test voltage Vt and the floating diffusion layer 323 in accordance with the drive signal TRG. The reset transistor 322, floating diffusion layer 323, amplifier transistor 324, and selection transistor 325 are connected in the same manner as the transistors of the same names in an effective pixel. This circuit configuration generates high-level and low-level identification pixel signals in sequence, and after CDS processing, a digital signal with a logic value of "1" is generated.

[0189] The ID pixel 330 also includes, for example, an amplification transistor 331 and a selection transistor 332. These transistors are inserted in series between the power supply voltage and the vertical signal line VSL. The gate of the amplification transistor 331 is connected to the power supply voltage, and a drive signal SELe is input to the gate of the selection transistor 332. This circuit configuration generates an identification pixel signal of a constant level, and after CDS processing, a digital signal with a logical value of "0" is generated.

[0190] Furthermore, in the pixel array unit 214, outside the area in which the effective pixels are arranged, multiple columns of ID pixels are arranged for each row. The code obtained by arranging the logical values ​​of each row of ID pixels corresponds to a unique identification code assigned to that row. For example, in the same figure, the first row is arranged with I (I is an integer) ID pixels, including, from left to right, an ID pixel that outputs "0", an ID pixel that outputs "0", and an ID pixel that outputs "1". In this case, the identification code assigned to this row is an I-bit code starting with "001".

[0191] In addition to the ADC for each column of effective pixels, an ADC is arranged for each column of ID pixels within the column signal processing unit 240 .

[0192] The self-diagnosis processor 280 determines whether the code obtained by arranging digital signals corresponding to the identification pixel signals of the row being accessed during the period in which the row of valid pixels is being read out is the identification code assigned to that row. If the code obtained by arranging digital signals is not the identification code, a break (in other words, a failure) is detected in one or more of the drive lines 217, 218, and 219 of the row being accessed.

[0193] It should be noted that the self-diagnosis processor 280 cannot detect a failure in a drive line during a period when no reading is performed, such as a V-blank period.

[0194] In the figure, the ID pixels are arranged only on the left side of the effective pixel area, but they can also be arranged on the right side of the effective pixel area or on both sides.

[0195] Moreover, the first and second modifications of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment can be applied to the fifth embodiment.

[0196] In this way, according to the fifth embodiment of the present technology, the self-diagnosis processing unit 280 determines whether or not a code arranged with digital signals corresponding to the identification pixel signals of the row to be accessed is the identification code of that row, and therefore, it is possible to detect a failure in the drive line.

[0197] 28 is a diagram summarizing the diagnosable periods in the first to fifth embodiments of the present technology. In the drawing, "Yes" indicates that the diagnosis is possible, and "No" indicates that the diagnosis is not possible.

[0198] As illustrated in the figure, in the first embodiment, the image sensor 200 diagnosed vertical signal lines, etc., but this part can be diagnosed outside the period from timing T3 to T5 when the readout periods overlap.

[0199] In the second embodiment, the latch section 250 and the like of the image sensor 200 are the subject of diagnosis, but this section can be diagnosed outside the period from timing T3 to T5 where the readout periods overlap.

[0200] In the third embodiment, the image sensor 200 targets the diagnosis of the data path, but this portion can be diagnosed outside the period from timing T3 to T5 where the readout periods overlap.

[0201] In the fourth embodiment, the image sensor 200 targets the temperature measurement unit 310 for diagnosis, but this part can be diagnosed outside the period from timing T3 to T5 when the readout periods overlap.

[0202] In the fifth embodiment, the image sensor 200 diagnoses the drive line, but this part can be diagnosed outside the period from timing T7 to T9 when no readout is performed.

[0203] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0204] FIG. 29 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0205] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0206] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0207] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0208] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0209] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0210] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0211] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0212] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0213] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0214] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 29, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0215] FIG. 30 is a diagram showing an example of the installation position of the imaging unit 12031.

[0216] In FIG. 30, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0217] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0218] 30 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0219] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0220] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0221] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0222] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0223] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. Applying the technology according to the present disclosure to the imaging unit 12031 enables fault detection in real time, thereby improving the safety of the vehicle control system.

[0224] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0225] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0226] The present technology may also be configured as follows: (1) An image sensor comprising: a vertical drive circuit that drives a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times; a column signal processing unit that reads out the first effective pixel signals in a first readout period and reads out the second effective pixel signals in a second readout period that partially overlaps with the first readout period; and a logic circuit that performs a predetermined self-diagnosis process within a predetermined period from the start of the first readout period to the end of the second readout period that does not fall within the portion of the period. (2) The image sensor according to (1), wherein the pixel array unit is further provided with a predetermined number of dummy pixels that output dummy pixel signals of a predetermined voltage, the column signal processing unit sequentially reads out the dummy pixel signals and one of the first and second effective pixel signals within the predetermined period, and the self-diagnosis process includes a process of determining whether the dummy pixel signals are equal to an expected value. (3) The image sensor according to (2), wherein the dummy pixels include adjacent first and second dummy pixels, and the first and second dummy pixels output first and second dummy pixel signals having different voltages. (4) The column signal processing unit includes: an analog-to-digital converter that converts each of the first and second effective pixel signals into a digital signal; a test pattern generation unit that generates a predetermined test pattern; a multiplexer that selects and outputs either the digital signal or the test pattern; and a latch unit that holds a signal from the multiplexer, and the self-diagnosis processing includes processing of determining whether the test pattern held in the latch unit is identical to the generated test pattern. (5) The image sensor according to (4), wherein the latch unit outputs the held signal in synchronization with a horizontal synchronization signal, and the column signal processing unit further includes a sense amplifier that amplifies the signal from the latch unit and supplies the amplified signal to the logic circuit.(6) The image sensor according to any of (1) to (5), wherein the logic circuit comprises: a first multiplexer that selects and outputs either a first digital signal or a predetermined test pattern, a second multiplexer that selects and outputs either a second digital signal or the test pattern, a first data path that processes a signal from the first multiplexer and outputs first processed data, a second data path that processes a signal from the second multiplexer and outputs second processed data, and a comparison unit that compares the first processed data with the second processed data. (7) The image sensor according to any of (1) to (6), further comprising: a temperature sensor that outputs a sensor voltage according to temperature, a selector that selects and outputs either a constant reference voltage or the sensor voltage as an output voltage, and an analog-to-digital converter that converts the voltage from the selector into a digital signal, and the self-diagnosis processing includes processing to determine whether the digital signal corresponding to the reference voltage is an expected value. (8) The image sensor according to any one of (1) to (7), wherein the pixel array unit further includes a predetermined number of identification pixels that output identification pixel signals indicating a specific logical value, and the self-diagnosis processing includes processing for determining whether a code obtained by arranging digital signals corresponding to the identification pixel signals in a row to be accessed is an identification code assigned to the row to be accessed. (9) The image sensor according to any one of (1) to (8), wherein the logic circuit includes: a self-diagnosis processing unit that performs the self-diagnosis processing within the predetermined period and outputs a diagnosis result; an image processing unit that generates RAW data by combining the first and second effective pixel signals; and a format processing unit that generates a frame including the RAW data. (10) The image sensor according to (9), wherein the format processing unit generates the frame in which the diagnosis result is embedded. (11) The image sensor according to (9), further including: a first transmission unit that transmits the frame; and a second transmission unit that transmits the diagnosis result. (12) The image sensor according to (9), further including a dedicated terminal that outputs the diagnosis result.(13) The image sensor according to any one of (1) to (12), wherein the logic circuit further performs the self-diagnosis processing within a period from the end of the second readout period to the start of the next first readout period. (14) An imaging device comprising: an image sensor including: a vertical drive circuit that drives a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times, a column signal processing unit that reads out the first effective pixel signals within the first readout period and reads out the second effective pixel signals within a second readout period that partially overlaps with the first readout period, and a logic circuit that performs a predetermined self-diagnosis processing within a predetermined period that does not fall within the partial period of the period from the start of the first readout period to the end of the second readout period; and a processing unit that processes a signal from the image sensor. (15) A control method for an image sensor comprising: a driving procedure for driving a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit in row units to sequentially output first and second effective pixel signals having different exposure times; a column signal processing procedure for reading out the first effective pixel signals in a first readout period and reading out the second effective pixel signals in a second readout period that partially overlaps with the first readout period; and a diagnosis procedure for performing a predetermined self-diagnosis process in a predetermined period that does not fall within the partial period from the start of the first readout period to the end of the second readout period.

[0227] 100 Imaging device 200 Image sensor 211 Vertical drive circuit 212 Timing control unit 213 DAC 214 Pixel array unit 215 Horizontal transfer control unit 220 Dummy pixel 221, 235, 324, 331 Amplification transistor 222, 236, 325, 332 Selection transistor 230 Effective pixel 231 Photoelectric conversion element 232, 321 Transfer transistor 233, 322 Reset transistor 234, 323 Floating diffusion layer 240 Column signal processing unit 241, 313 ADC 242 Comparator 243 Counter 244 Sense amplifier 245, 281 Test pattern generation unit 246, 261, 271, 272 Multiplexer 247, 312 Selector 250 Latch unit 251 Latch circuit 260 Logic circuit 262 Format processing unit 270 Image processing unit 273, 274 Data path 275, 276 Demultiplexer 277 RAW data generation unit 280 Self-diagnosis processing unit 282 Comparison unit 283 BIST data generation unit 291 Transmission unit 292, 430 Communication interface 293, 440 Dedicated terminal 300 Voltage generation unit 310 Temperature measurement unit 311 Temperature sensor 320, 330 ID pixel 400 Application processor 410 Reception unit 420 Processor 12031 Imaging unit

Claims

1. An image sensor comprising: a vertical drive circuit that drives a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times; a column signal processing unit that reads out the first effective pixel signals in a first readout period and reads out the second effective pixel signals in a second readout period that partially overlaps with the first readout period; and a logic circuit that performs a predetermined self-diagnosis process within a predetermined period that does not fall within the period from the start of the first readout period to the end of the second readout period.

2. The image sensor according to claim 1, wherein the pixel array section is further provided with a predetermined number of dummy pixels that output dummy pixel signals of a predetermined voltage, the column signal processing section sequentially reads out the dummy pixel signals and one of the first and second effective pixel signals within the predetermined period, and the self-diagnosis processing includes processing for determining whether the dummy pixel signals are equal to expected values.

3. The image sensor according to claim 2, wherein the dummy pixels include first and second dummy pixels adjacent to each other, and the first and second dummy pixels output first and second dummy pixel signals having different voltages.

4. The image sensor of claim 1, wherein the column signal processing unit comprises: an analog-to-digital converter that converts each of the first and second effective pixel signals into a digital signal; a test pattern generation unit that generates a predetermined test pattern; a multiplexer that selects and outputs either the digital signal or the test pattern; and a latch unit that holds a signal from the multiplexer; and the self-diagnosis processing includes processing for determining whether the test pattern held in the latch unit is identical to the generated test pattern.

5. The image sensor according to claim 4, wherein the latch section outputs the held signal in synchronization with a horizontal synchronizing signal, and the column signal processing section further includes a sense amplifier that amplifies the signal from the latch section and supplies the amplified signal to the logic circuit.

6. The image sensor of claim 1, wherein the logic circuit comprises: a first multiplexer that selects and outputs either a first digital signal or a predetermined test pattern; a second multiplexer that selects and outputs either a second digital signal or the test pattern; a first data path that processes the signal from the first multiplexer and outputs first processed data; a second data path that processes the signal from the second multiplexer and outputs second processed data; and a comparison section that compares the first processed data with the second processed data.

7. The image sensor according to claim 1, further comprising: a temperature sensor which outputs a sensor voltage according to temperature; a selector which selects either a constant reference voltage or the sensor voltage and outputs it as an output voltage; and an analog-to-digital converter which converts the voltage from the selector into a digital signal, wherein the self-diagnosis process includes a process of determining whether the digital signal corresponding to the reference voltage is an expected value.

8. The image sensor according to claim 1, wherein the pixel array section is further provided with a predetermined number of identification pixels that output identification pixel signals indicating specific logical values, and the self-diagnosis process includes a process of determining whether a code obtained by arranging digital signals corresponding to the identification pixel signals in the row to be accessed is an identification code assigned to the row to be accessed.

9. The image sensor according to claim 1, wherein the logic circuit comprises: a self-diagnosis processing unit that performs the self-diagnosis processing within the specified period and outputs a diagnosis result; an image processing unit that generates RAW data by combining the first and second effective pixel signals; and a format processing unit that generates a frame including the RAW data.

10. The image sensor according to claim 9, wherein the format processing unit generates the frame in which the diagnostic result is embedded.

11. The image sensor according to claim 9, further comprising: a first transmitting unit that transmits the frame; and a second transmitting unit that transmits the diagnosis result.

12. The image sensor according to claim 9, further comprising a dedicated terminal for outputting the diagnosis result.

13. The image sensor according to claim 1, wherein the logic circuit further performs the self-diagnosis process within a period from the end of the second readout period to the start of the next first readout period.

14. An imaging device comprising: an image sensor including a vertical drive circuit that drives a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times; a column signal processing unit that reads out the first effective pixel signal in a first readout period and reads out the second effective pixel signal in a second readout period that partially overlaps with the first readout period; and a logic circuit that performs a predetermined self-diagnosis process within a predetermined period that does not fall within the period from the start of the first readout period to the end of the second readout period; and a processing unit that processes a signal from the image sensor.

15. A method for controlling an image sensor comprising: a drive procedure for driving a plurality of effective pixels arranged in a two-dimensional lattice pattern in a pixel array unit on a row-by-row basis to sequentially output first and second effective pixel signals having different exposure times; a column signal processing procedure for reading out the first effective pixel signal in a first readout period and reading out the second effective pixel signal in a second readout period that partially overlaps with the first readout period; and a diagnosis procedure for performing a predetermined self-diagnosis process within a predetermined period that does not fall within the period from the start of the first readout period to the end of the second readout period.

Images