Light detection device, electronic apparatus, and method for manufacturing light detection device

Abstract

[Problem] To provide an advantageous technology for improving the degree of freedom of wiring layout in a light detection device provided with phase difference detection pixels. [Solution] At least some of light reception pixels each comprise a pair of photoelectric conversion parts, a first separation region disposed so as to surround the pair of photoelectric conversion parts, and a second separation region disposed between the pair of photoelectric conversion parts. The first separation region has a rectangular shape in plan view. The second separation region is disposed along one diagonal line of the first separation region in a plan view, is in contact with the first separation region on one end side of the one diagonal line, and is not in contact with the first separation region on the other end side of the one diagonal line.

Description

Photodetector, electronic device, and method for manufacturing photodetector

[0001] The present disclosure relates to a light detection device, an electronic device, and a method for manufacturing a light detection device.

[0002] Photodetection devices including phase difference detection pixels are widely known (see Patent Documents 1 and 2). Phase difference detection pixels include photoelectric conversion units (photodiodes) separated from each other by isolation structures.

[0003] International Publication No. 2016 / 158439 Japanese Patent Application Laid-Open No. 2021-97241

[0004] As the number of pixels increases and the size of each pixel becomes smaller in recent years, wiring layouts are becoming increasingly restricted, and it is no longer necessarily easy to ensure a photodiode of sufficient size in each pixel.

[0005] In particular, the area and volume of the photodiode allocated to each of the phase difference detection pixels having a separation structure tend to be small. Therefore, in a photodetection device such as a solid-state imaging device including phase difference detection pixels, a technique for appropriately performing wiring layout while ensuring a photodiode of a desired size for each phase difference detection pixel is useful.

[0006] The present disclosure provides a technique that is advantageous for improving the degree of freedom in wiring layout in a photodetection device including phase difference detection pixels.

[0007] One aspect of the present disclosure relates to a photodetector device having a semiconductor substrate including a plurality of photosensitive pixels arranged two-dimensionally, at least some of the plurality of photosensitive pixels having a pair of photoelectric conversion units, a first isolation region arranged to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in a planar view, and the second isolation region is arranged along one diagonal of the first isolation region in a planar view, contacting the first isolation region at one end of the one diagonal and not contacting the first isolation region at the other end of the one diagonal.

[0008] At least some of the light-receiving pixels have an overflow path that electrically connects a pair of photoelectric conversion units to each other in a portion where the second isolation region does not contact the first isolation region in a planar view, and the first isolation region may be arranged to separate the photoelectric conversion units between adjacent light-receiving pixels, and the second isolation region may be arranged to separate the pair of photoelectric conversion units in a corresponding light-receiving pixel.

[0009] At least some of the light-receiving pixels have a P-type diffusion region that forms a ground contact in a portion where the second isolation region does not contact the first isolation region in a planar view, and the P-type diffusion regions of multiple light-receiving pixels that have a pair of photoelectric conversion units, the first isolation region, the second isolation region, and a P-type diffusion region and are arranged adjacent to each other may be electrically connected to a single P-type diffusion region electrode.

[0010] The P-type diffusion region may have a P-type region provided in the semiconductor substrate and a P-type electrode connected to the P-type region, and at least a portion of the P-type electrode may be buried in the semiconductor substrate.

[0011] At least some of the light-receiving pixels may have a third isolation region arranged to surround the P-type region.

[0012] One electrode for the P-type diffusion region may be a vertical via extending in a direction perpendicular to the pixel surface, and may be electrically connected to the P-type diffusion region at one end and electrically connected to another wiring at the other end.

[0013] At least some of the light-receiving pixels have a transfer gate for reading out the accumulated charges of the pair of photoelectric conversion elements, and in each of at least some of the light-receiving pixels, the distance between the overflow path and the transfer gate may be greater than or equal to the length of one side of the rectangular light-receiving pixel.

[0014] The photodetector device includes readout transistors, which are transistors for reading out accumulated charges in the photoelectric conversion units of the plurality of light-receiving pixels, and at least some of the photoelectric conversion units and readout transistors of the plurality of light-receiving pixels may be provided on the same semiconductor substrate.

[0015] The transfer gate may be provided at a diagonal position different from the diagonal position through which one diagonal line of the light-receiving pixel passes.

[0016] The transfer gate may be shared by adjacently arranged light-sensitive pixels.

[0017] The transfer gate may be provided at a diagonal position where one diagonal line of the light-receiving pixel passes.

[0018] The transfer gate may be shared by a pair of photoelectric conversion units.

[0019] One transfer gate electrode is electrically connected to the transfer gate, and the one transfer gate electrode is a vertical via extending in a direction perpendicular to the pixel surface, and may be electrically connected to the transfer gate at one end and electrically connected to another wiring at the other end.

[0020] At least some of the light-receiving pixels have a floating diffusion electrically connected to a transfer gate, and the distance between one transfer gate electrode and the floating diffusion may be equal to or greater than half the length of one side of the rectangular light-receiving pixel.

[0021] Another aspect of the present disclosure relates to an electronic device comprising a photodetector, an optical system that focuses incident light on an imaging surface of the photodetector, and a signal processing circuit that processes signals output from the photodetector, wherein the photodetector comprises a plurality of photosensitive pixels arranged two-dimensionally, at least some of the plurality of photosensitive pixels having a pair of photoelectric conversion units, a first isolation region arranged to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in a planar view, and the second isolation region is arranged along one diagonal of the first isolation region in a planar view, and is in contact with the first isolation region at one end side of the one diagonal and is not in contact with the first isolation region at the other end side of the one diagonal.

[0022] Another aspect of the present disclosure relates to a method for manufacturing a photodetector including a semiconductor substrate including a plurality of photosensitive pixels arranged two-dimensionally, at least some of the plurality of photosensitive pixels having a pair of photoelectric conversion units, a first isolation region arranged to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in a planar view, and the second isolation region is arranged along one diagonal of the first isolation region in a planar view, and is in contact with the first isolation region at one end side of the one diagonal and not in contact with the first isolation region at the other end side of the one diagonal, the method including the steps of: preparing a semiconductor substrate in a state where a location corresponding to the second isolation region is a space; injecting an ionized injection substance into the semiconductor substrate after passing the location corresponding to the second isolation region in a space state; and filling the substance into the location corresponding to the second isolation region in a space state to form the second isolation region.

[0023] FIG. 1 is a system configuration diagram showing a schematic configuration example of a solid-state imaging device (photodetector). FIG. 2 is a diagram showing an example of a pixel circuit. FIG. 3 is a plan view showing an example configuration of a light-receiving pixel according to the first embodiment, exemplarily showing 16 light-receiving pixels (4 pixels x 4 pixels). FIG. 4 is a diagram showing an example cross-section of a light-receiving pixel taken along the IV-IV cross-sectional line shown in FIG. 3. FIG. 5 is a diagram showing an example cross-section of a light-receiving pixel taken along the V-V cross-sectional line shown in FIG. 3. FIG. 6 is a plan view showing an example configuration of a light-receiving pixel according to a modification of the first embodiment, exemplarily showing 16 light-receiving pixels (4 pixels x 4 pixels). FIG. 7 is a plan view showing an example configuration of a light-receiving pixel according to the second embodiment, exemplarily showing 16 light-receiving pixels (4 pixels x 4 pixels). FIG. 8 is a diagram showing an example cross-section of a light-receiving pixel taken along the VIII-VIII cross-sectional line shown in FIG. 7. FIG. 9 is a diagram showing an example cross-section of a light-receiving pixel taken along the IX-IX cross-sectional line shown in FIG. 7. FIG. 10 is a plan view showing an example of the configuration of a light-receiving pixel according to the third embodiment, exemplarily illustrating four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 11 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XI-XI cross section line shown in FIG. 10. FIG. 12 is a plan view showing an example of the configuration of a light-receiving pixel according to the fourth embodiment, exemplarily illustrating four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 13 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XIII-XIII cross section line shown in FIG. 10. FIG. 14 is a plan view of an example of a semiconductor substrate according to the fifth embodiment, showing the semiconductor substrate in a state in which the locations corresponding to the first isolation region and the second isolation region configured as an FFTI are empty. FIG. 15 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XV-XV cross section line shown in FIG. 14. FIG. 16 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XVI-XVI cross section line shown in FIG. 14. Fig. 17 is a plan view showing an example of the configuration of a light-receiving pixel according to the sixth embodiment, exemplifying four light-receiving pixels (2 pixels x 2 pixels; particularly, a first pixel unit). Fig. 18 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XVIII-XVIII cross section line shown in Fig. 17. Fig. 19 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XVIII-XVIII cross section line shown in Fig. 17. Fig. 20 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XX-XX cross section line shown in Fig. 17.FIG. 21 is a plan view showing an example of the configuration of a light-receiving pixel according to a modified example of the sixth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 22 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXII-XXII cross section line shown in FIG. 21. FIG. 23 is a plan view showing an example of the configuration of a light-receiving pixel according to the seventh embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 24 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXIV-XXIV cross section line shown in FIG. 23. FIG. 25 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XXIV-XXIV cross section line shown in FIG. 23. FIG. 26 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XXIV-XXIV cross section line shown in FIG. 23. FIG. 27 is a diagram showing an example of a pixel circuit according to the seventh embodiment. FIG. 28 is a plan view showing an example of the configuration of a light-receiving pixel according to a modified example of the seventh embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 29 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXIX-XXIX cross section line shown in FIG. 28. FIG. 30 is a plan view showing an example of the configuration of a light-receiving pixel according to the eighth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 31 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXXI-XXXI cross section line shown in FIG. 30. FIG. 32 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XXXI-XXXI cross section line shown in FIG. 30. FIG. 33 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXXIII-XXXIII cross section line shown in FIG. 30. FIG. 34 is a plan view showing an example of the configuration of a light-receiving pixel according to a modified example of the eighth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 35 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXXV-XXXV cross section line shown in FIG. 34. FIG. 36 is a plan view showing an example of the configuration of a light-receiving pixel according to the ninth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the first pixel unit). FIG. 37 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XXXVII-XXXVII cross section line shown in FIG. 36. FIG. 38 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XXXVII-XXXVII cross section line shown in FIG. 36. FIG. 39 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XXXVII-XXXVII cross section line shown in FIG. 36.FIG. 40 is a diagram showing an example of a cross section of a light-receiving pixel taken along the line XL-XL shown in FIG. 36 . FIG. 41 is a diagram showing another example of a cross section of a light-receiving pixel taken along the line XL-XL shown in FIG. 36 . FIG. 42 is a diagram showing an example of a pixel circuit according to the ninth embodiment. FIG. 43 is a plan view showing an example of the configuration of a light-receiving pixel according to a modification of the ninth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly the first pixel unit). FIG. 44 is a diagram showing an example of a cross section of a light-receiving pixel (particularly a planar type (see FIG. 37 ) or double vertical type (see FIG. 38 ) transfer gate) taken along the line XLIV-XLIV shown in FIG. 43 . FIG. 45 is a diagram showing another example of a cross section of a light-receiving pixel (particularly a single vertical type (see FIG. 39 ) transfer gate) taken along the line XLIV-XLIV shown in FIG. 43 . FIG. 46 is a plan view showing an example of the configuration of a light-receiving pixel according to the tenth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly the third pixel unit). FIG. 47 is a diagram showing an example of a cross section of a light-receiving pixel taken along the XLVII-XLVII cross section line shown in FIG. 46 . FIG. 48 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XLVII-XLVII cross section line shown in FIG. 46 . FIG. 49 is a diagram showing another example of a cross section of a light-receiving pixel taken along the XLVII-XLVII cross section line shown in FIG. 46 . FIG. 50 is a diagram showing an example of a cross section of a light-receiving pixel taken along the L-L cross section line shown in FIG. 46 . FIG. 51 is a diagram showing another example of a cross section of a light-receiving pixel taken along the L-L cross section line shown in FIG. 46 . FIG. 52 is a plan view showing an example of the configuration of a light-receiving pixel according to a modification of the tenth embodiment, exemplarily showing four light-receiving pixels (2 pixels × 2 pixels; particularly, the third pixel unit). FIG. 53 is a diagram showing an example of a cross section of a light-receiving pixel (particularly, a planar type (see FIG. 47 ) or double vertical type (see FIG. 48 ) transfer gate) taken along the LIII-LIII cross section line shown in FIG. 52 . FIG. 54 is a diagram showing another example of a cross section of a light-receiving pixel (particularly a single vertical type (see FIG. 49) transfer gate) taken along the LIII-LIII cross section line shown in FIG. 52. FIG. 55 is a plan view showing an example of the configuration of a light-receiving pixel according to the eleventh embodiment, exemplarily showing 16 light-receiving pixels (4 pixels x 4 pixels). FIG. 56 is a diagram showing an example of a cross section of a light-receiving pixel taken along the LVI-LVI cross section line shown in FIG. 55. FIG. 57 is a diagram showing an example of a cross section of a light-receiving pixel taken along the LVII-LVII cross section line shown in FIG. 55.Fig. 58 is a diagram showing an example cross section of a light receiving pixel taken along the LVIII-LVIII cross section line shown in Fig. 55. Fig. 59 is a plan view showing an example configuration of a light receiving pixel according to the twelfth embodiment, exemplarily showing 16 light receiving pixels (4 pixels x 4 pixels). Fig. 60 is a diagram showing an example cross section of a light receiving pixel taken along the LX-LX cross section line shown in Fig. 59. Fig. 61 is a block diagram showing an example configuration of an imaging device, which is an example of an electronic device to which the disclosed technology can be applied.

[0024] The following describes embodiments of the disclosed technology with reference to the drawings. While the following mainly describes embodiments relating to a solid-state image sensor as an example of a photodetector, the technology described below can also be applied to solid-state image sensors or other photodetectors having different configurations from those of the embodiments described below.

[0025] In a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor, there is a technology for detecting a phase difference by irradiating light onto a pair of photodiodes through the same on-chip lens. In such an image sensor, increasing the saturation signal charge (Qs) of the photodiode capable of detecting the phase difference leads to an improvement in the dynamic range and the signal-to-noise ratio.

[0026] Each light-receiving pixel used for phase difference detection (hereinafter also referred to as a "phase difference detection pixel") is provided with an isolation region that divides the photodiode into two regions (i.e., a pair of photodiodes) and an overflow path that electrically connects the pair of photodiodes. The isolation region and overflow path thus provided reduce space for other elements and wiring in each light-receiving pixel.

[0027] As described above, in the phase difference detection pixel, there is room for further improvement in terms of appropriately performing the wiring layout while ensuring an area for a photodiode of a desired size.

[0028] [Configuration Example of Photodetection Device] FIG. 1 is a system configuration diagram showing a schematic configuration example of a solid-state imaging device (photodetection device) 1.

[0029] The solid-state imaging device 1 shown in FIG. 1 is a CMOS image sensor and includes a pixel array section 10, a system control section 12, a vertical drive section 13, a column readout circuit section 14, a column signal processing section 15, a horizontal drive section 16, and a signal processing section 17.

[0030] The pixel array section 10, the system control section 12, the vertical drive section 13, the column readout circuit section 14, the column signal processing section 15, the horizontal drive section 16 and the signal processing section 17 may be provided on the same semiconductor substrate, or may be provided on multiple electrically connected stacked semiconductor substrates.

[0031] The pixel array unit 10 has a plurality of light-receiving pixels 11 arranged two-dimensionally in a matrix. Each light-receiving pixel 11 has a photodiode (photoelectric conversion unit) that can photoelectrically convert an amount of charge corresponding to the amount of incident light, store the charge internally, and output the charge as a signal.

[0032] The pixel array unit 10 may include dummy pixels that do not have a photodiode, light-shielding pixels that are blocked from external light incidence, and / or pixels that perform other arbitrary functions, in addition to the plurality of light-receiving pixels 11. The light-shielding pixels may be configured in the same manner as the light-receiving pixels 11, except that they have a light-shielded light-receiving surface.

[0033] Hereinafter, the photocharge having an amount corresponding to the amount of incident light may also be simply referred to as "charge," and the light-receiving pixel 11 may also be simply referred to as "pixel."

[0034] In the pixel array unit 10, pixel drive lines LD are formed for each row in the matrix-like pixel arrangement along the left-right direction in Fig. 1 (the direction in which pixels in the pixel rows are arranged), and vertical pixel wiring LV are formed for each column along the up-down direction in Fig. 1 (the direction in which pixels in the pixel columns are arranged). The vertical drive unit 13 has a plurality of output terminals corresponding to the respective rows of the pixel arrangement, and one end of each pixel drive line LD is connected to the corresponding output terminal of the vertical drive unit 13.

[0035] The column readout circuit unit 14 includes at least a circuit that supplies a constant current to the light-sensitive pixels 11 in a selected row in the pixel array unit 10 for each column, a current mirror circuit, and a switch for selecting the light-sensitive pixel 11 to be read out.

[0036] The column readout circuit unit 14 forms an amplifier together with a transistor in a selected pixel in the pixel array unit 10, converts a photocharge signal into a voltage signal, and outputs it to the vertical pixel line LV.

[0037] The vertical drive unit 13 includes a shift register, an address decoder, etc., and drives each of the light-receiving pixels 11 of the pixel array unit 10 simultaneously for all pixels or row by row, etc. The vertical drive unit 13 can have any configuration, and may have, for example, a readout scanning system and a sweep scanning system or a batch sweep and batch transfer system.

[0038] The readout scanning system sequentially selects and scans the light-receiving pixels 11 of the pixel array unit 10 row by row in order to read out pixel signals from the light-receiving pixels 11. In the case of row driving (rolling shutter operation), for sweeping, for the readout row on which readout scanning is performed by the readout scanning system, sweeping scanning is performed prior to the readout scanning by the shutter speed.

[0039] On the other hand, in the case of global exposure (global shutter operation), a collective sweep is performed prior to the collective transfer by the time of the shutter speed. This sweep sweeps out (resets) unnecessary charges from the photodiodes of the light-sensitive pixels 11 in the readout row. Then, the sweeping out (resetting) of unnecessary charges performs a so-called electronic shutter operation.

[0040] The electronic shutter operation here means an operation of discarding unnecessary photocharges that had accumulated in the photodiode until just before and starting new exposure (starting accumulation of photocharges).

[0041] The signal read by the readout operation by the readout scanning system corresponds to the amount of light that has entered since the immediately preceding readout operation or electronic shutter operation. In the case of row driving, the period from the readout timing of the immediately preceding readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the accumulation time (exposure time) of the photocharges in the light-sensitive pixels 11. In the case of global exposure, the time from the collective sweep to the collective transfer is the accumulation time (exposure time).

[0042] The pixel signals output from each light-receiving pixel 11 in a pixel row selected and scanned by the vertical drive unit 13 are supplied through each vertical pixel wiring LV to the column signal processing unit 15. The column signal processing unit 15 performs predetermined signal processing on the pixel signals output from each light-receiving pixel 11 in the selected row through the vertical pixel wiring LV for each pixel column in the pixel array unit 10, and temporarily holds the pixel signals after signal processing.

[0043] Specifically, the column signal processing unit 15 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing, as signal processing. The CDS processing by the column signal processing unit 15 removes pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistor AMP.

[0044] In addition to the noise removal processing, the column signal processing unit 15 may be configured to have, for example, an AD conversion function so as to output pixel signals as digital signals.

[0045] The horizontal drive unit 16 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 15. By selective scanning by this horizontal drive unit 16, pixel signals processed by the column signal processing unit 15 are sequentially output to the signal processing unit 17.

[0046] The system control unit 12 includes a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 13, column signal processing unit 15, horizontal driving unit 16, etc. based on the various timing signals generated by the timing generator.

[0047] The solid-state imaging device 1 further includes a signal processing unit 17 and a data storage unit (not shown). The signal processing unit 17 has at least an addition processing function and performs various signal processing such as addition processing on the pixel signals output from the column signal processing unit 15.

[0048] The data storage unit temporarily stores data necessary for signal processing in the signal processing unit 17. The signal processing unit 17 and the data storage unit may be provided on the same board as the solid-state imaging device 1, or may be provided on a board separate from the solid-state imaging device 1. In this way, the signal processing by the signal processing unit 17 may be processing by an external signal processing unit provided on a separate board, or may be processing by, for example, a DSP (Digital Signal Processor) or software.

[0049] [Pixel Circuit Example] FIG. 2 is a diagram showing an example of a pixel circuit.

[0050] 2 , two (or more) light-receiving pixels 11 share one readout circuit 18. Here, “sharing” means that the two light-receiving pixels 11 are electrically connected to a common readout circuit 18, that is, the outputs of the two light-receiving pixels 11 are input to the common readout circuit 18.

[0051] The two light-sensitive pixels 11 have common components. For convenience, in Fig. 2, the elements that make up the light-sensitive pixels 11 are designated by the reference numerals with identification numbers (1, 2) added to the end of the reference numerals.

[0052] When the components of each photosensitive pixel 11 need to be distinguished from one another, they may be described with an identification number added to the end of the reference numeral of the component of each photosensitive pixel 11. On the other hand, when it is not necessary to distinguish the components of each photosensitive pixel 11 from one another, the identification number added to the end of the reference numeral of the component of each photosensitive pixel 11 may be omitted.

[0053] Each of the light-receiving pixels 11 includes, for example, a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD. The photodiode PD is an example of a photoelectric conversion unit.

[0054] 2 share a floating diffusion FD electrically connected to each transfer transistor TR. Here, "sharing" means that the photodiode PD of each light-receiving pixel 11 is electrically connected to the floating diffusion FD.

[0055] The photodiode PD performs photoelectric conversion to generate charges according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential (e.g., ground potential).

[0056] The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR, that is, the transfer gate TG, is electrically connected to the pixel drive line LD (see FIG. 1). The transfer transistor TR is, for example, a CMOS transistor.

[0057] The floating diffusion FD temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The floating diffusion FD is electrically connected to the input terminal of the readout circuit 18. In this way, the two light-receiving pixels 11 are connected to the common readout circuit 18 via the floating diffusion FD.

[0058] 2 includes a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and a switching transistor FDG. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0059] The source of the switching transistor FDG, which is the input of the readout circuit 18, is electrically connected to the floating diffusion FD, the drain of the switching transistor FDG is electrically connected to the source of the reset transistor RST, and the gate of the switching transistor FDG is electrically connected to the pixel drive line LD.

[0060] The drain of the reset transistor RST is electrically connected to a power supply voltage VDD, and the gate of the reset transistor RST is electrically connected to a pixel drive line LD.

[0061] The source of the amplifier transistor AMP is electrically connected to the drain of the select transistor SEL, the drain of the amplifier transistor AMP is electrically connected to the power supply voltage VDD, and the gate of the amplifier transistor AMP is electrically connected to the source of the switching transistor FDG and the floating diffusion FD.

[0062] The source of the selection transistor SEL, which is the output part of the readout circuit 18, is electrically connected to the vertical pixel line LV, and the gate of the selection transistor SEL is electrically connected to the pixel drive line LD.

[0063] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD.

[0064] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion FD to the potential of the power supply voltage VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 18.

[0065] The amplifier transistor AMP generates a pixel signal having a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplifier transistor AMP constitutes a source follower amplifier, and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD.

[0066] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing unit 15 (see FIG. 1) via the vertical pixel line LV.

[0067] The switching transistor FDG is used to switch the conversion efficiency. Generally, the pixel signal obtained when shooting in a dark place is small. Based on Q = CV, when performing charge-voltage conversion, if the capacitance of the floating diffusion FD (hereinafter also referred to as FD capacitance) is large, V when converted to voltage by the amplification transistor AMP will be small.

[0068] On the other hand, the pixel signal obtained when shooting in a bright place becomes large, so if the FD capacitance is not large, the floating diffusion FD cannot receive all the charge from the photodiode PD. Furthermore, the FD capacitance needs to be large so that V does not become too large when converted to voltage by the amplification transistor AMP (in other words, so that it becomes small).

[0069] That is, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, and the overall FD capacitance increases. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance decreases. In this way, by switching the state of the switching transistor FDG, the FD capacitance can be made variable, and the conversion efficiency can be changed.

[0070] Next, various embodiments relating to specific configuration examples of the light-sensitive pixel 11 and examples of manufacturing methods of the light-sensitive pixel 11 will be described.

[0071] [First Embodiment] Fig. 3 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to the first embodiment, exemplarily showing 16 light-receiving pixels 11 (4 pixels x 4 pixels). Fig. 4 is a diagram showing an example of a cross section of the light-receiving pixel 11 taken along the IV-IV cross section line shown in Fig. 3. Fig. 5 is a diagram showing an example of a cross section of the light-receiving pixel 11 taken along the V-V cross section line shown in Fig. 3.

[0072] 4 and 5 partially show the cross-sectional configuration of the semiconductor substrate 20 on the side opposite to the light incident surface of the semiconductor substrate 20, and omit the cross-sectional configuration on the light incident surface side of the semiconductor substrate 20. Therefore, the floating diffusion FD and pixel transistors shown in Figures 4 and 5 are provided on the bottom surface (upper side surface in Figures 4 and 5) on the side opposite to the light incident surface of the semiconductor substrate 20.

[0073] In the pixel array unit 10 of this embodiment, a plurality of semiconductor substrates are stacked in a stacking direction (a direction perpendicular to the pixel surface), and one of the plurality of semiconductor substrates, a semiconductor substrate 20, is shown in Figures 3 to 5. Functional components such as transistors not shown in Figures 3 to 5 are provided on other semiconductor substrates.

[0074] 3 to 5 mainly show an enlarged view of the plurality of light-receiving pixels 11 formed on the semiconductor substrate 20 of the pixel array unit 10, but the pixel array unit 10 also includes components (not shown) other than the plurality of light-receiving pixels 11. As an example, the pixel array unit 10 may include a planarization film, a color filter, and an on-chip lens provided on the light-incident surface side of the semiconductor substrate 20.

[0075] In this embodiment, one microlens (on-chip lens) is assigned to each light-receiving pixel 11, and color filters of different colors are assigned to adjacent light-receiving pixels 11. However, the specific configurations of the planarization film, color filters, and on-chip lenses of the pixel array unit 10 are not limited. For example, one microlens may be assigned to two or more light-receiving pixels 11, or color filters of the same color may be assigned to adjacent light-receiving pixels 11.

[0076] The semiconductor substrate 20 can be configured as, for example, a silicon substrate and has a plurality of photodiodes PD. Each of these photodiodes PD forms a photoelectric conversion unit of a plurality of light-receiving pixels 11 and has a first impurity region containing impurities of a first conductivity type (e.g., N-type) and a second impurity region containing impurities of a second conductivity type (e.g., P-type). The first impurity region is disposed in the center of the photodiode PD, and the second impurity region is disposed along the sides and bottom of the first impurity region (the portion opposite to the side where light is incident).

[0077] 3 to 5, a pair of photodiodes PD functioning as phase difference detection pixels are provided in each of the light receiving pixels 11. That is, each of the light receiving pixels 11 includes two phase difference detection pixels (photodiodes PD).

[0078] It is possible to provide at least some of the light receiving pixels 11 as phase difference detection pixels among the plurality of light receiving pixels 11 included in the pixel array unit 10. That is, all of the light receiving pixels 11 included in the pixel array unit 10 may be provided as phase difference detection pixels, or only some of them may be provided as phase difference detection pixels.

[0079] Each light-receiving pixel 11 including a pair of phase difference detection pixels has a first isolation region 24 arranged to separate the photodiodes PD between adjacent light-receiving pixels 11, and a second isolation region 25 arranged to separate the pair of photodiodes PD from each other.

[0080] The first isolation region 24 is disposed so as to entirely surround the pair of photodiodes PD in each light-receiving pixel 11, and is provided as a different-color separation structure so as to penetrate the semiconductor substrate 20 as a front full trench isolation (FFTI). In the example shown in Fig. 3, the portion of the first isolation region 24 that surrounds each light-receiving pixel 11 has a hollow rectangular shape in a plan view, and this planar rectangular portion of the first isolation region 24 is repeatedly arranged two-dimensionally in the direction of extension of the pixel surface.

[0081] The first isolation region 24 optically and electrically isolates adjacent light-receiving pixels 11 (particularly photodiodes PD) from each other. The first isolation region 24 can be made of any material, for example, silicon oxide (SiO ２ ) or other low refractive index dielectrics.

[0082] The second separation region 25 is disposed between a pair of photodiodes PD positioned adjacent to each other in one light-receiving pixel 11, and is installed as an FFTI so as to penetrate the semiconductor substrate 20, and is provided as a same-color separation structure. In the example shown in Fig. 3, each second separation region 25 extends linearly in an oblique direction in a planar view, and the second separation regions 25 are arranged line-symmetrically in a planar view between adjacent light-receiving pixels 11. Such planar linear second separation regions 25 are repeatedly arranged two-dimensionally in the direction of extension of the pixel surface.

[0083] The second isolation region 25 optically and electrically isolates a pair of photodiodes PD located adjacent to each other in the corresponding light-receiving pixel 11. The second isolation region 25 can be made of any material, and may be made of a dielectric material with a low refractive index, such as silicon oxide.

[0084] In this way, the pair of photodiodes PD of each light-receiving pixel 11 separated from each other by the second separation region 25 can be used as a phase difference detection pixel for detecting the phase difference of incident light.

[0085] 3, the second isolation region 25 is arranged along one of two diagonals of the rectangular first isolation region 24 (i.e., each light-sensitive pixel 11) in plan view. More specifically, the second isolation region 25 is arranged along one diagonal of the first isolation region 24 in plan view, contacts the first isolation region 24 at one end of the one diagonal, and does not contact the first isolation region at the other end of the one diagonal.

[0086] Note that the term "diagonally arranged second isolation region 25" used here means that the second isolation region 25 is arranged so as to extend in a direction diagonal to the rectangular boundary line of each light-sensitive pixel 11 in a planar view. Therefore, the "diagonally arranged second isolation region 25" typically extends so as to overlap one diagonal line of each light-sensitive pixel 11 as shown in FIG. 3, but does not necessarily have to overlap that one diagonal line. For example, a second isolation region 25 that extends from one of two diagonal corners of a rectangular light-sensitive pixel 11 in a planar view to the other, but that extends so as not to overlap at least a portion of one of the diagonal lines, can also be considered a "diagonally arranged second isolation region 25."

[0087] Arranging the second isolation region 25 obliquely in this manner is advantageous for increasing the area and volume of the photodiode PD compared to when the second isolation region 25 is arranged in a different direction in plan view (for example, in a direction substantially parallel to one side of the first isolation region 24 in plan view). Therefore, the obliquely arranged second isolation region 25 is advantageous for increasing the amount of saturation signal charge of the photodiode PD that can be used as a phase difference detection pixel.

[0088] 3 extends from a portion of the first isolation region 24 located at the center of a second pixel unit PU2 (four light-receiving pixels 11) described below toward a portion of the first isolation region 24 located at the center of a first pixel unit PU1 (four light-receiving pixels 11) described below. However, each second isolation region 25 contacts the portion of the first isolation region 24 located at the center of the second pixel unit PU2, but does not contact the portion of the first isolation region 24 located at the center of the first pixel unit PU1.

[0089] This allows the P-type diffusion region PTAP to be shared among the four light-sensitive pixels 11 that make up the first pixel unit PU1, and also allows the floating diffusion FD to be shared among the four light-sensitive pixels 11 that make up the second pixel unit PU2, as will be described later. Furthermore, with respect to the four light-sensitive pixels 11 that make up the first pixel unit PU1, the same-color isolation implantation region SIR (described below) that is formed between the first isolation region 24 and the second isolation region 25 can be formed by a relatively simple process, which is advantageous in shortening the formation process time.

[0090] Each light-receiving pixel 11 has a P-type diffusion region PTAP, a same-color isolation implantation region SIR, and an overflow path OFP in a portion where the second isolation region 25 does not contact the first isolation region 24 in a planar view. More specifically, the P-type diffusion region PTAP, the same-color isolation implantation region SIR, and the overflow path OFP are provided in a corner of the first isolation region 24 that is diagonally opposite to the corner where the second isolation region 25 contacts, out of the four corners in a planar view. That is, the P-type diffusion region PTAP, the same-color isolation implantation region SIR, and the overflow path OFP are arranged in the region between the first isolation region 24 and the second isolation region 25.

[0091] 4, a same-color isolation implantation region SIR is formed in a partial region (e.g., a region of the silicon semiconductor layer 21) between the first isolation region 24 and the second isolation region 25 of the semiconductor substrate 20. An implantation region for the overflow path OFP is also formed in the same-color isolation implantation region SIR. A P-type diffusion region PTAP (including a P-type implantation region PTAPa and a P-type electrode PTAPb) is also formed on the bottom side (the side opposite to the light incident surface) of the same-color isolation implantation region SIR and the overflow path OFP.

[0092] Note that the specific methods for forming the P-type diffusion region PTAP, same-color isolation implantation region SIR, and overflow path OFP are not limited. For example, it is possible to form the P-type implantation region PTAPa by using PLAND (plasma doping). Furthermore, it is possible to form an implantation region for the overflow path OFP in the same-color isolation implantation region SIR by additionally using N-type doping (implantation process).

[0093] The same-color isolation implantation region SIR optically and electrically isolates a pair of photodiodes PD located adjacent to each other in each light-receiving pixel 11. On the other hand, the overflow path OFP electrically connects a pair of photodiodes PD separated by the second isolation region 25. Providing the overflow path OFP leads to suppression of a reduction in the volume of the photodiodes PD, and is advantageous for further increasing the saturation signal charge amount (Qs) of the photodiode PD of the phase difference detection pixel.

[0094] The P-type diffusion region PTAP (particularly the P-type electrode PTAPb (e.g., P-type polysilicon)) forms a ground contact, and one PTAP electrode VP connected to the ground (earth) and having a ground potential is electrically connected to each P-type electrode PTAPb. The P-type diffusion region PTAP has a P-type implantation region PTAPa provided in the semiconductor substrate 20, and a P-type electrode PTAPb connected to the P-type implantation region PTAPa. The P-type electrode PTAPb in this embodiment is not buried in the semiconductor substrate 20, but is provided on one surface of the semiconductor substrate 20.

[0095] 3 to 5, each light-receiving pixel 11 has a floating diffusion FD in a portion where, in plan view, the second isolation region 25 contacts the first isolation region 24. Each light-receiving pixel 11 also has a transfer gate TG for reading out the charges accumulated in the pair of photodiodes PD near the floating diffusion FD (i.e., near the portion where, in plan view, the second isolation region 25 contacts the first isolation region 24).

[0096] 5, the floating diffusion FD and the transfer gate TG are provided on the bottom side (upper side in FIG. 5) of the semiconductor substrate 20. In particular, the floating diffusion FD is shared by a plurality of (four) adjacent light-receiving pixels 11, as will be described later.

[0097] That is, an N-type implantation region (FD implantation region FDa) of the floating diffusion FD is formed in the semiconductor layer 21 (semiconductor substrate 20) of each light-receiving pixel 11. Furthermore, an FD electrode (e.g., N-type polysilicon) FDb of the floating diffusion FD is formed so as to span a plurality (four) of adjacent light-receiving pixels 11. As a result, the FD implantation regions FDa formed in a plurality (four) of adjacent light-receiving pixels 11 are connected to a single common FD electrode FDb. Since a single FD electrode VF is connected to each FD electrode FDb, a plurality (four) of adjacent light-receiving pixels 11 are electrically connected to a single common FD electrode VF via a single common FD electrode FDb.

[0098] In this embodiment, one P-type diffusion region PTAP (particularly, the P-type electrode PTAPb) is provided for four light-sensitive pixels (first pixel units PU1) arranged in a 2-pixel by 2-pixel array. Therefore, one common PTAP electrode (electrode for P-type diffusion region) VP electrically connected to the P-type diffusion region PTAP (particularly, the P-type electrode PTAPb) is provided for the four light-sensitive pixels 11 (first pixel units PU1) arranged adjacent to one another. In this way, one P-type diffusion region PTAP is shared by the four light-sensitive pixels 11 (first pixel units PU1).

[0099] 4 is a vertical via extending in a direction (up and down direction in FIGS. 4 and 5) perpendicular to the direction of extension of the pixel surface (for example, the left and right direction in FIGS. 4 and 5). Each PTAP electrode VP configured as a vertical via is electrically connected at one end to the P-type diffusion region PTAP (particularly the P-type electrode PTAPb) and at the other end to another wiring (not shown).

[0100] Furthermore, one common floating diffusion FD is provided for four light receiving pixels 11 (second pixel unit PU2) arranged in a 2 pixel by 2 pixel array, i.e., the four light receiving pixels 11 (second pixel unit PU2) share one common floating diffusion FD.

[0101] However, as shown in Figure 3, the four light-receiving pixels 11 (first pixel unit) that share one common PTAP electrode VP do not completely coincide with the four light-receiving pixels 11 (second pixel unit) that share one common floating diffusion FD.

[0102] In each light-receiving pixel 11, the P-type diffusion region PTAP and the floating diffusion FD are disposed at a diagonal position where one diagonal line of the first isolation region 24 (particularly the diagonal line along the second isolation region 25) passes in a plan view.

[0103] Furthermore, a transfer gate TG is provided for each of the pair of photodiodes PD near one of the four planar corners of the first isolation region 24 that is in contact with the second isolation region 25 (i.e., the corner where the floating diffusion FD is provided). This allows the distance between the overflow path OFP and the transfer gate TG in each light-sensitive pixel 11 to be set to be equal to or greater than the length of one side of each rectangular light-sensitive pixel 11 (length in planar view).

[0104] As described above, according to this embodiment, each second isolation region 25 is arranged along one diagonal of the first isolation region 24 in a plan view, contacting the first isolation region 24 at one end of the diagonal and not contacting the first isolation region 24 at the other end of the diagonal. A floating diffusion FD is provided in the region where the second isolation region 25 contacts the first isolation region 24. Meanwhile, a P-type diffusion region PTAP, a same-color isolation implantation region SIR, and an overflow path OFP are provided in the region where the second isolation region 25 does not contact the first isolation region 24.

[0105] This makes it possible to realize a configuration in which the P-type diffusion region PTAP is shared by a plurality (four) of light-receiving pixels 11 (first pixel unit PU1) and the floating diffusion FD is shared by a plurality (four) of light-receiving pixels 11 (second pixel unit PU2), thereby reducing the number of required wirings and improving the degree of freedom in wiring layout.

[0106] Furthermore, according to this embodiment, it is possible to create the same-color isolation implantation region SIR in units of multiple pixels (specifically, in units of four pixels constituting the first pixel unit PU1). For example, when creating the same-color isolation implantation region SIR in units of one pixel, particularly when creating a fine pattern that may cause pixel shrink, it is necessary to design the same-color isolation implantation region SIR wider than necessary due to process constraints, which raises concerns about the effects of ion seepage. On the other hand, when forming the same-color isolation implantation region SIR shared by multiple pixels, as in this embodiment, process constraints are alleviated. As a result, it is possible to suppress the seepage of ions (e.g., boron (B)), ensure an appropriate implantation region per pixel, and ensure an appropriate size of photodiode PD, thereby improving the saturation signal charge (Qs).

[0107] Furthermore, according to this embodiment, one end of the second isolation region 25 (the end on the side where the floating diffusion FD is provided in the example shown in FIG. 3 ) is in contact with the first isolation region 24. Therefore, the amount of ions (e.g., boron) for the second isolation region 25 that need to be implanted on the floating diffusion FD side can be reduced, and as a result, this embodiment is advantageous in ensuring a large area for the photodiode PD.

[0108] On the other hand, it is difficult to realize the beneficial configuration and effects of the present embodiment described above with a pixel array unit 10 (solid-state imaging device 1) having a conventional configuration.

[0109] For example, FIG. 3 of Japanese Patent Application Laid-Open No. 2021-97241 shows a pixel configuration in which the same-color separation structure (corresponding to the second separation region 25 in this embodiment) is not in contact with the different-color separation structure (corresponding to the first separation region 24 in this embodiment) at both ends. In such a pixel configuration, overflow may occur in a pair of photodiodes at both ends of the same-color separation structure, and the pixel design becomes more complex in order to appropriately control the overflow. Furthermore, the pixel configuration shown in FIG. 3 of Japanese Patent Application Laid-Open No. 2021-97241 requires a larger number of wirings than the above-described embodiment, thereby reducing the degree of freedom in the design of the wiring layer. Furthermore, electrical isolation processing such as implantation is required near both ends of the same-color separation structure to ensure its function as a phase difference detection pixel. However, creating a mask for such electrical isolation processing (such as implantation) is time-consuming.

[0110] [One Modification of First Embodiment] Fig. 6 is a plan view showing an example of the configuration of the light-receiving pixels 11 according to one modification of the first embodiment, and exemplifies 16 light-receiving pixels 11 (4 pixels x 4 pixels). In Fig. 6, elements that are the same as or correspond to those in the examples shown in Figs. 3 to 5 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0111] 3 to 5, other functional components may be provided on one semiconductor substrate 20. For example, at least some of the readout transistors, which are transistors for reading out the accumulated charges in the photodiodes PD of the plurality of light-receiving pixels 11, may be provided on the same semiconductor substrate 20 together with the photodiodes PD of the plurality of light-receiving pixels 11. The readout transistor referred to here is not limited to these, and the above-mentioned reset transistor RST, amplification transistor AMP, selection transistor SEL, and switching transistor FDG (see FIG. 2) may correspond to the readout transistor.

[0112] 6, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are shared by a plurality (four) of light receiving pixels 11 (second pixel unit PU2). That is, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are provided in each of the four light receiving pixels 11 that make up the second pixel unit PU2.

[0113] The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are arranged in a corner different from the P-type diffusion region PTAP and the floating diffusion FD in the corresponding light-receiving pixel 11. That is, of the four corners in a plan view of each light-receiving pixel 11, the corresponding pixel transistors RST, AMP, SEL, and FDG are provided in a corner through which the other diagonal end different from the one diagonal line along which the second isolation region 25 extends passes.

[0114] As described above, according to this modification, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are each shared by a plurality of (four) light-receiving pixels 11, thereby reducing the number of transistors.

[0115] In particular, by using the diagonally arranged second isolation region 25, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG can be shared by the four light-receiving pixels 11, resulting in a significant transistor reduction effect. Note that WO 2016 / 158439 discloses a pixel configuration in which phase difference detection pixels are separated by same-color isolation structures extending in the vertical direction (a direction parallel to one side of the pixel). In the pixel configuration of WO 2016 / 158439, various transistors are shared by two pixels, and the transistor reduction effect is smaller than in the modified example shown in FIG. 6 above.

[0116] [Second Embodiment] Fig. 7 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to a second embodiment, exemplarily showing 16 light-receiving pixels 11 (4 pixels x 4 pixels). Fig. 8 is a diagram showing an example cross-section of the light-receiving pixel 11 taken along the VIII-VIII cross-sectional line shown in Fig. 7. Fig. 9 is a diagram showing an example cross-section of the light-receiving pixel 11 taken along the IX-IX cross-sectional line shown in Fig. 7. Note that the FD electrode VF is omitted from Fig. 9.

[0117] In this embodiment, elements that are the same as or correspond to those in the first embodiment described above are given the same reference numerals, and detailed description thereof will be omitted.

[0118] In this embodiment, at least a portion of the P-type electrode PTAPb is embedded in the semiconductor substrate 20, and at least a portion of the FD electrode FDb is embedded in the semiconductor substrate 20. In the example shown in Figures 8 and 9, the entire P-type electrode PTAPb is embedded in the semiconductor substrate 20 (first isolation region 24), and the entire FD electrode FDb is embedded in the semiconductor substrate 20 (first isolation region 24 and second isolation region 25).

[0119] As an example, a part of the semiconductor substrate 20 may be removed before or after the P-type implantation region PTAPa is formed in the semiconductor substrate 20, and the P-type electrode PTAPb may be formed in the removed portion. Similarly, a part of the semiconductor substrate 20 may be removed before or after the FD implantation region FDa is formed in the semiconductor substrate 20, and the FD electrode FDb may be formed in the removed portion.

[0120] In this embodiment, the side surface of the P-type electrode PTAPb (particularly the portion buried in the semiconductor substrate 20) is in physical contact with and electrically connected to the P-type implantation region PTAPa. Similarly, the side surface of the FD electrode FDb (particularly the portion buried in the semiconductor substrate 20) is in physical contact with and electrically connected to the FD implantation region FDa.

[0121] 10 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a third embodiment, exemplifying four light-sensitive pixels 11 (2 pixels × 2 pixels; in particular, a first pixel unit PU1). Fig. 11 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XI-XI cross-sectional line shown in Fig. 10.

[0122] In this embodiment, elements that are the same as or correspond to those in the first embodiment described above are given the same reference numerals, and detailed description thereof will be omitted.

[0123] The pixel array unit 10 (solid-state imaging device 1) of this embodiment has third isolation regions 26 arranged to surround the P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa). The third isolation regions 26 optically and electrically isolate the corresponding P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa). The third isolation regions 26 can be made of any material, and may be made of a low-refractive-index dielectric material such as silicon oxide.

[0124] 10 and 11 , the third isolation region 26 is disposed adjacent to the P-type diffusion region PTAP (particularly the P-type implant region PTAPa), and is provided as STI (Shallow Trench Isolation) so as not to penetrate the semiconductor substrate 20. The third isolation region 26 shown in Fig. 10 has a hollow rectangular shape in a plan view, and extends so as to pass between the first isolation region 24 and the second isolation region 25 in the multiple (four) light-receiving pixels 11 (first pixel unit PU1) that share the corresponding P-type diffusion region PTAP.

[0125] According to this embodiment, the third isolation region 26 can prevent the P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) from diffusing into the semiconductor substrate 20 .

[0126] 12 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a fourth embodiment, exemplifying four light-sensitive pixels 11 (2 pixels × 2 pixels; in particular, a first pixel unit PU1). Fig. 13 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XIII-XIII cross-sectional line shown in Fig. 10.

[0127] In this embodiment, elements that are the same as or correspond to those in the second and third embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0128] Even when at least a portion of the P-type electrode PTAPb and / or the FD electrode FDb is buried in the semiconductor substrate 20 as in the second embodiment described above, it is possible to provide a third isolation region 26 arranged to surround the P-type diffusion region PTAP as in the third embodiment described above.

[0129] 12 and 13, each P-type electrode PTAPb and each FD electrode FDb are entirely buried in the semiconductor substrate 20. Then, a third isolation region 26 that optically and electrically isolates the corresponding P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) is provided in the semiconductor substrate 20 as an STI.

[0130] In this embodiment as well, the third isolation region 26 can prevent the P-type diffusion region PTAP from diffusing into the semiconductor substrate 20 .

[0131] [Fifth embodiment] This embodiment is one embodiment relating to a manufacturing method of a solid-state imaging element 1 (particularly an implantation region), and is also applicable to the manufacture of solid-state imaging elements 1 according to the embodiments described above and below, as well as solid-state imaging elements (photodetection devices) 1 having other configurations.

[0132] Fig. 14 is a plan view of an example of a semiconductor substrate 20 according to the fifth embodiment, showing the semiconductor substrate 20 in a state where the portions corresponding to the first isolation region 24 and the second isolation region 25 configured as FFTI are empty. Fig. 15 is a diagram showing an example cross section of the light-sensitive pixel 11 taken along the XV-XV cross section line shown in Fig. 14. Fig. 16 is a diagram showing an example cross section of the light-sensitive pixel 11 taken along the XVI-XVI cross section line shown in Fig. 14.

[0133] In this embodiment, elements that are the same as or correspond to those in the first to fourth embodiments described above are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0134] In this embodiment, a diagonally arranged second isolation region 25 is also used, but by utilizing the space before a substance (such as silicon oxide) is filled in the area corresponding to the second isolation region 25, an implantation region INP can be formed deep into the semiconductor substrate (e.g., silicon) 20 with high precision.

[0135] That is, it is possible to use so-called oblique implantation (ion implantation) when forming the implantation region INP in the semiconductor substrate 20. Oblique implantation is a technique for forming the implantation region INP by scattering ionized implantation material in an oblique direction (typically, "0°<tilt angle θ<90°") and implanting the implantation material into a target location in the semiconductor substrate 20.

[0136] Oblique implantation tends to be more advantageous than other common implantation techniques in suppressing the diffusion of ionized implanted materials, but is subject to the restriction that the implantable depth is determined by the allowable tilt angle θ. As is clear from Figures 15 and 16, the "tilt angle θ" is expressed by the angle formed by the flight direction of the implanted material with respect to a virtual reference line extending in a direction (up and down directions in Figures 15 and 16) perpendicular to the direction of expansion of the pixel surface (for example, the left and right directions in Figures 15 and 16).

[0137] According to this embodiment, the tilt angle θ of the oblique implantation can be made large by utilizing the space before the material is filled in the area corresponding to the obliquely arranged second isolation region 25 as a flight area for the ionized implanted material. Therefore, according to this embodiment, the oblique implantation can drive the implanted material deep into the semiconductor substrate 20.

[0138] 14 , in this embodiment in particular, the second isolation regions 25 of two diagonally adjacent light-sensitive pixels 11 extend linearly on the same straight line via the first isolation region 24. The space before the substance is filled into the locations corresponding to the second isolation regions 25 of the two light-sensitive pixels 11 and the intervening first isolation region 24 is used as a flight region for the injected substance, making it possible to implant the injected substance deeper into the semiconductor substrate 20.

[0139] When performing oblique implantation, regions of the semiconductor substrate 20 into which the implantation material is not to be implanted (see, for example, the regions indicated by the symbol "D1" in FIGS. 14 and 16) are protected by shadowing using a mask M. For example, as shown in FIGS. 15 and 16, when the mask M is placed on the entire surface (bottom surface) of the semiconductor substrate 20 (excluding the spatial portions corresponding to the first isolation region 24 and the second isolation region 25), the thickness (second distance D2) of the mask M is adjusted. That is, the thickness (height direction distance (second distance D2)) of the mask M is adjusted in accordance with the size (spreading direction distance) of the spatial portion corresponding to the first isolation region 24, the size (spreading direction distance (third distance D3)) of the spatial portion corresponding to the second isolation region 25, and the tilt angle θ.

[0140] The depth direction distance (fourth distance D4) of the implantation region INP can be adjusted according to the tilt angle θ that determines the flight angle of the ionized implantation material.

[0141] As the above-mentioned implantation region INP, for example, the above-mentioned P-type implantation region PTAPa, overflow path OFP, and same-color isolation implantation region SIR can be formed in the semiconductor substrate 20 by oblique implantation.

[0142] The method for manufacturing the solid-state imaging device (photodetector) 1 using the oblique implantation described above can include, for example, the following specific processing steps.

[0143] That is, a step of preparing the semiconductor substrate 20 in a state where the portions corresponding to the first isolation region 24 and the second isolation region 25 are empty is performed.

[0144] Thereafter, the ionized implantation material is passed through the portions of the space corresponding to the first isolation region 24 and the second isolation region 25, and then implanted into the semiconductor substrate 20.

[0145] Thereafter, a process is performed in which a substance is filled into the portions of the space corresponding to the first separation region 24 and the second separation region 25, thereby forming the first separation region 24 and the second separation region 25. The filling of the substance into the first separation region 24 and the second separation region 25 may be performed simultaneously or separately.

[0146] As described above, according to this embodiment, compared to the case where a same-color separation structure arranged in the vertical direction (see the above-mentioned WO 2016 / 158439) is used, it is possible to ensure a larger length (third distance D3) of the spatial portion corresponding to the obliquely arranged second separation region 25. This makes it possible to increase the tilt angle θ that is permissible in oblique implantation, and as a result, it is possible to implant the implantation substance deep into the semiconductor substrate 20 by oblique implantation.

[0147] Note that in the above example, "the space before the material is filled into the areas corresponding to the second isolation regions 25 of two diagonally adjacent light-sensitive pixels 11 and the area corresponding to the intervening first isolation region 24" is used as the flight region of the injected material, but this is not limited to this. For example, only "the space before the material is filled into the area corresponding to the second isolation region 25 of one light-sensitive pixel 11" may be used as the flight region of the injected material. In this case, too, by using the diagonally arranged second isolation region 25, it is possible to take a larger tilt angle θ of the diagonal implantation compared to when using same-color separation structures arranged vertically, and therefore the injected material can be implanted deeper into the semiconductor substrate 20.

[0148] Sixth Embodiment Fig. 17 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a sixth embodiment, exemplifying four light-sensitive pixels 11 (2 pixels x 2 pixels; in particular, a first pixel unit PU1). Fig. 18 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XVIII-XVIII cross section line shown in Fig. 17. Fig. 19 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XVIII-XVIII cross section line shown in Fig. 17. Fig. 20 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XX-XX cross section line shown in Fig. 17.

[0149] In this embodiment, elements that are the same as or correspond to those in the first to fifth embodiments described above are given the same reference numerals, and detailed description thereof will be omitted.

[0150] In the first to fourth embodiments described above, the transfer gate TG is provided in the vicinity of a corner (i.e., a corner where the floating diffusion FD is provided) of the four corners of the first isolation region 24 in a plan view that is in contact with the second isolation region 25 in each light-receiving pixel 11. On the other hand, the transfer gate TG of this embodiment is provided in two corners of the four corners of the first isolation region 24 in a plan view that are passed by a diagonal line different from one diagonal line along which the second isolation region 25 runs in each light-receiving pixel 11.

[0151] That is, transfer gates TG are provided in two corners, in which the floating diffusion FD, same-color isolation implantation region SIR, P-type diffusion region PTAP, and overflow path OFP are not provided, out of the four corners in plan view of the first isolation region 24. In this embodiment, two transfer gates TG are provided for each light-receiving pixel 11, one transfer gate TG is provided for each of a pair of photodiodes PD, and the transfer gates TG are not shared between the light-receiving pixels 11.

[0152] In the examples shown in FIGS. 17 to 20, the transfer gates TG between adjacent light-receiving pixels 11 are arranged adjacent to each other with the first isolation region 24 interposed therebetween.

[0153] The specific configuration of the transfer gate TG is not limited, and for example, a planar type transfer gate TG (see FIG. 18) or a vertical type (trench type) transfer gate TG (see FIG. 19) may be provided.

[0154] 18 , a transfer electrode (e.g., N-type polysilicon) TGa, which is an electrode of a transfer gate TG, is disposed on a flat surface of a semiconductor layer 21 of a semiconductor substrate 20 via a gate insulating film 30. Therefore, in the planar type transfer gate TG, the entire transfer electrode TGa is provided so as to protrude outward beyond the semiconductor layer 21.

[0155] On the other hand, in the vertical type, at least a part of the transfer electrode TGa arranged on the semiconductor layer 21 via the gate insulating film 30 is buried in the semiconductor layer 21. The transfer electrode TGa in the example shown in FIG. 19 includes a part buried in the semiconductor layer 21 and a part provided so as to protrude outward from the semiconductor layer 21.

[0156] 18 and 19 is a vertical via extending in a direction perpendicular to the pixel surface (the up-and-down direction in FIGS. 18 and 19), and is electrically connected to the transfer electrode TGa at one end and to another wiring (for example, an upper layer wiring) at the other end.

[0157] In the example shown in FIG. 20, an insulating film 31 is provided on the second isolation region 25 .

[0158] As described above, according to this embodiment, the transfer gate TG is provided at a diagonal position different from the diagonal position through which one diagonal line (particularly the diagonal line passing through the floating diffusion FD and the P-type diffusion region PTAP) passes in each of the light-receiving pixels 11. In other words, separate transfer gates TG are provided at the respective corners of the pair of photodiodes PD in each of the light-receiving pixels 11.

[0159] With this arrangement, the transfer gate TG is arranged at a corner different from the corner where the overflow path OFP and the floating diffusion FD are provided. Therefore, this embodiment is advantageous in increasing the distance between each transfer gate TG and the overflow path OFP, and also in increasing the distance between each transfer gate TG and the floating diffusion FD.

[0160] The voltage change of the transfer gate TG can be relatively large, and the overflow path OFP is affected by the voltage change (and thus the electric field change) of the transfer gate TG. Therefore, increasing the distance between each transfer gate TG and the overflow path OFP is advantageous for stabilizing the state of the overflow path OFP. Similarly, since the floating diffusion FD is affected by the voltage change of the transfer gate TG, increasing the distance between each transfer gate TG and the floating diffusion FD is advantageous for stabilizing the state of the floating diffusion FD.

[0161] 17, each transfer electrode TGa of each light-receiving pixel 11 extends toward the corner where the floating diffusion FD is installed, but may extend in another direction (for example, toward the overflow path OFP). Furthermore, the position of the TG electrode VT on each transfer electrode TGa is not limited, and the TG electrodes VT between adjacent light-receiving pixels 11 may be spaced apart by a relatively large distance.

[0162] However, from the viewpoint of reducing interference of the transfer gate TG with the floating diffusion FD and the overflow path OFP, it is preferable that the distance between each of the floating diffusion FD and the overflow path OFP and each of the transfer electrodes TGa is large. From the same viewpoint, it is also preferable that the distance between each of the floating diffusion FD and the overflow path OFP and each of the TG electrodes VT is large.

[0163] [One Modification of Sixth Embodiment] Fig. 21 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to one modification of the sixth embodiment, exemplifying four light-sensitive pixels 11 (2 pixels x 2 pixels; in particular, the first pixel unit PU1). Fig. 22 is a diagram showing an example cross section of the light-sensitive pixel 11 taken along the XXII-XXII cross section line shown in Fig. 21.

[0164] In this embodiment, elements that are the same as or correspond to those in the first to sixth embodiments described above are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0165] The pixel array unit 10 (solid-state imaging device 1) of this embodiment has third isolation regions 26 arranged to surround the P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), similar to the third embodiment (see FIGS. 10 and 11 ). The third isolation regions 26 optically and electrically isolate the corresponding P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), and can be made of any material, such as a low-refractive-index dielectric material, such as silicon oxide.

[0166] 21 and 22 , the third isolation region 26 is disposed adjacent to the P-type diffusion region PTAP (particularly the P-type implant region PTAPa), and is provided as STI (Shallow Trench Isolation) so as not to penetrate the semiconductor substrate 20. The third isolation region 26 shown in Fig. 21 has a hollow rectangular shape in a plan view, and extends so as to pass between the first isolation region 24 and the second isolation region 25 in the multiple (four) light-receiving pixels 11 (i.e., each first pixel unit PU1) that share the corresponding P-type diffusion region PTAP.

[0167] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIGS. 21 and 22 are similar to those of the pixel array section 10 of the sixth embodiment (see FIGS. 17 to 20).

[0168] According to this embodiment, the third isolation region 26 can prevent the P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) from diffusing into the semiconductor substrate 20 .

[0169] Seventh Embodiment Fig. 23 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a seventh embodiment, exemplifying four light-sensitive pixels 11 (2 pixels x 2 pixels; in particular, a first pixel unit PU1). Fig. 24 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XXIV-XXIV cross section line shown in Fig. 23. Fig. 25 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XXIV-XXIV cross section line shown in Fig. 23. Fig. 26 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XXIV-XXIV cross section line shown in Fig. 23.

[0170] In this embodiment, the transfer gates TG (TG1 to TG4) are shared by a plurality of adjacently arranged light-receiving pixels 11. In the example shown in FIG. 23, one transfer gate TG is provided for two adjacent light-receiving pixels 11. In FIG. 23 and FIG. 27 described below, the four transfer gates provided in the first pixel unit PU1 are respectively labeled with the symbols "TG1" to "TG4." However, when it is not necessary to distinguish between these four transfer gates TG1 to TG4 or when describing content common to the four transfer gates TG1 to TG4 (see FIGS. 24 to 26), the transfer gates are labeled with the symbol "TG."

[0171] As in the sixth embodiment (see FIGS. 17 to 20 ), the transfer gates TG of this embodiment are provided in two corners, in plan view, of the four corners of the first isolation region 24 in each light-receiving pixel 11, through which a diagonal line different from one diagonal line along which the second isolation region 25 runs passes. In particular, since one transfer gate TG is shared by two light-receiving pixels 11, the transfer gate TG (particularly the transfer electrode TGa) is provided so as to straddle the portion of the first isolation region 24 located between the two light-receiving pixels 11.

[0172] However, the specific configuration of the transfer gate TG is not limited, and for example, a planar type transfer gate TG (see FIG. 24) may be provided, a double vertical type transfer gate TG (see FIG. 25) may be provided, or a single vertical type transfer gate TG (see FIG. 26) may be provided.

[0173] 24 , the transfer electrode TGa of the transfer gate TG is disposed on the flat surface of the semiconductor layer 21 of the semiconductor substrate 20 via the gate insulating film 30. Therefore, in the planar type transfer gate TG, the entire transfer electrode TGa is provided so as to protrude outward beyond the semiconductor layer 21.

[0174] On the other hand, in the vertical type (including the double vertical type and the single vertical type), at least a portion of the transfer electrode TGa disposed on the semiconductor layer 21 via the gate insulating film 30 is embedded in the semiconductor layer 21. The transfer electrode TGa in the example shown in FIG. 25 (double vertical type) and the example shown in FIG. 26 (single vertical type) includes a portion embedded in the semiconductor layer 21 and a portion provided so as to protrude outward from the semiconductor layer 21. In the double vertical type (see FIG. 25), a portion of the first isolation region 24 is positioned between two transfer electrode TGa portions embedded in the semiconductor layer 21. On the other hand, in the single vertical type (see FIG. 26), the transfer electrode TGa portions embedded in the semiconductor layer 21 and the first isolation region 24 are arranged in series in the vertical direction (a direction perpendicular to the pixel surface (the up-and-down direction in FIGS. 25 and 26)).

[0175] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIG. 23 are similar to those of the pixel array section 10 of the sixth embodiment (see FIG. 17).

[0176] Fig. 27 is a diagram showing an example of a pixel circuit according to the seventh embodiment. Note that "PD1A," "PD1B," "PD2A," "PD2B," "PD3A," "PD3B," "PD4A," and "PD4B" shown in Fig. 27 correspond to the pairs of photodiodes PD of the four light-receiving pixels 11 (first pixel unit PU1) shown in Fig. 23, respectively.

[0177] The pixel array section 10 (solid-state imaging device 1) shown in FIG. 23 can have, for example, a pixel circuit configuration shown in FIG.

[0178] 27, a first selection transistor SEL1 is connected to a first vertical signal line VSL1 (see "vertical pixel wiring LV" in FIG. 1), and a pair of photodiodes PD1A and PD1B of one light-receiving pixel 11 are also connected to the first vertical signal line VSL1 (see "vertical pixel wiring LV" in FIG. 1). The pair of photodiodes PD1A and PD1B are connected to the first vertical signal line VSL1 via a first floating diffusion FD1.

[0179] Similarly, the second selection transistor SEL2, the third floating diffusion FD3, and the pair of photodiodes PD3A and PD3B are connected to the second vertical signal line VSL2. The third selection transistor SEL3, the second floating diffusion FD2, and the pair of photodiodes PD2A and PD2B are connected to the third vertical signal line VSL3. The fourth selection transistor SEL4, the fourth floating diffusion FD4, and the pair of photodiodes PD4A and PD4B are connected to the fourth vertical signal line VSL4.

[0180] A power supply voltage VDD is connected to each of the first to fourth vertical signal lines VSL1 to VSL4. Meanwhile, ground GND is connected to each of the pairs of photodiodes PD1A, PD1B, PD2A, PD2B, PD3A, PD3B, PD4A, and PD4B. A reset transistor RST is connected to each of the first to fourth floating diffusions FD1 to FD4.

[0181] Each of the transfer gates TG1, TG2, TG3, and TG4 is connected to two photodiodes positioned adjacent to each other, but the two photodiodes connected belong to different light-receiving pixels 11. That is, the first transfer gate TG1 is connected to the photodiode PD4B and the photodiode PD1A, and the second transfer gate TG2 is connected to the photodiode PD1B and the photodiode PD2A. The third transfer gate TG3 is connected to the photodiode PD2B and the photodiode PD3A, and the fourth transfer gate TG4 is connected to the photodiode PD3B and the photodiode PD4A.

[0182] According to the pixel circuit of FIG. 27 having the above-described configuration, it is possible to read out pixel signals from the four light-sensitive pixels 11 that make up each of the first pixel units PU1, for example, by the following method.

[0183] First, the first transfer gate TG1 and the third transfer gate TG3 are simultaneously turned ON, while the second transfer gate TG2 and the fourth transfer gate TG4 are simultaneously turned OFF. Then, while the ON / OFF states of the first transfer gate TG1 to the fourth transfer gate TG4 are maintained, the first selection transistor SEL1 to the fourth selection transistor SEL4 are simultaneously turned ON. As a result, pixel signals are read out from the photodiodes PD1A, PD4B, PD2B, and PD3A.

[0184] Thereafter, the reset transistor RST is turned ON, and the potentials of the first to fourth floating diffusions FD1 to FD4 are reset to predetermined potentials.

[0185] Meanwhile, simultaneously, the first transfer gate TG1 and the third transfer gate TG3 are turned OFF, while the second transfer gate TG2 and the fourth transfer gate TG4 are turned ON. Then, while the ON / OFF states of the first transfer gate TG1 to the fourth transfer gate TG4 are maintained, the first selection transistor SEL1 to the fourth selection transistor SEL4 are simultaneously turned ON. As a result, pixel signals are read out from the photodiodes PD1B, PD2A, PD3B, and PD4A.

[0186] Thereafter, the reset transistor RST is turned ON, and the potentials of the first to fourth floating diffusions FD1 to FD4 are reset to predetermined potentials.

[0187] As described above, according to this embodiment, one transfer gate TG (particularly, at least a part of the transfer electrode TGa and the TG electrode VT) is shared by a plurality of light-receiving pixels 11. This reduces the number of required wirings, thereby improving the degree of freedom in wiring layout.

[0188] Each transfer gate TG is electrically connected to one TG electrode (transfer gate electrode) VT. Each TG electrode VT is a vertical via extending in a direction perpendicular to the pixel surface, and is electrically connected to the transfer gate TG (particularly the transfer electrode TGa) at one end and to another wiring (not shown) at the other end.

[0189] 23, the TG electrodes VT connected to the transfer electrodes TGa are provided at positions overlapping the first isolation regions 24 in plan view, but may be provided at other positions (for example, positions not overlapping the first isolation regions 24 in plan view). However, from the viewpoint of reducing interference of the TG electrodes VT with the floating diffusions FD and overflow paths OFP, it is preferable that the distance between each of the floating diffusions FD and overflow paths OFP and the TG electrodes VT is large.

[0190] [One Modification of Seventh Embodiment] Fig. 28 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to one modification of the seventh embodiment, exemplifying four light-sensitive pixels 11 (2 pixels x 2 pixels; in particular, the first pixel unit PU1). Fig. 29 is a diagram showing an example cross section of the light-sensitive pixel 11 taken along the XXIX-XXIX cross-sectional line shown in Fig. 28.

[0191] In this embodiment, elements that are the same as or correspond to those in the first to seventh embodiments described above are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0192] The pixel array unit 10 (solid-state imaging device 1) of this embodiment has third isolation regions 26 arranged to surround the P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), similar to the third embodiment (see FIGS. 10 and 11 ). The third isolation regions 26 optically and electrically isolate the corresponding P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), and can be made of any material, such as a low-refractive-index dielectric material, such as silicon oxide.

[0193] 28 and 29 , the third isolation region 26 is arranged adjacent to the P-type diffusion region PTAP (particularly the P-type implant region PTAPa), and is installed as STI (Shallow Trench Isolation) so as not to penetrate the semiconductor substrate 20. The third isolation region 26 shown in Fig. 28 has a hollow rectangular shape in a plan view, and extends so as to pass between the first isolation region 24 and the second isolation region 25 in the multiple (four) light-receiving pixels 11 (i.e., each first pixel unit PU1) that share the corresponding P-type diffusion region PTAP.

[0194] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIGS. 28 and 29 are similar to those of the pixel array section 10 of the seventh embodiment (see FIGS. 23 to 27).

[0195] According to this embodiment, the third isolation region 26 can prevent the P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) from diffusing into the semiconductor substrate 20 .

[0196] Eighth Embodiment Fig. 30 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to an eighth embodiment, exemplifying four light-receiving pixels 11 (2 pixels x 2 pixels; in particular, a first pixel unit PU1). Fig. 31 is a diagram showing an example of a cross section of the light-receiving pixel 11 taken along the XXXI-XXXI cross section line shown in Fig. 30. Fig. 32 is a diagram showing another example of a cross section of the light-receiving pixel 11 taken along the XXXI-XXXI cross section line shown in Fig. 30. Fig. 33 is a diagram showing an example of a cross section of the light-receiving pixel 11 taken along the XXXIII-XXXIII cross section line shown in Fig. 30.

[0197] In the above-described embodiments (particularly the first to fourth, sixth and seventh embodiments), a floating diffusion FD is provided at a corner diagonally opposite to the corner where the overflow path OFP, same-color isolation implantation region SIR and P-type diffusion region PTAP are provided, whereas in the present embodiment, a transfer gate TG is provided at the diagonal corner.

[0198] 30 , two transfer gates TG are provided at corners diagonally opposite to the corner where the overflow path OFP, the same-color isolation implantation region SIR, and the P-type diffusion region PTAP are provided in each light-receiving pixel 11. The two transfer gates TG are assigned to each of the pair of photodiodes PD, and are provided separated from each other via a second isolation region 25.

[0199] In this way, since a unique transfer gate TG is provided for each of the pair of photodiodes PD, the transfer gate TG (e.g., the transfer electrode TGa) is not installed on the second isolation region 25 that separates the pair of photodiodes PD from each other (see Figures 31 to 33).

[0200] The specific configuration of the transfer gate TG is not limited, and for example, a planar type transfer gate TG (see FIG. 31) or a vertical type transfer gate TG (see FIG. 32) may be provided.

[0201] 31 , the transfer electrode TGa of the transfer gate TG is disposed on the flat surface of the semiconductor layer 21 of the semiconductor substrate 20 via the gate insulating film 30. Therefore, in the planar type transfer gate TG, the entire transfer electrode TGa is provided so as to protrude outward beyond the semiconductor layer 21.

[0202] On the other hand, in the vertical type, at least a part of the transfer electrode TGa arranged on the semiconductor layer 21 via the gate insulating film 30 is buried in the semiconductor layer 21. The transfer electrode TGa in the example shown in FIG. 32 includes a part buried in the semiconductor layer 21 and a part provided so as to protrude outward from the semiconductor layer 21.

[0203] In this embodiment, the floating diffusions FD are provided in two corners, as viewed in a plan view, of the four corners of the first isolation region 24 in each light-sensitive pixel 11, through which a diagonal line different from one diagonal line along which the second isolation region 25 runs passes. That is, of the four corners of the first isolation region 24 in a plan view, the floating diffusions FD are provided in two corners where the transfer gate TG, the same-color isolation implantation region SIR, the P-type diffusion region PTAP, and the overflow path OFP are not provided. In this embodiment, two floating diffusions FD are provided for each light-sensitive pixel 11, and a separate floating diffusion FD is assigned to each of the pair of photodiodes PD.

[0204] 30 , the floating diffusion FD is shared between adjacent light receiving pixels 11 (specifically, four light receiving pixels 11). That is, each floating diffusion FD is arranged so as to overlap with a portion of the first isolation region 24 located in the center of four light receiving pixels 11 arranged in a 2-pixel by 2-pixel matrix, and is provided so as to straddle the four light receiving pixels 11. Each floating diffusion FD is shared by only one of a pair of photodiodes PD in each of the corresponding four light receiving pixels 11.

[0205] As described above, according to this embodiment, the transfer gate TG is provided at a diagonal location of the light-sensitive pixel 11, where one diagonal line along which the second isolation region 25 extends passes, but where the overflow path OFP is not provided. Therefore, this embodiment is advantageous in increasing the distance between each transfer gate TG and the overflow path OFP.

[0206] Furthermore, in this embodiment, the floating diffusion FD is provided at a diagonal location where the other diagonal line of the light-receiving pixel 11 passes, so that the distance between each transfer gate TG and the floating diffusion FD is prevented from becoming short.

[0207] In this way, by arranging each transfer gate TG at a relatively long distance from the overflow path OFP and the floating diffusion FD, the influence of voltage changes (and hence electric field changes) on the transfer gate TG on these can be suppressed, and therefore this embodiment is advantageous in stabilizing the states of the overflow path OFP and the floating diffusion FD.

[0208] [One Modification of Eighth Embodiment] Fig. 34 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to one modification of the eighth embodiment, exemplifying four light-sensitive pixels 11 (2 pixels x 2 pixels; in particular, the first pixel unit PU1). Fig. 35 is a diagram showing an example cross section of the light-sensitive pixel 11 taken along the XXXV-XXXV cross section line shown in Fig. 34.

[0209] In this embodiment, elements that are the same as or correspond to those in the first to eighth embodiments described above are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0210] The pixel array unit 10 (solid-state imaging device 1) of this embodiment has third isolation regions 26 arranged to surround the P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), similar to the third embodiment (see FIGS. 10 and 11 ). The third isolation regions 26 optically and electrically isolate the corresponding P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), and can be made of any material, such as a low-refractive-index dielectric material, such as silicon oxide.

[0211] 34 and 35 , the third isolation region 26 is arranged so as to be adjacent to the P-type diffusion region PTAP (particularly the P-type implant region PTAPa), and is installed as STI (Shallow Trench Isolation) so as not to penetrate the semiconductor substrate 20. The third isolation region 26 shown in Fig. 34 has a hollow rectangular shape in a plan view, and extends so as to pass between the first isolation region 24 and the second isolation region 25 in the multiple (four) light-receiving pixels 11 (i.e., each first pixel unit PU1) that share the corresponding P-type diffusion region PTAP.

[0212] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIGS. 34 and 35 are similar to those of the pixel array section 10 of the above-described eighth embodiment (see FIGS. 30 to 33).

[0213] According to this embodiment, the third isolation region 26 can prevent the P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) from diffusing into the semiconductor substrate 20 .

[0214] Ninth Embodiment FIG. 36 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a ninth embodiment, exemplarily showing four light-sensitive pixels 11 (2 pixels × 2 pixels; in particular, a first pixel unit PU1). FIG. 37 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XXXVII-XXXVII cross section line shown in FIG. 36. FIG. 38 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XXXVII-XXXVII cross section line shown in FIG. 36. FIG. 39 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XXXVII-XXXVII cross section line shown in FIG. 36. FIG. 40 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XL-XL line shown in FIG. 36. FIG. 41 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XL-XL line shown in FIG. 36.

[0215] In this embodiment, the transfer gates TG (TG1 to TG4) are shared by a pair of photodiodes PD arranged adjacent to each other in each light-receiving pixel 11. In the example shown in FIG. 36, one transfer gate TG is provided for each pair of adjacent photodiodes PD in each light-receiving pixel 11. Note that in FIG. 36 and FIG. 42, which will be described later, the four transfer gates provided in the first pixel unit PU1 are each assigned the symbols "TG1" to "TG4." However, when it is not necessary to distinguish between these four transfer gates TG1 to TG4 or when describing content common to the four transfer gates TG1 to TG4 (see FIGS. 37 to 41), the transfer gates are assigned the symbol "TG."

[0216] As in the above-described eighth embodiment (see FIGS. 30 to 33 ), the transfer gate TG of this embodiment is provided in one of the four corners of the first isolation region 24 in plan view in each light-receiving pixel 11, at a corner through which passes one diagonal line along which the second isolation region 25 extends. That is, in each light-receiving pixel 11, one transfer gate TG is disposed at the corner where the second isolation region 25 abuts the first isolation region 24. In particular, since one transfer gate TG is shared by a pair of photodiodes PD in each light-receiving pixel 11, the one transfer gate TG (particularly the transfer electrode TGa) is provided so as to straddle the second isolation region 25 located between the pair of photodiodes PD.

[0217] However, the specific configuration of the transfer gate TG is not limited, and for example, a planar type transfer gate TG (see Figure 37) may be provided, a double vertical type transfer gate TG (see Figure 38) may be provided, or a single vertical type transfer gate TG (see Figure 39) may be provided.

[0218] 37 , the transfer electrode TGa of the transfer gate TG is disposed on the flat surface of the semiconductor layer 21 of the semiconductor substrate 20 via the gate insulating film 30. Therefore, in the planar type transfer gate TG, the entire transfer electrode TGa is provided so as to protrude outward beyond the semiconductor layer 21.

[0219] On the other hand, in the vertical type (including the double vertical type and the single vertical type), at least a portion of the transfer electrode TGa disposed on the semiconductor layer 21 via the gate insulating film 30 is buried in the semiconductor layer 21. The transfer electrode TGa in the example shown in FIG. 38 (double vertical type) and the example shown in FIG. 39 (single vertical type) includes a portion buried in the semiconductor layer 21 and a portion provided so as to protrude outward from the semiconductor layer 21. In the double vertical type (see FIG. 38), a portion of the first isolation region 24 is positioned between two transfer electrode TGa portions buried in the semiconductor layer 21. On the other hand, in the single vertical type (see FIG. 39), the transfer electrode TGa portions buried in the semiconductor layer 21 and the first isolation region 24 are arranged in series in the vertical direction (a direction perpendicular to the pixel surface (the up-and-down direction in FIGS. 38 and 39)).

[0220] 40 corresponds to FIG. 37 (planar type transfer gate TG) or FIG. 38 (double vertical type transfer gate TG), and FIG. 41 corresponds to FIG. 39 (single vertical type transfer gate TG).

[0221] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIG. 36 are similar to those of the pixel array section 10 of the above-described eighth embodiment (see FIGS. 30 to 33).

[0222] Fig. 42 is a diagram showing an example of a pixel circuit according to the ninth embodiment. Note that "PD1A," "PD1B," "PD2A," "PD2B," "PD3A," "PD3B," "PD4A," and "PD4B" shown in Fig. 42 correspond to the pairs of photodiodes PD of the four light-receiving pixels 11 (first pixel unit PU1) shown in Fig. 36, respectively.

[0223] The pixel array section 10 (solid-state imaging device 1) shown in FIG. 36 can have, for example, a pixel circuit configuration shown in FIG.

[0224] The pixel circuit shown in FIG. 42 basically has the same configuration as the pixel circuit (seventh embodiment) shown in FIG. 27 described above, but the connection relationship between the transfer gates TG1 to TG4 and the photodiodes is different from that of the pixel circuit in FIG. 27.

[0225] That is, each of the transfer gates TG1, TG2, TG3, and TG4 is connected to a pair of photodiodes PD (i.e., a pair of photodiodes PD adjacent to each other via the second isolation region 25) of the corresponding light-receiving pixel 11. Specifically, the first transfer gate TG1 is connected to the photodiode PD1A and the photodiode PD1B, and the second transfer gate TG2 is connected to the photodiode PD2A and the photodiode PD2B. The third transfer gate TG3 is connected to the photodiode PD3A and the photodiode PD3B, and the fourth transfer gate TG4 is connected to the photodiode PD4A and the photodiode PD4B.

[0226] According to the pixel circuit of FIG. 42 having the above-described configuration, it is possible to read out pixel signals from the four light-sensitive pixels 11 that make up each of the first pixel units PU1, for example, by the following method.

[0227] First, the first transfer gate TG1 and the third transfer gate TG3 are simultaneously turned ON, while the second transfer gate TG2 and the fourth transfer gate TG4 are simultaneously turned OFF. Then, while the ON / OFF states of the first transfer gate TG1 to the fourth transfer gate TG4 are maintained, the first selection transistor SEL1 to the fourth selection transistor SEL4 are simultaneously turned ON. As a result, pixel signals are read out from the photodiodes PD1A, PD1B, PD3A, and PD3B.

[0228] Thereafter, the reset transistor RST is turned ON, and the potentials of the first to fourth floating diffusions FD1 to FD4 are reset to predetermined potentials.

[0229] Meanwhile, simultaneously, the first transfer gate TG1 and the third transfer gate TG3 are turned OFF, while the second transfer gate TG2 and the fourth transfer gate TG4 are turned ON. Then, while the ON / OFF states of the first transfer gate TG1 to the fourth transfer gate TG4 are maintained, the first selection transistor SEL1 to the fourth selection transistor SEL4 are simultaneously turned ON. As a result, pixel signals are read out from the photodiodes PD2A, PD2B, PD4A, and PD4B.

[0230] Thereafter, the reset transistor RST is turned ON, and the potentials of the first to fourth floating diffusions FD1 to FD4 are reset to predetermined potentials.

[0231] As described above, according to this embodiment, each transfer gate TG (particularly at least a part of the transfer electrode TGa and the TG electrode VT) is shared by a pair of photodiodes PD of one light-receiving pixel 11. This reduces the number of required wirings, thereby improving the degree of freedom in wiring layout.

[0232] 36, the TG electrode VT connected to the transfer electrode TGa is provided at a position overlapping the second isolation region 25 in a plan view, but may be provided at another position (for example, a position not overlapping the second isolation region 25 in a plan view). However, from the viewpoint of reducing interference of the TG electrode VT with the floating diffusion FD and the overflow path OFP, it is preferable that the distance between each of the floating diffusion FD and the overflow path OFP and the TG electrode VT is large.

[0233] [One Modification of the Ninth Embodiment] Fig. 43 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to one modification of the ninth embodiment, and exemplarily shows four light-sensitive pixels 11 (2 pixels x 2 pixels; particularly a first pixel unit PU1). Fig. 44 is a diagram showing an example of a cross section of the light-sensitive pixel 11 (particularly a planar type (see Fig. 37) or double vertical type (see Fig. 38) transfer gate TG) along the XLIV-XLIV cross section line shown in Fig. 43. Fig. 45 is a diagram showing another example of a cross section of the light-sensitive pixel 11 (particularly a single vertical type (see Fig. 39) transfer gate TG) along the XLIV-XLIV cross section line shown in Fig. 43.

[0234] In this embodiment, elements that are the same as or correspond to those in the first to ninth embodiments described above are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0235] The pixel array unit 10 (solid-state imaging device 1) of this embodiment has third isolation regions 26 arranged to surround the P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), similar to the third embodiment (see FIGS. 10 and 11 ). The third isolation regions 26 optically and electrically isolate the corresponding P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), and can be made of any material, such as a low-refractive-index dielectric material, such as silicon oxide.

[0236] 43 to 45 , the third isolation region 26 is disposed adjacent to the P-type diffusion region PTAP (particularly the P-type implant region PTAPa), and is installed as STI (Shallow Trench Isolation) so as not to penetrate the semiconductor substrate 20. The third isolation region 26 shown in Fig. 43 has a hollow rectangular shape in a plan view, and extends so as to pass between the first isolation region 24 and the second isolation region 25 in the multiple (four) light-receiving pixels 11 (i.e., each first pixel unit PU1) that share the corresponding P-type diffusion region PTAP.

[0237] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIGS. 43 to 45 are similar to those of the pixel array section 10 of the above-described ninth embodiment (see FIGS. 36 to 42).

[0238] According to this embodiment, the third isolation region 26 can prevent the P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) from diffusing into the semiconductor substrate 20 .

[0239] Tenth Embodiment FIG. 46 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a tenth embodiment, exemplifying four light-sensitive pixels 11 (2 pixels × 2 pixels; in particular, the third pixel unit PU3). FIG. 47 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the XLVII-XLVII cross section line shown in FIG. 46. FIG. 48 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XLVII-XLVII cross section line shown in FIG. 46. FIG. 49 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the XLVII-XLVII cross section line shown in FIG. 46. FIG. 50 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the L-L cross section line shown in FIG. 46. FIG. 51 is a diagram showing another example of a cross section of the light-sensitive pixel 11 taken along the L-L cross section line shown in FIG. 46.

[0240] In each light-receiving pixel 11, the transfer gate TG of this embodiment is provided at one corner (particularly the corner where the second isolation region 25 contacts the first isolation region 24) of the four corners of the first isolation region 24 in a plan view, through which one diagonal line along which the second isolation region 25 runs. In particular, the transfer gate TG is shared by a pair of photodiodes PD arranged adjacent to each other in each light-receiving pixel 11, and is also shared by multiple (four) adjacent light-receiving pixels 11.

[0241] 46 , one transfer gate TG is provided for a third pixel unit PU3 configured by four light receiving pixels 11 arranged in a 2×2 matrix. Each transfer gate TG is arranged so as to overlap, in plan view, with a portion of the first isolation region 24 located in the center of the four light receiving pixels 11 of the third pixel unit PU3, and is provided so as to straddle the four light receiving pixels 11. The transfer electrode TGa of the transfer gate TG shown in FIG. 46 has a cross shape in plan view extending along the first isolation region 24, and the TG electrode VT connected to the transfer electrode TGa is arranged so as to overlap with a portion of the first isolation region 24 located in the center of the third pixel unit PU3.

[0242] 46 , each TG electrode VT may be disposed so as not to overlap with the portion of the first isolation region 24 located at the center of the third pixel unit PU3. Thus, the degree of freedom in the layout of the TG electrodes VT on the transfer electrode TGa is relatively high. Therefore, for example, the arrangement of each TG electrode VT may be determined so that the distance between each TG electrode VT and the floating diffusion FD is equal to or greater than half the length (planar length) of one side of the rectangular light-receiving pixel 11.

[0243] The specific configuration of the transfer gate TG is not limited, and for example, a planar type transfer gate TG (see FIG. 47) may be provided, a double vertical type transfer gate TG (see FIG. 48) may be provided, or a single vertical type transfer gate TG (see FIG. 49) may be provided.

[0244] 47 , the transfer electrode TGa of the transfer gate TG is disposed on the flat surface of the semiconductor layer 21 of the semiconductor substrate 20 via the gate insulating film 30. Therefore, in the planar type transfer gate TG, the entire transfer electrode TGa is provided so as to protrude outward beyond the semiconductor layer 21.

[0245] On the other hand, in the vertical type (including the double vertical type and the single vertical type), at least a portion of the transfer electrode TGa disposed on the semiconductor layer 21 via the gate insulating film 30 is buried in the semiconductor layer 21. The transfer electrode TGa in the example shown in FIG. 48 (double vertical type) and the example shown in FIG. 49 (single vertical type) includes a portion buried in the semiconductor layer 21 and a portion provided so as to protrude outward from the semiconductor layer 21. In the double vertical type (see FIG. 48), a portion of each of the first isolation region 24 and the second isolation region 25 is positioned between the two transfer electrode TGa portions buried in the semiconductor layer 21. On the other hand, in the single vertical type (see FIG. 49), the transfer electrode TGa portion buried in the semiconductor layer 21 and the first isolation region 24 and the second isolation region 25 are arranged in series in the vertical direction (a direction perpendicular to the pixel surface (the up-and-down direction in FIGS. 48 and 49)).

[0246] 50 corresponds to FIG. 47 (planar type transfer gate TG) or FIG. 48 (double vertical type transfer gate TG), and FIG. 51 corresponds to FIG. 49 (single vertical type transfer gate TG).

[0247] In each light-receiving pixel 11, the floating diffusions FD are provided near two of the four corners of the first isolation region 24 in a plan view, where one diagonal line different from the other diagonal line along which the second isolation region 25 runs passes. That is, of the four corners of the first isolation region 24 in a plan view, the floating diffusions FD are provided near two corners where the transfer gate TG, the same-color isolation implantation region SIR, the P-type diffusion region PTAP, and the overflow path OFP are not provided. In this embodiment, two floating diffusions FD are provided for each light-receiving pixel 11, and a separate floating diffusion FD is assigned to each of the pair of photodiodes PD of each light-receiving pixel 11.

[0248] 46 , two floating diffusions FD are provided so as to overlap portions of the first isolation region 24 that form two sides of each light receiving pixel 11, and one floating diffusion FD is shared between two adjacent light receiving pixels 11. That is, each floating diffusion FD is arranged so as to overlap a portion of the first isolation region 24 between two adjacent light receiving pixels 11, and is provided so as to straddle the two light receiving pixels 11. Each floating diffusion FD is shared by only one of a pair of photodiodes PD in each of the corresponding two light receiving pixels 11.

[0249] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIG. 46 are similar to those of the pixel array section 10 of the above-described ninth embodiment (see FIGS. 36 to 42).

[0250] As described above, according to this embodiment, the transfer gate TG is shared by adjacently arranged light-receiving pixels 11, and is also shared by a pair of photodiodes PD of each light-receiving pixel 11. This makes it possible to ensure a wide planar area for each transfer gate TG, improving the degree of freedom in the layout design of the TG electrodes VT connected to the transfer gate TG, and enabling high robustness to be exhibited with respect to misalignment of the electrode contacts of the transfer gate TG.

[0251] [One Modification of Tenth Embodiment] Fig. 52 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to one modification of the tenth embodiment, and exemplifies four light-sensitive pixels 11 (2 pixels x 2 pixels; in particular, the third pixel unit PU3). Fig. 53 is a diagram showing an example of a cross section of the light-sensitive pixel 11 (in particular, a transfer gate TG of a planar type (see Fig. 47) or a double vertical type (see Fig. 48)) taken along the LIII-LIII cross section line shown in Fig. 52. Fig. 54 is a diagram showing another example of a cross section of the light-sensitive pixel 11 (in particular, a transfer gate TG of a single vertical type (see Fig. 49)) taken along the LIII-LIII cross section line shown in Fig. 52.

[0252] In this embodiment, elements that are the same as or correspond to those in the first to tenth embodiments described above are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0253] The pixel array unit 10 (solid-state imaging device 1) of this embodiment has third isolation regions 26 arranged to surround the P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), similar to the third embodiment (see FIGS. 10 and 11 ). The third isolation regions 26 optically and electrically isolate the corresponding P-type diffusion regions PTAP (particularly the P-type implantation regions PTAPa), and can be made of any material, such as a low-refractive-index dielectric material, such as silicon oxide.

[0254] 52 to 54 , the third isolation region 26 is disposed adjacent to the P-type diffusion region PTAP (particularly the P-type implant region PTAPa), and is provided as STI (Shallow Trench Isolation) so as not to penetrate the semiconductor substrate 20. The third isolation region 26 shown in Fig. 52 has a hollow rectangular shape in a plan view, and extends so as to pass between the first isolation region 24 and the second isolation region 25 in the multiple (four) light-receiving pixels 11 (i.e., each first pixel unit PU1) that share the corresponding P-type diffusion region PTAP.

[0255] Other configurations of the pixel array section 10 (semiconductor substrate 20) shown in FIGS. 52 to 54 are similar to those of the pixel array section 10 of the above-described tenth embodiment (see FIGS. 46 to 51).

[0256] According to this embodiment, the third isolation region 26 can prevent the P-type diffusion region PTAP (particularly the P-type implantation region PTAPa) from diffusing into the semiconductor substrate 20 .

[0257] [Eleventh Embodiment] Fig. 55 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to an eleventh embodiment, exemplarily showing 16 light-sensitive pixels 11 (4 pixels x 4 pixels). Fig. 56 is a diagram showing an example cross-section of the light-sensitive pixel 11 taken along the LVI-LVI cross-section line shown in Fig. 55. Fig. 57 is a diagram showing an example cross-section of the light-sensitive pixel 11 taken along the LVII-LVII cross-section line shown in Fig. 55. Fig. 58 is a diagram showing an example cross-section of the light-sensitive pixel 11 taken along the LVIII-LVIII cross-section line shown in Fig. 55.

[0258] In the pixel array unit 10 (solid-state imaging device 1) of this embodiment, the pixel array unit 10 shown in Fig. 28 (a modified example of the seventh embodiment) described above and other pixel transistors (readout transistors) are provided on the same semiconductor substrate 20. That is, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and a switching transistor FDG are additionally provided to the pixel array unit 10 shown in Fig. 28 .

[0259] The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are each arranged along the second isolation region 25 of one light-receiving pixel 11 so as to overlap the pair of photodiodes PD and the second isolation region 25 in a planar view.

[0260] The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are each provided for each pixel unit formed of four light-receiving pixels 11 arranged in a 2-pixel by 2-pixel matrix. That is, each of the first pixel units PU1 described above includes one reset transistor RST, one amplification transistor AMP, one selection transistor SEL, and one switching transistor FDG. Similarly, each of the second pixel units PU2 described above includes one reset transistor RST, one amplification transistor AMP, one selection transistor SEL, and one switching transistor FDG.

[0261] As in the above-described modification of the seventh embodiment (see FIG. 28 ), one floating diffusion FD is provided for each second pixel unit PU2, which is made up of four light-receiving pixels 11 arranged in a 2-pixel by 2-pixel matrix. Therefore, in the pixel array section 10 of this embodiment, four pixel transistors RST, AMP, SEL, and FDG are provided for one floating diffusion FD.

[0262] The specific configuration of the pixel transistors RST, AMP, SEL, and FDG is not limited.

[0263] 56 to 58 has an AMPP-type region AMPa and an AMPN-type region AMPb formed in a semiconductor substrate 20, and an AMP gate electrode (e.g., polysilicon) AMPc provided on the AMPP-type region AMPa via an insulating film 33. The AMP gate electrode AMPc extends so as to straddle the second isolation region 25.

[0264] As described above, according to this embodiment, the readout transistors for reading out the accumulated charges in the photodiodes PD of the plurality of light-receiving pixels 11 are provided on the same substrate as the photodiodes PD. In addition, the floating diffusion FD is shared by the plurality of (four) light-receiving pixels 11. This makes it possible to arrange the readout transistors for reading out the accumulated charges in the photodiodes PD of the plurality of light-receiving pixels 11 with high area efficiency, thereby improving the degree of freedom in wiring layout.

[0265] Furthermore, this embodiment is advantageous in increasing the gate length L, which is represented by the length of the gate electrode of the pixel transistor, because the pixel transistors RST, AMP, SEL, and FDG are formed along the second isolation region 25 that extends diagonally (obliquely) across each light-receiving pixel 11. Furthermore, this embodiment is advantageous in increasing the gate width W, which is represented by the width of the gate electrode of the pixel transistor, because the pixel transistors RST, AMP, SEL, and FDG extend so as to straddle the second isolation region 25.

[0266] Increasing the gate length L and gate width W of the pixel transistors RST, AMP, SEL, and FDG (i.e., increasing the area of ​​the gate electrode in plan view) is advantageous for improving the driving capability of the pixel transistors. For example, in the amplifier transistor AMP, noise in the readout signal can be reduced.

[0267] 59 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to a twelfth embodiment, exemplifying 16 light-sensitive pixels 11 (4 pixels × 4 pixels). Fig. 60 is a diagram showing an example of a cross section of the light-sensitive pixel 11 taken along the LX-LX cross-sectional line shown in Fig. 59.

[0268] In the pixel array section 10 (solid-state imaging device 1) of this embodiment, the pixel array section 10 shown in the above-mentioned Fig. 43 (a modified example of the ninth embodiment) and other pixel transistors (readout transistors) are provided on the same semiconductor substrate 20. That is, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL are additionally provided to the pixel array section 10 shown in Fig. 43 .

[0269] The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are each provided along the second isolation region 25 of one light-receiving pixel 11 so as to overlap the photodiode PD in a plan view.

[0270] 59 and 60 , the amplification transistor AMP is arranged to overlap the pair of photodiodes PD and the second isolation region 25 in a planar view, but the reset transistor RST and the select transistor SEL do not overlap the second isolation region 25 in a planar view. That is, one reset transistor RST and one select transistor SEL are provided for each pair of photodiodes PD. In particular, in the examples shown in FIGS. 59 and 60 , two reset transistors RST are arranged adjacent to each other and spaced apart via the second isolation region 25 in one light-sensitive pixel 11. Similarly, two select transistors SEL are arranged adjacent to each other and spaced apart via the second isolation region 25 in another light-sensitive pixel 11.

[0271] On the other hand, in the pixel array unit 10 of the present embodiment, three pixel transistors RST, AMP, and SEL are provided for one floating diffusion FD. In Fig. 59, sets of the floating diffusion FD, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are exemplarily shown as a plurality of first group sets GS1 and a plurality of second group sets GS2.

[0272] The specific configuration of the pixel transistors RST, AMP, and SEL is not limited.

[0273] 59 and 60 has a SELP region SELa and a SELN region SELb formed in the semiconductor substrate 20, and a SEL gate electrode (e.g., polysilicon) SELc provided on the SELP region SELa via an insulating film 34. The SEL gate electrode SELc extends so as not to overlap the second isolation region 25.

[0274] As described above, according to this embodiment, readout transistors for reading out the accumulated charges in the photodiodes PD of the plurality of light-receiving pixels 11 are provided on the same substrate as the photodiodes PD. In addition, each floating diffusion FD is shared by a plurality (two) of light-receiving pixels 11 (particularly two photodiodes PD). This makes it possible to arrange the readout transistors for reading out the accumulated charges in the photodiodes PD of the plurality of light-receiving pixels 11 with high area efficiency, thereby improving the degree of freedom in wiring layout.

[0275] Furthermore, this embodiment is advantageous in increasing the gate length L, which is represented by the length of the gate electrode of the pixel transistor, because the pixel transistors RST, AMP, and SEL are formed along the second isolation region 25 that extends obliquely in the diagonal direction of each light-receiving pixel 11. Furthermore, this embodiment is advantageous in increasing the gate width W, which is represented by the width of the gate electrode of the amplifier transistor AMP, because the amplifier transistor AMP extends so as to straddle the second isolation region 25.

[0276] Increasing the gate length L and gate width W of the pixel transistors RST, AMP, and SEL (i.e., increasing the area of ​​the gate electrode in plan view) is advantageous for improving the driving capability of the pixel transistors. In particular, in the amplification transistor AMP, noise in the readout signal can be reduced.

[0277] [Electronic Device] The application of the disclosed technology is not limited to solid-state imaging elements, but can also be applied to, for example, camera modules, imaging devices, portable terminal devices with imaging functions, copiers with image reading units using solid-state imaging elements, other photodetection devices, and electronic devices in general that include photodetection devices.

[0278] Examples of imaging devices to which the disclosed technology can be applied include digital still cameras and video cameras, and examples of mobile terminal devices to which the disclosed technology can be applied include smartphones and tablet terminals.

[0279] FIG. 61 is a block diagram showing an example of the configuration of an imaging device, which is an example of an electronic device 1000 to which the disclosed technology can be applied.

[0280] In FIG. 61, electronic device 1000 includes a lens group 1001 , a solid-state image sensor 1002 , a DSP circuit 1003 , a frame memory 1004 , a display unit 1005 , a recording unit 1006 , an operation unit 1007 , and a power supply unit 1008 .

[0281] In the electronic device 1000 , a DSP circuit 1003 , a frame memory 1004 , a display unit 1005 , a recording unit 1006 , an operation unit 1007 , and a power supply unit 1008 are interconnected via a bus line 1009 .

[0282] The lens group 1001 is an optical system that guides incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging element 1002. The solid-state imaging element 1002 corresponds to the solid-state imaging element 1 of each of the above-described embodiments, and converts the amount of incident light that forms an image on the imaging surface into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0283] The DSP circuit 1003 is a signal processing circuit that processes signals output from the solid-state image sensor 1002. The frame memory 1004 temporarily stores image data processed by the DSP circuit 1003 on a frame-by-frame basis.

[0284] The display unit 1005 can be configured as a panel display device equipped with, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays images (moving or still images) captured by the solid-state imaging element 1002. The recording unit 1006 records data of images captured by the solid-state imaging element 1002 in a recording medium such as a semiconductor memory or a hard disk.

[0285] The operation unit 1007 receives operations by the user and issues operation command signals related to various functions of the electronic device 1000. The power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.

[0286] By applying the technology of each of the above-mentioned embodiments to the electronic device 1000 (e.g., solid-state imaging element 1002) configured in this manner, it is possible to achieve the same effects as the solid-state imaging element 1 of each of the above-mentioned embodiments, and to improve the freedom of wiring layout, for example.

[0287] It should be noted that the embodiments and modifications disclosed in this specification are merely illustrative in all respects and should not be construed as limiting. The above-described embodiments and modifications may be omitted, substituted, and modified in various ways without departing from the scope and spirit of the appended claims. For example, the above-described embodiments and modifications may be combined in whole or in part, and embodiments other than those described above may be combined with the above-described embodiments or modifications. Furthermore, the effects of the present disclosure described in this specification are merely illustrative, and other effects may be obtained.

[0288] The technical category embodying the above technical idea is not limited. For example, the above technical idea may be embodied by a computer program that causes a computer to execute one or more procedures (steps) included in a method of manufacturing or using the above device. The above technical idea may also be embodied by a computer-readable non-transitory recording medium on which such a computer program is recorded.

[0289] [Additional Notes] The disclosed technology may be embodied as, for example, a photodetector, an electronic device, and a method for manufacturing a photodetector described in the following items.

[0290] [Item 1] A photodetector comprising a semiconductor substrate including a plurality of light-receiving pixels arranged two-dimensionally, at least some of the plurality of light-receiving pixels having a pair of photoelectric conversion units, a first isolation region arranged so as to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in a plan view, and the second isolation region is arranged along one diagonal of the first isolation region in a plan view, and is in contact with the first isolation region at one end side of the one diagonal line and is not in contact with the first isolation region at the other end side of the one diagonal line.

[0291] [Item 2] The photodetector device according to Item 1, wherein at least some of the light-receiving pixels have an overflow path that electrically connects the pair of photoelectric conversion units to each other in a portion where the second isolation region is not in contact with the first isolation region in a planar view, the first isolation region is arranged to separate the photoelectric conversion units between adjacent light-receiving pixels, and the second isolation region is arranged to separate the pair of photoelectric conversion units in a corresponding one of the light-receiving pixels.

[0292] [Item 3] The photodetector device according to item 1 or 2, wherein at least some of the light-receiving pixels have a P-type diffusion region forming a ground contact in a portion where the second isolation region is not in contact with the first isolation region in a planar view, and the P-type diffusion regions of the plurality of light-receiving pixels, which have the pair of photoelectric conversion units, the first isolation region, the second isolation region, and the P-type diffusion region and are arranged adjacent to one another, are electrically connected to one P-type diffusion region electrode.

[0293] [Item 4] The photodetector according to Item 3, wherein the P-type diffusion region has a P-type implanted region provided in the semiconductor substrate and a P-type electrode connected to the P-type implanted region, and at least a portion of the P-type electrode is buried in the semiconductor substrate.

[0294] [Item 5] The photodetector device according to Item 4, wherein at least some of the light-receiving pixels have a third isolation region disposed so as to surround the P-type implanted region.

[0295] [Item 6] The photodetector according to any one of Items 3 to 5, wherein the one P-type diffusion region electrode is a vertical via extending in a direction perpendicular to the pixel surface, and is electrically connected to the P-type diffusion region at one end and to another wiring at the other end.

[0296] [Item 7] The photodetector according to Item 2 or any one of Items 3 to 6 which cite Item 2, wherein at least some of the light-receiving pixels have transfer gates for reading out accumulated charges of the pair of photoelectric conversion units, and in each of the at least some of the light-receiving pixels, the distance between the overflow path and the transfer gate is equal to or greater than the length of one side of the rectangular light-receiving pixel.

[0297] [Item 8] The photodetector according to any one of Items 1 to 7, further comprising readout transistors that are transistors for reading out accumulated charges in the photoelectric conversion units of the plurality of light-receiving pixels, and at least a portion of the photoelectric conversion units and the readout transistors of the plurality of light-receiving pixels are provided on the same semiconductor substrate.

[0298] [Item 9] The photodetector according to item 7 or item 8 which recites item 7, wherein the transfer gate is provided at a diagonal position of the light-receiving pixel different from a diagonal position through which the one diagonal line passes.

[0299] [Item 10] The photodetector device according to items 7 and 9, or item 8 which recites item 7, wherein the transfer gate is shared by adjacently arranged light-receiving pixels.

[0300] [Item 11] The photodetector according to items 7, 9, and 10, or item 8 which cites item 7, wherein the transfer gate is provided at a diagonal position of the light-receiving pixel through which the one diagonal line passes.

[0301] [Item 12] The photodetector according to items 7, 9 to 11, or 8 citing item 7, wherein the transfer gate is shared by the pair of photoelectric conversion units.

[0302] [Item 13] The photodetector according to Items 7, 9 to 12, or 8 which recites Item 7, wherein one transfer gate electrode is electrically connected to the transfer gate, and the one transfer gate electrode is a vertical via extending in a direction perpendicular to a pixel surface, and is electrically connected to the transfer gate at one end and to another wiring at the other end.

[0303] [Item 14] The photodetector device according to Item 13, wherein at least some of the light-receiving pixels have a floating diffusion electrically connected to the transfer gate, and the distance between one of the transfer gate electrodes and the floating diffusion is equal to or greater than half the length of one side of the rectangular light-receiving pixel.

[0304] [Item 15] An electronic device comprising: a photodetector; an optical system that forms an image of incident light on an imaging surface of the photodetector; and a signal processing circuit that processes signals output from the photodetector, wherein the photodetector comprises a plurality of light-receiving pixels that are two-dimensionally arranged, and at least some of the plurality of light-receiving pixels have a pair of photoelectric conversion units, a first isolation region that is arranged so as to surround the pair of photoelectric conversion units, and a second isolation region that is arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in plan view, and the second isolation region is arranged along one diagonal of the first isolation region in plan view, and is in contact with the first isolation region at one end side of the one diagonal line and is not in contact with the first isolation region at the other end side of the one diagonal line.

[0305] [Item 16] A method for manufacturing a photodetector comprising: a semiconductor substrate including a plurality of photosensitive pixels arranged two-dimensionally, at least some of the plurality of photosensitive pixels having a pair of photoelectric conversion units, a first isolation region arranged so as to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in a plan view, and the second isolation region is arranged along one diagonal of the first isolation region in a plan view, and is in contact with the first isolation region at one end side of the one diagonal and is not in contact with the first isolation region at the other end side of the one diagonal, the method comprising: preparing the semiconductor substrate in a state where a location corresponding to the second isolation region is a space; injecting an ionized injection substance into the semiconductor substrate after passing the ionized injection substance through the location corresponding to the second isolation region in a space; and filling the location corresponding to the second isolation region in a space with a substance to form the second isolation region.

[0306] 1 Solid-state imaging element, 10 Pixel array section, 11 Light-receiving pixel, 12 System control section, 13 Vertical drive section, 14 Column readout circuit section, 15 Column signal processing section, 16 Horizontal drive section, 17 Signal processing section, 18 Readout circuit, 20 Semiconductor substrate, 21 Semiconductor layer, 24 First isolation region, 25 Second isolation region, 26 Third isolation region, 30 Gate insulating film, 31 Insulating film, 33 Insulating film, 34 Insulating film, 1000 Electronic device, 1001 Lens group, 1002 Solid-state imaging element, 1003 DSP circuit, 1004 Frame memory, 1005 Display section, 1006 Recording section, 1007 Operation section, 1008 Power supply section, 1009 Bus line, AMP Amplifying transistor, AMPa AMPP-type region, AMPb AMPN-type region, AMPc AMP gate electrode, CH Channel section, D1 First distance, D2 second distance, D3 third distance, D4 ​​fourth distance, FD floating diffusion, FDa FD implantation region, FDb FD electrode, FDG switching transistor, GS1 first group set, GS2 second group set, INP implantation region, In implantation material, L gate length, LD pixel drive line, LV vertical pixel wiring, M mask, OFP overflow path, PD photodiode, PD1 photodiode, PD2 photodiode, PU1 first pixel unit, PU2 second pixel unit, PU3 third pixel unit, PTAP P-type diffusion region, PTAPa P-type implantation region, PTAPb P-type electrode, RST reset transistor, SEL selection transistor, SELa SELP-type region, SELb SELN-type region, SELc SEL gate electrode, SIR same-color isolation implantation region, TG transfer gate, TGa Transfer electrode, TR transfer transistor, VDD power supply voltage, VP PTAP electrode, VF FD electrode, VT TG electrode, W gate width

Claims

1. A photodetection device comprising a semiconductor substrate including a plurality of photosensitive pixels arranged two-dimensionally, at least some of the plurality of photosensitive pixels having a pair of photoelectric conversion units, a first isolation region arranged to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, the first isolation region being rectangular in a planar view, and the second isolation region being arranged along one diagonal of the first isolation region in a planar view, contacting the first isolation region at one end of the one diagonal and not contacting the first isolation region at the other end of the one diagonal.

2. The photodetection device described in claim 1, wherein at least some of the light-receiving pixels have an overflow path electrically connecting the pair of photoelectric conversion units to each other in a portion where the second isolation region is not in contact with the first isolation region in a planar view, the first isolation region is arranged to separate the photoelectric conversion units between adjacent light-receiving pixels, and the second isolation region is arranged to separate the pair of photoelectric conversion units in a corresponding one of the light-receiving pixels.

3. The photodetection device of claim 1, wherein at least some of the light-receiving pixels have a P-type diffusion region forming a ground contact in a portion where the second isolation region is not in contact with the first isolation region in a planar view, and the P-type diffusion regions of the plurality of light-receiving pixels having the pair of photoelectric conversion units, the first isolation region, the second isolation region and the P-type diffusion region and arranged adjacent to each other are electrically connected to a single P-type diffusion region electrode.

4. The photodetector according to claim 3, wherein the P-type diffusion region has a P-type region provided in the semiconductor substrate and a P-type electrode connected to the P-type region, and at least a portion of the P-type electrode is embedded in the semiconductor substrate.

5. The photodetection device according to claim 4, wherein at least a portion of the light-receiving pixels have a third isolation region disposed so as to surround the P-type region.

6. The photodetector according to claim 3, wherein the one P-type diffusion region electrode is a vertical via extending in a direction perpendicular to the pixel surface, and is electrically connected to the P-type diffusion region at one end and electrically connected to another wiring at the other end.

7. The photodetection device according to claim 2, wherein at least a portion of the light-receiving pixels have a transfer gate for reading out accumulated charges in the pair of photoelectric conversion elements, and in each of the at least a portion of the light-receiving pixels, the distance between the overflow path and the transfer gate is equal to or greater than the length of one side of the rectangular light-receiving pixel.

8. The photodetection device according to claim 1, further comprising readout transistors for reading out accumulated charges in the photoelectric conversion units of the plurality of photosensitive pixels, and at least a portion of the photoelectric conversion units and the readout transistors of the plurality of photosensitive pixels are provided on the same semiconductor substrate.

9. The photodetection device according to claim 7, wherein the transfer gate is provided at a diagonal position of the light-receiving pixel different from a diagonal position through which the one diagonal line passes.

10. The photodetection device according to claim 7, wherein the transfer gate is shared by adjacently arranged light-receiving pixels.

11. The photodetection device according to claim 7, wherein the transfer gate is provided at a diagonal location of the light-receiving pixel through which the one diagonal line passes.

12. The photodetector according to claim 7, wherein the transfer gate is shared by the pair of photoelectric conversion units.

13. The photodetection device according to claim 7, wherein one transfer gate electrode is electrically connected to the transfer gate, and the one transfer gate electrode is a vertical via extending in a direction perpendicular to the pixel surface, electrically connected to the transfer gate at one end and electrically connected to another wiring at the other end.

14. The photodetection device according to claim 13, wherein at least some of the light-receiving pixels have a floating diffusion electrically connected to the transfer gate, and the distance between one of the transfer gate electrodes and the floating diffusion is equal to or greater than half the length of one side of the rectangular light-receiving pixel.

15. An electronic device comprising: a photodetection device; an optical system that forms an image of incident light on an imaging surface of the photodetection device; and a signal processing circuit that processes signals output from the photodetection device, wherein the photodetection device comprises a plurality of light-receiving pixels arranged two-dimensionally, at least a portion of the plurality of light-receiving pixels have a pair of photoelectric conversion units, a first isolation region arranged to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, wherein the first isolation region is rectangular in a planar view, and the second isolation region is arranged along one diagonal of the first isolation region in a planar view, contacting the first isolation region at one end side of the one diagonal and not contacting the first isolation region at the other end side of the one diagonal.

16. A method for manufacturing a photodetector comprising: a semiconductor substrate including a plurality of photosensitive pixels arranged two-dimensionally, at least some of the plurality of photosensitive pixels having a pair of photoelectric conversion units, a first isolation region arranged to surround the pair of photoelectric conversion units, and a second isolation region arranged between the pair of photoelectric conversion units, the first isolation region being rectangular in a planar view, and the second isolation region being arranged along one diagonal of the first isolation region in a planar view, contacting the first isolation region at one end side of the one diagonal and not contacting the first isolation region at the other end side of the one diagonal, the method comprising: preparing the semiconductor substrate in a state where a location corresponding to the second isolation region is space; injecting an ionized injection substance into the semiconductor substrate after passing the location corresponding to the second isolation region in a space; and filling a substance into the location corresponding to the second isolation region in a space to form the second isolation region.

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