Control circuit

Abstract

The present invention includes: a first control circuit that outputs, to a gate of a first rectification transistor, a first control signal for controlling the first rectification transistor to the on state when the voltage at a first input point is higher than the voltage at a second input point; a second control circuit that outputs, to a gate of a second rectification transistor, a second control signal for controlling the second rectification transistor to the on state when the voltage between the first input point and a second output point is at or below a threshold value; a third control circuit that outputs, to a gate of a third rectification transistor, a third control signal for controlling the third rectification transistor to the on state when the voltage at the first input point is lower than the voltage at the second input point; and a fourth control circuit that outputs, to a gate of a fourth rectification transistor, a fourth control signal for controlling the fourth rectification transistor to the on state when the voltage between the second input point and the second output point is at or below a threshold value.

Description

Control circuit

[0001] The present disclosure relates to a control circuit for controlling a bridge circuit.

[0002] Patent Document 1 describes an AC synchronous rectification circuit.

[0003] In a conventional synchronous rectifier circuit, four rectifier transistors are controlled by four control circuits (four semiconductor devices). Each of the four semiconductor devices includes a high-voltage (e.g., several hundred volts) MOSFET for detecting the drain potential of the rectifier transistor using the source potential as a reference potential. To reduce costs and miniaturize the device, it is preferable to reduce the number of semiconductor devices from four to two or one.

[0004] U.S. Pat. No. 10,756,645

[0005] Generally, semiconductor devices use PN isolation to separate elements. However, when considering integrating the above four semiconductor devices into a single chip, the PN isolation poses the following problems.

[0006] The reference potential of the control circuit on the high side of the first arm, the reference potential of the control circuit on the high side of the second arm, and the reference potential of the control circuits on the low sides of the first arm and second arm are different. In other words, there are three reference potentials.

[0007] Each of the high-side control circuits of the first arm and the second arm requires the formation of a high-voltage MOSFET in the high-side (high-voltage) region. For example, a 600V MOSFET must be formed in the high-side region, which is provided with a 600V rated voltage by PN isolation from ground (the reference potential of the low-side control circuits of the first arm and second arm). This is impossible from a process standpoint.

[0008] Using SOI (Silicon On Insulator) technology, the high-side high-voltage MOSFET of the first arm, the high-side high-voltage MOSFET of the second arm, and the low-side high-voltage MOSFETs of the first arm and the second arm are fabricated on SiO ２If the four semiconductor devices are separated by a film, it is possible to integrate them into a single chip. ２ Forming a film significantly increases the cost of the process, so it is preferable not to use the SOI technology.

[0009] The present disclosure aims to keep costs down.

[0010] A control circuit according to one aspect of the present disclosure is a control circuit for controlling a bridge circuit that rectifies an AC voltage input between a first input point, which is a connection point between a source of a first rectifier transistor on a high side of a first arm and a drain of a second rectifier transistor on a low side, and a second input point, which is a connection point between a source of a third rectifier transistor on a high side of a second arm and a drain of a fourth rectifier transistor on a low side, and outputs a DC voltage between a first output point, which is a connection point between the drain of the first rectifier transistor and the drain of the third rectifier transistor, and a second output point, which is a connection point between the source of the second rectifier transistor and the source of the fourth rectifier transistor; the control circuit includes: a first control circuit that outputs a first control signal to a gate of the first rectifier transistor when a voltage at the first input point is higher than a voltage at the second input point, to control the first rectifier transistor to an ON state; and a second control circuit that outputs a second control signal to a gate of the second rectifier transistor when a voltage between the first input point and the second output point is equal to or lower than a threshold value, to control the second rectifier transistor to an ON state. a third control circuit that outputs a third control signal to the gate of the third rectifier transistor to control the third rectifier transistor to an on state when the voltage at the first input point is lower than the voltage at the second input point; and a fourth control circuit that outputs a fourth control signal to the gate of the fourth rectifier transistor to control the fourth rectifier transistor to an on state when the voltage between the second input point and the second output point is equal to or lower than a threshold.

[0011] the control circuit includes a comparison circuit that compares the voltage at the first input point with the voltage at the second input point and outputs a first comparison signal and a second comparison signal having an inverse logic to the first comparison signal; the first control circuit includes a first level shift circuit that shifts the voltage level of the first comparison signal; and a first driver circuit that outputs the first control signal, which is an amplified output signal of the first level shift circuit, to the gate of the first rectifier transistor; and the third control circuit includes a second level shift circuit that shifts the voltage level of the second comparison signal; and a second driver circuit that outputs the third control signal, which is an amplified output signal of the second level shift circuit, to the gate of the third rectifier transistor.

[0012] The control circuit includes a suppression circuit that suppresses the first control signal, the second control signal, the third control signal, and the fourth control signal when a signal instructing diode rectification using parasitic diodes of the first rectification transistor, the second rectification transistor, the third rectification transistor, and the fourth rectification transistor is input.

[0013] In the control circuit, the first control circuit includes: a first phase detection circuit that detects the phase between the voltage at the first input point and the voltage at the second input point; and a first driver circuit that outputs the first control signal based on the detection result of the first phase detection circuit to the gate of the first rectifier transistor; and the third control circuit includes: a second phase detection circuit that detects the phase between the voltage at the first input point and the voltage at the second input point; and a second driver circuit that outputs the third control signal based on the detection result of the second phase detection circuit to the gate of the third rectifier transistor.

[0014] In the control circuit, the first phase detection circuit includes: a first diode having an anode electrically connected to the first input point and a cathode electrically connected to one end of a resistor; a first Zener diode having an anode electrically connected to the first input point and a cathode electrically connected to the cathode of the first diode; a first transistor having a source electrically connected to the first input point and a gate electrically connected to the cathode of the first diode; and a first pull-up resistor that pulls up the drain of the first transistor; and the second phase detection circuit includes: a second diode having an anode electrically connected to the second input point and a cathode electrically connected to the other end of the resistor; a second Zener diode having an anode electrically connected to the second input point and a cathode electrically connected to the cathode of the second diode; a second transistor having a source electrically connected to the second input point and a gate electrically connected to the cathode of the second diode; and a second pull-up resistor that pulls up the drain of the second transistor; and the first driver circuit includes: The first driver circuit amplifies the drain voltage of the first transistor and outputs the first control signal to the gate of the first rectifier transistor, and the second driver circuit amplifies the drain voltage of the second transistor and outputs the third control signal to the gate of the third rectifier transistor.

[0015] In the control circuit, the first phase detection circuit further includes a first offset voltage application circuit that applies an offset voltage to the gate of the first transistor, and the second phase detection circuit further includes a second offset voltage application circuit that applies an offset voltage to the gate of the second transistor.

[0016] The control circuit includes a suppression circuit that suppresses the second control signal and the fourth control signal and suppresses the power supply voltage of the first control circuit and the third control circuit when a signal instructing diode rectification using parasitic diodes of the first rectification transistor, the second rectification transistor, the third rectification transistor, and the fourth rectification transistor is input.

[0017] According to the present disclosure, costs can be reduced.

[0018] FIG. 1 is a diagram showing the configuration of a rectifier circuit according to a first embodiment. FIG. 2 is a diagram showing the configuration of a control circuit according to the first embodiment. FIG. 3 is a diagram explaining the operation of the control circuit according to the first embodiment. FIG. 4 is a diagram showing the configuration of a control circuit according to a modified example of the first embodiment. FIG. 5 is a diagram showing the configuration of a control circuit according to a second embodiment. FIG. 6 is a diagram showing the operation of the control circuit according to the second embodiment. FIG. 7 is a diagram showing the configuration of a control circuit according to a first modified example of the second embodiment. FIG. 8 is a diagram showing the configuration of a control circuit according to a second modified example of the second embodiment.

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0020] 1 is a diagram showing the configuration of a rectifier circuit according to the first embodiment. A rectifier circuit 1 receives an AC input voltage Vin (=VS_R-VS_L) and an input current Iin from an AC power supply 2, and outputs a DC output voltage Vout (=Vout_P-Vout_N) and an output current Iout to a load 4. A capacitor 3 smoothes the output voltage Vout.

[0021] The rectifier circuit 1 includes a bridge circuit 11 and a control circuit 12. The bridge circuit 11 includes a first arm 11-1 and a second arm 11-2. The first arm 11-1 includes a high-side first rectifier transistor 21 and a low-side second rectifier transistor 22. The second arm 11-2 includes a high-side third rectifier transistor 23 and a low-side fourth rectifier transistor 24.

[0022] In the embodiment, each transistor is a MOSFET, but the present disclosure is not limited to this. Each transistor may be a silicon power device, a GaN power device, a SiC power device (e.g., an IGBT (Insulated Gate Bipolar Transistor)), or the like.

[0023] Each transistor has a parasitic diode (body diode) that can actively conduct current, or has a diode connected in anti-parallel, which is the pn junction between the back gate and the source and drain of the MOSFET.

[0024] In the first embodiment, the first rectifier transistor 21 has a first parasitic diode 21a, the second rectifier transistor 22 has a second parasitic diode 22a, the third rectifier transistor 23 has a third parasitic diode 23a, and the fourth rectifier transistor 24 has a fourth parasitic diode 24a.

[0025] The source of the first rectifier transistor 21 and the drain of the second rectifier transistor 22 are electrically connected to a first node N1. A voltage VS_R is input to the first node N1 from one end of the AC power supply 2.

[0026] The source of the third rectifier transistor 23 and the drain of the fourth rectifier transistor 24 are electrically connected to a second node N2. A voltage VS_L is input to the second node N2 from the other end of the AC power supply 2. The difference between the voltage VS_R and the voltage VS_L is the input voltage Vin.

[0027] The drain of the first rectifier transistor 21 and the drain of the third rectifier transistor 23 are electrically connected to a third node N3. A voltage Vout_P is output from the third node N3 to one end of the capacitor 3.

[0028] The source of the second rectifier transistor 22 and the source of the fourth rectifier transistor 24 are electrically connected to a fourth node N4. A voltage Vout_N is output from the fourth node N4 to the other end of the capacitor 3. The difference between the voltage Vout_P and the voltage Vout_N is the output voltage Vout.

[0029] The first node N1 corresponds to an example of a "first input point" in the present disclosure. The second node N2 corresponds to an example of a "second input point" in the present disclosure. The third node N3 corresponds to an example of a "first output point" in the present disclosure. The fourth node N4 corresponds to an example of a "second output point" in the present disclosure.

[0030] The control circuit 12 controls the first rectifier transistor 21 to the fourth rectifier transistor 24 to cause the bridge circuit 11 to perform synchronous rectification.

[0031] As will be described later, the control circuit 12 can be realized by a single semiconductor device with PN isolation.

[0032] 2 is a diagram showing the configuration of the control circuit according to the first embodiment. The control circuit 12 has terminals 12a to 12j. The control circuit 12 includes a first control circuit 41, a second control circuit 42, a third control circuit 43, a fourth control circuit 44, and a comparison circuit 45.

[0033] The terminal 12 a is electrically connected to one end of a resistor 301. The other end of the resistor 301 is electrically connected to the gate of the first rectifier transistor 21.

[0034] The terminal 12 b is electrically connected to one end of the capacitor 302 .

[0035] The terminal 12c is electrically connected to the other end of the capacitor 302 and the first node N1.

[0036] As will be described later, the capacitor 302 is charged via the diode 51 by the capacitor 303, which is charged by the second control circuit 42 and the fourth control circuit 44. The capacitor 302 generates a voltage when it is charged. The first control circuit 41 operates using the voltage generated by the capacitor 302 as a power supply voltage.

[0037] The terminal 12 d is electrically connected to one end of the capacitor 303 .

[0038] The terminal 12e is electrically connected to one end of a resistor 304. The other end of the resistor 304 is electrically connected to the gate of the second rectifier transistor 22.

[0039] The terminal 12f is electrically connected to the other end of the capacitor 303 and the fourth node N4.

[0040] As will be described later, the capacitor 303 is charged by the second control circuit 42 and the fourth control circuit 44. The capacitor 303 generates a voltage when it is charged. The second control circuit 42, the fourth control circuit 44, and the comparison circuit 45 operate using the voltage generated by the capacitor 303 as a power supply voltage.

[0041] The terminal 12g is electrically connected to one end of a resistor 305. The other end of the resistor 305 is electrically connected to the gate of the third rectifier transistor 23.

[0042] The terminal 12 h is electrically connected to one end of the capacitor 306 .

[0043] The terminal 12i is electrically connected to the other end of the capacitor 306 and the second node N2.

[0044] As will be described later, the capacitor 306 is charged via the diode 52 by the capacitor 303, which is charged by the second control circuit 42 and the fourth control circuit 44. The capacitor 306 generates a voltage when it is charged. The third control circuit 43 operates using the voltage generated by the capacitor 306 as a power supply voltage.

[0045] The terminal 12j is electrically connected to one end of a resistor 307. The other end of the resistor 307 is electrically connected to the gate of the fourth rectifier transistor 24.

[0046] (Configuration and Operation of Comparator Circuit) The comparator circuit 45 includes resistors 141 to 144, a comparator 145, and a logic inversion circuit 146. The comparator 145 and the logic inversion circuit 146 operate using the voltage generated by the capacitor 303 as a power supply voltage.

[0047] For example, the ratio of the resistance value of the resistor 141 to the resistance value of the resistor 142 is the same as the ratio of the resistance value of the resistor 143 to the resistance value of the resistor 144.

[0048] One end of the resistor 141 is electrically connected to the terminal 12c. The other end of the resistor 141 is electrically connected to one end of the resistor 142. The other end of the resistor 142 is electrically connected to the terminal 12f. The voltage V11 at the connection point between the resistors 141 and 142 is a divided voltage obtained by dividing the difference between the voltage VS_R and the voltage Vout_N.

[0049] One end of the resistor 143 is electrically connected to the terminal 12i. The other end of the resistor 143 is electrically connected to one end of the resistor 144. The other end of the resistor 144 is electrically connected to the terminal 12f. The voltage V12 at the connection point between the resistors 143 and 144 is a divided voltage obtained by dividing the difference between the voltage VS_L and the voltage Vout_N.

[0050] A voltage V11 is input to the inverting input terminal (negative terminal) of the comparator 145. A voltage V12 is input to the non-inverting input terminal (positive terminal) of the comparator 145. The comparator 145 outputs a high-level signal S11 when voltage V11<voltage V12, i.e., when voltage VS_R<voltage VS_L. The comparator 145 outputs a low-level signal S11 when voltage V11>voltage V12, i.e., when voltage VS_R>voltage VS_L.

[0051] The logic inversion circuit 146 outputs a signal S12 obtained by logically inverting the signal S11. The logic inversion circuit 146 outputs a low-level signal S12 when the voltage V11 is lower than the voltage V12, i.e., when the voltage VS_R is lower than the voltage VS_L. The logic inversion circuit 146 outputs a high-level signal S12 when the voltage V11 is higher than the voltage V12, i.e., when the voltage VS_R is higher than the voltage VS_L.

[0052] (Configuration and Operation of First Control Circuit) The first control circuit 41 includes a first level shift circuit 61 and a first driver circuit 62. Known circuits can be used for the first level shift circuit 61 and the first driver circuit 62. The first level shift circuit 61 and the first driver circuit 62 operate using the voltage generated by the capacitor 302 as a power supply voltage.

[0053] The first level shift circuit 61 shifts the voltage level of the signal S12. The first driver circuit 62 outputs a first control signal S1 to the gate of the first rectifier transistor 21 via the terminal 12a and the resistor 301 based on the signal output from the first level shift circuit 61. When the signal S12 is at a high level, the first driver circuit 62 outputs a high-level first control signal S1 to the gate of the first rectifier transistor 21 via the terminal 12a and the resistor 301.

[0054] That is, the first control circuit 41 controls the first rectifier transistor 21 to be in the on state when the voltage VS_R is greater than the voltage VS_L.

[0055] (Configuration and Operation of Second Control Circuit) The second control circuit 42 includes a resistor 81, a Zener diode 82, a transistor 83, a current passing circuit 84, a voltage passing circuit 85, and a signal output circuit 86. The signal output circuit 86 operates using the voltage generated by the capacitor 303 as a power supply voltage.

[0056] In the embodiment, the transistor 83 is an enhancement-type transistor (normally off), but the present disclosure is not limited to this. If the transistor 83 is a depletion-type transistor (normally on), the resistor 81, which is a startup resistor (described later), is not required. Furthermore, without the resistor 81, the voltage at the node N11 does not flow back to the terminal 12d via the voltage passing circuit 85. Therefore, the voltage passing circuit 85 does not require the diode 85b.

[0057] The current passing circuit 84 includes a resistor 84a and a diode 84b.

[0058] The voltage passing circuit 85 includes a resistor 85a and a diode 85b.

[0059] The signal output circuit 86 includes a constant voltage source 86a, a comparator 86b, and a buffer circuit 86c.

[0060] One end of the resistor 81 is electrically connected to the terminal 12c, and the other end of the resistor 81 is electrically connected to the node N11. As will be described later, the resistor 81 is a bias resistor for turning on the transistor 83.

[0061] The cathode of the Zener diode 82 is electrically connected to the node N11. The anode of the Zener diode 82 is electrically connected to the terminal 12f. The Zener diode 82 clamps the voltage of the node N11 to its own Zener voltage (breakdown voltage).

[0062] The drain of the transistor 83 is electrically connected to the terminal 12c, the gate of the transistor 83 is electrically connected to the node N11, and the source of the transistor 83 is electrically connected to the node N12.

[0063] Since the voltage of node N11 is clamped by Zener diode 82, the voltage of node N12 is clamped to (voltage of node N11) - (threshold voltage of transistor 83). Specifically, if the Zener voltage (breakdown voltage) of Zener diode 82 is 18 V and the threshold voltage of transistor 83 is 1.5 V, the voltage of node N11 is clamped to 18 V. Therefore, when node N12 rises to 18 V - 1.5 V = 16.5 V, the gate-source voltage of transistor 83 falls below the threshold, turning transistor 83 off. When the voltage of node N12 falls below 16.5 V, the gate-source voltage of transistor 83 rises above the threshold, turning transistor 83 on. In this way, the voltage of node N12 is clamped by turning transistor 83 on and off.

[0064] One end of the resistor 84a is electrically connected to the node N12. The other end of the resistor 84a is electrically connected to the anode of the diode 84b. The cathode of the diode 84b is electrically connected to the terminal 12d.

[0065] One end of the resistor 85a is electrically connected to the terminal 12d, and the other end of the resistor 85a is electrically connected to the anode of the diode 85b, and the cathode of the diode 85b is electrically connected to the node N11.

[0066] The low-potential end of the constant voltage source 86a is electrically connected to the terminal 12f. The high-potential end of the constant voltage source 86a is electrically connected to the non-inverting input terminal (+ terminal) of the comparator 86b. As will be described later, the constant voltage source 86a outputs a first threshold voltage (e.g., −0.2 V) when the second control signal S2 output from the signal output circuit 86 is at a low level (i.e., the second rectifier transistor 22 is off). The constant voltage source 86a outputs a second threshold voltage (e.g., 0 V) ​​when the second control signal S2 is at a high level (i.e., the second rectifier transistor 22 is on).

[0067] The inverting input terminal (negative terminal) of the comparator 86b is electrically connected to the node N12. The output terminal of the comparator 86b is electrically connected to the input terminal of the buffer circuit 86c. The output terminal of the buffer circuit 86c is electrically connected to the terminal 12e.

[0068] The inverting input terminal (negative terminal) of the comparator 86b is electrically connected to the drain of the second rectifier transistor 22 via the source-drain path of the transistor 83. The non-inverting input terminal (positive terminal) of the comparator 86b is electrically connected to the source of the second rectifier transistor 22 via the constant voltage source 86a. In other words, the comparator 86b compares the drain-source voltage of the second rectifier transistor 22 with the voltage of the constant voltage source 86a.

[0069] The operation of the second control circuit 42 will now be described.

[0070] When the voltage of the fourth node N4 is higher than the voltage of the first node N1, the second parasitic diode 22 a of the second rectifier transistor 22 is conductive, and therefore the voltage between the voltage of the fourth node N4 and the first node N1 is clamped to the voltage drop of the second parasitic diode 22 a. When the voltage of the first node N1 is higher than the voltage of the fourth node N4, the voltage between the voltage of the first node N1 and the fourth node N4 can rise to the input voltage Vin.

[0071] When the voltage at the first node N1 increases and becomes higher than the voltage at the fourth node N4 (voltage at the terminal 12c>voltage at the terminal 12f), a voltage is applied to the node N11 via the resistor 81, and the transistor 83 is turned on. When the transistor 83 is turned on, a voltage and a current are supplied to the node N12 via the drain-source path of the transistor 83.

[0072] The current passing circuit 84 passes a current from the node N12 to the terminal 12d. This charges the capacitor 303, which generates a voltage. This voltage is the voltage at the node N12 minus the voltage drop across the current passing circuit 84. The constant voltage source 86a, the comparator 86b, and the buffer circuit 86c operate using the voltage of the capacitor 303 as their power supply voltage.

[0073] Furthermore, the capacitor 302 is charged by the voltage of the capacitor 303 via the diode 51 when the voltage of the first node N1 drops to a value close to the voltage of the fourth node N4.

[0074] When the voltage of capacitor 303 reaches a certain level (above the threshold voltage of diode 85b), voltage passing circuit 85 passes the voltage at terminal 12d to node N11. Therefore, even if the voltage at terminal 12c drops, transistor 83 can remain on. Furthermore, resistor 81, which is a startup resistor, is no longer necessary for operation.

[0075] Next, the voltage at the first node N1 drops and becomes lower than the voltage at the fourth node N4 (voltage at the terminal 12c<voltage at the terminal 12f). As described above, the transistor 83 can maintain the on state, so the voltage at the node N12 becomes approximately the voltage at the terminal 12c (approximately the drain voltage of the second rectifier transistor 22).

[0076] The constant voltage source 86a outputs a first threshold voltage (for example, −0.2 V) when the second control signal S2 output from the signal output circuit 86 is at a low level (= the second rectifier transistor 22 is off). The constant voltage source 86a outputs a second threshold voltage (for example, 0 V) ​​when the second control signal S2 is at a high level (= the second rectifier transistor 22 is on).

[0077] When the voltage at node N12 (approximately the drain voltage of the second rectifier transistor 22) becomes equal to or lower than a first threshold voltage (e.g., −0.2 V), the comparator 86b outputs a high-level signal to the buffer circuit 86c. The buffer circuit 86c outputs a high-level second control signal S2 to the gate of the second rectifier transistor 22 via terminal 12e and resistor 304. This switches the second rectifier transistor 22 to an ON state. Furthermore, the constant voltage source 86a switches its output voltage to a second threshold voltage (e.g., 0 V).

[0078] Next, the voltage at the first node N1 rises and reaches the voltage at the fourth node N4 (the voltage at the terminal 12c = the voltage at the terminal 12f). As described above, the constant voltage source 86a outputs the second threshold voltage (for example, 0 V).

[0079] When the voltage at node N12 (approximately the drain voltage of the second rectifier transistor 22) becomes equal to or higher than a second threshold voltage (e.g., 0 V), the comparator 86b outputs a low-level signal to the buffer circuit 86c. The buffer circuit 86c outputs a low-level second control signal S2 to the gate of the second rectifier transistor 22 via the terminal 12e and the resistor 304. This turns the second rectifier transistor 22 off. Furthermore, the constant voltage source 86a switches its output voltage to a first threshold voltage (e.g., −0.2 V).

[0080] That is, the second control circuit 42 controls the second rectifier transistor 22 to be in the on state when the voltage between the first node N1 and the fourth node N4 is equal to or lower than the threshold value.

[0081] (Configuration and Operation of Third Control Circuit) The third control circuit 43 includes a second level shift circuit 101 and a second driver circuit 102. Known circuits can be used for the second level shift circuit 101 and the second driver circuit 102. The second level shift circuit 101 and the second driver circuit 102 operate using the voltage generated by the capacitor 306 as a power supply voltage.

[0082] The second level shift circuit 101 shifts the voltage level of the signal S11. The second driver circuit 102 outputs a third control signal S3 to the gate of the third rectifier transistor 23 via the terminal 12g and the resistor 305 based on the signal output from the second level shift circuit 101. When the signal S11 is at a high level, the second driver circuit 102 outputs a high-level third control signal S3 to the gate of the third rectifier transistor 23 via the terminal 12g and the resistor 305.

[0083] That is, the third control circuit 43 controls the third rectifier transistor 23 to be in the on state when the voltage VS_R<the voltage VS_L.

[0084] (Configuration and Operation of Fourth Control Circuit) The fourth control circuit 44 includes a resistor 121, a Zener diode 122, a transistor 123, a current passing circuit 124, a voltage passing circuit 125, and a signal output circuit 126. The signal output circuit 126 operates using the voltage generated by the capacitor 303 as a power supply voltage.

[0085] In the embodiment, the transistor 123 is an enhancement type transistor (normally off), but the present disclosure is not limited to this. If the transistor 123 is a depletion type transistor (normally on), the resistor 121, which is a startup resistor (described later), is not required. Furthermore, without the resistor 121, the voltage at the node N21 does not flow back to the terminal 12d via the voltage passing circuit 125. Therefore, the voltage passing circuit 125 does not require the diode 125b.

[0086] The current passing circuit 124 includes a resistor 124a and a diode 124b.

[0087] The voltage passing circuit 125 includes a resistor 125a and a diode 125b.

[0088] The signal output circuit 126 includes a constant voltage source 126a, a comparator 126b, and a buffer circuit 126c.

[0089] One end of the resistor 121 is electrically connected to the terminal 12i. The other end of the resistor 121 is electrically connected to the node N21. As will be described later, the resistor 121 is a bias resistor for turning on the transistor 123.

[0090] The cathode of the Zener diode 122 is electrically connected to the node N21. The anode of the Zener diode 122 is electrically connected to the terminal 12f. The Zener diode 122 clamps the voltage of the node N21 to its own Zener voltage (breakdown voltage).

[0091] The drain of the transistor 123 is electrically connected to the terminal 12i, the gate of the transistor 123 is electrically connected to the node N21, and the source of the transistor 123 is electrically connected to the node N22.

[0092] Since the voltage of node N21 is clamped by Zener diode 122, the voltage of node N22 is clamped to (voltage of node N21) - (threshold voltage of transistor 123). Specifically, if the Zener voltage (breakdown voltage) of Zener diode 122 is 18 V and the threshold of transistor 123 is 1.5 V, the voltage of node N21 is clamped to 18 V. Therefore, when node N22 rises to 18 V - 1.5 V = 16.5 V, the gate-source voltage of transistor 123 falls below the threshold, turning transistor 123 off. When the voltage of node N22 falls below 16.5 V, the gate-source voltage of transistor 123 rises above the threshold, turning transistor 123 on. In this way, the voltage of node N22 is clamped by turning transistor 123 on and off.

[0093] One end of the resistor 124a is electrically connected to the node N22. The other end of the resistor 124a is electrically connected to the anode of the diode 124b. The cathode of the diode 124b is electrically connected to the terminal 12d.

[0094] One end of the resistor 125a is electrically connected to the terminal 12d, and the other end of the resistor 125a is electrically connected to the anode of the diode 125b, and the cathode of the diode 125b is electrically connected to the node N21.

[0095] The low-potential end of the constant voltage source 126a is electrically connected to the terminal 12f. The high-potential end of the constant voltage source 126a is electrically connected to the non-inverting input terminal (+ terminal) of the comparator 126b. As will be described later, the constant voltage source 126a outputs a first threshold voltage (e.g., −0.2 V) when the fourth control signal S4 output from the signal output circuit 126 is at a low level (i.e., the fourth rectifier transistor 24 is off). The constant voltage source 126a outputs a second threshold voltage (e.g., 0 V) ​​when the fourth control signal S4 is at a high level (i.e., the fourth rectifier transistor 24 is on).

[0096] The inverting input terminal (negative terminal) of the comparator 126b is electrically connected to the node N22. The output terminal of the comparator 126b is electrically connected to the input terminal of the buffer circuit 126c. The output terminal of the buffer circuit 126c is electrically connected to the terminal 12j.

[0097] The inverting input terminal (negative terminal) of the comparator 126b is electrically connected to the drain of the fourth rectifier transistor 24 via the source-drain path of the transistor 123. The non-inverting input terminal (positive terminal) of the comparator 126b is electrically connected to the source of the fourth rectifier transistor 24 via the constant voltage source 126a. In other words, the comparator 126b compares the drain-source voltage of the fourth rectifier transistor 24 with the voltage of the constant voltage source 126a.

[0098] The operation of the fourth control circuit 44 will now be described.

[0099] When the voltage of the fourth node N4 is higher than the voltage of the second node N2, the fourth parasitic diode 24 a of the fourth rectifier transistor 24 is conductive, and therefore the voltage between the voltage of the fourth node N4 and the second node N2 is clamped to the voltage drop of the fourth parasitic diode 24 a. When the voltage of the second node N2 is higher than the voltage of the fourth node N4, the voltage between the voltage of the second node N2 and the fourth node N4 can rise to the input voltage Vin.

[0100] When the voltage at the second node N2 increases and becomes higher than the voltage at the fourth node N4 (voltage at the terminal 12i>voltage at the terminal 12f), a voltage is applied to the node N21 via the resistor 121, turning on the transistor 123. When the transistor 123 turns on, a voltage and a current are supplied to the node N22 via the drain-source path of the transistor 123.

[0101] The current passing circuit 124 passes a current from the node N22 to the terminal 12d. This charges the capacitor 303, causing the capacitor 303 to generate a voltage. This voltage is (the voltage at the node N22) - (the voltage drop across the current passing circuit 124). The constant voltage source 126a, the comparator 126b, and the buffer circuit 126c operate using the voltage of the capacitor 303 as a power supply voltage.

[0102] At this time, the capacitor 306 is charged by the voltage of the capacitor 303 via the diode 52 when the voltage of the second node N2 drops to a value close to the voltage of the fourth node N4.

[0103] When the voltage of the capacitor 303 reaches a certain level (above the threshold voltage of the diode 125b), the voltage passing circuit 125 passes the voltage at the terminal 12d to the node N21. Therefore, even if the voltage at the terminal 12i drops, the transistor 123 can remain on.

[0104] Next, the voltage at the second node N2 drops and becomes lower than the voltage at the fourth node N4 (voltage at the terminal 12i<voltage at the terminal 12f). As described above, the transistor 123 can maintain the on state, so the voltage at the node N22 becomes approximately the voltage at the terminal 12i (approximately the drain voltage of the fourth rectifier transistor 24).

[0105] The constant voltage source 126a outputs a first threshold voltage (e.g., −0.2 V) when the fourth control signal S4 output from the signal output circuit 126 is at a low level (= the fourth rectifier transistor 24 is off). The constant voltage source 126a outputs a second threshold voltage (e.g., 0 V) ​​when the fourth control signal S4 is at a high level (= the fourth rectifier transistor 24 is on).

[0106] When the voltage at node N22 (approximately the drain voltage of the fourth rectifier transistor 24) becomes equal to or lower than a first threshold voltage (e.g., −0.2 V), the comparator 126b outputs a high-level signal to the buffer circuit 126c. The buffer circuit 126c outputs a high-level fourth control signal S4 to the gate of the fourth rectifier transistor 24 via the terminal 12j and the resistor 307. This switches the fourth rectifier transistor 24 to an ON state. Furthermore, the constant voltage source 126a switches its output voltage to a second threshold voltage (e.g., 0 V).

[0107] Next, the voltage at the second node N2 rises and reaches the voltage at the fourth node N4 (the voltage at the terminal 12i = the voltage at the terminal 12f). As described above, the constant voltage source 126a outputs the second threshold voltage (for example, 0 V).

[0108] When the voltage at node N22 (approximately the drain voltage of the fourth rectifier transistor 24) becomes equal to or higher than a second threshold voltage (e.g., 0 V), the comparator 126b outputs a low-level signal to the buffer circuit 126c. The buffer circuit 126c outputs a low-level fourth control signal S4 to the gate of the fourth rectifier transistor 24 via the terminal 12j and the resistor 307. This turns the fourth rectifier transistor 24 off. Furthermore, the constant voltage source 126a switches its output voltage to a first threshold voltage (e.g., −0.2 V).

[0109] That is, the fourth control circuit 44 controls the fourth rectifier transistor 24 to the on state when the voltage between the second node N2 and the fourth node N4 is equal to or lower than the threshold value.

[0110] (Overall Operation of the Control Circuit) FIG. 3 is a diagram for explaining the operation of the control circuit of the first embodiment.

[0111] Line 401 represents the input voltage Vin. Line 402 represents the input current Iin. Line 403 represents the first control signal S1. Line 404 represents the third control signal S3. Line 405 represents the second control signal S2. Line 406 represents the fourth control signal S4.

[0112] Note that the dead time is omitted in Fig. 3. In reality, a dead time is provided between the first control signal S1 and the third control signal S3.

[0113] Timing t ０ From timing t ６ The timing t is one period of the input voltage Vin. ０ From timing t ３ The first half period (positive period) of the input voltage Vin is from the timing t ３ From timing t ６ This is the second half period (negative period) of the input voltage Vin.

[0114] Timing t ０ In this case, when the input voltage Vin becomes positive (voltage VS_R>voltage VS_L), the first control circuit 41 outputs a high-level first control signal S1 to the gate of the first rectifier transistor 21, as shown by line 403. This causes the first rectifier transistor 21 to enter an on state.

[0115] At this time, the fourth control circuit 44 outputs a low-level fourth control signal S4 to the gate of the fourth rectifier transistor 24, as indicated by a line 406. Therefore, the control circuit 12 can prevent a reverse current from flowing from the capacitor 3 to the AC power supply 2 even if the voltage VC of the capacitor 3 is greater than the input voltage Vin.

[0116] Timing t １ In this case, when the input voltage Vin becomes higher than the voltage VC of the capacitor 3, the voltage between the second node N2 and the fourth node N4 becomes equal to or lower than the threshold value. Therefore, the fourth control circuit 44 outputs a high-level fourth control signal S4 to the gate of the fourth rectifier transistor 24, as shown by line 406. This turns the fourth rectifier transistor 24 on.

[0117] As a result, the input current Iin starts to flow as shown by the line 402. The input current Iin flows through the path of one end of the AC power supply 2, the first rectifier transistor 21, the capacitor 3 and the load 4, the fourth rectifier transistor 24, and the other end of the AC power supply 2.

[0118] Timing t ２In this case, when the input voltage Vin becomes lower than the voltage VC of the capacitor 3, the voltage between the second node N2 and the fourth node N4 becomes equal to or higher than the threshold value. Therefore, the fourth control circuit 44 outputs a low-level fourth control signal S4 to the gate of the fourth rectifier transistor 24, as shown by line 406. This turns the fourth rectifier transistor 24 off.

[0119] Therefore, the control circuit 12 can prevent a current from flowing back from the capacitor 3 to the AC power supply 2 even if the voltage VC of the capacitor 3 is greater than the input voltage Vin.

[0120] Timing t ３ In this case, when the input voltage Vin becomes negative (voltage VS_R<voltage VS_L), the first control circuit 41 outputs a low-level first control signal S1 to the gate of the first rectifier transistor 21, as shown by line 403. This causes the first rectifier transistor 21 to be turned off. Furthermore, the third control circuit 43 outputs a high-level third control signal S3 to the gate of the third rectifier transistor 23, as shown by line 404. This causes the third rectifier transistor 23 to be turned on.

[0121] At this time, the second control circuit 42 outputs a low-level second control signal S2 to the gate of the second rectifier transistor 22, as shown by a line 405. Therefore, the control circuit 12 can prevent a reverse current from flowing from the capacitor 3 to the AC power supply 2 even if the voltage VC of the capacitor 3 is greater than the input voltage Vin.

[0122] Timing t ４ In this case, when the absolute value of the input voltage Vin becomes higher than the voltage VC of the capacitor 3, the voltage between the first node N1 and the fourth node N4 becomes equal to or lower than the threshold value. Therefore, the second control circuit 42 outputs a high-level second control signal S2 to the gate of the second rectifier transistor 22, as shown by line 405. This turns the second rectifier transistor 22 on.

[0123] As a result, the input current Iin starts to flow as shown by the line 402. The input current Iin flows through the path of the other end of the AC power supply 2, the third rectifier transistor 23, the capacitor 3 and the load 4, the second rectifier transistor 22, and the one end of the AC power supply 2.

[0124] Timing t ５ In this case, when the absolute value of the input voltage Vin becomes lower than the voltage VC of the capacitor 3, the voltage between the first node N1 and the fourth node N4 becomes equal to or higher than the threshold value. Therefore, the second control circuit 42 outputs a low-level second control signal S2 to the gate of the second rectifier transistor 22, as shown by line 405. This turns the second rectifier transistor 22 off.

[0125] Therefore, the control circuit 12 can prevent a current from flowing back from the capacitor 3 to the AC power supply 2 even if the voltage VC of the capacitor 3 is greater than the input voltage Vin.

[0126] Timing t ６ In this example, when the input voltage Vin becomes positive (voltage VS_R>voltage VS_L), the third control circuit 43 outputs a low-level third control signal S3 to the gate of the third rectifier transistor 23, as shown by line 404. This causes the third rectifier transistor 23 to be turned off. Furthermore, the first control circuit 41 outputs a high-level first control signal S1 to the gate of the first rectifier transistor 21, as shown by line 403. This causes the first rectifier transistor 21 to be turned on.

[0127] Thereafter, the control circuit 12 repeats the same operation.

[0128] In this way, the control circuit 12 can cause the bridge circuit 11 to perform synchronous rectification.

[0129] (Effects) [1] The second control circuit 42 includes a high-voltage MOSFET (transistor 83) for detecting the drain potential using the source potential of the second rectifier transistor 22 as a reference potential. Similarly, the fourth control circuit 44 includes a high-voltage MOSFET (transistor 123) for detecting the drain potential using the source potential of the fourth rectifier transistor 24 as a reference potential.

[0130] However, the first control circuit 41 does not detect the drain potential using the source potential of the first rectifier transistor 21 as a reference potential. Similarly, the third control circuit 43 does not detect the drain potential using the source potential of the third rectifier transistor 23 as a reference potential. In other words, the first control circuit 41 and the third control circuit 43 do not include a high-voltage MOSFET.

[0131] Therefore, the control circuit 12 includes the second control circuit 42, the fourth control circuit 44, the first control circuit 41, and the third control circuit 43, and is made of SiO ２ There is no need to separate them with a film, and they can be realized with a single semiconductor device with PN isolation, which allows the cost of the control circuit 12 to be reduced.

[0132] [2] For example, consider the case where the fourth control circuit 44 controls the fourth rectifier transistor 24 to be in the on state at the same time that the first control circuit 41 controls the first rectifier transistor 21 to be in the on state. In this case, during the period when the voltage VC of the capacitor 3 is greater than the input voltage Vin (for example, the period t ０ From timing t １ During this period, current flows back from the capacitor 3 to the AC power supply 2.

[0133] On the other hand, in the first embodiment, as described above, the fourth control circuit 44 controls the fourth rectifier transistor 24 to the on state when the voltage between the second node N2 and the fourth node N4 becomes equal to or lower than the threshold value.

[0134] Therefore, the control circuit 12 can prevent a current from flowing back from the capacitor 3 to the bridge circuit 11 during the period when the voltage VC of the capacitor 3 is greater than the input voltage Vin.

[0135] [3] For example, consider the case where the first control circuit 41 controls the first rectifier transistor 21 to be in the on state at the same time that the fourth control circuit 44 controls the fourth rectifier transistor 24 to be in the on state.

[0136] In this case, during the dead time period (when the first rectifier transistor 21 to the fourth rectifier transistor 24 are in the off state), the fourth control circuit 44 detects that the voltage between the second node N2 and the fourth node N4 is below the threshold value.

[0137] During the dead time, the voltage difference between the voltage VC of the capacitor 3 and the input voltage Vin is applied to the off-state first rectifier transistor 21 and the fourth rectifier transistor 24. If there is an individual difference between the impedance of the first rectifier transistor 21 and the impedance of the fourth rectifier transistor 24, the voltages at the second node N2 and the fourth node N4 will change, and the fourth control circuit 44 will not be able to perform stable detection.

[0138] On the other hand, in the first embodiment, the first rectifier transistor 21 is already in the on state at the timing when the fourth control circuit 44 detects the voltages of the second node N2 and the fourth node N4. In other words, the voltage that is the difference between the voltage VC of the capacitor 3 and the input voltage Vin is applied only to the fourth rectifier transistor 24.

[0139] Therefore, the fourth control circuit 44 can stably detect the timing when the voltage at the node N22 becomes equal to or lower than the first threshold voltage, and can stabilize the timing when the fourth rectifier transistor 24 is turned on. This makes it possible to suppress the influence of the individual differences described above on the control circuit 12.

[0140] <Modification of First Embodiment> FIG. 4 is a diagram showing the configuration of a control circuit according to a modification of the first embodiment.

[0141] Compared to the control circuit 12 (see FIG. 2), the control circuit 12A further includes a terminal 12k. The control circuit 12A also includes a first circuit 46a, a second circuit 46b, a third circuit 46c, and a fourth circuit 46d. Hereinafter, the first circuit 46a, the second circuit 46b, the third circuit 46c, and the fourth circuit 46d will be collectively referred to as the inhibition circuit 46.

[0142] (Configuration of the Suppression Circuit) The first circuit 46a includes resistors 151, 152, 153, and 157, and transistors 154, 155, and 156. The second circuit 46b includes a logical product circuit 158. The third circuit 46c includes a logical product circuit 159. The fourth circuit 46d includes logical product circuits 160 and 161.

[0143] A standby signal Sstd that instructs diode rectification by the first parasitic diode 21a, the second parasitic diode 22a, the third parasitic diode 23a, and the fourth parasitic diode 24a is input to the terminal 12k.

[0144] One end of the resistor 151 is electrically connected to the terminal 12k, and the other end of the resistor 151 is electrically connected to the gate of the transistor 154.

[0145] The source of the transistor 154 is electrically connected to the terminal 12f, and the drain of the transistor 154 is electrically connected to the node N21.

[0146] One end of the resistor 152 is electrically connected to the terminal 12k, and the other end of the resistor 152 is electrically connected to the gate of the transistor 155.

[0147] The source of the transistor 155 is electrically connected to the terminal 12f, and the drain of the transistor 155 is electrically connected to the node N11.

[0148] One end of the resistor 153 is electrically connected to the terminal 12k, and the other end of the resistor 153 is electrically connected to the gate of the transistor 156.

[0149] The source of the transistor 156 is electrically connected to the terminal 12f. The drain of the transistor 156 is electrically connected to one end of the resistor 157. The other end of the resistor 157 is electrically connected to the terminal 12d.

[0150] A first input terminal of the AND circuit 158 ​​is electrically connected to the output terminal of the comparator 86b. A second input terminal of the AND circuit 158 ​​is electrically connected to the drain of the transistor 156. An output terminal of the AND circuit 158 ​​is electrically connected to the input terminal of the buffer circuit 86c.

[0151] A first input terminal of the AND circuit 159 is electrically connected to the output terminal of the comparator 126b. A second input terminal of the AND circuit 159 is electrically connected to the drain of the transistor 156. An output terminal of the AND circuit 159 is electrically connected to the input terminal of the buffer circuit 126c.

[0152] A first input terminal of the AND circuit 160 is electrically connected to the output terminal of the logic inversion circuit 146. A second input terminal of the AND circuit 160 is electrically connected to the drain of the transistor 156. An output terminal of the AND circuit 160 is electrically connected to the first level shift circuit 61.

[0153] A first input terminal of the AND circuit 161 is electrically connected to the output terminal of the comparator 145. A second input terminal of the AND circuit 161 is electrically connected to the drain of the transistor 156. An output terminal of the AND circuit 161 is electrically connected to the second level shift circuit 101.

[0154] (Operation of the Inhibition Circuit) The operation of the inhibition circuit 46 will be described.

[0155] First, the case where the standby signal Sstd is at a low level will be described.

[0156] When the standby signal Sstd is at a low level, the transistors 154, 155, and 156 are in an off state.

[0157] When transistor 154 is off, the voltage at node N21 is unaffected. When transistor 155 is off, the voltage at node N11 is unaffected.

[0158] When the transistor 156 is in the off state, the voltage of the terminal 12 d , that is, the voltage (high level) of the capacitor 303 is input to the second terminals of the AND circuits 158 to 161 .

[0159] Therefore, the level of the output signal from AND circuit 158 ​​is the same as the level of the output signal from comparator 86b. The level of the output signal from AND circuit 159 is the same as the level of the output signal from comparator 126b. The level of the output signal from AND circuit 160 is the same as the level of the output signal from logic inversion circuit 146. The level of the output signal from AND circuit 161 is the same as the level of the output signal from comparator 145.

[0160] To summarize the above, when the standby signal Sstd is at a low level, the operation of the control circuit 12A is the same as the operation of the control circuit 12. In other words, the control circuit 12A can cause the bridge circuit 11 to perform synchronous rectification.

[0161] Next, the case where the standby signal Sstd is at a high level will be described.

[0162] When the standby signal Sstd is at a high level, the transistors 154, 155, and 156 are turned on.

[0163] When the transistor 154 is on, the voltage of the node N21 becomes low, which turns off the transistor 123. Therefore, the current supply to the current passing circuit 124 is cut off, and the current supply to the capacitors 302, 303, and 306 is cut off.

[0164] When the transistor 155 is on, the voltage of the node N11 becomes low, which turns off the transistor 83. Therefore, the current supply to the current passing circuit 84 is cut off, and the current supply to the capacitors 302, 303, and 306 is cut off.

[0165] When the transistor 156 is in an on state, a low level is input to the second terminals of the AND circuits 158 to 161. Therefore, the levels of the output signals from the AND circuits 158 to 161 are low.

[0166] Furthermore, when the transistor 156 is in the on state, the capacitor 303 is discharged, and the power supply voltage to each part in the control circuit 12A is cut off.

[0167] To summarize the above, when the standby signal Sstd is at a high level, the control circuit 12A does not turn on the first rectifier transistor 21 to the fourth rectifier transistor 24, but keeps them in an off state. In other words, the control circuit 12A can cause the bridge circuit 11 to perform diode rectification.

[0168] (Effect) In the conventional control circuit, there are three reference potentials, making it difficult to switch from synchronous rectification to diode rectification.

[0169] On the other hand, the control circuit 12A can switch from synchronous rectification to diode rectification by the standby signal Sstd.

[0170] Second Embodiment FIG. 5 is a diagram showing the configuration of a control circuit according to a second embodiment.

[0171] Compared to the control circuit 12 (see FIG. 2), the control circuit 12B further includes a terminal 12l and a terminal 12m. A resistor 311 is electrically connected between the terminal 12l and the terminal 12m. The resistance value of the resistor 311 is, for example, about 1 MΩ (megaohms) to 3 MΩ, but the present disclosure is not limited thereto.

[0172] Furthermore, compared to the control circuit 12, the control circuit 12B includes a first control circuit 41B instead of the first control circuit 41. Furthermore, compared to the control circuit 12, the control circuit 12B includes a third control circuit 43B instead of the third control circuit 43.

[0173] (Configuration of First Control Circuit) Compared to the first control circuit 41 (see FIG. 2), the first control circuit 41B includes a phase detection circuit 63 instead of the first level shift circuit 61.

[0174] The phase detection circuit 63 includes a resistor 181 , a transistor 182 , a diode 183 , and a Zener diode 184 .

[0175] One end of the resistor 181 is electrically connected to the terminal 12b. The other end of the resistor 181 is electrically connected to a node N32. The drain of the transistor 182 is electrically connected to the node N32. The gate of the transistor 182 is electrically connected to the node N31. The source of the transistor 182 is electrically connected to the terminal 12c.

[0176] The cathode of the diode 183 is electrically connected to the node N31, and the anode of the diode 183 is electrically connected to the terminal 12c.

[0177] The cathode of the Zener diode 184 is electrically connected to the node N31. The anode of the Zener diode 184 is electrically connected to the terminal 12c. The Zener diode 184 clamps the voltage between the node N31 and the terminal 12c to its own Zener voltage (breakdown voltage).

[0178] The node N31 is electrically connected to the terminal 12l.

[0179] (Configuration of Third Control Circuit) Compared to the third control circuit 43 (see FIG. 2), the third control circuit 43B includes a phase detection circuit 103 instead of the second level shift circuit 101.

[0180] The phase detection circuit 103 includes a resistor 201 , a transistor 202 , a diode 203 , and a Zener diode 204 .

[0181] One end of the resistor 201 is electrically connected to the terminal 12h. The other end of the resistor 201 is electrically connected to a node N42. The drain of the transistor 202 is electrically connected to the node N42. The gate of the transistor 202 is electrically connected to the node N41. The source of the transistor 202 is electrically connected to the terminal 12i.

[0182] The cathode of the diode 203 is electrically connected to the node N41, and the anode of the diode 203 is electrically connected to the terminal 12i.

[0183] The cathode of the Zener diode 204 is electrically connected to the node N41. The anode of the Zener diode 204 is electrically connected to the terminal 12i. The Zener diode 204 clamps the voltage between the node N41 and the terminal 12i to its own Zener voltage (breakdown voltage).

[0184] The node N41 is electrically connected to the terminal 12m.

[0185] That is, the phase detection circuit 63 and the phase detection circuit 103 are electrically connected via the resistor 311 .

[0186] (Operations of the First Control Circuit and the Third Control Circuit) The operations of the first control circuit 41B and the third control circuit 43B will be described.

[0187] FIG. 6 is a diagram illustrating the operation of the control circuit according to the second embodiment.

[0188] Line 401 represents the input voltage Vin. Line 402 represents the input current Iin. Line 411 represents the voltage V31 between node N31 and terminal 12c. Line 412 represents the voltage V41 between node N41 and terminal 12i. Line 403 represents the first control signal S1. Line 404 represents the third control signal S3. Line 405 represents the second control signal S2. Line 406 represents the fourth control signal S4.

[0189] Timing t １０ From timing t １６ The timing t is one period of the input voltage Vin. １０ From timing t １３ The first half period (positive period) of the input voltage Vin is from the timing t １３ From timing t １６ This is the second half period (negative period) of the input voltage Vin.

[0190] Timing t １０ When the input voltage Vin becomes positive (voltage VS_R>voltage VS_L), conduction occurs through the path terminal 12c→diode 183→node N31→resistor 311→node N41→zener diode 204→terminal 12i.

[0191] Therefore, the voltage V31 becomes negative (corresponding to the voltage drop of the diode 183), and the voltage V41 becomes positive (corresponding to the breakdown voltage of the Zener diode 204).

[0192] The transistor 182 is turned off because the gate-source voltage (voltage V31) is negative (corresponding to the voltage drop of the diode 183). Therefore, the node N32 is pulled up by the resistor 181 and goes high.

[0193] As a result, the first driver circuit 62 outputs a high-level first control signal S1 to the gate of the first rectifier transistor 21 via the resistor 301 .

[0194] Furthermore, the transistor 202 is turned on because the gate-source voltage (voltage V41) is positive (corresponding to the breakdown voltage of the Zener diode 204). Therefore, the drain current of the transistor 202 flows through the resistor 201, causing a voltage drop at the node N42, which becomes low level.

[0195] As a result, the second driver circuit 102 outputs a low-level third control signal S3 to the gate of the third rectifier transistor 23 via the resistor 305 .

[0196] Timing t １１ and timing t １２ The operation of the fourth control circuit 44 at the timing t １ and timing t ２ Since the operation of the fourth control circuit 44 is the same as that of the fourth control circuit 44 in the first embodiment, the explanation thereof will be omitted.

[0197] Timing t １３ When the input voltage Vin becomes negative (voltage VS_R<voltage VS_L), conduction occurs through the path terminal 12i→diode 203→node N41→resistor 311→node N31→zener diode 184→terminal 12c.

[0198] Therefore, the voltage V31 becomes positive (corresponding to the breakdown voltage of the Zener diode 184), and the voltage V41 becomes negative (corresponding to the voltage drop of the diode 203).

[0199] The transistor 182 is turned on because the gate-source voltage (voltage V31) is positive (corresponding to the breakdown voltage of the Zener diode 184). Therefore, the drain current of the transistor 182 flows through the resistor 181, causing a voltage drop at the node N32, which becomes low level.

[0200] As a result, the first driver circuit 62 outputs a low-level first control signal S1 to the gate of the first rectifier transistor 21 via the resistor 301 .

[0201] Furthermore, the transistor 202 is turned off because the gate-source voltage (voltage V41) is negative (corresponding to the voltage drop of the diode 203). Therefore, the node N42 is pulled up by the resistor 201 and goes high.

[0202] As a result, the second driver circuit 102 outputs a high-level third control signal S3 to the gate of the third rectifier transistor 23 via the resistor 305 .

[0203] Timing t １４ and timing t １５ The operation of the second control circuit 42 at the timing t ４ and timing t ５ Since the operation of the second control circuit 42 is the same as that of the second control circuit 42 in the first embodiment, the explanation will be omitted.

[0204] Timing t １６ When the input voltage Vin becomes positive (voltage VS_R>voltage VS_L), conduction occurs through the path terminal 12c→diode 183→node N31→resistor 311→node N41→zener diode 204→terminal 12i.

[0205] Therefore, the voltage V31 becomes negative (corresponding to the voltage drop of the diode 183), and the voltage V41 becomes positive (corresponding to the breakdown voltage of the Zener diode 204).

[0206] The transistor 182 is turned off because the gate-source voltage (voltage V31) is negative (corresponding to the voltage drop of the diode 183). Therefore, the node N32 is pulled up by the resistor 181 and goes high.

[0207] As a result, the first driver circuit 62 outputs a high-level first control signal S1 to the gate of the first rectifier transistor 21 via the resistor 301 .

[0208] Furthermore, the transistor 202 is turned on because the gate-source voltage (voltage V41) is positive (corresponding to the breakdown voltage of the Zener diode 204). Therefore, the drain current of the transistor 202 flows through the resistor 201, causing a voltage drop at the node N42, which becomes low level.

[0209] As a result, the second driver circuit 102 outputs a low-level third control signal S3 to the gate of the third rectifier transistor 23 via the resistor 305 .

[0210] Thereafter, the first control circuit 41B and the third control circuit 43B repeat the same operations.

[0211] In this way, the control circuit 12B can cause the bridge circuit 11 to perform synchronous rectification.

[0212] (Effect) Compared to the control circuit 12, the control circuit 12B can eliminate the need for the first level shift circuit 61 and the second level shift circuit 101.

[0213] This allows the control circuit 12B to have a simple circuit configuration.

[0214] (Additional Note) The transistor 182 may be replaced with a comparator that compares the voltage at the node N31 with the voltage at the terminal 12c. Similarly, the transistor 202 may be replaced with a comparator that compares the voltage at the node N41 with the voltage at the terminal 12i. When a comparator is used, more precise timing adjustment is possible, such as changing the on / off threshold value, and more precise adjustment of the dead time is possible.

[0215] <First Modification of Second Embodiment> FIG. 7 is a diagram showing the configuration of a control circuit according to a first modification of the second embodiment.

[0216] Compared to the control circuit 12B (see FIG. 5), the control circuit 12C includes a first control circuit 41C instead of the first control circuit 41B. Also, compared to the control circuit 12B, the control circuit 12C includes a third control circuit 43C instead of the third control circuit 43B.

[0217] Compared to the first control circuit 41B (see FIG. 5), the first control circuit 41C includes a phase detection circuit 63C instead of the phase detection circuit 63. Compared to the phase detection circuit 63, the phase detection circuit 63C includes a first offset voltage application circuit 221. The first offset voltage application circuit 221 further includes a constant current source 221a and a resistor 221b. The constant current source 221a operates using the voltage of the capacitor 302 as a power supply voltage.

[0218] One end of the constant current source 221a is electrically connected to the terminal 12b. The other end of the constant current source 221a is electrically connected to the node N31. One end of the resistor 221b is electrically connected to the node N31. The other end of the resistor 221b is electrically connected to the terminal 12c.

[0219] The output current of the constant current source 221a flows through the resistor 221b. As a result, the voltage V31 is offset in the positive direction. Therefore, the phase detection circuit 63C can adjust the timing at which the transistor 182 turns on and off by adjusting the output current value of the constant current source 221a and the resistance value of the resistor 221b.

[0220] Compared to the third control circuit 43B (see FIG. 5), the third control circuit 43C includes a phase detection circuit 103C instead of the phase detection circuit 103. Compared to the phase detection circuit 103, the phase detection circuit 103C includes a second offset voltage application circuit 241. The second offset voltage application circuit 241 further includes a constant current source 241a and a resistor 241b. The constant current source 241a operates using the voltage of the capacitor 306 as a power supply voltage.

[0221] One end of the constant current source 241a is electrically connected to the terminal 12h. The other end of the constant current source 241a is electrically connected to the node N41. One end of the resistor 241b is electrically connected to the node N41. The other end of the resistor 241b is electrically connected to the terminal 12i.

[0222] The output current of the constant current source 241a flows through the resistor 241b. This causes the voltage V41 to be offset in the positive direction. Therefore, the phase detection circuit 103C can adjust the timing at which the transistor 202 turns on and off by adjusting the output current value of the constant current source 241a and the resistance value of the resistor 241b.

[0223] (Effect) The phase detection circuit 63C can adjust the timing at which the transistor 182 turns on and off by adjusting the output current value of the constant current source 221a and the resistance value of the resistor 221b. Furthermore, the phase detection circuit 103C can adjust the timing at which the transistor 202 turns on and off by adjusting the output current value of the constant current source 241a and the resistance value of the resistor 241b.

[0224] Therefore, the control circuit 12C can easily adjust the dead time.

[0225] <Second Modification of Second Embodiment> FIG. 8 is a diagram showing the configuration of a control circuit according to a second modification of the second embodiment.

[0226] Compared to the control circuit 12B (see FIG. 5), the control circuit 12D further includes a terminal 12k. The control circuit 12D also includes a first circuit 46a, a second circuit 46b, and a third circuit 46c. Hereinafter, the first circuit 46a, the second circuit 46b, and the third circuit 46c will be collectively referred to as the suppression circuit 46D.

[0227] The configuration and operation of the inhibiting circuit 46D are similar to those of the inhibiting circuit 46 of the modified example of the first embodiment, and therefore a description thereof will be omitted.

[0228] In this modified example, the first control circuit 41B and the third control circuit 43B cannot be turned on or off directly, but the first control circuit 41B and the third control circuit 43B can be turned on or off indirectly by cutting off the charging of the capacitors 302 and 306.

[0229] (Effect) The control circuit 12D can switch from synchronous rectification to diode rectification using the standby signal Sstd.

[0230] (Additional Note) The first modified example of the second embodiment may be combined with the second modified example of the second embodiment, that is, the control circuit 12B (see FIG. 5) may include the inhibit circuit 46D.

[0231] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the contents of these embodiments. Furthermore, the above-described components include those that can be easily imagined by a person skilled in the art, those that are substantially the same, and those that are within the so-called equivalent range. Furthermore, the above-described components can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the spirit of the above-described embodiments.

[0232] 1 Rectifier circuit 2 AC power supply 3 Capacitor 4 Load 11 Bridge circuit 11-1 First arm 11-2 Second arm 12, 12A, 12B, 12C, 12D Control circuit 21 First rectifier transistor 21a First parasitic diode 22 Second rectifier transistor 22a Second parasitic diode 23 Third rectifier transistor 23a Third parasitic diode 24 Fourth rectifier transistor 24a Fourth parasitic diode 41, 41B, 41C First control circuit 42 Second control circuit 43, 43B, 43C Third control circuit 44 Fourth control circuit 45 Comparison circuit 46a First circuit 46b Second circuit 46c Third circuit 46d Fourth circuit 51, 52, 84b, 85b, 124b, 125b, 183, 203 Diode 61 First level shift circuit 62 First driver circuit 63, 103 Phase detection circuit 81, 84a, 85a, 121, 124a, 125a, 141, 142, 143, 144, 151, 152, 153, 157, 181, 201, 221b, 241b, 301, 304, 305, 307, 311 Resistor 82, 122, 184, 204 Zener diode 83, 123, 182, 202 Transistor 84, 124 Current passing circuit 85, 125 Voltage passing circuit 86, 126 Signal output circuit 86a, 126a Constant voltage source 86b, 126b, 145 Comparator 86c, 126c Buffer circuit 101 Second level shift circuit 102 Second driver circuit 146 Logic inversion circuits 158, 159, 160, 161 Logical product circuit 221 First offset voltage application circuit 221a, 241a Constant current source 241 Second offset voltage application circuit 302, 303, 306 Capacitor

Claims

1. A control circuit for controlling a bridge circuit that rectifies an AC voltage input between a first input point, which is a connection point between a source of a first rectifier transistor on the high side of a first arm and a drain of a second rectifier transistor on the low side of a first arm, and a second input point, which is a connection point between a source of a third rectifier transistor on the high side of a second arm and a drain of a fourth rectifier transistor on the low side of a second arm, and outputs a DC voltage from between a first output point, which is a connection point between a drain of the first rectifier transistor and a drain of the third rectifier transistor, and a second output point, which is a connection point between a source of the second rectifier transistor and a source of the fourth rectifier transistor, the first control circuit outputting a first control signal to a gate of the first rectifier transistor for controlling the first rectifier transistor to an ON state when a voltage of the first input point is higher than a voltage of the second input point; and a second control circuit outputting a second control signal to a gate of the second rectifier transistor for controlling the second rectifier transistor to an ON state when a voltage between the first input point and the second output point is equal to or lower than a threshold value. a third control circuit that outputs a third control signal to a gate of the third rectifier transistor to control the third rectifier transistor to an on state when a voltage of the first input point is lower than a voltage of the second input point; and a fourth control circuit that outputs a fourth control signal to the gate of the fourth rectifier transistor to control the fourth rectifier transistor to an on state when a voltage between the second input point and the second output point is equal to or lower than a threshold.

2. The control circuit according to claim 1, further comprising a comparison circuit which compares the voltage at the first input point with the voltage at the second input point and outputs a first comparison signal and a second comparison signal having an inverse logic to the first comparison signal, wherein the first control circuit comprises: a first level shift circuit which shifts the voltage level of the first comparison signal; and a first driver circuit which outputs the first control signal obtained by amplifying the output signal of the first level shift circuit to the gate of the first rectifier transistor, and wherein the third control circuit comprises: a second level shift circuit which shifts the voltage level of the second comparison signal; and a second driver circuit which outputs the third control signal obtained by amplifying the output signal of the second level shift circuit to the gate of the third rectifier transistor.

3. The control circuit according to claim 2, further comprising an inhibition circuit that inhibits the first control signal, the second control signal, the third control signal, and the fourth control signal when a signal instructing to perform diode rectification using parasitic diodes of the first rectifier transistor, the second rectifier transistor, the third rectifier transistor, and the fourth rectifier transistor is input.

4. The control circuit according to claim 1, characterized in that the first control circuit includes: a first phase detection circuit that detects the phase between the voltage at the first input point and the voltage at the second input point; and a first driver circuit that outputs the first control signal based on the detection result of the first phase detection circuit to the gate of the first rectifier transistor; and the third control circuit includes: a second phase detection circuit that detects the phase between the voltage at the first input point and the voltage at the second input point; and a second driver circuit that outputs the third control signal based on the detection result of the second phase detection circuit to the gate of the third rectifier transistor.

5. The first phase detection circuit includes: a first diode having an anode electrically connected to the first input point and a cathode electrically connected to one end of a resistor; a first Zener diode having an anode electrically connected to the first input point and a cathode electrically connected to the cathode of the first diode; a first transistor having a source electrically connected to the first input point and a gate electrically connected to the cathode of the first diode; and a first pull-up resistor that pulls up the drain of the first transistor; the second phase detection circuit includes: a second diode having an anode electrically connected to the second input point and a cathode electrically connected to the other end of the resistor; a second Zener diode having an anode electrically connected to the second input point and a cathode electrically connected to the cathode of the second diode; a second transistor having a source electrically connected to the second input point and a gate electrically connected to the cathode of the second diode; and a second pull-up resistor that pulls up the drain of the second transistor; and the first driver circuit includes:

5. The control circuit according to claim 4, wherein the first control signal is an amplified version of the drain voltage of the first transistor, and the second driver circuit is configured to output the third control signal, which is an amplified version of the drain voltage of the second transistor, to the gate of the third rectifier transistor.

6. The control circuit according to claim 5, wherein the first phase detection circuit further includes a first offset voltage application circuit that applies an offset voltage to the gate of the first transistor, and the second phase detection circuit further includes a second offset voltage application circuit that applies an offset voltage to the gate of the second transistor.

7. The control circuit according to claim 4, further comprising an inhibition circuit that inhibits the second control signal and the fourth control signal and inhibits the power supply voltages of the first control circuit and the third control circuit when a signal instructing to perform diode rectification using parasitic diodes of the first rectifier transistor, the second rectifier transistor, the third rectifier transistor, and the fourth rectifier transistor is input.

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