Method and system for operating 7-switch zero inductor voltage converter

Abstract

A method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter includes: selectively controlling a first set of switches of a first stage having a first flying capacitor to control a first current between a positive input terminal and a first internal node; selectively controlling a second set of switches of a second stage having a second flying capacitor to control a second current between the first internal node and a second internal node; conducting, by an inductor, current between the second internal node and a positive output terminal for supplying power to a load connected to the positive output terminal. The inductor has zero average voltage thereacross for each switching cycle of a plurality of switching cycles and the 2-stage ZIV power converter is operable with a conversion ratio between an input voltage and an output voltage and having a value greater than 0.5.

Description

[0001] Attorney Docket No.18402-05172 (713299PCT) METHOD AND SYSTEM FOR OPERATING 7-SWITCH ZERO INDUCTOR VOLTAGE CONVERTER CROSS-REFERENCE TO RELATED APPLICATIONS This PCT International Patent Application claims the benefit of and priority to U.S. Provisional Patent Application Serial No. 63 / 605,606 filed on December 4, 2023, and titled “Method And System For Operating 7-Switch Zero Inductor Voltage Converter,” the entire disclosure of which is hereby incorporated by reference. FIELD The present disclosure relates generally to Zero Inductor Voltage (ZIV) type direct current (DC) to DC (DC-DC) power converters, and methods of operating such power converters. BACKGROUND In recent times, there has been a surge of interest in the 48 V bus system development in data centers and automotive applications. The 48 V buses significantly reduce the power delivery loss and decrease the load demand on traditionally used 12 V buses. An intermediate bus converter (IBC) is typically used between 48 V and 12 V busses, followed by another converter at the point of load (POL) for load voltages as low as 1 V. It is challenging to obtain a step-down voltage conversion from 48 V to POL voltage in a single stage while maintaining high efficiency of the system. Several topologies such as coupled-inductor-based step- down converters, magnetic-based LLC resonant converters, and switched–capacitors have been developed to step-down the 48 V. Due to their use of very large inductors, the coupled-inductor converters have a lower power density, and they must compromise on efficiency to reduce their size. The LLC converter is generally superior to coupled-inductor converters in terms of power density and efficiency, but a significant disadvantage is its high cost, limited scalability, and Attorney Docket No.18402-05172 (713299PCT) complex transformer design. The switched capacitor converter (SCC) is generally preferred among these options. In these SCC converters, compared to the other converters, the voltage across the inductor is significantly low (only the AC voltage component of the capacitors), so they utilize a relatively small inductor. Another advantage of these converters is a fast dynamic response and good voltage regulation at the nominal point. However, conventional SCC converters are generally limited by a discrete voltage conversion ratio that may be restricted by the structure of the converter circuit. Several control strategies and hardware arrangements have been proposed to operate SCC converters over a wide voltage conversion range either by variable duty cycle or by frequency modulation. However, such control strategies have several drawbacks, such as a limited voltage conversion ratio of 0.3 to 0.7, high ripple current, EMI (electromagnetic interference) issues, and / or low efficiency at high and / or low voltage ratios. SUMMARY The present disclosure provides a method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter, including: selectively controlling a first set of switches of a first stage having a first flying capacitor to control a first current between a positive input terminal and a first internal node; selectively controlling a second set of switches of a second stage having a second flying capacitor to control a second current between the first internal node and a second internal node; and conducting, by an inductor, current between the second internal node and a positive output terminal for supplying power to a load connected to the positive output terminal. The inductor has zero average voltage thereacross for each switching cycle of a plurality of switching cycles, and selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to operate with a conversion ratio between an input voltage Attorney Docket No.18402-05172 (713299PCT) of the positive input terminal and an output voltage of the positive output terminal and having a value greater than 0.5. The present disclosure also provides a method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter, including: selectively controlling each of a first set of switches of a first stage and a second set of switches of a second stage to conduct current via an inductor and to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 58 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.0 A. The present disclosure also provides a power converter system. The power converter system includes: a 2-stage Zero Inductor Voltage (ZIV) power converter and a controller. The 2-stage ZIV power converter includes: a first stage including a first set of switches and a first flying capacitor and configured to control a first current between a positive input terminal and a first internal node; a second stage including a second set of switches and a second flying capacitor and configured to control a second current between the first internal node and a second internal node; and an inductor connected directly between the second internal node and a positive output terminal. The controller is configured to command each switch of the first set of switches and each switch of the second set of switches to selectively conduct current to cause: the inductor to have zero average voltage thereacross for each switching cycle of a plurality of switching cycles, and the 2-stage ZIV power converter to operate with a conversion ratio between an input voltage of the positive input terminal and an output voltage of the positive output terminal and having a value greater than 0.5. Attorney Docket No.18402-05172 (713299PCT) BRIEF DESCRIPTION OF THE DRAWINGS Further details, features and advantages of designs of the invention result from the following description of embodiment examples in reference to the associated drawings. FIG.1 shows a schematic block diagram of a system, in accordance with an aspect of the present disclosure; FIG.2 shows a schematic diagram showing a 7-switch Zero Inductor Voltage (ZIV) power converter of the present disclosure; FIG. 3 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a first control mode for operating the power converter with a conversion ratio D between 0 and 0.25, in accordance with an aspect of the present disclosure; FIGS.4-9 shows the schematic diagram of the power converter, illustrating current flow therethrough in the first control mode and during each of six successive timing intervals, t11,t12, t13, t14, t15, and t16, respectively, in accordance with an aspect of the present disclosure; FIG. 10 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a conversion ratio D = 0.25, in accordance with an aspect of the present disclosure; FIG. 11 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a second control mode for operating the power converter with a conversion ratio D between 0.25 and 0.33, in accordance with an aspect of the present disclosure; FIGS. 12-15 shows the schematic diagram of the power converter, illustrating current flow therethrough in the second control mode and during each of four successive timing intervals, t21,t22,t23,and t24, respectively, in accordance with an aspect of the present disclosure; Attorney Docket No.18402-05172 (713299PCT) FIG. 16 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a conversion ratio D = 0.33, in accordance with an aspect of the present disclosure; FIG. 17 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a third control mode for operating the power converter with a conversion ratio D between 0.33 and 0.5, in accordance with an aspect of the present disclosure; FIGS. 18-21 shows the schematic diagram of the power converter, illustrating current flow therethrough in the third control mode and during each of four successive timing intervals, t31,t32,t33,and t34, respectively, in accordance with an aspect of the present disclosure; FIG. 22 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a conversion ratio D = 0.5, in accordance with an aspect of the present disclosure; FIG. 23 shows a graph illustrating switch control signals, inductor voltage, and inductor current for a fourth control mode for operating the power converter with a conversion ratio D between 0.5 and 1.0, in accordance with an aspect of the present disclosure; FIGS. 24-27 shows the schematic diagram of the power converter, illustrating current flow therethrough in the fourth control mode and during each of four successive timing intervals, t41, t42, t43, and t44, respectively, in accordance with an aspect of the present disclosure; FIG.28 shows a graph illustrating inductor current over one switching cycle in the power converter operating in the first control mode, in accordance with an aspect of the present disclosure; Attorney Docket No.18402-05172 (713299PCT) FIG. 29 shows a graph illustrating first flying capacitor current over one switching cycle in the power converter operating in the first control mode, in accordance with an aspect of the present disclosure; FIG. 30 shows a graph illustrating normalized output voltage with respect to duty cycle for the power converter operated in accordance with the present disclosure; FIG. 31 shows a graph illustrating voltage across the first flying capacitor with respect to the input voltage and for the power converter operated in accordance with the present disclosure; FIG. 32 shows a graph illustrating voltage across the second flying capacitor with respect to the input voltage and for the power converter operated in accordance with the present disclosure; and FIG. 33 shows a graph illustrating peak-to-peak output current ripple with respect to input voltage for the power converter operated in accordance with the present disclosure. DETAILED DESCRIPTION Referring to the drawings, the present invention will be described in detail in view of following embodiments. To overcome the technical limitations of the existing approaches, the present disclosure provides a method and system for operating a 7-switch Zero Inductor Voltage (ZIV) power converter. The converter is a step-down capacitive solution which may be operated with a fixed input to output conversion ratio. It has almost zero output current ripple and high efficiency, especially at high output current. Applications for the converter, with the fixed conversion ratio, may be limited. However, with the control strategy of the present disclosure, the control ability of the converter is extended to the fullest. Unlike the other control methods that may be used, this Attorney Docket No.18402-05172 (713299PCT) method does not need any auxiliary components, and the regulation range is extended to the fullest. At the same time, the output current ripple is kept low to achieve high efficiency. The other merit of low current ripple is that a smaller inductor can be used which improves the power density and reduced cost significantly. The solutions of the present disclosure provide several benefits and advantages over conventional ZIV power converter control techniques and other power converters with conventional designs. FIG. 1 shows a block diagram of system 10 in accordance with an aspect of the present disclosure. The system 10 includes a 7-switch converter 20 connected between a power source 12 and a load 16 for transmitting power therebetween. The power source 12 supplies input current Iin to the 7-switch converter 20 via a positive input terminal 14a and a negative input terminal 14b a defining an input voltage Vintherebetween. The 7-switch converter 20 supplies an output current Io to the load 16 via a positive output terminal 18a and a negative output terminal 18b a defining an output voltage Vintherebetween. The system 10 of FIG. 1 also includes an electronic control unit (ECU) 30 in communication with the 7-switch converter 20 control operation of the 7-switch converter 20. The ECU 30 may also monitor parameters measured by one or more sensors associated with the 7- switch converter 20. The ECU 30 includes a processor 32 coupled to a storage memory 34. The storage memory 34 stores instructions, such as program code for execution by the processor 32, in an instruction storage 36. The storage memory 34 also includes data storage 38 for holding data to be used by the processor 32. The data storage 38 may record, for example, values of the parameters measured by the one or more sensors and / or the outcome of functions calculated by the processor 32. Attorney Docket No.18402-05172 (713299PCT) FIG. 2 shows a schematic diagram showing details of the 7-switch converter 20, having a 7-switch ZIV type configuration. The 7-switch ZIV power converter is a type of switched capacitor converter (SCC) with an output inductor having zero average voltage across each switching cycle of a plurality of switching cycles. FIG.2 shows the system 10 including the power source 12 as a battery. However, the power source 12 may include any suitable source of DC power, such as one or more batteries, capacitors, other electronic converters, etc. As shown in FIG.2, the 7-switch converter 20 includes a first stage 40 and a second stage 50 and defines a first internal node 22 a second internal node 24, a third internal node 26, a fourth internal node 28, and a fifth internal node 29. The first stage 40 contains a first set of switches S1, S2, S3, S4including four switches and a first flying capacitor 42 defining a first capacitance Cf1 between the third internal node 26 and the fourth internal node 28. The first flying capacitor 42 may also be called Cf1. The second stage 50 includes a second set of switches M1, M2, M3 including three switches, and a second flying capacitor 52 defining a second capacitance Cf2 between the first internal node 22 and the fifth internal node 29. The second flying capacitor 52 may also be called Cf2. The first stage 40 controls a flow of current between the positive input terminal 14a and the first internal node 22, and the second stage 50 controls a flow of current between the first internal node 22 and the second internal node 24. An inductor 54 having an inductance LO is connected between the second internal node 24 and the positive output terminal 18a and controls a surge current among the charging and discharging capacitors at the output side. The inductor 54 may also be called LO. The first set of switches S1, S2, S3, S4includes a first switch S1configured to selectively conduct current between the positive input terminal 14a and the third internal node 26. Attorney Docket No.18402-05172 (713299PCT) The first set of switches S1, S2, S3, S4 also includes a second switch S2 configured to selectively conduct current between the third internal node 26 and the first internal node 22. The first set of switches S1, S2, S3, S4 also includes a third switch S3 configured to selectively conduct current between the first internal node 22 and the fourth internal node 28. The first set of switches S1, S2, S3, S4also includes a fourth switch S4configured to selectively conduct current between the fourth internal node 28 and a common ground. The common ground may be connected to each of the negative input terminal 14b and the negative output terminal 18b. The second set of switches M1, M2, M3 includes a fifth switch M1 configured to selectively conduct current between the first internal node 22 and the second internal node 24. The second set of switches M1, M2, M3also includes a sixth switch M2configured to selectively conduct current between the second internal node 24 and the fifth internal node 29. The second set of switches M1, M2, M3also includes a seventh switch M3configured to selectively conduct current between the fifth internal node 29 and the common ground. Each of the switches S1, S2, S3, S4, M1, M2, and M3may include field effect transistor (FET) devices. However, other types of devices, such as junction transistors, may be used in any or all of the switches S1, S2, S3, S4, M1, M2, and M3. The 7-switch converter 20 also includes an output capacitor 56 connected between the positive output terminal 18a and the common ground and having a capacitance CO. The output capacitor 56 may also be called CO. Additionally, the load 16 is shown as a resistor having a load resistance RL. However, the load 16 may have a complex impedance with a resistive and / or inductive component, and each component of the complex impedance may be fixed or variable over time. Input and Attorney Docket No.18402-05172 (713299PCT) output voltages are defined as Vin and VO, respectively. The voltage across the first flying capacitor 42 is VCf1, and the voltage across the second flying capacitor 52 is VCf2. Several assumptions are made in the analysis of the 7-switch converter 20. Real- world operation may vary depending on numerous factors. For simplicity of explanation and modeling, the following assumptions are made: - All switches are ideal; dead time between the switches gate-pulses is ignored. However, a small amount of dead time is necessary for the experiment depending on the switch type, driver speed, etc. - The capacitors voltages (VCf1 and VCf2) are assumed to be constant. - “switch” means any type of controlled semiconductor which can be turned on and off by signal command. Moreover, instead of switches S3, S4, M2, and M3, diodes or uncontrolled semiconductor switches can be utilized too. - The duty cycle (D) is the fraction of a switching cycle when S1 is turned on, as describedby equation (1):^^^^ ൌ ௌభ (1)where tS1 is the time duration in which FIG. 1 shows input and output parameters of the 7-switch converter 20. The input voltage (Vin) and the input current (Iin) are the input parameters, and the output voltage (VO) and the output current (IO) are the output parameters. The control method presented in the present disclosure includes an objective to make the output voltage VOand / or output current IOproperly follow a corresponding reference value (which can be a fixed or variable value) when the input voltage Vinand / or the input current Iinis fixed or changing. In this disclosure, control of output voltage VOis discussed, but the techniques of the present disclosure may be applied to control of output current IO as well. Attorney Docket No.18402-05172 (713299PCT) Moreover, another objective is to keep the output current ripple minimum. In the 7-switch converter 20, the output inductor (2.2uH) is small and the switching frequency (100kHz) is also not high, hence a slight increase in the voltage across the inductor leads to a significant current ripple. This abrupt current ripple increases the circulating current in the converter 20 and degrades the efficiency. Therefore, the inductor current ripple is controlled by applying an appropriate pulse pattern to the switches S1, S2, S3, S4, M1, M2, and M3 in order to limit a voltage across the inductor 54. The proposed control method can make one of the output parameters (VO or IO) follow the (fixed or variable) reference value when either of the input parameters (Vinor Iin) is fixed or variable while also maintaining the output current ripple below an acceptable value. The proposed Control Method - Based on the duty cycle value, the converter’s operation is divided into four modes as follows: Mode I: 0 ≤ D ≤ 0.25; Mode II: 0.25 < D ≤ 0.33; Mode III: 0.33 < D ≤ 0.5; and Mode IV: 0.5< D ≤ 1. For the sake of simplicity, an input filter is not shown or described. However, real- world applications may include an input filter. Mode I: Duty cycle up to a quarter (0 ≤ D ≤ 0.25) The pulse pattern and inductor voltage and inductor current in a switching cycle for D ≤ 0.25 are presented in FIG. 3. In this mode: 1) Switches S1 and S3 turn on simultaneously at the beginning of the switching cycle and turn off after DTS. 2) Switches S2and S4also turn on simultaneously at t = 0.25Ts and are turned off after DTS. Attorney Docket No.18402-05172 (713299PCT) 3) Switch M1 turns on at t = 0.5TS and remains on for 2DTS. 4) Switch M2operates complementary with M1meaning that whenever M1is off, M2is on and vice versa. 5) Finally, switch M3 is turned on when S2 turns off, and it turned off at the end of the switching cycle. Therefore, one switching cycle can be divided into six intervals that are described in detail, below. Mode I, Interval 1: from 0 to t11(0 ≤ t < DTs) At t=0, S1and S3turn on. Since M2was turned on before, the voltage across theinductor LO would be Vin-VCf1-VCf2-VO. The inductor current variation during this first interval,∆^^^^_^^ can be calculated as set forth in equation (2):∆^^ ^ ೞ்^^_^^ ൌ ^^ ^^^^^ െ ^^^^^ െ ^^^^ଶ െ ^^ை^ (2)first interval ends at t11, when S1 and S3 go off. The current ^^^^in the converter 20 for this first interval is shown in FIG. 4. Mode I, Interval 2: from t11to t12(DTs ≤ t < 0.25Ts) At t11, S1 and S3 go off and only M2 remains on until t2. In this interval, the inductor current flows through M2 and the body diode of M3. As a result, the voltage across the inductor would be -VO, and the current variation during this second interval, ∆^^^^_^ଶcan be calculated asset forth in equation (3):∆^^ ൌ ^^.ଶହି^^ ೞ்^^_^ଶ ^^ ^െ^^ை^ (3) flow ^^^^in the converter 20 for this second interval is shown in FIG. 5. Mode I, Interval 3: from t12to t13(0.25Ts ≤ t <(0.25+D) Ts) Attorney Docket No.18402-05172 (713299PCT) At t12, S2 and S4 turn on and M2 is still on. So, in this interval, the voltage across the inductor would be VCf1 -VCf2 -VO, and the current variation during this third interval, ∆^^^^_^ଷcan becalculated as set forth in equation (4):∆^^^^_^ଷ ൌ ^ ೞ்^^ ^^^^^^ െ ^^^^ଶ െ ^^ை^ (4)Cf2. This interval ends at t13, when S2and S3turn off. The current ^^^^in the converter 20 during this third interval is shown in FIG. 6. Mode I, Interval 4: from t13to t14((0.25 + D) Ts ≤ t < 0.5Ts) At t13, S2and S4are turned off and M3turns on. Also, M2remains on. Therefore, the inductor current ^^^^flows through M3and M2leading to -VOacross the inductor Lo. The currentvariation during this fourth interval, ∆^^^^_^ସ is set forth in equation (5):∆^^ ^^.ଶହି^^^_^ସ ൌ ^ ೞ்^^ ^െ^^ை^ (5)condition. The current ^^^^in the converter 20 for the fourth interval is shown in FIG. 7. Mode I, Interval 5: from t14to t15(0.5Ts ≤ t < (0.5 +2D)Ts) At t14, M2 goes off and M1 turns on. So, the voltage across the inductor would beVCf2-VO leading to the current variation ∆^^^^_^ହ as described by equation (6):∆^^ ଶ^ ೞ்^^_^ହ ൌ ^^ ^^^^^ଶ െ ^^ை^ (6) M1 turns off and M2 turns on again. The current ^^^^in the converter 20 for the fifth interval is shown in FIG. 8. Mode I, Interval 6: from t15to Ts ((0.5+2D) Ts ≤ t < Ts) At t15, M1turns off and the same as the fourth interval only M2and M3are on. So, the voltage across the inductor would be -VO and the current variation is: Attorney Docket No.18402-05172 (713299PCT)∆^^ ^^.ହିଶ^^ ೞ்^^_^^ ൌ ^^ ^െ^^ை^ (7)on again. The current ^^^^in the converter 20 for the sixth interval is shown in FIG. 9. When the duty cycle is zero, the converter is off, and when it increases from zero to 0.25, the converter’s operation would be the same as the six-interval explained above. As D approaches 0.25 intervals 2, 3, and 6 shrink, and whenever it becomes equal to 0.25, these intervals totally vanish. The waveforms for D=0.25 are presented in FIG. 10. At this condition, the voltage across the inductor is zero, in all intervals, as a result the current ripple will be zero. When the duty cycle keeps increasing and passes 0.25, the converter’s operation enters Mode II. Mode II: Duty cycle between a quarter and one-third (0.25 < D ≤ 0.33) The pulse pattern and inductor voltage and inductor current in a switching cycle for the 0.25 < D ≤ 0.33 are presented in FIG. 11. In this mode: 1) Switches S1and S3turn on simultaneously at the beginning of the switching cycle and turn off after DTS. 2) Switches S2 and S4 also turn on at t = DTs and are turned off at t = 2DTS. 3) Switch M1 turns on at t = 2DTS and remains on for 2DTS completing some of its duration in the next switching cycle. 4) Switch M2 operates complementary with M1 meaning that whenever M1 is off, M2 is on and vice versa. So it turns on at t = (4D-1)TS and turns off at t = 2DTS. 5) Finally, switch M3is turned on when S2and S4turn off (t = 2DTS), and it turns off at the end of the switching cycle. Therefore, one switching cycle could be divided into four intervals that are explained in detail below. Attorney Docket No.18402-05172 (713299PCT) Mode II, Interval 1: from 0 to t21(0 ≤ t < (4D-1) Ts) At t=0, S1and S3turn on and M1is already on from the previous switching cycle, the voltage across the inductor LO would be Vin-VCf1-VO. Hence, the inductor current variation canbe calculated as:∆^^^^_ଶ^ ൌ ^ସ^ି^^ ೞ்^^ ^^^^^ െ ^^^^^ െ ^^ை^ (8)interval ends at t21, when S1and S2go off. The current ^^^^in the converter 20 for this first interval is shown in FIG. 12. Mode II, Interval 2: from t21to t22((4D-1) Ts ≤ t < DTs) At t21, M1goes off and M2turns on. Until t2, S1, S3and M2stay on. In this second interval, the inductor current ^^^^flows through Cf1and Cf2charging both capacitors. Therefore, thevoltage across the inductor would be Vin-VCf1-VCf2-VO, and the current variation would be:∆^^^^_ଶଶ ൌ ^^ିଷ^^ ೞ்^^ ^^^^^ െ ^^^^^ െ ^^^^ଶ െ ^^ை^ (9) ^^^^in the converter 20 for this second interval is shown in FIG. 13. Mode II, Interval 3: from t22to t23(DTS≤ t < 2DTS) At t22, S2 on. So, in this third interval, the voltageacross the inductor would be VCf1 - VCf2-VO, and the inductor current change is:∆^^^^_ଶଷ ൌ ^ ೞ்^^ ^^^^^^ െ ^^^^ଶ െ ^^ை^ (10) ends at t23, when S2 and S3 turn off. The current ^^^^in the converter 20 for this third interval is shown in FIG. Attorney Docket No.18402-05172 (713299PCT) Mode II, Interval 4: from t23to Ts (2DTS≤ t < TS) At t23, S2, same time M1and M3turn on. As a result, Cf2 discharges and the inductor current flows through M1 and M3 leading to VCf2-VO across the inductor.Therefore, its current variation would be:∆^^ ^^ିଶ^^ ೞ்^^_ଶସ ൌ ^^ ^^^^^ଶ െ ^^ை^ (11)The current ^^^^ in the converter 20 for this interval is shown in FIG. 15.When the duty cycle is greater than 0.25 and less than 0.33 the converter operates in the four intervals shown in FIGS. 12-15. As the duty cycle increases, interval 2 shrinks. However, when D=0.33 interval 2 completely vanishes. The pulse pattern, inductor voltage and inductor current for D=0.33 is shown in FIG.16. At this condition, the voltage across the inductor is zero, in all intervals, as a result the current ripple will be zero. As the duty cycle continues to increase beyond 0.33 the converter enters Mode III. Mode II, Interval III: Duty cycle higher than a third and lower than half (0.33 < D ≤0.5) The pulse pattern and inductor voltage and inductor current in a switching cycle for the 0.33 ≤ D ≤ 0.5 are presented in FIG. 17. In this third mode: 1) Switches S1 and S3 turn on simultaneously at the beginning of the switching cycle and turn off after DTS. 2) Switches S2and S4also turn on at t = DTs and are turned off at t = 2DTS. 3) Switch M1 turns on at t = (1-D)TS and remains on for 2DTS completing some of its duration in the next switching cycle. In this mode, M1 turns off at the same time as S1 and S3. 4) Switch M2operates complementary with M1meaning that whenever M1is off, M2is on and vice versa. So it turns on at t = DTSand turns off at t = (1-D)TS. 5) Finally, switch M3 is turned on when S2 and S4 turn off (t = 2DTS), and it turns off at the end of the switching cycle. Attorney Docket No.18402-05172 (713299PCT) Therefore, one switching cycle can be divided into four intervals that are explained in detail below. Mode III, Interval 1: from 0 to t31(0 ≤ t < DTS) At t=0, S1and S3turn on. Since M1is already on from the previous switching cycle, the voltage across the inductor LOwould be Vin-VCf1-VO. So, the inductor current variation can becalculated as:∆^^^^_ଷ^ ൌ ^ ೞ்^^ ^^^^^ െ ^^^^^ െ ^^ை^ (12)ends at t31, when S1 and S2 go off. The current ^^^^in the converter 20 for this first interval is shown in FIG. 18. Mode III, Interval 2: from t31to t32(DTS≤ t < (1-D) TS) At t31, S1, S3 and M1 go off and S2, S4 and M2 turn on. Until t2, M2 stays on. In this second interval, the inductor current flows through both flying capacitors discharging Cf1and charging Cf2. Therefore, the voltage across the inductor would be VCf1-VCf2-VO, and the currentvariation would be:∆^^^^_ଷଶ ൌ ^^ିଶ^^ ೞ்^^ ^^^^^^ െ ^^^^ଶ െ ^^ை^ (13) The current^^^^ in the converter 20 for this interval is shown in FIG. 19.Mode III, Interval 3: from t32to t33((1-D)TS≤ t < 2DTS) At t , M 32 1 the previous interval. Therefore, thevoltage across the inductor would be VCf1 -VO, and the inductor current change is:∆^^ ^ଷ^ି^^ ೞ^ ൌ ் ^^^^^^ െ (14) Attorney Docket No.18402-05172 (713299PCT) The inductor current ^^^^discharges Cf1. Interval 3 ends at t33, when S2 and S4 turn off. The current ^^^^in the converter 20 for this interval is shown in FIG. 20. Mode III, Interval 4: from t33to Ts (2DTS≤ t < TS) At t33, S2 and S4 turn off and M1 stays on. Additionally, M3 turns on. As a result, Cf2 discharges and the inductor current flows through M1and M3leading to VCf2-VOacross the inductor.So, its current variation would be:∆^^ ^^ିଶ^^_ଷସ ൌ ^^ ೞ்^^ ^^^^^ଶ െ ^^ை^ (15)The ^^^^ in the converter 20 for this fourth interval is shown in FIG. 21Between 0.33 to 0.5 duty cycle the converter operates in the four intervals shown in FIGS. 18 - 21. As the duty cycle increases, intervals 2 and 4 shrink and eventually vanish when D=0.5. The pulse pattern, inductor voltage and inductor current for D=0.5 is shown in FIG. 22. At this condition, the voltage across the inductor is zero, in all intervals, as a result the current ripple will be zero. As the duty cycle continues to increase beyond 0.5 up to 1 the converter enters Mode IV. Mode IV: Duty cycle higher than half and lower than one (0.5 < D ≤ 1) The pulse pattern and inductor voltage and inductor current in a switching cycle for 0.5 ≤ D ≤1 are presented in FIG. 23. In this mode: 1) Switch S1turns on at the beginning of the switching cycle and turns off after DTS. 2) Switch S2 also turns on at t = 0.5Ts and turns off after DTS, completing some of its duration in the next switching cycle. So it turns off at t = (D-0.5)TS. 3) Switch S3operates complementary with S2, so it turns on at t = (D-0.5)TSand turns off at t = 0.5TS. 4) Switch S4 operates complementary with S1, so it turns on at t = DTS and turns off at the end of the switching cycle. Attorney Docket No.18402-05172 (713299PCT) 5) Switch M1 is always on and bypasses the second stage. 6) Switch M2is always turned off. 7) Switch M3is always off too. Therefore, one switching cycle could be divided into four intervals that are explained in detail below. Mode IV, Interval 1: from t40to t41(0 ≤ t < (D-0.5)TS) At t=0, S1 and S2 turn on. Since M1 stays on throughout the switching cycle, the voltage across the inductor LOwould be Vin-VO. So, the inductor current variation can be calculatedas:∆^^ ^^ି^.ହ^^^_ସ^ ൌ ೞ்^^ ^^^^^ െ ^^ை^ (16)ends at t41, when S2goes off. The current ^^^^in the converter 20 for this first interval is shown in FIG. 24. Mode IV, Interval 2: from t41to t42((D-0.5)TS≤ t < 0.5TS) At t41, S2 goes off and S3 turns on. Until t42, S1 and S3 stay on. In this interval, the inductor current flows through Cf1 charging it. Therefore, the voltage across the inductor would beVin-VCf1-VO, and the current variation would be:∆^^ ^^ ^^^_ସଶ ൌ ି^ ೞ்^^ ^^^^^ െ ^^^^^ െ ^^ை^ (17) on. The current ^^^^in the converter 20 for this interval is shown in FIG. 25. Mode IV, Interval 3: from t42to t43(0.5TS≤ t < DTS) At t42, S2 on. So, in this interval, the voltage acrossthe inductor would be Vin -VO, and the inductor current change is:∆^^ ൌ ^^ି^.ହ^ ೞ் ^^^^^ െ (18) Attorney Docket No.18402-05172 (713299PCT) The inductor current ^^^^flows through S1, S2 and M1 like interval 1. This third interval ends at t43, when S1turns off. The current ^^^^in the converter 20 for this third interval is shown in FIG. 26. Mode IV, Interval 4: from t43to TS(DTS≤ t < TS) At t43, S1, turns off while S2and M1continue to be on. At the same time S4also turns on. As a result, Cf1 discharges and the inductor current flows through M1, S2 and S4 leading to VCf1-VO across the inductor. So, its current variation would be:∆^^^^_ସସ ൌ ^^ି^^ ೞ்^^ ^^^^^^ െ ^^ை^ (19)stay on. The current ^^^^in the converter 20 for this interval is shown in FIG. 27. Beyond 0.5 duty cycle, the converter operates in the four intervals shown in FIGS. 24-27. As the duty cycle increases, intervals 2 and 4 shrink and eventually vanish when D=1. At D=1, the converter bypasses both flying capacitors and the output voltage is equal to the input voltage. Theoretical Analysis of the Control Strategy In this section, the output voltage, capacitor voltages across the flying capacitors and the inductor current equations are described for all four operation modes. Analysis of Mode I (0 ≤ D ≤ 0.25) In the steady state the summation of inductor current ripple is zero which is knownas volt-second balance:∆^^^^_^^ ^ ∆^^^^_^ଶ ^ ∆^^^^_^ଷ ^ ∆^^^^_^ସ ^ ∆^^^^_^ହ ^ ∆^^^^_^^ ൌ 0 (20)Therefore, substituting equations (2), (3), (4), (5), (6) and (7) into (20) computes output voltage to: Attorney Docket No.18402-05172 (713299PCT) ^^ை ൌ ^^^^^^ (21)FIG. 28 shows inductor current ^^^in the power converter 20 operating in the first control mode. The initial value of inductor current at each switching cycle is defined as i1, which is depicted in FIG. 28. In the steady state, the charging and discharging current of a capacitor are equal, which is known as charge-second balance. Accordingly, the charge-second relation for Cf1using i1 would be:^^^^ ^ ∆^^^_భభ ∆^^^_భయௌ ^^^ ^ ଶ ^ ൌ ^^^^ௌ ^^^^ ^ ∆^^^^_^^ ^ ∆^^^^_^ଶ ^ ଶ ^ (22)where its timing and current amplitudes are indicated. Using equations (2), (3), (4), and (21) in equation (22), gives:^^^^ଶ ൌ ^^^^ / 4 (23)In a same way, for the second flying capacitor the charge-second balance would be:^^^^ ^^^ ^ ∆^^^_భభ ∆^^^_భ ∆^ଶ ^ ^ ^^^^ௌ ^^^^ ^ ∆^^ య ^^_భఱௌ ^ ^^_^^ ^ ∆^^^^_^ଶ ^ ଶ ^ ൌ 2^^^^ௌ ^^^^ െ ∆^^^^_^^ െ ଶ ^ (24) voltage can be written as:^^^^^ ൌ ^^^ ^ 0.25^^^^^ (25)Substitution of equations (21), (23), and (25) into equations (2), (4) and (6) results in: ^^^^∆^^ ^^^ ^^^^^ ^^ ^^

[0002] Attorney Docket No.18402-05172 (713299PCT) ∆^^ ^ ೞ் ^^^_^ଷ ൌ ^^ ^^^^^^^^ ^ 0.25^ െ ^^ସ െ ^^^^^^^^0 ≤ D ≤ 0.25, and when the duty cycle reaches 0.25, ΔiLo_11and ΔiLo_15also become zero. Moreover, at this moment (D=0.25) the time duration for the second, fourth, and sixth intervals goes down to zero making ΔiLo_12, ΔiLo_14, and ΔiLo_16, equal to zero. Hence, it can be concluded that the inductor current ripple at 0.25 duty cycle is zero. B- Analysis of Mode II (0.25 < D ≤ 0.33) Like Mode I, the inductor’s volt-second balance in Mode II is:∆^^^^_ଶ^ ^ ∆^^^^_ଶଶ ^ ∆^^^^_ଶଷ ^ ∆^^^^_ଶସ ൌ 0 (29)Substituting equations (8), (9), (10), and (11) into (29) gives the output voltage as VO=DVin, which is the same as equation (21). The charge-second equation for Cf1is: ∆^^^4^^ 1^^^ ^^మభ ∆^^^^మ^ ^ ^ ^ ^1 3^^^ ^ ^ మ ^ మ^^ ൌ ^ ^ଶ^ି^^^^^^ (31) Attorney Docket No.18402-05172 (713299PCT) ∆^^^1 െ 3^^^^^ ^^మమ ∆^^^^మయௌ ൬^^^ ^ ∆^^^^మభ ^2 ^ ^ ^^^^ௌ ൬^^^ ^ ∆^^^^మభ ^ ∆^^^^ିଶଶ ^2 ^ ൌbe

[0003] Attorney Docket No.18402-05172 (713299PCT)∆^^ ൌ ^^^ିଶ^^^^ିଷ^^^ସ^ି^^ ೞ்^^_ଶସ ^^^^ସ^మି଼^ା^^ ^^^^ (37)equal to 0.25 and 1 / 3, the inductor current variation in all the four intervals becomes zero. C- Analysis of Mode III (0.33 < D ≤ 0.5) Following the same convention as the previous two modes, the inductor’s volt-second balance is:∆^^^^_ଷ^ ^ ∆^^^^_ଷଶ ^ ∆^^^^_ଷଷ ^ ∆^^^^_ଷସ ൌ 0 (38)voltage as VO=DVin, which is the same as equation (21). The charge-second equation for Cf1 can be written as: ∆^^^^^^ ^^ ^ ^^యభௌ ൬ ^ ^ ൌ in:^మ^^^^ଶ ൌ ସ^ି^ ^^^^ (40)The charge-second relation for Cf2 is: ∆^^^1 െ 2^^^^^ ൬^^ ^^యమ^ ^ ∆^^ ^ ൌbe Attorney Docket No.18402-05172 (713299PCT) ^^^^ ଶ^ െ2^^∆^^^^_ଷ^ ൌ^^ ^^^^^ െ ^^^^ െ ^^^^^^^^ 1 െ 4^^ to 1 / 3 and 1 / 2, the inductor current variation in all the four intervals becomes zero. Analysis of Mode IV (0.5 < D ≤ 1) Following the same pattern as the previous three modes the inductor’s volt-secondbalance is:∆^^^^_ସ^ ^ ∆^^^^_ସଶ ^ ∆^^^^_ସଷ ^ ∆^^^^_ସସ ൌ 0 (47)Substituting equations (16), (17), (18), and (19) into (47) gives the output voltage as VO=DVin, which is the same as equation (21). Attorney Docket No.18402-05172 (713299PCT) The charge second balance equation for Cf1 can be written as:∆^^^^_ସ^ ^ ∆^^^^_ସଶ ൌ 0 (48)Simplifying equation (48) using equations (16) and (17), results in:^^^^^ ൌ ^ଶ ^^^^ (49)(19) can be rewritten as: ^^^ െ 0.5^^^∆^^^^_ସ^ ൌ ^^^ ^^^^^ െ ^^ை^^

[0004] Attorney Docket No.18402-05172 (713299PCT) According to equations (50), (51), (52) and (53) when duty cycle becomes equal to 0.5 and 1, the inductor current change in all intervals becomes zero. Graphical Analysis of the Control Strategy The equations derived in theoretical analysis of the control strategy are presented in their graphical form to investigate the converter’s behavior more clearly. Table 1 lists the design specifications used for converter circuit analysis. Table 1: Design specifciations of the converter Item Value Description V 12V O t t v lt CO20µF Output capacitor The normalized output voltage versus duty cycle is plotted in FIG. 30 using equation (21). As discussed, the output to input voltage relation obeys equation (21) in all modes the same as a conventional buck converter. Therefore, the output voltage can be regulated from 0 to Vin. The voltage variation for the flying capacitors Cf1 and Cf2 are plotted in FIG.31 and FIG.32, respectively. For VCf1, the equations (25), (33), (42), and (49) are used for the four modes. In addition, for VCf2, equations (23), (31), and (40) are used for the first three modes. Since the Attorney Docket No.18402-05172 (713299PCT) second stage is bypassed in the Mode IV operation, and Cf2 does not contribute to the converter’s operation. The maximum output current ripple (peak-to-peak) is presented in FIG.33. In each of the operation modes, the maximum and minimum current values are calculated using equations (2)-(7) (for Mode I), (8)-(11) (for Mode II), (12)-(15) (for Mode III), and (16)-(19) (for Mode IV). As expected, FIG. 33 shows that the output current ripple is zero at D= 0.25, 0.33, 0.5, and 1. FIGS. 29 – 33 illustrate that the inductor current and capacitor voltages are continuous when transmitting between the different operation modes when the 7-switch converter 20 is operated in accordance with the control method of the present disclosure. The present disclosure provides a method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter, including: selectively controlling a first set of switches of a first stage having a first flying capacitor to control a first current flow between a positive input terminal and a first internal node; selectively controlling a second set of switches of a second stage having a second flying capacitor to control a second current flow between the first internal node and a second internal node; and conducting, by an inductor, current between the second internal node and a positive output terminal for supplying power to a load connected to the positive output terminal. The inductor has zero average voltage thereacross for each switching cycle of a plurality of switching cycles, and selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to operate with a conversion ratio between an input voltage of the positive input terminal and an output voltage of the positive output terminal and having a value greater than 0.5. In some embodiments, the selectively controlling the first set of switches and the second set of switches to cause the 2-stage ZIV power converter to operate with the conversion Attorney Docket No.18402-05172 (713299PCT) ratio greater than 0.5 further includes operating the second set of switches to conduct the second current between the first internal node and the second internal node, bypassing the second flying capacitor, at all times throughout a switching cycle. In some embodiments, the method further includes selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to operate with a conversion ratio having a value between 0 and 0.5. In some embodiments, the second flying capacitor defines a capacitance between the first internal node and a fifth internal node, wherein the second set of switches includes: a fifth switch configured to selectively conduct current between the first internal node and the second internal node, a sixth switch configured to selectively conduct current between the second internal node and the fifth internal node, and a seventh switch configured to selectively conduct current between the fifth internal node and a common ground node. In some embodiments, selectively controlling the first set of switches and the second set of switches to operate the 2-stage ZIV power converter with a conversion ratio between 0 and 0.5 further includes: selectively controlling the first set of switches and the second set of switches over a periodic switching cycle having a switching interval during which the first set of switches are active, and followed by a non- switching interval during which the first set of switches are inactive, and in at least one of: a first mode, a second mode, and a third mode. In some embodiments, the first mode includes the fifth switch is conductive only during the non-switching interval, the sixth switch is complementary of the fifth switch, and the seventh switch is conducive throughout the non-switching interval and non-conductive throughout the switching interval. In some embodiments, the second mode includes the fifth switch is turned-on at the end of the switching interval and stays on through the non-switching interval and remains on for at least some of the switching interval of a next cycle Attorney Docket No.18402-05172 (713299PCT) of the periodic switching cycle, the sixth switch is complementary of the fifth switch, and the seventh switch is conducive throughout the non-switching interval and non-conductive throughout the switching interval. In some embodiments, the third mode includes the fifth switch is turned-on during the switching interval and stays on through the non-switching interval and remains on for at least some of the switching interval of a next cycle of the periodic switching cycle, the sixth switch is complementary of the fifth switch, and the seventh switch is conducive throughout the non-switching interval and non-conductive throughout the switching interval. In some embodiments, selectively controlling the first set of switches and the second set of switches in the at least one of the first mode, the second mode, and the third mode further includes selectively controlling the first set of switches and the second set of switches in each of the first mode, the second mode, and the third mode for corresponding ranges of the conversion ratio between 0 and 0.5. In some embodiments, selectively controlling the first set of switches and the second set of switches in the at least one of the first mode, the second mode, and the third mode further includes selectively controlling the first set of switches and the second set of switches in the first mode for conversion ratios having values between 0 and 0.25, in the second mode for conversion ratios values between 0.25 and 0.33, and in the third mode for conversion ratios between 0.33 and 0.5. In some embodiments, selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 58 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.0 A. These values describe an example embodiment, and other design implementations and / or Attorney Docket No.18402-05172 (713299PCT) method implementations that are also in accordance with the inventive concepts of the present disclosure may have different values for voltages, currents, and / or current ripple. In some embodiments, selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 60 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.5 A. These values describe an example embodiment, and other design implementations and / or method implementations that are also in accordance with the inventive concepts of the present disclosure may have different values for voltages, currents, and / or current ripple. In some embodiments, the inductor has an inductance of not more than about 2.2 microhenry (μH). However, the concepts of the present disclosure are not limited to any specific inductance value. In some embodiments, selectively controlling the first set of switches and the second set of switches includes operating the first set of switches and the second set of switches at a switching frequency of not more than about 100kHz. However, the concepts of the present disclosure are not limited to any specific frequency value. The present disclosure also provides a method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter, including: selectively controlling each of a first set of switches of a first stage and a second set of switches of a second stage to conduct current via an inductor and to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 58 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.0 A. These values describe an example embodiment, and other design implementations and / or method implementations that are also in accordance with the Attorney Docket No.18402-05172 (713299PCT) inventive concepts of the present disclosure may have different values for voltages, currents, and / or current ripple. In some embodiments, the inductor has an inductance of not more than about 2.2 microhenry (μH). However, the concepts of the present disclosure are not limited to any specific inductance value. In some embodiments, the method further includes selectively controlling each of the first set of switches and the second set of switches to supply the DC output power to the load at an output voltage of 12 V from a power source having a range of values between 12V and 60 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.5 A. These values describe an example embodiment, and other design implementations and / or method implementations that are also in accordance with the inventive concepts of the present disclosure may have different values for voltages, currents, and / or current ripple. The present disclosure also provides a power converter system. The power converter system includes: a 2-stage Zero Inductor Voltage (ZIV) power converter and a controller. The 2-stage ZIV power converter includes: a first stage including a first set of switches and a first flying capacitor and configured to control a first current flow between a positive input terminal and a first internal node; a second stage including a second set of switches and a second flying capacitor and configured to control a second current flow between the first internal node and a second internal node; and an inductor connected directly between the second internal node and a positive output terminal. The controller is configured to command each switch of the first set of switches and each switch of the second set of switches to selectively conduct current to cause: the inductor to have zero average voltage thereacross, and the 2-stage ZIV power converter Attorney Docket No.18402-05172 (713299PCT) to operate with a conversion ratio between an input voltage of the positive input terminal and an output voltage of the positive output terminal and having a value greater than 0.5. In some embodiments, the commanding each switch of the first set of switches and each switch of the second set of switches to selectively conduct current to cause the 2-stage ZIV power converter to operate with the conversion ratio greater than 0.5 further includes operating the second set of switches to conduct the second current between the first internal node and the second internal node, bypassing the second flying capacitor, at all times throughout a switching cycle. In some embodiments, the controller is further configured to command each of the first set of switches and the second set of switches to cause the 2-stage ZIV power converter to operate with a conversion ratio having a value between 0 and 0.5. In some embodiments, selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 58 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.0 A. These values describe an example embodiment, and other design implementations and / or method implementations that are also in accordance with the inventive concepts of the present disclosure may have different values for voltages, currents, and / or current ripple. In some embodiments, selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 60 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.5 A. These values describe an example embodiment, and other design implementations and / or Attorney Docket No.18402-05172 (713299PCT) method implementations that are also in accordance with the inventive concepts of the present disclosure may have different values for voltages, currents, and / or current ripple. In some embodiments, the inductor has an inductance of not more than about 2.2 microhenry (μH). However, the concepts of the present disclosure are not limited to any specific inductance value. In some embodiments, selectively controlling the first set of switches and the second set of switches includes operating the first set of switches and the second set of switches at a switching frequency of not more than about 100kHz. However, the concepts of the present disclosure are not limited to any specific frequency value. The system, methods and / or processes described above, and steps thereof, may be realized in hardware, software or any combination of hardware and software suitable for a particular application. The hardware may include a general purpose computer and / or dedicated computing device or specific computing device or particular aspect or component of a specific computing device. The processes may be realized in one or more microprocessors, microcontrollers, embedded microcontrollers, programmable digital signal processors or other programmable device, along with internal and / or external memory. The processes may also, or alternatively, be embodied in an application specific integrated circuit, a programmable gate array, programmable array logic, or any other device or combination of devices that may be configured to process electronic signals. It will further be appreciated that one or more of the processes may be realized as a computer executable code capable of being executed on a machine readable medium. The computer executable code may be created using a structured programming language such as C, an object oriented programming language such as C++, or any other high- Attorney Docket No.18402-05172 (713299PCT) level or low-level programming language (including assembly languages, hardware description languages, and database programming languages and technologies) that may be stored, compiled or interpreted to run on one of the above devices as well as heterogeneous combinations of processors processor architectures, or combinations of different hardware and software, or any other machine capable of executing program instructions. Thus, in one aspect, each method described above and combinations thereof may be embodied in computer executable code that, when executing on one or more computing devices performs the steps thereof. In another aspect, the methods may be embodied in systems that perform the steps thereof, and may be distributed across devices in a number of ways, or all of the functionality may be integrated into a dedicated, standalone device or other hardware. In another aspect, the means for performing the steps associated with the processes described above may include any of the hardware and / or software described above. All such permutations and combinations are intended to fall within the scope of the present disclosure. The foregoing description is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Claims

Attorney Docket No.18402-05172 (713299PCT) CLAIMS What is claimed is:

1. A method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter, comprising: selectively controlling a first set of switches of a first stage having a first flying capacitor to control a first current between a positive input terminal and a first internal node; selectively controlling a second set of switches of a second stage having a second flying capacitor to control a second current between the first internal node and a second internal node; and conducting, by an inductor, current between the second internal node and a positive output terminal for supplying power to a load connected to the positive output terminal, wherein the inductor has zero average voltage thereacross for each switching cycle of a plurality of switching cycles, and wherein selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to operate with a conversion ratio between an input voltage of the positive input terminal and an output voltage of the positive output terminal and having a value greater than 0.

5.

2. The method of Claim 1, wherein selectively controlling the second set of switches further includes operating the second set of switches to conduct the second current between the first internal node and the second internal node, bypassing the second flying capacitor, at all times throughout a switching cycle.Attorney Docket No.18402-05172 (713299PCT) 3. The method of Claim 1, further including selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to operate with a conversion ratio having a value between 0 and 0.

5.

4. The method of Claim 3, wherein the second flying capacitor defines a capacitance between the first internal node and a fifth internal node, wherein the second set of switches includes: a fifth switch configured to selectively conduct current between the first internal node and the second internal node, a sixth switch configured to selectively conduct current between the second internal node and the fifth internal node, and a seventh switch configured to selectively conduct current between the fifth internal node and a common ground node, and wherein selectively controlling the first set of switches and the second set of switches to operate the 2-stage ZIV power converter with a conversion ratio between 0 and 0.5 further includes: selectively controlling the first set of switches and the second set of switches over a periodic switching cycle having a switching interval during which the first set of switches are active, and followed by a non-switching interval during which the first set of switches are inactive, and in at least one of: a first mode wherein the fifth switch is conductive only during the non-switching interval, the sixth switch is complementary of the fifth switch, and the seventh switch is conducive throughout the non-switching interval and non-conductive throughout the switching interval;Attorney Docket No.18402-05172 (713299PCT) a second mode wherein the fifth switch is turned-on at an end of the switching interval and stays on through the non-switching interval and remains on for at least some of the switching interval of a next cycle of the periodic switching cycle, the sixth switch is complementary of the fifth switch, and the seventh switch is conducive throughout the non- switching interval and non-conductive throughout the switching interval; and a third mode wherein the fifth switch is turned-on during the switching interval and stays on through the non-switching interval and remains on for at least some of the switching interval of a next cycle of the periodic switching cycle, the sixth switch is complementary of the fifth switch, and the seventh switch is conducive throughout the non- switching interval and non-conductive throughout the switching interval.

5. The method of Claim 4, wherein selectively controlling the first set of switches and the second set of switches in the at least one of the first mode, the second mode, and the third mode further includes selectively controlling the first set of switches and the second set of switches in each of the first mode, the second mode, and the third mode for corresponding ranges of the conversion ratio between 0 and 0.

5.

6. The method of Claim 5, wherein selectively controlling the first set of switches and the second set of switches in the at least one of the first mode, the second mode, and the third mode further includes selectively controlling the first set of switches and the second set of switches in the first mode for conversion ratios having values between 0 and 0.25, in the second mode for conversion ratios values between 0.25 and 0.33, and in the third mode for conversion ratios between 0.33 and 0.5.Attorney Docket No.18402-05172 (713299PCT) 7. A method of operating a 2-stage Zero Inductor Voltage (ZIV) power converter, comprising: selectively controlling each of a first set of switches of a first stage and a second set of switches of a second stage to conduct current via an inductor and to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 58 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.0 A.

8. The method of Claim 7, further including selectively controlling each of the first set of switches and the second set of switches to supply the DC output power to the load at an output voltage of 12 V from a power source having a range of values between 12V and 60 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.5 A.

9. A power converter system, comprising: a 2-stage Zero Inductor Voltage (ZIV) power converter including: a first stage including a first set of switches and a first flying capacitor and configured to control a first current between a positive input terminal and a first internal node; a second stage including a second set of switches and a second flying capacitor and configured to control a second current between the first internal node and a second internal node; and an inductor connected directly between the second internal node and a positive output terminal; andAttorney Docket No.18402-05172 (713299PCT) a controller configured to command each switch of the first set of switches and each switch of the second set of switches to selectively conduct current to cause: the inductor to have zero average voltage thereacross for each switching cycle of a plurality of switching cycles, and the 2-stage ZIV power converter to operate with a conversion ratio between an input voltage of the positive input terminal and an output voltage of the positive output terminal and having a value greater than 0.

5.

10. The power converter system of Claim 9, wherein the controller is further configured to command the second set of switches to conduct the second current between the first internal node and the second internal node, bypassing the second flying capacitor, at all times throughout a switching cycle.

11. The power converter system of Claim 9, wherein the controller is further configured to command each of the first set of switches and the second set of switches to cause the 2-stage ZIV power converter to operate with a conversion ratio having a value between 0 and 0.

5.

12. The power converter system of Claim 9, wherein selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 58 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.0 A.Attorney Docket No.18402-05172 (713299PCT) 13. The power converter system of Claim 9, wherein selectively controlling the first set of switches and the second set of switches causes the 2-stage ZIV power converter to supply direct current (DC) output power to a load at an output voltage of 12 V from a power source having a range of values up to 60 V, wherein the DC output power has a current up to 20 A with a current ripple of less than 5.5 A.

14. The power converter system of Claim 9, wherein the inductor has an inductance of not more than about 2.2 microhenry (μH).

15. The power converter system of Claim 9, wherein selectively controlling the first set of switches and the second set of switches includes operating the first set of switches and the second set of switches at a switching frequency of not more than about 100kHz.

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