Display panel and display device

Abstract

The present application provides a display panel and a display device. In the display panel, a through hole is designed in such a way that when the position of the through hole deviates, the overlapping area of any clock signal line and the through hole keeps unchanged and the overlapping areas of the clock signal lines and the through hole are equal to each other, such that the parasitic capacitances of the clock signal lines are close or even equal to each other, so as to avoid different signal delays of the adjacent clock signal lines and a signal delay change caused by an impedance change of the clock signal lines, allowing for the normal display of a display panel.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays are widely used due to their advantages, including self-luminescence, wide color gamut, low power consumption, and flexible display capabilities. OLED displays utilize GOA (Gate Driver On Array) technology to reduce bezels. To release moisture from the organic layer in the GOA region and reduce its impact on the device's electrical performance, existing OLED displays incorporate grooves in the large metal block above the organic layer. Specifically, these devices groove the anode metal layer over the clock signal lines, with one groove located on the first and second clock lines, and another groove located on the third and fourth clock lines, ensuring that the grooves on each clock line have equal area. However, in the actual preparation process, due to the problem of mask plate alignment offset during the trenching of the anode layer, the trenching will be offset relative to the clock line, which in turn leads to different overlapping areas between different clock lines and the trenching, resulting in changes in the parasitic capacitance between different clock lines and the metal of the anode layer, causing the total impedance of the clock line to change, affecting its signal delay, and the change trends between adjacent clock lines are opposite, resulting in increased signal delay differences between different clock lines, affecting signal output.

[0003] Therefore, existing OLED display devices have a technical problem in which the grooves on the clock line are offset, resulting in excessive changes in the parasitic capacitance of the clock line, thereby affecting the display. SUMMARY OF THE INVENTION

[0004] Embodiments of the present application provide a display panel and a display device for improving the technical problem in existing OLED display devices where the slots on the clock line are offset, resulting in excessive changes in the parasitic capacitance of the clock line and affecting the display.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] An embodiment of the present application provides a display panel, comprising a display area and a driving circuit area disposed on at least one side of the display area, the display panel comprising:

[0007] A plurality of clock signal lines are arranged in the driving circuit area, and the plurality of clock signal lines extend along a first direction;

[0008] A low-potential signal line is provided in the driving circuit area, and the orthographic projections of the plurality of clock signal lines on the low-potential signal line are located within the low-potential signal line;

[0009] In which, a plurality of through holes are opened on the low-potential signal line, and the through hole array is arranged to form a plurality of repeating units. In the repeating unit, the number of through holes in each column is the same. In any two of the clock signal lines, the overlapping area between one of the clock signal lines and all the corresponding through holes in a repeating unit is equal to the overlapping area between the other clock signal line and all the corresponding through holes in a repeating unit, and the overlapping area between any one of the clock signal lines and the corresponding through holes in a repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the through hole in the first direction and the number of through holes in a column in a repeating unit; the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0010] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0012] FIG1 is a schematic diagram of a conventional display device in which the trenches for a clock line and a low-potential power signal line are not offset.

[0013] FIG. 2 is a schematic diagram showing a situation in which the trenching of the clock line and the low-potential power signal line in FIG. 1 is offset.

[0014] FIG3 is a bar graph showing the offset of the trenches of the clock line and the low-potential power signal line in FIG1 and the change in the parasitic capacitance of the clock signal line.

[0015] FIG4 is a first schematic diagram of a display panel provided in an embodiment of the present application.

[0016] FIG5 is a second schematic diagram of a display panel provided in an embodiment of the present application.

[0017] FIG6 is a third schematic diagram of a display panel provided in an embodiment of the present application.

[0018] FIG. 7 is a fourth schematic diagram of a display panel provided in an embodiment of the present application.

[0019] FIG8 is a first schematic diagram of an embodiment of the present application when the through holes of the clock signal line and the low-potential signal line are not offset.

[0020] FIG. 9 is a schematic diagram showing a situation in which positions of through holes in the clock signal line and the low-potential signal line in FIG. 8 are offset.

[0021] FIG. 10 is a bar graph showing the offset of the through holes in the clock signal line and the low potential signal line in FIG. 8 and the change in the parasitic capacitance of the clock signal line.

[0022] FIG11 is a second schematic diagram of an embodiment of the present application when the through holes of the clock signal line and the low-potential signal line are not offset.

[0023] FIG12 is a schematic diagram showing a situation in which positions of through holes in the clock signal line and the low potential signal line provided in FIG11 are offset.

[0024] FIG. 13 is a bar graph showing the offset of the through holes in the clock signal line and the low potential signal line and the change in the parasitic capacitance of the clock signal line provided in FIG. 11 . Modes for Carrying Out the Invention

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0026] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0028] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0029] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0030] As shown in Figure 1, (a) in Figure 1 is a stacked diagram of the low-potential power signal line and the clock line, (b) in Figure 1 is an exploded diagram of the low-potential power signal line in (a) in Figure 1, and (c) in Figure 1 is an exploded diagram of the clock line in (a) in Figure 1. As can be seen from Figure 1, in order to release moisture in the organic layer in the gate drive circuit area, the existing OLED display device will groove the low-potential power signal line 12 of the anode layer in the area corresponding to the clock line. Specifically, as shown in Figure 1, in theory, one row of grooves 121 is located on the first clock line 111 and the second clock line 112, and another row of grooves 121 is located on the third clock line 113 and the fourth clock line 114. However, in the actual manufacturing process, due to the problem of offset between the mask plate and the anode layer, the grooves will be offset.

[0031] As shown in Figure 2, (a) in Figure 2 is a schematic diagram of the OLED display device when the groove is offset to the left by 3 microns, (b) in Figure 2 is a schematic diagram of the OLED display device when the groove is offset to the left by 2 microns, (c) in Figure 2 is a schematic diagram of the OLED display device when the groove is offset to the left by 1 micron, (d) in Figure 2 is a schematic diagram of the OLED display device when the groove is offset to the right by 1 micron, (e) in Figure 2 is a schematic diagram of the OLED display device when the groove is offset to the right by 2 microns, and (f) in Figure 2 is a schematic diagram of the OLED display device when the groove is offset to the right by 3 microns. It can be seen from Figure 2 that when the groove is offset, the overlapping area between the two adjacent clock lines and the groove changes, and the overlapping areas between the two adjacent clock lines and the groove are different, which causes the parasitic capacitance between the clock line and the low-potential power signal line to change.

[0032] As shown in Figure 3, the value -3 on the abscissa of Figure 3(a) indicates that the trench is offset by 3 microns to the left, and 3 indicates that the trench is offset by 3 microns to the right. Similarly, for other values ​​and the value in Figure 3(b), refer to the above description. Figure 3(a) shows the change in parasitic capacitance between each clock line and the low-potential power signal line at different offsets. The abscissa in Figure 3(a) indicates the offset of the trench for the clock line and the low-potential power signal line, and the ordinate indicates the change in parasitic capacitance between the clock line and the low-potential power signal line compared to when the trench for the clock line and the low-potential power signal line is not offset. The bar graph in Figure 3 shows the change in parasitic capacitance between different clock lines and the low-potential power signal line. CK1-ANO indicates the change in parasitic capacitance between the first clock line and the low-potential power signal line, CK2-ANO indicates the change in parasitic capacitance between the second clock line and the low-potential power signal line, CK3-ANO indicates the change in parasitic capacitance between the third clock line and the low-potential power signal line, and CK4-ANO indicates the change in parasitic capacitance between the fourth clock line and the low-potential power signal line. (b) in Figure 3 shows the change in parasitic capacitance between each clock line and all signal lines at different offsets. The horizontal axis in (b) in Figure 3 shows the offset of the groove between the clock line and the low-potential power signal line, and the vertical axis shows the change in parasitic capacitance between the clock line and all signal lines compared with the case where the groove between the clock line and the low-potential power signal line is not offset. The bar graph in Figure 3 shows the change in parasitic capacitance between different clock lines and all signal lines. CK1-Total shows the change in parasitic capacitance between the first clock line and all signal lines, CK2-Total shows the change in parasitic capacitance between the second clock line and all signal lines, CK3-Total shows the change in parasitic capacitance between the third clock line and all signal lines, and CK4-Total shows the change in parasitic capacitance between the fourth clock line and all signal lines.

[0033] As can be seen from Figures 2 and 3, compared to when the grooves of the clock line and the low-potential power signal line are not offset, when the low-potential power signal line and the mask are offset, resulting in the grooves of the low-potential power signal line being offset relative to the clock line, the parasitic capacitance between each clock line and the low-potential power signal line changes, and the parasitic capacitance between adjacent clock lines and the low-potential power signal line has opposite changing trends. For example, the parasitic capacitance between the first clock line 111 and the second clock line 112 and the low-potential power signal line 12 has opposite changing trends, resulting in an increase in the signal delay difference between different clock lines. It can be understood that due to the change in the parasitic capacitance between the clock line and the low-potential power signal line, the electrical signal output by the clock line does not match the preset electrical signal, and the signal delay difference between different clock lines increases, resulting in different turn-on times or turn-on voltages of different transistors, affecting the display effect. Therefore, the existing OLED display device has a technical problem in which the grooves on the clock line are offset, resulting in excessive changes in the parasitic capacitance of the clock line, which affects the display.

[0034] In response to the above technical problems, embodiments of the present application provide a display panel and a display device to improve the above technical problems.

[0035] Figure 4 is a first schematic diagram of a display panel provided in an embodiment of the present application. Figure 5 is a second schematic diagram of a display panel provided in an embodiment of the present application. Figure 6 is a third schematic diagram of a display panel provided in an embodiment of the present application. Figure 7 is a fourth schematic diagram of a display panel provided in an embodiment of the present application. Figure 8 is a first schematic diagram of an embodiment of the present application when the through-holes of the clock signal line and the low-potential signal line are not offset. Figure 9 is a schematic diagram of an embodiment of the present application when the positions of the through-holes in the clock signal line and the low-potential signal line are offset. Figure 10 is a bar graph of the offset of the through-holes in the clock signal line and the low-potential signal line in Figure 8 and the change in the parasitic capacitance of the clock signal line. Figure 11 is a second schematic diagram of an embodiment of the present application when the through-holes of the clock signal line and the low-potential signal line are not offset. Figure 12 is a schematic diagram of an embodiment of the present application when the positions of the through-holes in the clock signal line and the low-potential signal line are offset. Figure 13 is a bar graph of the offset of the through-holes in the clock signal line and the low-potential signal line and the change in the parasitic capacitance of the clock signal line provided in Figure 11.

[0036] As shown in FIG. 4 to FIG. 13 , an embodiment of the present application provides a display panel 2 , which includes a display area 21 and a driving circuit area 221 disposed on at least one side of the display area 21 . The display panel 2 includes:

[0037] A plurality of clock signal lines 41 are provided in the driving circuit area 221 , and the plurality of clock signal lines 41 extend along a first direction X;

[0038] A low-potential signal line 42 is provided in the driving circuit area 221 , and the orthographic projections of the plurality of clock signal lines 41 on the low-potential signal line 42 are located within the low-potential signal line 42 ;

[0039] Among them, a plurality of through holes 421 are opened on the low potential signal line 42, and the through holes 421 are arranged in an array to form a plurality of repeating units 40. In the repeating unit 40, the number of through holes 421 in each column is the same (for example, in each repeating unit 40 in FIG8 , the number of through holes in each column is 1). In any two of the clock signal lines 41, the overlapping area between one of the clock signal lines 41 and all the through holes 421 corresponding to a repeating unit 40 is equal to the overlapping area between the other clock signal line 41 and all the through holes 421 corresponding to a repeating unit 40 (for example, in FIG8 , the overlapping area between the first clock signal line 311 and all the through holes 421 corresponding to a repeating unit 40 is L4). *L1*1, the overlapping area between the second clock signal line 312 and all the corresponding through holes 421 in a repeating unit 40 is L4*L1*1, and the two are equal), and the overlapping area between any clock signal line 41 and the corresponding through hole 421 in a repeating unit 40 is equal to the product of the width L1 of the clock signal line 41 in the second direction Y, the length L4 of the through hole 421 in the first direction X, and the number of through holes 421 in a column of the repeating unit 40 (for example, in FIG. 8 , the overlapping area between the first clock signal line 311 and all the corresponding through holes 421 in a repeating unit 40 is L4*L1*1); the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0040] An embodiment of the present application provides a display panel, which makes the overlapping area between one clock signal line and all corresponding through-holes in a repeating unit equal to the overlapping area between the other clock signal line and all corresponding through-holes in a repeating unit, and the overlapping area between any clock signal line and the through-holes in a repeating unit is equal to the product of the width of the clock signal line, the width of the through-hole and the number of through-holes in a column in a repeating unit. When the position of the through-hole shifts, the overlapping area between any clock signal line and the through-hole remains unchanged, and the overlapping areas between each clock signal line and the through-hole are equal, so that the parasitic capacitance of each clock signal line is close or even equal, thereby avoiding different signal delays of adjacent clock signal lines and avoiding changes in signal delay caused by changes in impedance of the clock signal line, so that the display panel can display normally.

[0041] Specifically, in the drawings of the present application, the number of through holes in each column in the repeating unit 40 is 1, but the embodiments of the present application are not limited thereto. For example, the number of through holes in each column in the repeating unit 40 is 2.

[0042] Specifically, as shown in Figure 4, the display panel 2 includes a display area 21 and a non-display area 22. The non-display area 22 includes a driving circuit area 221 and a binding area 222. A gate driving circuit is provided in the driving circuit area 221. As shown in Figure 5, the gate driving circuit includes a first scan driving unit 31, a second scan driving unit 32, a third scan driving unit 34 and a signal control unit 33. The first scan driving unit 31 and the signal control unit 33 can be arranged in the driving circuit area 221 on both sides of the display area 21. The first scan driving unit 31 includes a clock signal line 41.

[0043] Specifically, the low-potential signal line 42 is a low-potential power supply signal line connected to the light-emitting devices of the display panel. After connecting to the common electrode of the display panel, the low-potential signal line 42 is transferred through the pixel electrode layer 521 and then connected to the signal line of the second source-drain layer 517 for signal input (the rest of the low-potential signal line 42 is not shown in the figure). Therefore, in Figure 7, part of the pixel electrode layer 521 is the low-potential signal line 42, and the low-potential signal line 42 does not contact the pixel electrode in the pixel electrode layer 521.

[0044] 5 and 8 , the plurality of clock signal lines 41 include a first clock signal line 311 , a second clock signal line 312 , a third clock signal line 313 and a fourth clock signal line 314 . The width of each clock signal line 41 is equal, and the spacing between adjacent clock signal lines 41 is equal.

[0045] Specifically, as shown in FIG. 7 , the clock signal line 41 is routed in parallel using the second source-drain layer 517 and the third source-drain layer 519 .

[0046] In some embodiments, each column of the through holes is arranged along the first direction, and there is a distance between two adjacent rows of the through holes in the first direction.

[0047] In some embodiments, the number of columns of the through holes is equal to the number of the clock signal lines, each column of the through holes is arranged in a one-to-one correspondence with each clock signal line, the through holes are arranged symmetrically about the center line axis of the clock signal line, and the spacing between one end of the through hole corresponding to one clock signal line close to another clock signal line and the other clock signal line is greater than or equal to the maximum offset of the through hole, and the width of the through hole exceeding the clock signal line is greater than or equal to the maximum offset of the through hole.

[0048] In some embodiments, the width of the through hole is equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines.

[0049] In some embodiments, a spacing between adjacent clock signal lines is greater than a sum of a maximum offset of the through-hole and half of a width of a portion of the through-hole extending beyond the clock signal line.

[0050] In some embodiments, each column of the through holes is arranged in one-to-one correspondence with each clock signal line. Within the repeating unit, the minimum spacing between the two ends of the through hole and the corresponding clock signal line is not equal, and in any two of the clock signal lines, the minimum spacing between one end of each through hole and the corresponding clock signal line is equal, and the minimum spacing between the other end of each through hole and the corresponding clock signal line is equal.

[0051] In some embodiments, each column of the through holes is arranged in one-to-one correspondence with each clock signal line, one end of the through hole corresponding to one clock signal line is aligned with one end of the clock signal line, and the other end of the through hole is aligned with one end of another clock signal line.

[0052] In some embodiments, the minimum spacing between the left end of the through hole and the corresponding clock signal line is greater than the minimum spacing between the right end of the through hole and the corresponding clock signal line; or the minimum spacing between the left end of the through hole and the corresponding clock signal line is less than the minimum spacing between the right end of the through hole and the corresponding clock signal line.

[0053] In some embodiments, the through hole includes a first through hole corresponding to two adjacent clock signal lines and a second through hole corresponding to one clock signal line. Along the first direction, in two adjacent columns of through holes, one end of the through holes in one column close to the through holes in the other column is located on the same straight line as one end of the through holes in the other column.

[0054] In some embodiments, the first through hole is symmetrically arranged about the center line of the portion of the low potential signal line located between two adjacent clock signal lines, and the width of the portion of the second through hole extending beyond the clock signal line is greater than the maximum offset of the through hole.

[0055] In some embodiments, one end of the through hole corresponding to one of the clock signal lines and one end of the through hole corresponding to another of the clock signal lines are respectively located on the center lines of the two clock signal lines.

[0056] In some embodiments, in the first through hole and the second through hole corresponding to the same clock signal line, the overlapping area between one second through hole and the corresponding clock signal line is smaller than the overlapping area between one first through hole and the corresponding clock signal line, the overlapping area between another second through hole and the corresponding clock signal line is larger than the overlapping area between another first through hole and the corresponding clock signal line, and the overlapping areas between any first through hole and the corresponding two adjacent clock signal lines are not equal.

[0057] In some embodiments, the display panel includes two symmetrically arranged groups of first scan driving units, each group of first scan driving units includes four clock signal lines, the through holes include two columns of second through holes and three columns of first through holes, and the three columns of first through holes are located between the two columns of second through holes.

[0058] In some embodiments, as shown in FIG8 , each column of through holes 421 is arranged along the first direction X, and there is a gap between two adjacent rows of through holes 421 in the first direction X. By arranging two adjacent columns of through holes to alternate vertically in the arrangement direction of the clock signal lines, the through holes on each clock signal line are distributed more evenly, which can release moisture from various areas and improve the performance of the display panel.

[0059] Specifically, (a) in Figure 8 is a first stacking diagram of the clock signal line 41 and the low-potential signal line 42, (b) in Figure 8 is a decomposition diagram of the low-potential signal line 42 in (a) in Figure 8, and (c) in Figure 8 is a decomposition diagram of the clock signal line 41 in (a) in Figure 8.

[0060] Specifically, it can be understood that the drawings in FIG. 8 and FIG. 9 may be designs within different display panels during the actual manufacturing process.

[0061] Specifically, it can be seen that within two adjacent rows of through holes, one row of through holes is shifted downward relative to the other row of through holes in the direction in which the clock signal lines are arranged. This results in a more even distribution of through holes along each clock signal line, releasing moisture from various areas and preventing moisture intrusion that could cause changes in the performance of the thin-film transistors. However, the present invention is not limited to this embodiment, and adjacent rows of through holes can be arranged in contact in the direction in which the clock signal lines are arranged.

[0062] In some embodiments, the left end of the through-hole located on the far left extends beyond the leftmost clock signal line, the right end of the through-hole located on the far right extends beyond the rightmost clock signal line, and half the width of the portion of the through-hole extending beyond the clock signal line is greater than the maximum offset of the through-hole. By overlapping the through-hole with each clock signal line, and half the width of the portion of the through-hole extending beyond the clock signal line being greater than the maximum offset of the through-hole, when the position of the through-hole shifts, the overlapping area of ​​the through-hole and any clock signal line is equal, thereby making the difference in parasitic capacitance between each clock signal line and the low-potential signal line less variable, and the difference in parasitic capacitance between adjacent clock signal lines and low-potential signal lines being similar or even identical, thereby avoiding excessive changes in parasitic capacitance between the clock signal line and the low-potential signal line, resulting in poor display, and avoiding excessive differences in parasitic capacitance between different clock signal lines and low-potential signal lines, further avoiding poor display.

[0063] Specifically, as shown in Figure 8, the left end of the through hole 421 located on the leftmost side extends beyond the leftmost clock signal line (the first clock signal line 311 in Figure 8), and the right end of the through hole 421 located on the rightmost side extends beyond the rightmost clock signal line (the second clock signal line 314 in Figure 8), and half of the width of the portion of the through hole 421 extending beyond the clock signal line 41 is greater than the maximum offset of the through hole 421. Taking Figure 8 as an example, half of the width of the portion of the through hole 421 extending beyond the clock signal line 41 is (L3-L1) / 2. If this value is greater than the maximum offset of the through hole, the overlapping area of ​​the through hole and any clock signal line can be made equal.

[0064] Specifically, in the embodiment of the present application, the through hole is in an unshifted state, which means that the through hole is located at the theoretical design position, and no alignment offset occurs between the mask plate and the pixel electrode layer; the through hole is in an offset state, which means that the through hole is in a non-theoretical design position, and an alignment offset occurs between the mask plate and the pixel electrode layer, resulting in an offset in the position of the through hole.

[0065] Specifically, the maximum offset of the through hole refers to the maximum lateral offset of the through hole relative to the design position during the actual preparation process. For example, during the design, the center line of the through hole coincides with the center line of the clock signal line, but in the actual preparation process, the maximum offset of the center line of the through hole to the right relative to the center line of the clock signal line is 3 microns. Considering that when the through hole is offset, the maximum offset to both sides is equal, therefore, the maximum offset of the through hole is 3 microns. However, when the offset to both sides is unequal when the through hole is offset, the maximum offset of the through hole is the offset that the through hole shifts more to one side as the maximum offset of the through hole.

[0066] In some embodiments, as shown in Figure 8, the number of columns of the through holes 421 is equal to the number of the clock signal lines 41, and each column of the through holes 421 is arranged in a one-to-one correspondence with each clock signal line 41. The through holes 421 are arranged symmetrically about the center line axis of the clock signal line 41, and the spacing between one end of the through hole 421 corresponding to one clock signal line 41 close to another clock signal line 41 and the other clock signal line 41 is greater than or equal to the maximum offset of the through hole 421, and the width of the portion of the through hole 421 that exceeds the clock signal line 41 on any side (for example, (L3-L1) / 2 in Figure 8) is greater than or equal to the maximum offset of the through hole 421.

[0067] Specifically, when designing the relative positions of the through hole and the clock signal line, the through hole can be in an unshifted state or in the actual product, the through hole can be symmetrical about the center line of the clock signal line. Therefore, in the actual preparation process, even if the through hole is offset relative to the clock signal line, since the width of the part of the through hole on any side that exceeds the clock signal line is greater than or equal to the maximum offset of the through hole, and the spacing between one end of the through hole close to the other clock signal line and the other clock signal line is greater than or equal to the maximum offset of the through hole, the overlapping area of ​​the clock signal line and the corresponding through hole does not change, thereby making the parasitic capacitance between the clock signal line and the low power signal line change small or even unchanged, the impedance change of the clock signal line small or even unchanged, and the difference in impedance change between any two clock signal lines small or even equal, avoiding poor display due to impedance difference of different clock signal lines.

[0068] Specifically, as shown in FIG8 , the number of columns of through holes 421 is 4, and the number of clock signal lines 41 is 4, and the two are equal, so that each column of through holes 421 is arranged in a one-to-one correspondence with each clock signal line 41, and the through holes 421 are symmetrically arranged about the center line of the clock signal line 41, so that the widths of the two parts of the through holes 421 extending beyond the clock signal line 41 are equal, and the spacing between the through hole 421 corresponding to each clock signal line 41 and another clock signal line 41 is greater than or equal to the maximum offset of the through hole 421. For example, the spacing between the through hole 421 corresponding to the first clock signal line 311 and the second clock signal line 312 is greater than the maximum offset of the through hole 421. This can prevent the through hole corresponding to the first clock signal line from offsetting to the second clock signal line, thereby maintaining the overlapping area between each clock signal line and the through hole unchanged, and the width of the part of the through hole on either side extending beyond the clock signal line 41 is greater than or equal to the maximum offset of the through hole 421. For example, in FIG8 , the width of the right side of the through hole extending beyond the first clock signal line 311 is greater than the maximum offset of the through hole 421.

[0069] Specifically, each column of through holes is arranged in one-to-one correspondence with the clock signal line, and when the through holes are in an un-offset state, the through holes are arranged symmetrically about the axis of the clock signal line, and the spacing between one end of the through hole corresponding to one clock signal line close to the other clock signal line and the other clock signal line is greater than or equal to the maximum offset of the through hole, and the width of the through hole beyond the clock signal line is greater than the maximum offset of the through hole, so that when the through hole is offset, the through hole will not be offset to another clock signal line, and the overlapping area of ​​a single through hole and the corresponding clock signal line is maintained at the product of the length of the through hole and the width of the clock signal line, so that the overlapping area of ​​the through hole and the clock signal line does not change, the parasitic capacitance between the clock signal line and the low power signal line changes little or even does not change, the impedance change of the clock signal line changes little or even does not change, and the difference in impedance change between any two clock signal lines is small or even equal, thereby avoiding poor display caused by impedance differences between different clock signal lines.

[0070] Specifically, the above embodiments are described using the example of a through hole being arranged symmetrically about the center line of the clock signal line, but the embodiments of the present application are not limited to this. For example, when the through hole is in an un-offset state, that is, in a theoretical design or an actual product, the through hole may not be arranged symmetrically about the center line of the clock signal line, but the spacing between the two ends of the through hole and other clock signal lines is greater than or equal to the maximum offset of the through hole, and the width of the part of the through hole that exceeds the corresponding clock signal line is greater than or equal to the maximum offset of the through hole, so that the through hole will not be offset to another clock signal line, and the overlapping area between the through hole and the corresponding clock signal line does not change.

[0071] For example, the leftmost through-hole is not symmetrical about the center line of the first clock signal line 311, but the width of the portion of the leftmost through-hole on either side that extends beyond the first clock signal line 311 is greater than or equal to the maximum offset of the through-hole, and the spacing between the two sides of the through-hole and other clock signal lines is greater than or equal to the maximum offset of the through-hole. For example, the width of the portion of the left side of the through-hole that extends beyond the first clock signal line 311 is 4, and the width of the portion of the right side of the through-hole that extends beyond the first clock signal line 311 is 3, but both are greater than the maximum offset of the through-hole. In this way, the overlapping area between the first clock signal line and the through-hole can be equal to the overlapping area between the other clock signal lines and the through-hole.

[0072] In some embodiments, as shown in FIG8 , the width L3 of the through hole 421 is equal to the sum of the width L1 of the clock signal line 41 and the spacing L2 between adjacent clock signal lines 41. By making the width of the through hole equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines, and by symmetrically arranging the through holes about the clock signal line, and by extending the through hole beyond the clock signal line by a width greater than or equal to the maximum offset of the through hole, the two portions of the through hole extending beyond the clock signal line are symmetrical about the clock signal line, and in two adjacent columns of through holes, the right end of one column of through holes is aligned with the left end of the other column of through holes. This ensures that when the through hole is offset, whether to the left or right, the overlapping area between the clock signal line and the through hole remains unchanged, and the overlapping area between each clock signal line and the through hole is close to or even equal, so that the impedance change of each clock signal line is small or even unchanged, and the difference in impedance change between any two clock signal lines is small or even equal, thereby avoiding poor display caused by impedance differences between different clock signal lines.

[0073] Specifically, taking the example of a clock signal line with a width of 8 microns and a spacing of 6 microns between adjacent clock signal lines, the width of the through-hole is 14 microns and the length is 14 microns, then the width of the portion of the through-hole extending beyond one side of the clock signal line is 3 microns. Taking the example of a maximum offset of the through-hole being 3 microns, then regardless of whether the through-hole is offset to the left or to the right, the overlapping area of ​​a single through-hole and the clock signal line remains 14 microns * 8 microns, and the overlapping area of ​​each clock signal line and the through-hole is the same. Therefore, the impedance change difference of each clock signal line is small (the reason for the change may be that the electrical properties of each signal line are slightly changed due to the offset of the through-hole position, causing the impedance change of the clock signal line) or even no change, thereby avoiding poor display caused by the impedance change of the clock signal line, and the impedance change difference of any two clock signal lines is small or even equal, thereby avoiding poor display caused by the impedance difference of different clock signal lines.

[0074] In some embodiments, as shown in FIG8 , the spacing L2 between adjacent clock signal lines 41 is greater than the sum of the maximum offset of the through-hole 421 and half the width of the portion of the through-hole extending beyond the clock signal line 41. By making the spacing between adjacent clock signal lines greater than the sum of the maximum offset of the through-hole and half the width of the portion of the through-hole extending beyond the clock signal line, even if the through-hole is offset during the actual manufacturing process, the through-hole will not be offset onto the adjacent clock signal line, and the width of the through-hole extending beyond the clock signal line is greater than or equal to the maximum offset of the through-hole. This ensures that the overlapping area between the clock signal line and the through-hole does not change, and the overlapping area between each clock signal line and the through-hole is close to or even equal, so that the impedance change of each clock signal line is small or even unchanged, and the difference in impedance change between any two clock signal lines is small or even equal, thereby avoiding poor display caused by impedance differences between different clock signal lines.

[0075] Specifically, taking the example of a spacing between adjacent clock signal lines of 8 microns, a maximum offset of the through-hole of 3 microns, and a width of the portion of the through-hole extending beyond the clock signal line of 8 microns, the spacing between adjacent clock signal lines is greater than the sum of the maximum offset of the through-hole and half the width of the portion of the through-hole extending beyond the clock signal line. When the through-hole is offset, the through-hole will not be offset to other clock signal lines, and the overlapping area between the through-hole and the clock signal line remains unchanged.

[0076] Specifically, the above embodiment is described by taking the through-holes as being arranged axially symmetrically about the center line of the clock signal line as an example, but the embodiments of the present application are not limited thereto. For example, when the through-hole is in an undeflected state, the width of the portion of the through-hole extending beyond the clock signal line on either side is greater than or equal to the maximum deflection of the through-hole, and the spacing between adjacent clock signal lines is greater than or equal to the sum of the maximum deflection of the through-hole and the maximum width of the portion of the through-hole extending beyond the clock signal line. For example, if the widths of the two portions of the through-hole extending beyond the clock signal line are different, the width of one portion of the through-hole extending beyond the clock signal line is 4 microns, and the width of the other portion of the through-hole extending beyond the clock signal line is 3 microns, then the maximum width of the portion of the through-hole extending beyond the clock signal line is 4 microns. At the same time, the spacing between adjacent clock signal lines is greater than or equal to the sum of the maximum deflection of the through-hole and the maximum width of the portion of the through-hole extending beyond the clock signal line. For example, the spacing between adjacent clock signal lines is 8 microns, and the maximum deflection of the through-hole is 3 microns. This ensures that the through-hole will not shift onto other clock signal lines when deflected, and the overlapping area between each clock signal line and the through-hole will not be changed.

[0077] In some embodiments, as shown in Figure 9, each column of the through holes 421 is arranged in a one-to-one correspondence with each clock signal line 41. In the repeating unit 40, the minimum spacing between the two ends of the through hole 421 and the corresponding clock signal line 41 is not equal, and in any two of the clock signal lines 41, the minimum spacing between one end of each through hole 421 and the corresponding clock signal line 41 is equal, and the minimum spacing between the other end of each through hole 421 and the corresponding clock signal line 41 is equal.

[0078] Specifically, in the actual preparation process, due to the deviation of the process, the position of the through hole will be offset relative to the theoretical design position. At this time, the minimum spacing between the two ends of the through hole and the corresponding clock signal line is not equal, but within any two clock signal lines, one end of each through hole is equal to the minimum spacing between the corresponding clock signal line, and the other end of each through hole is equal to the minimum spacing between the corresponding clock signal line, so that the relative offset of each through hole and the clock signal line is the same, and the overlapping area of ​​each through hole and the corresponding clock signal line remains unchanged, and the overlapping area of ​​each through hole and the corresponding clock signal line is equal, so that the parasitic capacitance between the clock signal line and the low power signal line can be changed less or even not changed, the impedance change of the clock signal line is small or even does not change, and the difference in impedance change between any two clock signal lines is small or even equal, avoiding poor display due to impedance difference of different clock signal lines.

[0079] Specifically, the minimum spacing between the two ends of the through hole 421 and the corresponding clock signal line 41 means that the through hole has left and right ends, and the spacing L6 between the left end of the through hole and the left end of the corresponding clock signal line is the minimum spacing between the left end of the through hole and the corresponding clock signal line, and the spacing L7 between the right end of the through hole and the right end of the corresponding clock signal line is the minimum spacing between the right end of the through hole and the corresponding clock signal line. Then, the spacing between the left end of the through hole and the left end of the corresponding clock signal line and the spacing between the right end of the through hole and the right end of the corresponding clock signal line are the minimum spacings between the two ends of the through hole and the corresponding clock signal line.

[0080] Specifically, as shown in Figure 9, it can be seen that the distance L6 between the left end of the through hole and the left end of the corresponding clock signal line and the distance L7 between the right end of the through hole and the right end of the corresponding clock signal line are not equal, but in any two clock signal lines 41, for example, the first clock signal line 311 and the second clock signal line 312, the distance between the left end of the through hole 421 corresponding to the first clock signal line 311 and the left end of the first clock signal line 311 is equal to the distance between the left end of the through hole 421 corresponding to the second clock signal line 312 and the left end of the second clock signal line 312, and the distance between the right end of the through hole 421 corresponding to the first clock signal line 311 and the right end of the first clock signal line 311 is equal to the distance between the right end of the through hole 421 corresponding to the second clock signal line 312 and the right end of the second clock signal line 312, so that the offset of the through hole corresponding to each clock signal line and the clock signal line is equal, and the overlapping area of ​​each through hole and the corresponding clock signal line remains unchanged.

[0081] In some embodiments, as shown in (a) and (f) of FIG9 , each column of through-holes 421 is provided in a one-to-one correspondence with each clock signal line 41, with one end of the through-hole 421 corresponding to one clock signal line 41 aligned with one end of the clock signal line 41, and the other end of the through-hole 421 aligned with one end of another clock signal line 41. By aligning one end of a through-hole with one end of another clock signal line, the through-hole is prevented from shifting onto another clock signal line, and the overlapping area between each clock signal line and the through-hole remains unchanged, resulting in minimal or even no impedance change for each clock signal line, and the difference in impedance change between any two clock signal lines is minimal or even equal, thus preventing poor display caused by impedance differences between different clock signal lines.

[0082] In some embodiments, as shown in FIG9 , when the through-hole 421 is in an offset state, one end of the through-hole 421 corresponding to one clock signal line 41 is aligned with one end of another clock signal line 41. By aligning one end of a through-hole with one end of another clock signal line when the through-hole is in an offset state, the through-hole is prevented from shifting onto another clock signal line, and the overlapping area between each clock signal line and the through-hole remains unchanged. This results in minimal or even no impedance change for each clock signal line, and the difference in impedance change between any two clock signal lines is minimal or even equal, thus preventing poor display caused by impedance differences between different clock signal lines.

[0083] Specifically, taking the maximum offset of the through hole as an example of 3 microns, (a) in Figure 9 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 8 is offset by 3 microns to the left relative to the clock signal line, (b) in Figure 9 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 8 is offset by 2 microns to the left relative to the clock signal line, (c) in Figure 9 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 8 is offset by 1 micron to the left relative to the clock signal line, (d) in Figure 9 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 8 is offset by 1 micron to the right relative to the clock signal line, (e) in Figure 9 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 8 is offset by 2 microns to the right relative to the clock signal line, and (f) in Figure 9 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 8 is offset by 3 microns to the right relative to the clock signal line.

[0084] As shown in FIG9(a), when the through hole 421 is in the offset state, the left end of the through hole 421 corresponding to the second clock signal line 312 is aligned with the right end of the first clock signal line 311, the left end of the through hole 421 corresponding to the third clock signal line 313 is aligned with the right end of the second clock signal line 312, and the left end of the through hole 421 corresponding to the fourth clock signal line 314 is aligned with the right end of the third clock signal line 313. As shown in FIG9(f), the right end of the through hole 421 corresponding to the first clock signal line 311 is aligned with the left end of the second clock signal line 312, the right end of the through hole 421 corresponding to the second clock signal line 312 is aligned with the left end of the third clock signal line 313, and the right end of the through hole 421 corresponding to the third clock signal line 313 is aligned with the left end of the fourth clock signal line 314.

[0085] Specifically, when the through hole is at its maximum offset, one end of the through hole is aligned with one end of another clock signal line, so that the through hole will not be offset to other clock signal lines, thereby avoiding changes in the overlapping area between the clock signal line and the through hole, which will cause changes in the impedance of the clock signal line, thereby improving the display effect of the display panel.

[0086] In some embodiments, as shown in (a) to (c) in Figure 9 , the minimum spacing L6 between the left end of the through hole 421 and the corresponding clock signal line 41 is greater than the minimum spacing L7 between the right end of the through hole 421 and the corresponding clock signal line 41; or as shown in (d) to (f) in Figure 9 , the minimum spacing L6 between the left end of the through hole 421 and the corresponding clock signal line 41 is less than the minimum spacing L7 between the right end of the through hole 421 and the corresponding clock signal line 41 (L7 is 0 in (a) in Figure 9 , and L6 is 0 in (f) in Figure 9 ).

[0087] In some embodiments, as shown in FIG9 , when the through hole 421 is in an offset state, there is a spacing between the two ends of the through hole 421 corresponding to a clock signal line 41 and the two clock signal lines 41 on either side of the clock signal line 41, and the spacing between the two ends of the through hole 421 and the two clock signal lines 41 on either side of the clock signal line 41 is unequal. By ensuring that there is a spacing between the two ends of the through hole and the two clock signal lines on either side, and the spacing between the two ends of the through hole and the two clock signal lines on either side of the clock signal line is unequal, when the through hole is offset, the through hole will not be offset to other clock signal lines, and the overlapping area between the through hole and the corresponding clock signal line remains unchanged, so that the impedance change of each clock signal line is small or even unchanged, and the difference in impedance change between any two clock signal lines is small or even equal, thereby avoiding poor display caused by impedance differences between different clock signal lines.

[0088] Specifically, as shown in (b), (c), (d) and (e) in Figure 9 , the distance between the left end of the through hole 421 corresponding to the second clock signal line 312 and the first clock signal line 311 is not the same as the distance between the right end of the through hole 421 corresponding to the second clock signal line 312 and the third clock signal line 313.

[0089] Specifically, for a through hole with clock signal lines on both sides, there can be a distance between the through hole and the clock signal lines on both sides. For a through hole with a clock signal line on only one side, there can be a distance between the through hole and the clock signal line on one side, and the widths of the two parts of the through hole exceeding the corresponding clock signal line are not equal.

[0090] Specifically, the lengths and widths of the through holes corresponding to the clock signal lines are the same.

[0091] Specifically, as shown in FIG10 , -3 on the horizontal axis of FIG10 (a) indicates that the through hole is shifted 3 microns to the left, and 3 indicates that the through hole is shifted 3 microns to the right. Similarly, other values ​​and the values ​​in FIG10 (b) can refer to the above description. (a) in Figure 10 shows the change in parasitic capacitance of each clock signal line and the low-potential signal line in Figure 8 at different offsets. The horizontal axis in (a) in Figure 10 shows the offset of the through-holes of the clock signal line and the low-potential signal line, and the vertical axis shows the change in parasitic capacitance of the clock signal line and the low-potential signal line compared with the case where the through-holes of the clock signal line and the low-potential signal line are not offset. The bar graph in Figure 10 shows the change in parasitic capacitance of different clock signal lines and low-potential signal lines. CK1-ANO shows the change in parasitic capacitance of the first clock signal line 311 and the low-potential signal line, CK2-ANO shows the change in parasitic capacitance of the second clock signal line 312 and the low-potential signal line, CK3-ANO shows the change in parasitic capacitance of the third clock signal line 313 and the low-potential signal line, and CK4-ANO shows the change in parasitic capacitance of the fourth clock signal line 314 and the low-potential signal line. (b) in Figure 10 is the change in parasitic capacitance between each clock signal line and all signal lines in Figure 8 at different offsets. The horizontal axis in (b) in Figure 10 represents the offset of the through-hole between the clock signal line and the low-potential signal line, and the vertical axis represents the change in parasitic capacitance between the clock signal line and all signal lines compared to when the through-hole between the clock signal line and the low-potential signal line is not offset. The bar graph in Figure 10 is the change in parasitic capacitance between different clock signal lines and all signal lines. CK1-Total represents the change in parasitic capacitance between the first clock signal line and all signal lines, CK2-Total represents the change in parasitic capacitance between the second clock signal line and all signal lines, CK3-Total represents the change in parasitic capacitance between the third clock signal line and all signal lines, and CK4-Total represents the change in parasitic capacitance between the fourth clock signal line and all signal lines.

[0092] From the comparison between Figures 3 and 10, it can be seen that compared with the display device in the prior art, in the display panel provided by the present application, as the offset of the through hole changes, the change in the parasitic capacitance between each clock signal line and the low-potential signal line, as well as the change in the parasitic capacitance between each clock signal line and all signal lines are greatly reduced. For example, in Figure 3, the change in the parasitic capacitance between each clock line and the low-potential power supply signal line reaches 3.3%, and the change in the parasitic capacitance between each clock line and all signal lines reaches 2.7%. In Figure 10, the change in the parasitic capacitance between each clock signal line and the low-potential signal line is less than 0.9%, and the change in the parasitic capacitance between each clock signal line and all signal lines is less than 0.3%. That is, in the present application, the change in the parasitic capacitance on each clock signal line becomes smaller, the parasitic capacitance on the clock signal line is relatively stable, and the change trends of some clock signal lines are the same, so that the parasitic capacitance of each clock signal line is close or even equal, thereby avoiding different signal delays of adjacent clock signal lines and avoiding signal delay changes caused by impedance changes of the clock signal lines, so that the display panel can display normally.

[0093] In some embodiments, as shown in FIG11 , the through holes 421 include a first through hole 421a corresponding to two adjacent clock signal lines 41 and a second through hole 421b corresponding to one clock signal line 41. In the first direction X, in two adjacent rows of through holes 421, one end of one row of through holes 421 adjacent to the other row of through holes 421 is aligned with one end of the other row of through holes 421. By aligning one end of the second through hole with one end of the first through hole, and by ensuring that the width of the portion of the second through hole extending beyond the clock signal line is greater than the maximum offset of the through hole, the overlapping area between the clock signal line and the through hole remains unchanged, resulting in minimal or even no impedance change for each clock signal line. Furthermore, the impedance change difference between any two clock signal lines is minimal or even equal, thereby preventing display defects caused by impedance differences between different clock signal lines.

[0094] In some embodiments, as shown in FIG11 , the first through-hole 421a is symmetrically arranged about the centerline of the portion of the low-potential signal line 42 located between two adjacent clock signal lines 41, and the width of the portion of the second through-hole 421b extending beyond the clock signal line 41 (e.g., L5 in FIG11 ) is greater than the maximum offset of the through-hole 421. By arranging the first through-hole symmetrically about the centerline of the portion of the low-potential signal line located between two adjacent clock signal lines, aligning one end of the second through-hole with one end of the first through-hole, and extending the width of the portion of the second through-hole extending beyond the clock signal line greater than the maximum offset of the through-hole, the overlapping area between the clock signal line and the through-hole remains unchanged, resulting in minimal or even no impedance change between the clock signal lines, and ensuring that the difference in impedance change between any two clock signal lines is minimal or even equal, thereby preventing display defects caused by impedance differences between different clock signal lines.

[0095] Specifically, the relative positions of the through-holes and the clock signal lines in the display panel shown in FIG11 are the relative positions of the through-holes and the clock signal lines when the through-holes are in an unshifted state, or in other words, when the through-holes are in their theoretically designed positions. As can be seen from FIG11 , even if the positions of the through-holes shift during the actual manufacturing process, the overlapping area between the through-holes and the clock signal lines does not change, and the overlapping area between each clock signal line and the through-hole remains unchanged. This results in minimal or even no change in the impedance of each clock signal line, and the difference in impedance change between any two clock signal lines is minimal or even equal, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0096] Specifically, (a) in Figure 11 is a second stacking diagram of the clock signal line 41 and the low-potential signal line 42, (b) in Figure 11 is a decomposition diagram of the low-potential signal line 42 in (a) in Figure 11, and (c) in Figure 11 is a decomposition diagram of the clock signal line 41 in (a) in Figure 11.

[0097] Specifically, it can be understood that the drawings in FIG. 11 and FIG. 12 may be designs within different display panels during the actual manufacturing process.

[0098] Specifically, as shown in FIG. 11 , it can be seen that part of the through holes 421 are located on two clock signal lines 41 , and part of the through holes 421 are located on one clock signal line 41 .

[0099] In some embodiments, as shown in FIG11 , one end of the through-hole 421 corresponding to one clock signal line 41 and one end corresponding to another clock signal line 41 are respectively located on the center lines of the two clock signal lines 41. This ensures that when two adjacent rows of through-holes are offset, the increased overlapping area between one row of through-holes and the clock signal line is equal to the decreased overlapping area between the other row of through-holes and the clock signal line. This ensures that the overlapping area between the clock signal lines and the through-holes remains unchanged, resulting in minimal or even no change in the impedance of each clock signal line. Furthermore, the difference in impedance change between any two clock signal lines is minimal or even equal, thereby preventing display defects caused by impedance differences between different clock signal lines.

[0100] Specifically, when the through hole 421 is in an unshifted state, when two adjacent columns of through holes are shifted, the increased overlapping area between one column of through holes and the clock signal line is equal to the reduced overlapping area between the other column of through holes and the clock signal line, so that the overlapping area between the clock signal line and the through hole does not change, so that the impedance change of each clock signal line is small or even does not change, and the difference in impedance change between any two clock signal lines is small or even equal, thereby avoiding poor display due to impedance differences between different clock signal lines.

[0101] Specifically, both ends of the first through hole are respectively located on the center lines of the two clock signal lines, and one end of the second through hole is located on the center line of one clock signal line.

[0102] Specifically, as shown in FIG. 11 , the left end of the first through hole 421 a on the first clock signal line 311 is located on the center line of the first clock signal line 311 , and the right end of the first through hole 421 a is located on the center line of the second clock signal line 312 .

[0103] In some embodiments, as shown in Figure 12, in the first through hole 421a and the second through hole 421b corresponding to the same clock signal line 41, the overlapping area between one second through hole 421b and the corresponding clock signal line 41 is smaller than the overlapping area between one first through hole 421a and the corresponding clock signal line 41, and the overlapping area between another second through hole 421b and the corresponding clock signal line 41 is larger than the overlapping area between another first through hole 421a and the corresponding clock signal line 41, and the overlapping areas between any first through hole 421a and the corresponding two adjacent clock signal lines 41 are not equal. When the through hole is offset, the overlapping area between a second through hole and the clock signal line is reduced, and the overlapping area between the corresponding first through hole and the clock signal line is increased; the overlapping area between a second through hole and the clock signal line is increased, and the overlapping area between the corresponding first through hole and the clock signal line is reduced, so that when the through hole is offset, the overlapping area between each clock signal line and the through hole does not change, so that the impedance change of each clock signal line is small or even does not change, and the difference in impedance change between any two clock signal lines is small or even equal, thereby avoiding poor display caused by impedance differences between different clock signal lines.

[0104] Specifically, when the through hole 421 is in the offset state, the offset amounts of the through holes corresponding to any two clock signal lines are equal, so that the overlapping area between each clock signal line and the corresponding through hole remains unchanged.

[0105] Specifically, as shown in FIG11 , the display panel further includes a low-voltage signal line 44 and a start signal line 43. Since the low-voltage signal line 44 transmits a DC signal, the overlap between the low-voltage signal line 44 and the through-hole does not affect the signal on the low-voltage signal line 44. However, for the start signal line 43, the overlap between the through-hole and the start signal line 43 reduces the impedance of the start signal line, thereby reducing signal loss.

[0106] Specifically, taking the maximum offset of the through hole as an example of 3 microns, (a) in Figure 12 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 11 is offset by 3 microns to the left relative to the clock signal line, (b) in Figure 12 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 11 is offset by 2 microns to the left relative to the clock signal line, (c) in Figure 12 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 11 is offset by 1 micron to the left relative to the clock signal line, (d) in Figure 12 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 11 is offset by 1 micron to the right relative to the clock signal line, (e) in Figure 12 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 11 is offset by 2 microns to the right relative to the clock signal line, and (f) in Figure 12 is a stacking diagram of the clock signal line and the low-potential signal line when the through hole in Figure 11 is offset by 3 microns to the right relative to the clock signal line.

[0107] As shown in Figures 11, 12(a), 12(b), and 12(c), when the through hole 421 is in a state of being shifted to the left, the overlapping area between the first clock signal line 311 and the corresponding second through hole 421b is smaller than the overlapping area between the first clock signal line 311 and the corresponding first through hole 421a, and the overlapping area between the fourth clock signal line 314 and the corresponding second through hole 421b is larger than the overlapping area between the fourth clock signal line 314 and the corresponding first through hole 421a; as shown in Figures 11, 12(d), 12(e), and 12(f), when the through hole 421 is in a state of being shifted to the right, the overlapping area between the first clock signal line and the corresponding second through hole 421b is larger than the overlapping area between the first clock signal line 311 and the corresponding first through hole 421a, and the overlapping area between the fourth clock signal line 314 and the corresponding second through hole 421b is smaller than the overlapping area between the fourth clock signal line 314 and the corresponding first through hole 421a. In addition, in FIG. 12( a ) to FIG. 12 ( f ), the overlapping areas between any clock signal line 41 and the corresponding two first through holes are different.

[0108] Specifically, when the through hole is offset, the offset direction of the first through hole and the second through hole is the same, the increased overlapping area between the second through hole and the clock signal line is equal to the decreased overlapping area between the corresponding first through hole and the clock signal line, the decreased overlapping area between the second through hole and the clock signal line is equal to the increased overlapping area between the corresponding first through hole and the clock signal line, and the increased overlapping area between a first through hole and the clock signal line is equal to the decreased overlapping area between another first through hole and the clock signal line, thereby ensuring that the overlapping area between each clock signal line and the through hole remains unchanged.

[0109] Specifically, as shown in FIG13 , -3 on the horizontal axis of (a) in FIG13 indicates that the through hole is shifted 3 microns to the left, and 3 indicates that the through hole is shifted 3 microns to the right. Similarly, other values ​​and the values ​​in (b) in FIG13 can refer to the above description. (a) in Figure 13 shows the change in parasitic capacitance of each clock signal line and the low-potential signal line in Figure 11 at different offsets. The horizontal axis in (a) in Figure 13 shows the offset of the through-holes of the clock signal line and the low-potential signal line, and the vertical axis shows the change in parasitic capacitance of the clock signal line and the low-potential signal line compared with the case where the through-holes of the clock signal line and the low-potential signal line are not offset. The bar graph in Figure 13 shows the change in parasitic capacitance of different clock signal lines and low-potential signal lines. CK1-ANO shows the change in parasitic capacitance of the first clock signal line 311 and the low-potential signal line, CK2-ANO shows the change in parasitic capacitance of the second clock signal line 312 and the low-potential signal line, CK3-ANO shows the change in parasitic capacitance of the third clock signal line 313 and the low-potential signal line, and CK4-ANO shows the change in parasitic capacitance of the fourth clock signal line 314 and the low-potential signal line. (b) in Figure 13 shows the change in parasitic capacitance between each clock signal line and all signal lines in Figure 11 at different offsets. The horizontal axis in (b) in Figure 13 represents the offset of the through-hole between the clock signal line and the low-potential signal line, and the vertical axis represents the change in parasitic capacitance between the clock signal line and all signal lines compared to when the through-hole between the clock signal line and the low-potential signal line is not offset. The bar graph in Figure 13 shows the change in parasitic capacitance between different clock signal lines and all signal lines. CK1-Total represents the change in parasitic capacitance between the first clock signal line and all signal lines, CK2-Total represents the change in parasitic capacitance between the second clock signal line and all signal lines, CK3-Total represents the change in parasitic capacitance between the third clock signal line and all signal lines, and CK4-Total represents the change in parasitic capacitance between the fourth clock signal line and all signal lines.

[0110] From the comparison between Figures 3 and 13, it can be seen that compared with the display device in the prior art, in the display panel provided by the present application, as the offset of the through hole changes, the change in the parasitic capacitance between each clock signal line and the low-potential signal line, as well as the change in the parasitic capacitance between each clock signal line and all signal lines are greatly reduced. For example, in Figure 3, the change in the parasitic capacitance between each clock line and the low-potential power supply signal line reaches 3.3%, and the change in the parasitic capacitance between each clock line and all signal lines reaches 2.7%. In Figure 13, the change in the parasitic capacitance between each clock signal line and the low-potential signal line is less than 0.3%, and the change in the parasitic capacitance between each clock signal line and all signal lines is less than 0.1%. That is, in the present application, the change in the parasitic capacitance on each clock signal line becomes smaller, the parasitic capacitance on the clock signal line is relatively stable, and the change trends of some clock signal lines are the same, so that the parasitic capacitance of each clock signal line is similar or even equal, thereby avoiding different signal delays of adjacent clock signal lines, and avoiding signal delay changes caused by impedance changes of the clock signal lines, so that the display panel can display normally.

[0111] In some embodiments, as shown in FIG. 5 to FIG. 11 , the display panel 2 includes two symmetrically arranged groups of first scan driving units 31 , and each group of first scan driving units 31 includes four clock signal lines 41 .

[0112] In some embodiments, the through holes 421 include two columns of second through holes 421 b and three columns of first through holes 421 a , and the three columns of first through holes 421 a are located between the two columns of second through holes 421 b .

[0113] Specifically, the width of the first through hole may be unequal to the width of the second through hole, and the length of the first through hole may be equal to the length of the second through hole.

[0114] Specifically, when the through hole is in an unshifted state, the second through hole 421b may not overlap with the low-voltage signal line 44, and / or the second through hole 421b may not overlap with the starting signal line 43. Alternatively, the second through hole 421b may not overlap with the low-voltage signal line, and the second through hole 421b may overlap with the starting signal line 43. Alternatively, the second through hole 421b may overlap with the low-voltage signal line, and the second through hole 421b may not overlap with the starting signal line 43.

[0115] Specifically, the above embodiments are described by taking the example of equal areas, lengths, and widths of the through holes, but the embodiments of the present application are not limited to this. It is only necessary that in any state, the overlapping area between any clock signal line and the corresponding through hole remains unchanged, and the overlapping area between any two clock signal lines and the through holes is equal.

[0116] In some embodiments, as shown in FIG6 , the display panel 2 includes: a substrate 501, a light shielding layer 502, a buffer layer 503, a barrier layer 504, a first active layer 50, a first gate insulating layer 506, a first metal layer 507, a second gate insulating layer 508, a second metal layer 509, a first interlayer insulating layer 510, a second active layer 511, a third gate insulating layer 512, a third metal layer 513, a second interlayer insulating layer 514, a first source and drain layer 515, a first planarizing layer 516, a second source and drain layer 517, a second planarizing layer 518, a third source and drain layer 519, a third planarizing layer 520, a pixel electrode layer 521, and a pixel definition layer. Layer 522, a first active layer 505 is arranged on one side of the substrate 501, a first gate insulating layer 506 is arranged on one side of the first active layer 505, a first metal layer 507 is arranged on a side of the first gate insulating layer 506 away from the first active layer 505, a second gate insulating layer 508 is arranged on a side of the first metal layer 507 away from the first gate insulating layer 506, a second metal layer 509 is arranged on a side of the second gate insulating layer 508 away from the first metal layer 507, a first interlayer insulating layer 510 is arranged on a side of the second metal layer 509 away from the second gate insulating layer 508, and a second active layer 511 is arranged on The first interlayer insulating layer 510 is located on a side away from the second metal layer 509, the third gate insulating layer 512 is located on a side away from the first interlayer insulating layer 510 of the second active layer 511, the third metal layer 513 is located on a side away from the second active layer 511, the second interlayer insulating layer 514 is located on a side away from the third metal layer 513 of the third gate insulating layer 512, the first source and drain layer 515 is located on a side away from the second interlayer insulating layer 514 of the third metal layer 513, and the first planarizing layer 516 is located on a side away from the first source and drain layer 515 of the second interlayer insulating layer 514, the second source-drain electrode layer 517 is arranged on the side of the first planarization layer 516 away from the first source-drain electrode layer 515, the second planarization layer 518 is arranged on the side of the second source-drain electrode layer 517 away from the first planarization layer 516, the third source-drain electrode layer 519 is arranged on the side of the second planarization layer 518 away from the second source-drain electrode layer 517, the third planarization layer 520 is arranged on the side of the third source-drain electrode layer 519 away from the second planarization layer 518, the pixel electrode layer 521 is arranged on the side of the third planarization layer 520 away from the third source-drain electrode layer 519, and the pixel definition layer 522 is arranged on the side of the pixel electrode layer 521 away from the third planarization layer 520.

[0117] Specifically, the base substrate 501 supports the various layers provided on the base substrate 501. When the display panel 2 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 2 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate or a transparent base substrate can be used.

[0118] Specifically, the base substrate 501 is used to support the various film layers provided on the base substrate 501. The base substrate 501 can be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 501 can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0119] Specifically, the base substrate 501 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer that are stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0120] Specifically, the thin film transistors in the display panel can be of etch barrier type, back channel etch type, or divided into bottom gate thin film transistors, top gate thin film transistors and other structures according to the position of the gate and the active layer, or divided into N-type thin film transistors and P-type thin film transistors according to the performance of the thin film transistors.

[0121] Specifically, the above embodiments describe the display panel in the embodiments of the present application from different perspectives. When there is no conflict between the embodiments, the embodiments can be combined to achieve better technical effects.

[0122] Meanwhile, embodiments of the present application provide a display device comprising a display panel as described in any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0123] According to the above embodiments, it can be seen that:

[0124] Embodiments of the present application provide a display panel and a display device. The display panel includes a display area and a drive circuit area disposed on at least one side of the display area. The display panel includes multiple clock signal lines and low-potential signal lines. The clock signal lines are disposed in the drive circuit area and extend along a first direction. The low-potential signal lines are disposed within the drive circuit area, and orthographic projections of the multiple clock signal lines on the low-potential signal lines are located within the low-potential signal lines. The low-potential signal lines are provided with multiple through-holes. The through-hole array is formed into multiple repeating units. Within the repeating units, the number of through-holes in each column is the same. For any two clock signal lines, the overlapping area between one clock signal line and all corresponding through-holes within a repeating unit is equal to the overlapping area between the other clock signal line and all corresponding through-holes within the repeating unit. The overlapping area between any clock signal line and the corresponding through-holes within a repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the through-hole in the first direction, and the number of through-holes in a column within the repeating unit. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The present application makes the overlapping area between one clock signal line and all corresponding through-holes in a repeating unit equal to the overlapping area between the other clock signal line and all corresponding through-holes in a repeating unit among any two clock signal lines, and the overlapping area between any clock signal line and the through-holes in a repeating unit is equal to the product of the width of the clock signal line, the width of the through-hole and the number of through-holes in a column in a repeating unit. When the position of the through-hole shifts, the overlapping area between any clock signal line and the through-hole remains unchanged, and the overlapping areas between each clock signal line and the through-hole are equal, so that the parasitic capacitance of each clock signal line is similar or even equal, thereby avoiding different signal delays of adjacent clock signal lines and avoiding changes in signal delay caused by changes in impedance of the clock signal line, so that the display panel can display normally.

[0125] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, which includes a display area and a driving circuit area disposed on at least one side of the display area, and the display panel includes: A plurality of clock signal lines are disposed in the driving circuit region, and the plurality of clock signal lines extend along a first direction; A low-potential signal line is disposed in the driving circuit region, and the positive projections of the plurality of clock signal lines on the low-potential signal line are located within the low-potential signal line; Wherein, a plurality of through holes are formed in the low-potential signal line, and the through holes are arranged in an array to form a plurality of repeating units. In the repeating unit, the number of through holes in each column is the same. Among any two of the clock signal lines, the overlapping area between one of the clock signal lines and all the corresponding through holes in a repeating unit is equal to the overlapping area between the other clock signal line and all the corresponding through holes in a repeating unit, and the overlapping area between any one of the clock signal lines and the corresponding through holes in a repeating unit is equal to the product of the width of the clock signal line in a second direction, the length of the through hole in the first direction, and the number of through holes in a column in a repeating unit; the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

2. The display panel according to claim 1, wherein, Each column of the through holes is arranged along the first direction, and there is a spacing between adjacent two rows of the through holes in the first direction.

3. The display panel according to claim 1, wherein, The number of columns of the through holes is equal to the number of the clock signal lines. Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. The through holes are symmetrically arranged about the center line of the clock signal line, and the spacing between the end of the through hole corresponding to one clock signal line close to the other clock signal line and the other clock signal line is greater than or equal to the maximum offset of the through hole, and the width by which the through hole exceeds the width of the clock signal line is greater than or equal to the maximum offset of the through hole.

4. The display panel according to claim 3, wherein, The width of the through hole is equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines.

5. The display panel according to claim 3, wherein, The spacing between adjacent clock signal lines is greater than the sum of half of the maximum offset of the through hole and the width of the part by which the through hole exceeds the clock signal line.

6. The display panel according to claim 1, wherein, Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. In the repeating unit, the minimum spacings between the two ends of the through hole and the corresponding clock signal line are not equal, and among any two clock signal lines, the minimum spacing between one end of each through hole and the corresponding clock signal line is equal, and the minimum spacing between the other end of each through hole and the corresponding clock signal line is equal.

7. The display panel according to claim 6, wherein, Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. One end of the through hole corresponding to one clock signal line is aligned with one end of the clock signal line, and the other end of the through hole is aligned with one end of the other clock signal line.

8. The display panel according to claim 6, wherein, The minimum spacing between the left end of the through hole and the corresponding clock signal line is greater than the minimum spacing between the right end of the through hole and the corresponding clock signal line; or the minimum spacing between the left end of the through hole and the corresponding clock signal line is less than the minimum spacing between the right end of the through hole and the corresponding clock signal line.

9. The display panel according to claim 1, wherein, The through holes include first through holes corresponding to two adjacent clock signal lines and second through holes corresponding to one clock signal line. Along a first direction, in two adjacent columns of the through holes, one end of one column of the through holes close to the other column of the through holes and one end of the other column of through holes are on the same straight line.

10. The display panel according to claim 9, wherein, The first through holes are symmetrically arranged with respect to the center line of the part of the low-potential signal line located between two adjacent clock signal lines, and the width of the part of the second through holes extending beyond the clock signal lines is greater than the maximum offset of the through holes.

11. The display panel according to claim 10, wherein, One end of the through hole corresponding to one clock signal line and one end of the through hole corresponding to the other clock signal line are respectively on the center lines of the two clock signal lines.

12. The display panel according to claim 9, wherein, Among the first through holes and the second through holes corresponding to the same clock signal line, the overlapping area of one second through hole and the corresponding clock signal line is smaller than the overlapping area of one first through hole and the corresponding clock signal line, and the overlapping area of the other second through hole and the corresponding clock signal line is greater than the overlapping area of the other first through hole and the corresponding clock signal line, and the overlapping areas of any first through hole and the two adjacent corresponding clock signal lines are not equal.

13. The display panel according to claim 9, wherein, The display panel includes two groups of first scanning driving units arranged symmetrically. Each group of first scanning driving units includes four clock signal lines. The through holes include two columns of second through holes and three columns of first through holes, and the three columns of first through holes are located between the two columns of second through holes.

14. A display device, which includes a display panel, the display panel includes a display area and a driving circuit area disposed on at least one side of the display area, and the display panel includes: A plurality of clock signal lines are arranged in the driving circuit region, and the plurality of clock signal lines extend along a first direction; Low-potential signal lines are arranged in the driving circuit region, and the orthographic projections of the plurality of clock signal lines on the low-potential signal lines are located within the low-potential signal lines; Among them, a plurality of through holes are formed in the low-potential signal line, and the through holes are arranged in an array to form a plurality of repeating units. In each repeating unit, the number of through holes in each column is the same. Among any two clock signal lines, the overlapping area of one clock signal line and all the corresponding through holes in one repeating unit is equal to the overlapping area of the other clock signal line and all the corresponding through holes in one repeating unit, and the overlapping area of any clock signal line and the corresponding through holes in one repeating unit is equal to the product of the width of the clock signal line in a second direction, the length of the through hole in the first direction, and the number of through holes in one column in one repeating unit; the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

15. The display device according to claim 14, wherein, Each column of the through holes is arranged along the first direction, and there is a spacing between two adjacent rows of the through holes in the first direction.

16. The display device according to claim 14, wherein, The number of columns of the through holes is equal to the number of the clock signal lines. Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. The through holes are arranged symmetrically about the center line of the clock signal line. And the distance between the end of the through hole corresponding to one clock signal line and the other clock signal line, which is closer to the other clock signal line, is greater than or equal to the maximum offset of the through hole. The width by which the through hole extends beyond the clock signal line is greater than or equal to the maximum offset of the through hole.

17. The display device according to claim 16, wherein, The width of the through hole is equal to the sum of the width of the clock signal line and the distance between adjacent clock signal lines.

18. The display device according to claim 16, wherein,The distance between adjacent clock signal lines is greater than the sum of the maximum offset of the through hole and half of the width of the part by which the through hole extends beyond the clock signal line.

19. The display device according to claim 14, wherein, Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. Within the repeating unit, the minimum distances between the two ends of the through hole and the corresponding clock signal line are not equal. And among any two clock signal lines, the minimum distance between one end of each through hole and the corresponding clock signal line is equal, and the minimum distance between the other end of each through hole and the corresponding clock signal line is equal.

20. The display device according to claim 19, wherein, Each column of the through holes is arranged in one-to-one correspondence with each clock signal line. One end of the through hole corresponding to one clock signal line is aligned with one end of the clock signal line, and the other end of the through hole is aligned with one end of the other clock signal line.

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