Semiconductor device, manufacturing method therefor, and electronic apparatus

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic apparatus. The semiconductor device comprises at least one transistor. The transistor comprises a first source-drain, a second source-drain, a channel region and a gate structure. The channel region is located between the first source-drain and the second source-drain. The gate structure comprises a gate dielectric layer in contact with the channel region, a gate conductive layer and a first threshold voltage regulation layer between the gate dielectric layer and the gate conductive layer, wherein the first threshold voltage regulation layer is used to regulate the threshold voltage of the transistor. The embodiments of the present disclosure can improve the electrical performance of the semiconductor device.

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 11, 2023, with application number 202311698246.6 and application name “Semiconductor device and manufacturing method thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0003] As the integration density of memories develops toward a higher direction, higher requirements are placed on the arrangement of transistors in the array structure of the memories and the size of the transistors.

[0004] Currently, the structure of the memory needs further improvement.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device.

[0007] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0008] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, comprising at least one transistor, wherein the transistor comprises: a first source and drain, a second source and drain, a channel region, and a gate structure; the channel region is located between the first source and drain and the second source and drain; the gate structure comprises a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0009] In some embodiments, the gate structure further includes a second threshold voltage adjustment layer located between the first threshold voltage adjustment layer and the gate conductive layer; wherein a work function of the second threshold voltage adjustment layer is smaller than a work function of the first threshold voltage adjustment layer.

[0010] In some embodiments, each of the transistors includes a transistor column, and the transistor column includes the first source and drain, the channel region, and the second source and drain in sequence along the extension direction; the gate structure covers at least one sidewall of the transistor column.

[0011] In some embodiments, the semiconductor device includes a plurality of transistors arranged in an array along a first direction and a second direction, each of the transistors including a transistor column extending along a third direction; wherein any two of the first direction, the second direction and the third direction are perpendicular to each other; the semiconductor device also includes: a plurality of word lines extending along the first direction, and the word lines are connected to the gate structures of the plurality of transistors arranged along the first direction; a plurality of bit lines extending along the second direction, and the bit lines are connected to a plurality of second sources and drains arranged along the second direction; a plurality of storage capacitors, and the storage capacitors are connected to the first source and drain.

[0012] In some embodiments, the work function of the first threshold voltage adjustment layer ranges from 4.6 eV to 6.9 eV.

[0013] In some embodiments, the thickness of the first threshold voltage adjustment layer ranges from 0.25 nm to 4 nm.

[0014] In some embodiments, the transistor is a junctionless field effect transistor or a P-type transistor.

[0015] In some embodiments, the first threshold voltage adjustment layer includes molybdenum trioxide; and / or, the second threshold voltage adjustment layer includes molybdenum nitride; and / or, the gate conductive layer includes molybdenum.

[0016] In some embodiments, the first threshold voltage adjustment layer is molybdenum trioxide; and the gate conductive layer is molybdenum.

[0017] In some embodiments, the gate structure covers the four side walls of the transistor column to form a full-surround gate transistor, wherein the gate dielectric layer surrounds the channel region of the transistor column, the first threshold voltage adjustment layer surrounds the gate dielectric layer, the second threshold voltage adjustment layer surrounds the first threshold voltage adjustment layer, and the gate conductive layer surrounds the second threshold voltage adjustment layer.

[0018] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes at least one transistor, and the method includes: providing at least one transistor column; the transistor column includes a first source and drain, a channel region, and a second source and drain in sequence along an extension direction; forming a gate dielectric layer covering at least one side wall of the transistor column; forming a first metal material layer covering the gate dielectric layer; oxidizing the first metal material layer to form a first threshold voltage adjustment layer; forming a gate conductive layer covering the first threshold voltage adjustment layer; wherein the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0019] In some embodiments, before forming the gate conductive layer covering the first threshold voltage adjustment layer, the method also includes: forming a second threshold voltage adjustment layer covering the first threshold voltage adjustment layer; wherein the work function of the second threshold voltage adjustment layer is smaller than the work function of the first threshold voltage adjustment layer.

[0020] In some embodiments, the material of the second threshold voltage adjustment layer is molybdenum nitride.

[0021] In some embodiments, the first metal material layer is molybdenum, and the first threshold voltage adjustment layer is molybdenum trioxide, wherein the step of oxidizing the first metal material layer to form the first threshold voltage adjustment layer includes: using oxygen or ozone to oxidize the molybdenum multiple times to obtain the molybdenum trioxide.

[0022] In some embodiments, the thickness of the first threshold voltage adjustment layer ranges from 0.25 nm to 4 nm.

[0023] In some embodiments, the step of forming the gate conductive layer includes: using the molybdenum nitride as a seed layer and growing molybdenum as the gate conductive layer on the second threshold voltage adjustment layer through an ALD process.

[0024] In some embodiments, the transistor is a junctionless field effect transistor or a P-type transistor.

[0025] In some embodiments, before the step of forming a gate dielectric layer covering at least one side wall of the transistor column, the method further includes: forming a first isolation layer and a second isolation layer, the second isolation layer being located between adjacent transistor columns, and the first isolation layer penetrating the second isolation layer between adjacent transistor columns along a first direction.

[0026] In some embodiments, the gate structure covers the four side walls of the transistor column to form a full-surround gate transistor, wherein the gate dielectric layer surrounds the channel region of the transistor column, the first threshold voltage adjustment layer surrounds the gate dielectric layer, the second threshold voltage adjustment layer surrounds the first threshold voltage adjustment layer, and the gate conductive layer surrounds the second threshold voltage adjustment layer.

[0027] In a second aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processing device; and a semiconductor device electrically connected to the processing device, the semiconductor device comprising at least one transistor, the transistor comprising: a first source and drain, a second source and drain, a channel region and a gate structure; the channel region is located between the first source and drain and the second source and drain; the gate structure comprises a gate dielectric layer, a gate conductive layer and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0028] The embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device includes at least one transistor, and the transistor includes: a first source and drain, a second source and drain, a channel region, and a gate structure; the channel region is located between the first source and drain and the second source and drain; the gate structure includes a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor. In the embodiments of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer, and the first threshold voltage adjustment layer with a high work function is used to increase the difference between the work function of the gate structure and the channel region material, thereby increasing the threshold voltage of the transistor, and further improving the electrical performance of the semiconductor device by adjusting the threshold voltage of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic cross-sectional view of a semiconductor device provided by an example;

[0030] FIG2 is a schematic cross-sectional view of a semiconductor device according to another embodiment;

[0031] FIG3 is a schematic cross-sectional view of a semiconductor device according to another embodiment;

[0032] FIG4 is a schematic top view of a semiconductor device according to another embodiment;

[0033] FIG5 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0034] 6A to 6E are schematic top-view structural diagrams of the semiconductor device provided by an embodiment of the present disclosure during the manufacturing process.

[0035] FIG7 is a schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure.

[0036] FIG8 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0038] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0039] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0040] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0044] As dynamic random access memory (DRAM) integration density continues to increase, higher requirements are placed on the arrangement and size of transistors within the DRAM array structure. Gate-all-around (GAA) transistors, used in DRAM, enable smaller sizes, contributing to higher DRAM integration density.

[0045] However, the threshold voltage of the all-around gate transistor is relatively low. Therefore, there is a need to further improve the structure of the transistor in the memory to adjust the threshold voltage of the transistor.

[0046] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0047] Referring to FIG1 , FIG1 is a schematic cross-sectional view of a semiconductor device provided in an example. As shown in FIG1 , an embodiment of the present disclosure provides a semiconductor device 100, which includes at least one transistor 102 (shown as a dotted box in FIG1 ). The transistor 102 includes: a first source / drain 106, a second source / drain 108, and a channel region 110 disposed in a substrate 104; wherein the channel region 110 is located between the first source / drain 106 and the second source / drain 108; a gate structure 112 disposed on the substrate 104, the gate structure 112 including a gate dielectric layer 114, a gate conductive layer 116, and a first threshold voltage adjustment layer 118 located between the gate dielectric layer 114 and the gate conductive layer 116; the gate dielectric layer 114 is in contact with the channel region 110; wherein the first threshold voltage adjustment layer 118 is used to adjust the threshold voltage of the transistor 102.

[0048] In the embodiment of the present disclosure, a first threshold voltage adjustment layer 118 is provided between the gate dielectric layer 114 and the gate conductive layer 116. By increasing the work function of the first threshold voltage adjustment layer 118, the difference between the work functions of the gate structure 112 and the channel region 110 material is increased, thereby increasing the threshold voltage of the transistor 102. That is, the purpose of using the first threshold voltage adjustment layer 118 to adjust the threshold voltage of the transistor 102 to improve the electrical performance of the semiconductor device 100 is achieved.

[0049] Here, the substrate 104 can be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, and a silicon-germanium substrate, etc.

[0050] For example, the substrate 104 may be doped to form a first source / drain 106 and a second source / drain 108 , wherein the first source / drain 106 and the second source / drain 108 are doped regions. For example, the substrate 104 may be doped to form a channel region 110 .

[0051] In some embodiments, when the first source / drain 106 serves as the source of the transistor 102 , the second source / drain 108 serves as the drain of the transistor 102 . In other embodiments, when the first source / drain 106 serves as the drain of the transistor 102 , the second source / drain 108 serves as the source of the transistor 102 .

[0052] In some embodiments, the dopant ion type in the doping region may be different from the dopant ion type in the channel region. For example, for a P-type metal-oxide-semiconductor field effect transistor (MOSFET), the dopant ions in the doping region are N-type ions, and the dopant ions in the channel region are P-type ions. The N-type ions may be, for example, arsenic ions, phosphorus ions, or antimony ions; and the P-type ions may be, for example, boron ions, indium ions, or gallium ions.

[0053] In some other embodiments, the doping ion type in the doping region may be the same as the doping ion type in the channel region. For example, a junctionless field effect transistor (JLT) may be formed.

[0054] Here, the material of the gate dielectric layer 114 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0055] For example, silicon oxide may be formed on a substrate whose material is silicon through a thermal oxidation process.

[0056] In some embodiments, the process of forming the gate dielectric layer 114 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0057] Here, the material of the gate conductive layer 116 may include, but is not limited to, metal materials and semiconductor materials. The metal materials may be, for example, gold, aluminum, copper, tungsten, or molybdenum; the semiconductor materials may be, for example, polysilicon.

[0058] In some embodiments, the process of forming the gate conductive layer 116 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0059] In some embodiments, the work function of the first threshold voltage adjusting layer 118 ranges from 4.6 eV to 6.9 eV. Alternatively, the work function of the first threshold voltage adjusting layer 118 ranges from 6 eV to 6.9 eV.

[0060] In the embodiment of the present disclosure, a first threshold voltage adjustment layer 118 is provided between the gate dielectric layer 114 and the gate conductive layer 116 in the gate structure 112. By increasing the work function of the first threshold voltage adjustment layer 118, the difference between the work functions of the gate structure 112 and the channel region 110 material is increased, thereby increasing the threshold voltage of the transistor 102.

[0061] In some embodiments, the material of the first threshold voltage adjustment layer 118 may be molybdenum trioxide (MoO 3 ).

[0062] Here, molybdenum trioxide is an indirect bandgap material with a band gap of approximately 3.0 eV. It is also an excellent semiconductor oxide material with a high work function and is the most stable oxide of molybdenum. Specifically, the work function of molybdenum trioxide can reach 6.9 eV.

[0063] For example, molybdenum can be formed on the gate dielectric layer by an ALD process, and molybdenum trioxide can be obtained by performing multiple oxidation treatments on the molybdenum using oxygen (O2) or ozone (O3).

[0064] In some embodiments, the thickness of the first threshold voltage adjusting layer 118 is in a range of 0.25 nm to 4 nm.

[0065] Here, in the case where the material of the first threshold voltage adjusting layer 118 is the same, the thickness is one of the factors that affect the work function of the first threshold voltage adjusting layer 118 .

[0066] Taking molybdenum trioxide as an example, as the thickness of the first threshold voltage adjustment layer 118 increases, the work function of the first threshold voltage adjustment layer 118 first increases and then remains substantially unchanged. When the thickness of the first threshold voltage adjustment layer 118 is greater than 0.25 nm, the work function of the first threshold voltage adjustment layer 118 is greater than 6.0 eV. However, as the thickness of the first threshold voltage adjustment layer 118 increases, the size of the semiconductor device 100 also increases, which is not conducive to improving the integration density of the semiconductor device 100.

[0067] In the above embodiment, by limiting the thickness of the first threshold voltage adjusting layer 118 to the above range, both high work function and high integration density can be achieved.

[0068] In some embodiments, transistor 102 includes a junctionless field effect transistor and a P-type transistor.

[0069] Here, since the threshold voltages of the junctionless vertical channel transistor (VCT) and the P-type transistor are relatively low, it is more necessary to improve the structures of the junctionless vertical channel transistor and the P-type transistor to increase the threshold voltages of the junctionless vertical channel transistor and the P-type transistor.

[0070] Referring to FIG. 2 , which is a schematic cross-sectional view of another exemplary semiconductor device, in some embodiments, the gate structure 112 further includes a second threshold voltage adjustment layer 120 located between the first threshold voltage adjustment layer 118 and the gate conductive layer 116 ; the work function of the second threshold voltage adjustment layer 120 is less than that of the first threshold voltage adjustment layer 118 .

[0071] In the embodiment of the present disclosure, a second threshold voltage adjustment layer 120 is further provided between the first threshold voltage adjustment layer 118 and the gate conductive layer 116 in the gate structure 112. By increasing the work function of the second threshold voltage adjustment layer 120 and utilizing the high work functions of the first threshold voltage adjustment layer 118 and the second threshold voltage adjustment layer 120, the difference between the work functions of the gate structure 112 and the channel region 110 materials is increased, thereby increasing the threshold voltage of the transistor 102.

[0072] In addition, the work function of the second threshold voltage adjustment layer 120 is smaller than the work function of the first threshold voltage adjustment layer 118 . The second threshold voltage adjustment layer 120 can not only increase the threshold voltage of the transistor 102 but also reduce the resistance of the gate structure 112 .

[0073] In some embodiments, the material of the second threshold voltage adjusting layer 120 may be molybdenum nitride.

[0074] Here, the work function of molybdenum nitride varies depending on the nitrogen content. Compared to MoN, Mo2N has a lower nitrogen content and a smaller work function; the work function of Mo2N is approximately 4.47 eV, while the work function of MoN is greater than 5 eV.

[0075] In some embodiments, the process of forming the second threshold voltage adjusting layer 120 may include, but is not limited to, ALD.

[0076] In some embodiments, the first threshold voltage adjustment layer 118 includes molybdenum trioxide; and / or the second threshold voltage adjustment layer 120 includes molybdenum nitride; and / or the gate conductive layer 116 includes molybdenum.

[0077] For example, molybdenum can be formed on the gate dielectric layer 114 through an ALD process, and the molybdenum can be oxidized to form molybdenum trioxide as the first threshold voltage adjustment layer 118; molybdenum nitride can be formed on the first threshold voltage adjustment layer 118 through an ALD process, and the molybdenum nitride can be used as the second threshold voltage adjustment layer 120; or molybdenum nitride can be used as a seed layer, and molybdenum can be grown on the second threshold voltage adjustment layer 120 through an ALD process as the gate conductive layer 116.

[0078] As previously mentioned, the gate structure 112 provided in the embodiments of the present disclosure is particularly useful for vertical channel transistors and P-type transistors. Referring to Figures 3 and 4 , Figure 3 is a schematic cross-sectional view of a semiconductor device according to another example, and Figure 4 is a schematic top view of a semiconductor device according to another example. The following detailed description will be given, using Figures 3 and 4 as an example, using a vertical channel transistor 202 as the semiconductor device 200.

[0079] Before introducing the vertical channel transistor, the various directions of the semiconductor device are defined. The extension direction of the transistor column 204 in the vertical channel transistor 202 is defined as the third direction, namely the Z direction. In a plane perpendicular to the third direction Z, a first direction and a second direction intersecting each other are defined, namely the X direction and the Y direction. Alternatively, the semiconductor device 200 includes a plurality of transistors 202 arranged in an array, and the directions in which the plurality of transistors 202 are arranged are defined as the first direction and the second direction intersecting each other, namely the X direction and the Y direction. In some embodiments, any two of the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0080] In some embodiments, the semiconductor device 200 includes a plurality of transistors 202 arranged in an array along a first direction (ie, X direction) and a second direction (ie, Y direction), and each transistor 202 includes a transistor pillar 204 extending along a third direction (ie, Z direction).

[0081] Figure 3 illustrates a YZ cross-sectional view of the semiconductor device, and Figure 4 illustrates an XY top view of the semiconductor device. As shown in Figures 3 and 4, in some embodiments, the semiconductor device 200 includes at least one transistor 202 (indicated by the dashed circle in Figure 4). Each transistor 202 includes a transistor pillar 204. The transistor pillar 204 includes, in sequence along its extension direction, a first source and drain 206, a channel region 210, and a second source and drain 208. A gate structure 212 covers at least one sidewall of the transistor pillar 204.

[0082] In some embodiments, the orthographic projection of the transistor pillar on the XY plane can be a quadrilateral, and the transistor pillar includes four sidewalls, wherein two sidewalls are arranged opposite to each other along the X direction, and the other two sidewalls are arranged opposite to each other along the Y direction. In other embodiments, the orthographic projection of the transistor pillar on the XY plane can also be a circle, an ellipse, etc. The present disclosure does not specifically limit the shape of the orthographic projection of the transistor pillar on the XY plane.

[0083] In some embodiments, the gate structure covers one sidewall of the transistor pillar, ie, forming a single-gate transistor.

[0084] In some embodiments, the gate structure covers both sidewalls of the transistor pillar, ie, forming a dual-gate transistor.

[0085] In some embodiments, the gate structure covers three sidewalls of the transistor pillar, ie, forming a tri-gate transistor.

[0086] In some embodiments, the gate structure covers the four sidewalls of the transistor pillar, forming a gate-all-around transistor. Figures 3 and 4 illustrate a gate-all-around transistor.

[0087] Here, the gate structure 212 includes a gate dielectric layer 214, a first threshold voltage adjustment layer 218, a second threshold voltage adjustment layer 220 and a gate conductive layer 216 in sequence; wherein, the gate dielectric layer 214 surrounds the channel region 210 of the transistor column 204, the first threshold voltage adjustment layer 218 surrounds the gate dielectric layer 214, the second threshold voltage adjustment layer 220 surrounds the first threshold voltage adjustment layer 218, and the gate conductive layer 216 surrounds the second threshold voltage adjustment layer 220.

[0088] As shown in FIG4 and FIG7 , in some embodiments, the semiconductor device 200 further includes: a plurality of word lines 222 extending along the X direction (as shown by the dotted-dash box in FIG4 ), and the word lines 222 are connected to the gate structures 212 of the plurality of transistors 202 arranged along the X direction; a plurality of bit lines 230 extending along the Y direction, and the bit lines are connected to the plurality of second sources and drains 208 arranged along the Y direction; and a plurality of storage capacitors 240, and the storage capacitors 240 are connected to the first sources and drains 206.

[0089] Here, the semiconductor device includes a plurality of word lines 222 extending along the X direction and sequentially arranged along the Y direction, and a plurality of bit lines 230 extending along the Y direction and sequentially arranged along the X direction. Adjacent word lines 222 are isolated by a first isolation layer 224 .

[0090] In some embodiments, when the transistor column includes a first source and drain 206, a channel region 210, and a second source and drain 208 in sequence from top to bottom along the extension direction, a bit line connected to the first source and drain 206 can be formed on the front side of the substrate, the back side of the substrate is thinned to expose the second source and drain 208, and a storage capacitor connected to the second source and drain 208 is formed on the back side of the substrate.

[0091] In other embodiments, for example, as shown in Figure 7, when the transistor column includes a first source and drain 206, a channel region 210, and a second source and drain 208 from top to bottom along the extension direction, a buried bit line connected to the second source and drain 208 can be formed on the front side of the substrate, and a storage capacitor connected to the first source and drain 206 can be formed on the front side of the substrate.

[0092] In other embodiments, when the transistor column includes a first source and drain 206, a channel region 210, and a second source and drain 208 from top to bottom along the extension direction, a storage capacitor connected to the first source and drain 206 can be formed on the front side of the substrate, the back side of the substrate is thinned to expose the second source and drain 208, and a bit line connected to the second source and drain 208 is formed on the back side of the substrate.

[0093] In some embodiments, the material of the bit line may include, but is not limited to, a metal, a metal compound, or an alloy. The metal may be, for example, copper, aluminum, tungsten, gold, or silver; the metal compound may be, for example, tantalum nitride or titanium nitride; and the alloy may be an alloy formed by at least two of the following metal elements: copper, aluminum, tungsten, gold, or silver.

[0094] Referring to FIG5 , FIG5 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG5 , an embodiment of the present disclosure further provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes at least one transistor, and the method includes:

[0095] Step S501: providing at least one transistor column; the transistor column sequentially comprises a first source and drain electrode, a channel region, and a second source and drain electrode along an extension direction;

[0096] Step S502: forming a gate dielectric layer covering at least one sidewall of the transistor column;

[0097] Step S503: forming a first metal material layer covering the gate dielectric layer;

[0098] Step S504: performing oxidation treatment on the first metal material layer to form a first threshold voltage adjustment layer;

[0099] Step S505: forming a gate conductive layer covering the first threshold voltage adjustment layer; wherein the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0100] In the embodiment of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer. By increasing the work function of the first threshold voltage adjustment layer, the difference between the work functions of the gate structure and the channel region material is increased, thereby increasing the threshold voltage of the transistor, that is, achieving the purpose of using the first threshold voltage adjustment layer to adjust the threshold voltage of the transistor to improve the electrical performance of the semiconductor device.

[0101] 6A to 6E are top views of the semiconductor device during the manufacturing process according to an embodiment of the present disclosure. The manufacturing process of the semiconductor device will be described in detail below in conjunction with FIG5 and FIG6A to 6E.

[0102] In the embodiment of the present disclosure, in step S501 , at least one transistor column 204 is provided; the transistor column 204 includes a first source and drain 206 , a channel region 210 , and a second source and drain 208 in sequence along the extension direction.

[0103] As shown in FIG. 6A , transistor pillars 204 arranged in an array along the X direction and the Y direction are formed on a substrate.

[0104] Exemplarily, forming the transistor pillars 204 may include: providing a substrate; etching the substrate to form a plurality of first grooves extending along the Y direction and a plurality of semiconductor strips 204 extending along the Y direction, and filling the first grooves with an isolation material; etching the substrate to form a plurality of second grooves extending along the X direction and a plurality of semiconductor pillars 204 (i.e., transistor pillars) arranged in an array along the X and Y directions, and filling the second grooves with an isolation material.

[0105] In some embodiments, after the semiconductor pillar 204 is formed, the semiconductor pillar 204 may be doped to form a doped region (ie, the first source and drain 206 and the second source and drain 208 ) and a channel region 210 .

[0106] For example, after forming the semiconductor pillars 204, the semiconductor pillars 204 may be doped by ion implantation or thermal diffusion. Alternatively, after doping the substrate, the substrate may be etched to form a plurality of semiconductor pillars 204 arranged in an array, such that the semiconductor pillars 204 have a channel region 210 and a first source / drain 206 and a second source / drain 208 located on both sides of the channel region 210.

[0107] As shown in FIG6A , in some embodiments, before forming the gate dielectric layer 214 , the method further includes: forming a first isolation layer 224 and a second isolation layer 226 , wherein the second isolation layer 226 is located between adjacent transistor pillars 204 , and the first isolation layer 224 penetrates the second isolation layer 226 between adjacent transistor pillars 204 along the X direction; wherein the first isolation layer 224 is used to isolate adjacent word lines formed subsequently to prevent electrical interference between adjacent conductive structures.

[0108] In some embodiments, the material of the first isolation layer 224 and the second isolation layer 226 may include, but is not limited to, silicon nitride.

[0109] In the embodiment of the present disclosure, in step S502 , a gate dielectric layer 214 is formed to cover at least one sidewall of the transistor pillar 204 .

[0110] As shown in FIG6B , the second isolation layer 226 is removed to form a word line groove 230 (shown as a dotted box in FIG6B ) that exposes the sidewall of the transistor pillar 204 ; and a gate dielectric layer 214 is formed that surrounds the sidewall of the transistor pillar 204 and covers the sidewall of the word line groove 230 .

[0111] For example, silicon oxide may be formed as the gate dielectric layer 214 by an ALD process or an in-situ steam growth (ISSG) process.

[0112] In the embodiment of the present disclosure, in step S503 , a first metal material layer 228 is formed to cover the gate dielectric layer 214 .

[0113] As shown in FIG. 6B , a first metal material layer 228 is formed surrounding the gate dielectric layer 214 on the sidewalls of the transistor pillar 204 and covering the sidewalls of the word line groove 230 .

[0114] For example, molybdenum may be formed as the first metal material layer 228 by an ALD process.

[0115] In the embodiment of the present disclosure, in step S504 , the first metal material layer 228 is oxidized to form the first threshold voltage adjustment layer 218 .

[0116] 6C , the first metal material layer 228 is oxidized to form a first threshold voltage adjustment layer 218 , which surrounds the gate dielectric layer 214 on the sidewalls of the transistor pillar 204 and covers the sidewalls of the word line groove 230 .

[0117] For example, the first metal material layer 228, such as molybdenum, can be formed by an ALD process. The first metal material layer 228 can be oxidized using oxygen or ozone to form the first threshold voltage adjustment layer 218, such as molybdenum trioxide. The first metal material layer 228 can be formed multiple times and oxidized multiple times to form the first threshold voltage adjustment layer 218.

[0118] In some embodiments, before step S505 , the method further includes: forming a second threshold voltage adjustment layer 220 covering the first threshold voltage adjustment layer 218 ; wherein a work function of the second threshold voltage adjustment layer 220 is smaller than a work function of the first threshold voltage adjustment layer 218 .

[0119] As shown in FIG. 6D , a second threshold voltage adjusting layer 220 is formed to surround the first threshold voltage adjusting layer 218 on the sidewalls of the transistor pillar 204 and cover the sidewalls of the word line groove 230 .

[0120] In the embodiment of the present disclosure, in step S505, a gate conductive layer 216 is formed to cover the first threshold voltage adjustment layer 218; wherein the first threshold voltage adjustment layer 218 is used to adjust the threshold voltage of the transistor 202. Here, after forming the second threshold voltage adjustment layer 220, the gate conductive layer 216 is formed to cover the second threshold voltage adjustment layer 220.

[0121] As shown in Figure 6E, a second threshold voltage adjustment layer 220 is formed on the side wall of the transistor column 204 and a gate conductive layer 216 is formed to cover the side wall of the word line groove 230; wherein, the gate dielectric layer 214 surrounding the side wall of the transistor column 204, the first threshold voltage adjustment layer 218, the second threshold voltage adjustment layer 220 and the gate conductive layer 216 together form a gate structure 212.

[0122] For example, the second threshold voltage adjustment layer 220 , such as molybdenum nitride, may be formed by an ALD process; and the gate conductive layer 216 , such as molybdenum, may be grown using molybdenum nitride as a seed layer.

[0123] As shown in Figures 6E and 7, in the embodiment of the present disclosure, the method further includes: forming a plurality of word lines 222 extending along the X direction (as shown in the dotted line box in Figure 6E), and the word lines 222 are connected to the gate structures 212 of the plurality of transistors 202 arranged along the X direction; forming a plurality of bit lines 230 extending along the Y direction, and the bit lines 230 are connected to the plurality of second sources and drains 208 arranged along the Y direction; and forming a plurality of storage capacitors 240, and the storage capacitors 240 are connected to the first sources and drains 206.

[0124] The embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least one transistor, and the transistor includes: a first source and drain, a second source and drain, a channel region, and a gate structure; the channel region is located between the first source and drain and the second source and drain; the gate structure includes a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor. In the embodiment of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer, and the first threshold voltage adjustment layer with a high work function is used to increase the difference between the work function of the gate structure and the channel region material, thereby increasing the threshold voltage of the transistor, and further improving the electrical performance of the semiconductor device by adjusting the threshold voltage of the transistor.

[0125] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0126] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

[0127] FIG8 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Referring to FIG28 , an embodiment of the present disclosure further provides an electronic device 1, comprising a processing device 2 and a storage device 3 electrically connected to the processing device 2, wherein the storage device 3 comprises the semiconductor structure 300 shown in any of the above embodiments. The electronic device 1 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device 1 may be implemented by the following storage device 3: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0128] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device (100, 200), characterized in that: The semiconductor device (100, 200) comprises at least one transistor (102, 202), wherein the transistor (102, 202) comprises: a first source and drain (106, 206), a second source and drain (108, 208), a channel region (110, 210) and a gate structure (112, 212); The channel region (110, 210) is located between the first source and drain (106, 206) and the second source and drain (108, 208); The gate structure (112, 212) comprises a gate dielectric layer (114, 214), a gate conductive layer (116, 216), and a first threshold voltage adjustment layer (118, 218) located between the gate dielectric layer (114, 214) and the gate conductive layer (116, 216); the gate dielectric layer (114, 214) is in contact with the channel region (110, 210); wherein the first threshold voltage adjustment layer (118, 218) is used to adjust the threshold voltage of the transistor (102, 202).

2. The semiconductor device (100, 200) according to claim 1, characterized in that The gate structure (112, 212) further includes a second threshold voltage adjustment layer (120, 220) located between the first threshold voltage adjustment layer (118, 218) and the gate conductive layer (116, 216); wherein the work function of the second threshold voltage adjustment layer (120, 220) is smaller than the work function of the first threshold voltage adjustment layer (118, 218).

3. The semiconductor device (200) according to claim 1 or 2, characterized in that: Each of the transistors (202) comprises a transistor column (204), and the transistor column (204) comprises the first source and drain (206), the channel region (210), and the second source and drain (208) in sequence along the extension direction; The gate structure (212) covers at least one sidewall of the transistor column (204).

4. The semiconductor device (200) according to claim 3, characterized in that: The semiconductor device (200) comprises a plurality of transistors (202) arranged in an array along a first direction (X) and a second direction (Y), each of the transistors (202) comprising a transistor column (204) extending along a third direction (Z); wherein any two of the first direction (X), the second direction (Y) and the third direction (Z) are perpendicular to each other; the semiconductor device (200) further comprises: A plurality of word lines (222) extending along the first direction (X), wherein the word lines (222) are connected to gate structures (212) of a plurality of transistors (202) arranged along the first direction (X); A plurality of bit lines extending along the second direction, wherein the bit lines are connected to a plurality of second source drains (208) arranged along the second direction (Y); A plurality of storage capacitors (240) are provided, and the storage capacitors (240) are connected to the first source and drain (206).

5. The semiconductor device (100, 200) according to claim 1, characterized in that The work function of the first threshold voltage adjustment layer (118, 218) ranges from 4.6 eV to 6.9 eV.

6. The semiconductor device (100, 200) according to claim 1, characterized in that The thickness of the first threshold voltage adjustment layer (118, 218) is in the range of 0.25 nm to 4 nm.

7. The semiconductor device (100, 200) according to claim 1, characterized in that The transistor (102, 202) is a junctionless field effect transistor or a P-type transistor.

8. The semiconductor device (100, 200) according to claim 2, characterized in that The first threshold voltage adjustment layer (118, 218) includes molybdenum trioxide; and / or the second threshold voltage adjustment layer (120, 220) includes molybdenum nitride; and / or the gate conductive layer (116, 216) includes molybdenum.

9. The semiconductor device (100, 200) according to claim 1, characterized in that The first threshold voltage adjustment layer (118, 218) is molybdenum trioxide; and the gate conductive layer (116, 216) is molybdenum.

10. The semiconductor device (200) according to claim 2, characterized in that The gate structure (212) covers the four sidewalls of the transistor column (204) to form a full-surround gate transistor, wherein: The gate dielectric layer (214) surrounds the channel region (210) of the transistor column (204), the first threshold voltage adjustment layer (218) surrounds the gate dielectric layer (214), the second threshold voltage adjustment layer (220) surrounds the first threshold voltage adjustment layer (218), and the gate conductive layer (216) surrounds the second threshold voltage adjustment layer (220).

11. A method for manufacturing a semiconductor device (200), characterized in that: The semiconductor device (200) comprises at least one transistor (202), and the method comprises: Providing at least one transistor column (204); the transistor column (204) sequentially comprises a first source and drain electrode (206), a channel region (210), and a second source and drain electrode (208) along an extension direction; forming a gate dielectric layer (214) covering at least one sidewall of the transistor column (204); forming a first metal material layer (228) covering the gate dielectric layer (214); Performing an oxidation treatment on the first metal material layer (228) to form a first threshold voltage adjustment layer (218); A gate conductive layer (216) is formed to cover the first threshold voltage adjustment layer (218); wherein the first threshold voltage adjustment layer (218) is used to adjust the threshold voltage of the transistor (202).

12. The method for manufacturing a semiconductor device (200) according to claim 11, characterized in that: Before forming a gate conductive layer (216) covering the first threshold voltage adjustment layer (218), the method further comprises: A second threshold voltage adjustment layer (220) is formed to cover the first threshold voltage adjustment layer (218); wherein the work function of the second threshold voltage adjustment layer (220) is smaller than the work function of the first threshold voltage adjustment layer (218).

13. The method for manufacturing a semiconductor device (200) according to claim 12, characterized in that: The material of the second threshold voltage adjustment layer (220) is molybdenum nitride.

14. The method for manufacturing a semiconductor device (200) according to any one of claims 11 to 13, characterized in that: The first metal material layer (228) is molybdenum, and the first threshold voltage adjustment layer (218) is molybdenum trioxide, wherein the step of performing an oxidation treatment on the first metal material layer (228) to form the first threshold voltage adjustment layer (218) comprises: The molybdenum trioxide is obtained by subjecting the molybdenum to multiple oxidation treatments using oxygen or ozone.

15. The method for manufacturing a semiconductor device (200) according to claim 14, characterized in that: The thickness of the first threshold voltage adjustment layer (218) is in the range of 0.25 nm to 4 nm.

16. The method for manufacturing a semiconductor device (200) according to claim 13, characterized in that: The step of forming the gate conductive layer (26) comprises: The molybdenum nitride is used as a seed layer, and molybdenum is grown on the second threshold voltage adjustment layer (220) through an ALD process as a gate conductive layer (216).

17. The method for manufacturing a semiconductor device (200) according to claim 11, characterized in that: The transistor (202) is a junctionless field effect transistor or a P-type transistor.

18. The method for manufacturing a semiconductor device (200) according to claim 11, characterized in that: Before the step of forming a gate dielectric layer (214) covering at least one sidewall of the transistor column (204), the method further comprises: A first isolation layer (224) and a second isolation layer (226) are formed, wherein the second isolation layer (226) is located between adjacent transistor pillars (204), and the first isolation layer (224) penetrates the second isolation layer (226) between adjacent transistor pillars (204) along a first direction (X).

19. The method for manufacturing a semiconductor device (200) according to claim 11 or 18, characterized in that: The gate structure (212) covers the four sidewalls of the transistor column (204) to form a full-surround gate transistor, wherein: The gate dielectric layer (214) surrounds the channel region (210) of the transistor column (204), the first threshold voltage adjustment layer (218) surrounds the gate dielectric layer (214), the second threshold voltage adjustment layer (220) surrounds the first threshold voltage adjustment layer (218), and the gate conductive layer (216) surrounds the second threshold voltage adjustment layer (220).

20. An electronic device (1), characterized in that: include: Processing device (2); as well as A memory device (3) electrically connected to the processing device (2), wherein the memory device (3) comprises the semiconductor device (100, 200) according to any one of claims 1 to 10.

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