Processing method and apparatus for clock stretching in transparent transmission mode of integrated circuit bus

Abstract

A processing method and apparatus for clock stretching in a transparent transmission mode of an integrated circuit bus. The method comprises: acquiring target data transmitted, by means of a first integrated circuit bus, to a slave device by a master device; on the basis of the target data, detecting whether the master device has completed sending one byte of data to the slave device; in response to determining that the master device has completed sending one byte of data to the slave device, determining that the master device will send an acknowledgement character bit to the slave device; and taking over the first integrated circuit bus between the master device and the slave device, disabling the transparent transmission mode between the master device and the slave device, and controlling the master device and / or the slave device.

Description

Method and device for processing clock extension in integrated circuit bus transparent transmission mode

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on December 13, 2023, with application number 202311708718.1 and entitled “Processing Method and Device for Clock Extension in Integrated Circuit Bus Transparent Transmission Mode,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a method and device for processing clock extension in an integrated circuit bus transparent transmission mode. Background Art

[0004] In server machines, integrated circuit bus (IC) signals are typically used by the on-board BMC (Board Management Controller) to access devices such as temperature sensors, fan controllers, backplanes, and PCIe (Peripheral Component Interconnect Express) add-in cards. The BMC manages these devices through polling, acting as the master of the IC bus signals and other devices as slaves. When a slave device becomes busy and unable to immediately respond to the BMC's IC bus access, it actively pulls down the IC bus's serial data line signal to suspend polling. When the slave device exits the busy state, it releases the serial data line signal to respond to IC bus access again. This process is known as IC bus clock stretching.

[0005] Clock stretching for integrated circuit buses can be performed at both the byte and bit levels. Byte-level clock stretching involves pulling the serial data line signal low after a slave device receives a complete byte of data or command, allowing the slave device to process the received data internally. Bit-level clock stretching is primarily used when the serial data line signal rate of the integrated circuit bus supported by the slave device is lower than the serial data line signal rate sent by the master device. In this case, the slave device pulls the serial data line signal low to reduce the actual serial data line signal rate.

[0006] In actual hardware design, when selecting the serial data line signal rate for the master device, the supported rates of all slave devices are comprehensively considered to avoid bit-level clock stretching. A more common approach is byte-level clock stretching. However, byte-level clock stretching can cause short pulses on the serial data line signals—the first serial clock line signal corresponding to the master device and the second serial clock line signal corresponding to the slave device. This violates the communication protocol and can affect normal communication between the master and slave devices.

[0007] Summary of the Invention

[0008] In a first aspect, the present application provides a method for processing clock stretching in an integrated circuit bus transparent transmission mode, which is applied to a complex programmable logic device. The method includes:

[0009] Acquire target data transmitted by the master device to the slave device based on the first integrated circuit bus;

[0010] According to the target data, detect whether the master device has completed sending a byte of data to the slave device;

[0011] In response to determining that the master device has completed sending one byte of data to the slave device, confirming that the master device is about to send an acknowledgement character bit to the slave device; and

[0012] Take over the first integrated circuit bus between the master device and the slave device, turn off the transparent transmission mode between the master device and the slave device, and control the master device and / or the slave device.

[0013] In some embodiments, taking over a first integrated circuit bus between a master device and a slave device, disabling a transparent transmission mode between the master device and the slave device, and controlling the master device and / or the slave device includes:

[0014] controlling the master device to be in a waiting state based on a second integrated circuit bus between the complex programmable logic device and the master device;

[0015] detecting, based on a third integrated circuit bus between the complex programmable logic device and the slave device, whether the slave device enters a clock stretching state, and obtaining a first detection result; and

[0016] The master device and / or the slave device are controlled according to the first detection result.

[0017] In some embodiments, controlling the master device to be in a waiting state based on a second integrated circuit bus between the complex programmable logic device and the master device includes:

[0018] Based on the second integrated circuit bus between the complex programmable logic device and the master device, the master device is controlled to enter a clock stretch state, and a first serial clock line signal corresponding to the master device is pulled low to put the master device in a waiting state.

[0019] In some embodiments, detecting whether the slave device enters a clock stretching state based on a third integrated circuit bus between the complex programmable logic device and the slave device to obtain a first detection result includes:

[0020] Continuously pull up the second serial clock line signal corresponding to the slave device, and send the third serial clock line signal corresponding to the confirmation character bit to the slave device;

[0021] Detecting whether a second serial clock line signal corresponding to the slave device is at a high level, and obtaining a second detection result; and

[0022] According to the second detection result, it is determined whether the slave device enters the clock stretch state to obtain the first detection result.

[0023] In some implementations, determining whether the slave device enters a clock stretch state based on the second detection result to obtain the first detection result includes:

[0024] In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, it is determined that the slave device has not entered the clock stretch state or has exited the clock stretch state, and the first detection result is obtained.

[0025] In some embodiments, the method further comprises:

[0026] In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, it is determined that the slave device enters a clock stretching state, and the first detection result is obtained.

[0027] In some embodiments, controlling the master device and / or the slave device according to the first detection result includes:

[0028] In response to determining that the first detection result indicates that the slave device has entered a clock stretch state, starting a timeout counter; a preset time duration is set in the timeout counter;

[0029] Based on the timeout timer, detecting whether the time for the slave device to enter the clock stretch state exceeds a preset time period, and obtaining a third detection result; and

[0030] The master device and / or the slave device are controlled according to the third detection result.

[0031] In some embodiments, detecting, based on a timeout timer, whether the time for the slave device to enter the clock stretch state exceeds a preset time period, and obtaining a third detection result includes:

[0032] Continuously detecting whether the second serial clock line signal corresponding to the slave device changes to a high level within a preset time period to obtain a fourth detection result; and

[0033] According to the fourth detection result, it is determined whether the time for the slave device to enter the clock stretch state exceeds a preset time period to obtain a third detection result.

[0034] In some embodiments, determining, based on the fourth detection result, whether the time for the slave device to enter the clock stretch state exceeds a preset duration, to obtain the third detection result, includes:

[0035] In response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes a high level within the preset time period, it is determined that the time for the slave device to enter the clock stretch state does not exceed the preset time period, and a third detection result is obtained.

[0036] In some embodiments, the method further comprises:

[0037] In response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device does not become a high level within the preset time period, it is determined that the time for the slave device to enter the clock stretch state exceeds the preset time period, and a third detection result is obtained.

[0038] In some embodiments, controlling the master device and / or the slave device according to the third detection result includes:

[0039] In response to determining that the third detection result is that the time for the slave device to enter the clock stretch state exceeds a preset time period, determining that the slave device is in an abnormal state; and

[0040] Based on the third integrated circuit bus between the complex programmable logic device and the master device, a high impedance is output to the master device, and a first serial clock line signal corresponding to the master device is pulled high.

[0041] In some embodiments, the method further comprises:

[0042] In response to determining that the third detection result is that the time for the slave device to enter the clock stretch state does not exceed the preset time period, when it is determined that the slave device is in a normal state, waiting for the slave device to exit the clock stretch state.

[0043] In some embodiments, the method further comprises:

[0044] In response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, pulling high a second serial clock line signal corresponding to the slave device, and recording a determination character signal returned by the slave device to the master device in a determination character register corresponding to the slave device;

[0045] Control the master device to exit the waiting state; and

[0046] Based on the second integrated circuit bus between the complex programmable logic device and the main device, the determination character signal is regarded as a confirmation character bit and returned to the main device.

[0047] In some implementations, controlling the master device to exit the wait state includes:

[0048] Pull up the first serial clock line signal corresponding to the master device to release the clock stretch state corresponding to the master device.

[0049] In some embodiments, after outputting the determination character signal as a confirmation character bit to the master device based on a second integrated circuit bus between the complex programmable logic device and the master device, the method further includes:

[0050] Recognizing a certain character signal;

[0051] Determine the character state corresponding to the character signal according to the recognition result; the character state includes a response state and a non-response state; and

[0052] The first integrated circuit bus between the master device and the slave device is processed according to the character state corresponding to the determined character signal.

[0053] In some embodiments, processing a first integrated circuit bus between a master device and a slave device based on determining a representation state corresponding to a character signal includes:

[0054] In response to determining that the representation state corresponding to the character signal is a non-responsive state, the takeover of the first integrated circuit bus between the master device and the slave device is exited, and the interaction between the master device and the slave device based on the first integrated circuit bus ends; the non-responsive state is used to characterize that the slave device does not process the target data sent by the master device.

[0055] In some embodiments, the method further comprises:

[0056] In response to determining that the character signal corresponds to a response state, obtaining the highest bit of the next byte sent by the master device to the slave device; and recording the highest bit of the next byte to the serial data line register; the response state is used to indicate that the slave device processes the target data sent by the master device;

[0057] Send the highest bit of the next byte to the slave device;

[0058] Check again whether the slave device has entered the clock stretch state; and

[0059] Until the communication between the master device and the slave device is completed, it returns to the transparent transmission mode.

[0060] In a second aspect, the present application provides a clock stretching processing device in an integrated circuit bus transparent transmission mode, which is applied to a complex programmable logic device, and the device includes:

[0061] an acquisition module, configured to acquire target data transmitted by the master device to the slave device based on the first integrated circuit bus;

[0062] A detection module is used to detect whether the master device has completed sending one byte of data to the slave device based on the target data;

[0063] a confirmation module, configured to, in response to determining that the master device has completed sending one byte of data to the slave device, confirm that the master device is about to send a confirmation character bit to the slave device; and

[0064] The takeover module takes over the first integrated circuit bus between the master device and the slave device, turns off the transparent transmission mode between the master device and the slave device, and controls the master device and / or the slave device.

[0065] In a third aspect, the present application provides an electronic device comprising: a complex programmable logic device for executing the clock stretching processing method in the integrated circuit bus transparent transmission mode of the above-mentioned first aspect or any corresponding embodiment thereof.

[0066] In a fourth aspect, the present application provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method for processing clock stretching in an integrated circuit bus transparent transmission mode according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] FIG1 is a schematic diagram of a flow chart of transparent transmission control of integrated control bus signals in a related art provided by an embodiment of the present application;

[0069] FIG2 is a schematic diagram showing a short pulse appearing on a serial clock line signal when a slave device is in clock stretching according to an embodiment of the present application;

[0070] 3 is a flow chart of a method for processing clock stretching in an integrated circuit bus transparent transmission mode provided by an embodiment of the present application;

[0071] FIG4 is a flowchart of another method for processing clock stretching in an integrated circuit bus transparent transmission mode provided by an embodiment of the present application;

[0072] FIG5 is a flowchart of another method for processing clock stretching in an integrated circuit bus transparent transmission mode provided by an embodiment of the present application;

[0073] 6 is a structural block diagram of a clock stretching processing device in an integrated circuit bus transparent transmission mode provided by an embodiment of the present application;

[0074] FIG7 is a schematic diagram of the structure of a complex programmable logic device provided in an embodiment of the present application;

[0075] FIG8 is a schematic diagram of the structure of the electronic device hardware provided in an embodiment of the present application. DETAILED DESCRIPTION

[0076] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without making creative efforts are all within the scope of protection of this application.

[0077] In server machines, integrated circuit bus (IC) signals are commonly used by the on-board BMC to access devices such as temperature sensors, fan controllers, backplanes, and PCIe add-in cards. The BMC manages these devices through polling, with the BMC acting as the master of the IC bus signals and other devices acting as slaves. When a slave device becomes busy and unable to immediately respond to BMC IC bus access, it actively pulls down the IC bus serial data line signal to suspend IC bus polling. When the slave device exits the busy state, it releases the serial data line signal to respond to IC bus access again. This process is known as IC bus clock stretching.

[0078] Clock stretching for integrated circuit buses can be performed at both the byte and bit levels. Byte-level clock stretching involves pulling the serial data line signal low after a slave device receives a complete byte of data or command, allowing the slave device to process the received data internally. Bit-level clock stretching is primarily used when the serial data line signal rate of the integrated circuit bus supported by the slave device is lower than the serial data line signal rate sent by the master device. In this case, the slave device pulls the serial data line signal low to reduce the actual serial data line signal rate.

[0079] In actual hardware design, when selecting the serial data line signal rate of the master device, the rate supported by the slave device is comprehensively considered to avoid bit-level clock stretching. Byte-level clock stretching is more common.

[0080] For example, as shown in Figure 1, in a scenario where the BMC accesses a fan controller via an integrated circuit bus, to prevent fan control failure if the BMC fails, the BMC integrated circuit bus is typically connected to a complex programmable logic device (CPLD) in hardware. The CPLD then transparently transmits the IC bus to the fan controller. If the CPLD detects a BMC failure, it proactively takes over the fan controller's IC bus to perform fan control.

[0081] In the related CPLD-IC bus transparent transmission solution, since CPLDs are digital logic devices, they cannot achieve real-time bidirectional transparent transmission between the BMC-side IC bus and the FAN_IC-side IC bus. Therefore, the low-level priority method is adopted, as shown in the following table.

[0082] Table 1 IC bus signal judgment in transparent transmission mode

[0083] In related art, when a slave device triggers clock stretching, a short pulse appears on the integrated circuit bus. For example, as shown in Figure 2, after the slave device receives the last bit of a byte of data at t1, it triggers clock stretching at t2, pulling down the slave's corresponding serial clock line signal. However, at this time, both the slave's serial clock line signal and the master's serial clock line signal are low, so the master cannot detect that the slave has triggered clock stretching. The complex programmable logic device (CPLD) then determines that the signal direction is from master to slave. At t3, the master device pulls up the serial clock line signal to generate a high-level serial clock line signal corresponding to the confirmation character bit. Upon detecting the master's high-level serial clock line signal, the CPLD synchronously pulls up the slave's corresponding serial clock line signal. However, because the slave device has triggered clock stretching, the slave's corresponding serial clock line signal has already been pulled down, and the CPLD cannot pull it up. At this point, the signal direction detected by the complex programmable logic device changes from slave to master. Therefore, at time t4, the low level of the serial clock line signal corresponding to the slave device is transparently transmitted to the serial clock line signal corresponding to the master device, thereby pulling the serial clock line signal corresponding to the master device low. A short pulse appears on the serial clock line signal corresponding to the master device between time t3 and t4.

[0084] Similarly, when the slave device exits clock stretching at time t5 and pulls up the serial clock line signal corresponding to the slave device, a short pulse from t5 to t6 is also generated on the serial clock line signal corresponding to the slave device.

[0085] After the slave receives a byte and generates the corresponding acknowledgment signal, clock stretching occurs. That is, time t1 is the acknowledgment bit, and time t3 is the most significant bit of the next byte. The triggering and releasing of clock stretching also generates the two pulses mentioned above.

[0086] The short pulses do not comply with the definition of clock stretching in the integrated circuit bus protocol, which may cause an error in the integrated circuit bus and affect the normal communication between the master device and the slave device.

[0087] Based on the above content, an embodiment of the present application provides an embodiment of a method for processing clock stretching in an integrated circuit bus transparent transmission mode. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-readable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0088] It should be noted that the method for processing clock stretching in an integrated circuit bus transparent transmission mode provided in the embodiments of the present application can be executed by a device for processing clock stretching in this mode. This device for processing clock stretching in this mode can be implemented as part or all of a complex programmable logic device (CPLD) through software, hardware, or a combination of software and hardware. The following method embodiments are all described using a CPLD as the execution subject.

[0089] In some embodiments, a method for processing clock stretching in an integrated circuit bus transparent transmission mode is provided, which can be used in the above-mentioned complex programmable logic device. FIG3 is a flow chart of the method for processing clock stretching in an integrated circuit bus transparent transmission mode according to an embodiment of the present application. As shown in FIG3 , the flow chart includes the following steps:

[0090] Step S101 : acquiring target data transmitted from a master device to a slave device based on a first integrated circuit bus.

[0091] In some embodiments, the complex programmable logic device can obtain target data transmitted by the master device to the slave device based on the first integrated circuit bus based on the communication connection between the master device and the slave device.

[0092] Step S102: Detecting whether the master device has completed sending one byte of data to the slave device based on the target data.

[0093] In some embodiments, the complex programmable logic device can identify the target data, determine the data size corresponding to the target data, and detect whether the master device has completed sending a byte of data to the slave device based on the data size corresponding to the target data.

[0094] In some embodiments, since one byte of data is 8 bits, in response to determining that the target data is 8 bits, it is determined that the master device has completed sending one byte of data to the slave device. In response to determining that the target data is less than 8 bits, it is determined that the master device has not completed sending one byte of data to the slave device.

[0095] In response to determining that the target data is less than 8 bits and determining that the master device has not completed sending one byte of data to the slave device, continue to enable the transparent transmission mode between the master device and the slave device to enable the master device to complete sending one byte of data to the slave device.

[0096] Step S103 : In response to determining that the master device has completed sending one byte of data to the slave device, confirm that the master device is about to send a confirmation character bit to the slave device.

[0097] In some embodiments, in response to determining that the master device has completed sending a byte of data to the slave device, the master device will send an acknowledgement character bit to the slave device. Therefore, the complex programmable logic device determines that the master device is about to send an acknowledgement character bit to the slave device.

[0098] Step S104 , taking over the first integrated circuit bus between the master device and the slave device, turning off the transparent transmission mode between the master device and the slave device, and controlling the master device and / or the slave device.

[0099] In some embodiments, the complex programmable logic device takes over the first integrated circuit bus between the master device and the slave device, that is, disconnects the first integrated circuit bus between the master device and the slave device, connects the second integrated circuit bus between the complex programmable logic device and the master device, and connects the third integrated circuit bus between the complex programmable logic device and the slave device.

[0100] Then, the complex programmable logic device turns off the transparent transmission mode between the master device and the slave device, identifies the status of the slave device based on the third integrated circuit bus between the complex programmable logic device and the slave device, and controls the master device and / or slave device according to the status of the slave device.

[0101] This step will be described in detail below.

[0102] The present invention provides a method for processing clock stretching in an integrated circuit bus transparent transmission mode. The method obtains target data transmitted by a master device to a slave device via a first integrated circuit bus, and then, based on the target data, detects whether the master device has completed sending a byte of data to the slave device. The accuracy of the result obtained by detecting whether the master device has completed sending a byte of data to the slave device is ensured. In response to determining that the master device has completed sending a byte of data to the slave device, the method confirms that the master device is about to send an acknowledgment character bit to the slave device, thereby ensuring the accuracy of the result confirming that the first integrated circuit bus is about to enter the acknowledgment character bit state. The method takes over the first integrated circuit bus between the master and slave devices, disables the transparent transmission mode between the master and slave devices, and controls the master and / or slave devices to prevent short pulses from being generated on the first serial clock line signal corresponding to the master device and the second serial clock line signal corresponding to the slave device after the master device sends the acknowledgment character bit to the slave device, thereby preventing normal communication between the master and slave devices from being affected. The method ensures stable interaction on the first integrated circuit bus without changing the existing hardware connection architecture, thereby increasing the continuity and stability of the server's BMC (master device) managing peripherals.

[0103] In some embodiments, a method for processing clock stretching in an integrated circuit bus transparent transmission mode is provided, which can be used in the above-mentioned complex programmable logic device. FIG4 is a flow chart of the method for processing clock stretching in an integrated circuit bus transparent transmission mode according to an embodiment of the present application. As shown in FIG4 , the flow chart includes the following steps:

[0104] Step S201: acquiring target data transmitted from a master device to a slave device based on a first integrated circuit bus.

[0105] For details about this step, please refer to the introduction of step S101 in FIG1 , which will not be described in detail here.

[0106] Step S202: Detecting whether the master device has completed sending one byte of data to the slave device based on the target data.

[0107] For details about this step, please refer to the introduction of step S102 in FIG1 , which will not be described in detail here.

[0108] Step S203 : In response to determining that the master device has completed sending one byte of data to the slave device, confirm that the master device is about to send a confirmation character bit to the slave device.

[0109] For details about this step, please refer to the introduction of step S103 in FIG1 , which will not be described in detail here.

[0110] Step S204 , taking over the first integrated circuit bus between the master device and the slave device, turning off the transparent transmission mode between the master device and the slave device, and controlling the master device and / or the slave device.

[0111] In some embodiments, the above step S204 includes:

[0112] Step S2041: Based on the second integrated circuit bus between the complex programmable logic device and the master device, control the master device to be in a waiting state.

[0113] In some implementations of the present application, the above step S2041 may include the following:

[0114] Based on the second integrated circuit bus between the complex programmable logic device and the master device, the master device is controlled to enter a clock stretch state, and a first serial clock line signal corresponding to the master device is pulled low to put the master device in a waiting state.

[0115] In some embodiments, the complex programmable logic device triggers the clock stretch of the master device based on the second integrated circuit bus between the master device and the master device, thereby controlling the master device to enter the clock stretch state and pulling down the first serial clock line signal corresponding to the master device to put the master device into a waiting state.

[0116] It should be noted that, based on the second integrated circuit bus between the master device and the master, the master device is controlled to enter a clock stretch state, and the first serial clock line signal corresponding to the master device is pulled low, thereby placing the master device in a standby state. This prevents the master device from sending an acknowledgment character bit state to the slave device, thereby preventing the first serial clock line signal corresponding to the master device from generating pulses that could affect normal communication between the master and slave devices.

[0117] Step S2042: Based on the third integrated circuit bus between the complex programmable logic device and the slave device, detect whether the slave device enters the clock stretching state to obtain a first detection result.

[0118] It should be noted that, based on the third integrated circuit bus between the complex programmable logic device and the slave device, whether the slave device enters the clock stretch state is detected to obtain the first detection result, thereby ensuring the accuracy of the obtained first detection result.

[0119] In some implementations of the present application, the above step S2042 may include the following:

[0120] Step a1: continuously pull up the second serial clock line signal corresponding to the slave device, and send the third serial clock line signal corresponding to the confirmation character bit to the slave device.

[0121] In some embodiments, the complex programmable logic device may continuously pull up a second serial clock line signal corresponding to the slave device, and send a third serial clock line signal corresponding to a confirmation character bit to the slave device.

[0122] Step a2: Detect whether the second serial clock line signal corresponding to the slave device is at a high level, and obtain a second detection result.

[0123] In some embodiments, the complex programmable logic device continuously detects whether the second serial clock line signal corresponding to the slave device is at a high level while continuously pulling up the second serial clock line signal corresponding to the slave device and sending the third serial clock line signal corresponding to the confirmation character bit to the slave device, thereby obtaining a second detection result.

[0124] Step a3: Determine whether the slave device enters the clock stretch state based on the second detection result to obtain the first detection result.

[0125] It should be noted that the second serial clock line signal corresponding to the slave device is continuously pulled high, and the third serial clock line signal corresponding to the confirmation character bit is sent to the slave device. Whether the second serial clock line signal corresponding to the slave device is at a high level is detected to obtain a second detection result, thereby ensuring the accuracy of the second detection result obtained. Then, based on the second detection result, it is determined whether the slave device has entered the clock extension state to obtain the first detection result, thereby ensuring the accuracy of the result of determining whether the slave device has entered the clock extension state. In this way, the accuracy of controlling the master device and / or slave device based on whether the slave device has entered the clock extension state can be guaranteed. This can avoid affecting the normal communication between the master device and the slave device. This ensures the stability of the first integrated circuit bus interaction without changing the original hardware connection architecture, thereby increasing the continuity and stability of the BMC in the server, i.e., the master device managing peripherals.

[0126] In some embodiments of the present application, step a3 includes the following situations:

[0127] In one case, in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, it is determined that the slave device has not entered the clock stretch state or has exited the clock stretch state, and the first detection result is obtained.

[0128] It should be noted that, in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, it is determined that the slave device has not entered the clock stretch state or the slave device has exited the clock stretch state, and the first detection result is obtained, thereby ensuring the accuracy of the result that the slave device has not entered the clock stretch state or the slave device has exited the clock stretch state.

[0129] In some embodiments, in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, the complex programmable logic device determines that the slave device has not entered the clock stretching state or the slave device has exited the clock stretching state, and obtains the first detection result.

[0130] In another case, in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, it is determined that the slave device enters a clock stretching state, and the first detection result is obtained.

[0131] In some embodiments, in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, it is determined that the slave device enters the clock stretch state, and the first detection result is obtained, thereby ensuring the accuracy of the determination that the slave device enters the clock stretch state.

[0132] Step S2043: Control the master device and / or the slave device according to the first detection result.

[0133] Based on the first detection result, the master device and / or slave device are controlled, ensuring accurate control of the master device and / or slave device, avoiding the generation of pulses in the second serial clock line signal corresponding to the slave device, thereby preventing normal communication between the master and slave devices from being affected. This ensures stable interaction with the first integrated circuit bus without changing the existing hardware connection architecture, thereby increasing the continuity and stability of the server's BMC, i.e., the master device, in managing peripheral devices.

[0134] In some implementations of the present application, the above step S2043 may include the following:

[0135] Step b1: In response to determining that the first detection result indicates that the slave device has entered a clock stretch state, starting a timeout counter.

[0136] The timeout counter is set with a preset duration, which may be 0.1 seconds, 0.2 seconds, or other durations. The present embodiment does not limit the preset duration.

[0137] Step b2: Based on the timeout timer, detect whether the time when the slave device enters the clock stretch state exceeds a preset time period, and obtain a third detection result.

[0138] In some embodiments of the present application, a complex programmable logic device can continuously detect whether the second serial clock line signal corresponding to the slave device is at a high level, and record the time when the second serial clock line signal corresponding to the slave device becomes high. Based on the time when the second serial clock line signal corresponding to the slave device becomes high, the duration of the slave device entering the clock stretching state is determined;

[0139] The duration is compared with the preset duration. Based on the comparison result, it is determined whether the duration of time during which the slave device enters the clock stretch state exceeds the preset duration. In response to determining that the duration is greater than the preset duration, it is determined that the duration of time during which the slave device enters the clock stretch state exceeds the preset duration, and a third detection result is obtained. In response to determining that the duration is less than the preset duration, it is determined that the duration of time during which the slave device enters the clock stretch state does not exceed the preset duration, and a third detection result is obtained.

[0140] It should be noted that, in response to determining that the first detection result indicates that the slave device has entered a clock stretch state, a timeout counter is started. Based on the timeout timer, it is detected whether the time the slave device has entered the clock stretch state exceeds a preset time length, and a third detection result is obtained, thereby ensuring the accuracy of the third detection result. Based on the third detection result, the master device and / or the slave device are controlled, ensuring the accuracy of the control of the master device and / or the slave device, thereby avoiding affecting the normal communication between the master device and the slave device. This ensures the stability of the first integrated circuit bus interaction without changing the original hardware connection architecture, thereby increasing the continuity and stability of the BMC in the server, i.e., the master device managing peripherals.

[0141] In some embodiments of the present application, the above step b2 may include the following:

[0142] Step b21: continuously detecting whether the second serial clock line signal corresponding to the slave device changes to a high level within a preset time period, and obtaining a fourth detection result.

[0143] In some embodiments, the complex programmable logic device may continuously detect whether the second serial clock line signal corresponding to the slave device changes to a high level within a preset time period to obtain a fourth detection result.

[0144] Exemplarily, assuming that the preset time length is 0.1 seconds, the complex programmable logic device continuously detects whether the second serial clock line signal corresponding to the slave device becomes a high level within this 0.1 second, and obtains a fourth detection result.

[0145] Step b22: Determine, based on the fourth detection result, whether the time for the slave device to enter the clock stretch state exceeds a preset time period, and obtain a third detection result.

[0146] It should be noted that the accuracy of the fourth detection result is ensured by continuously detecting whether the second serial clock line signal corresponding to the slave device reaches a high level within a preset time period. Based on the fourth detection result, it is determined whether the time the slave device has entered the clock stretch state exceeds the preset time period to obtain the third detection result. This ensures the accuracy of the third detection result obtained by determining whether the time the slave device has entered the clock stretch state exceeds the preset time period based on the fourth detection result.

[0147] In some embodiments of the present application, the above step b22 may include the following situations:

[0148] In one case, in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes a high level within the preset time length, it is determined that the time for the slave device to enter the clock stretch state does not exceed the preset time length, and a third detection result is obtained.

[0149] Exemplarily, in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes a high level within 0.1 seconds, the complex programmable logic device determines that the time for the slave device to enter the clock stretching state does not exceed the preset time length, and obtains the third detection result.

[0150] It should be noted that, in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes a high level within the preset time length, it is determined that the time for the slave device to enter the clock stretch state does not exceed the preset time length, and the third detection result is obtained, thereby ensuring the accuracy of the result that the time for the slave device to enter the clock stretch state does not exceed the preset time length.

[0151] In another case, in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device does not become a high level within the preset time length, it is determined that the time for the slave device to enter the clock stretch state exceeds the preset time length, and a third detection result is obtained.

[0152] Exemplarily, in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device does not become a high level within 0.1 seconds, the complex programmable logic device determines that the time for the slave device to enter the clock stretching state exceeds a preset duration, and obtains a third detection result.

[0153] It should be noted that, in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device has not become a high level within the preset time length, it is determined that the time for the slave device to enter the clock stretch state exceeds the preset time length, and the third detection result is obtained, thereby ensuring the accuracy of the result that the time for the slave device to enter the clock stretch state exceeds the preset time length.

[0154] Step b3: Control the master device and / or the slave device according to the third detection result.

[0155] In some embodiments of the present application, the above step b3 may include the following situations:

[0156] In one case, in response to determining that the third detection result is that the time for the slave device to enter the clock stretch state exceeds a preset time period, it is determined that the slave device is in an abnormal state.

[0157] Based on the third integrated circuit bus between the complex programmable logic device and the master device, a high impedance is output to the master device, and a first serial clock line signal corresponding to the master device is pulled high.

[0158] In some embodiments, in response to determining as a third detection result that the slave device has entered a clock stretching state for a period exceeding a preset duration, the slave device is determined to be in an abnormal state. The complex programmable logic device outputs a high impedance to the master device based on a third integrated circuit bus between the complex programmable logic device and the master device, pulls up a first serial clock line signal corresponding to the master device, and thereby disconnects a transparent transmission mode between the master and slave devices.

[0159] It should be noted that, in response to determining that the third detection result is that the time for the slave device to enter the clock stretch state exceeds the preset time length, it is determined that the slave device is in an abnormal state. Based on the third integrated circuit bus between the complex programmable logic device and the master device, a high impedance is output to the master device, and the first serial clock line signal corresponding to the master device is pulled high, thereby disconnecting the transparent transmission mode between the master device and the slave device, preventing the slave device in the abnormal state from affecting other devices on the integrated circuit bus.

[0160] In another case, in response to determining that the third detection result is that the time for the slave device to enter the clock stretch state does not exceed the preset time period, when it is determined that the slave device is in a normal state, the slave device is waited to exit the clock stretch state.

[0161] In some embodiments, in response to determining that the third detection result is that the time the slave device enters the clock stretch state does not exceed a preset time period, when it is determined that the slave device is in a normal state, the slave device is waited to exit the clock stretch state.

[0162] It should be noted that, in response to determining that the third detection result is that the time for the slave device to enter the clock stretch state does not exceed the preset time length, when it is determined that the slave device is in a normal state, the slave device is waited for to exit the clock stretch state, thereby ensuring normal communication between the master device and the slave device.

[0163] Step b4, in response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, pull up the second serial clock line signal corresponding to the slave device, and record the confirmation character signal returned by the slave device to the master device in the confirmation character register corresponding to the slave device.

[0164] In some embodiments, in response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, the complex programmable logic device pulls up the second serial clock line signal corresponding to the slave device, and obtains the determination character signal returned by the slave device to the master device, and records the determination character signal returned by the slave device to the master device in the determination character register corresponding to the slave device.

[0165] Step b5: Control the master device to exit the waiting state.

[0166] In some embodiments of the present application, the above step b5 may include the following:

[0167] Pull up the first serial clock line signal corresponding to the master device to release the clock stretch state corresponding to the master device.

[0168] In some embodiments, the complex programmable logic device pulls up the first serial clock line signal corresponding to the master device and releases the clock stretch state corresponding to the master device, so that the master device can communicate normally.

[0169] It should be noted that, by pulling up the first serial clock line signal corresponding to the master device, the clock stretch state corresponding to the master device is released, thereby causing the master device to exit the waiting state.

[0170] Step b6: Based on the second integrated circuit bus between the complex programmable logic device and the host device, the determination character signal is regarded as a confirmation character bit and returned to the host device.

[0171] In some embodiments, the complex programmable logic device, based on a second integrated circuit bus between the complex programmable logic device and the master device, treats the obtained confirmation character signal returned from the slave device to the master device as a confirmation character bit and returns it to the master device.

[0172] It should be noted that, in response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, the second serial clock line signal corresponding to the slave device is pulled high so that the slave device can return a confirmation character signal to the master device. The confirmation character signal returned by the slave device to the master device is recorded in the confirmation character register corresponding to the slave device, so that the confirmation character signal returned by the slave device to the master device can be obtained. The master device is controlled to exit the waiting state so that the master device is in a normal communication state. Based on the second integrated circuit bus between the complex programmable logic device and the master device, the confirmation character signal is treated as a confirmation character bit and returned to the master device, so that the master device can receive the confirmation character signal returned by the slave device, thereby ensuring the next communication between the master device and the slave device.

[0173] Step b7: Recognize the determined character signal.

[0174] In some embodiments, the complex programmable logic device can recognize a certain character signal.

[0175] Step b8: Determine the representation state corresponding to the character signal based on the recognition result.

[0176] The representation state includes a response state and a non-response state.

[0177] In some embodiments, the complex programmable logic device determines a representation state corresponding to the character signal based on the recognition result.

[0178] Step b9: Processing the first integrated circuit bus between the master device and the slave device according to the representation state corresponding to the determined character signal.

[0179] It should be noted that identifying a specific character signal and determining the corresponding character state of the character signal based on the identification result ensures the accuracy of the corresponding character state of the specific character signal. Processing the first integrated circuit bus between the master device and the slave device based on the corresponding character state of the specific character signal ensures the accuracy of the processing of the first integrated circuit bus between the master device and the slave device.

[0180] In some embodiments of the present application, the above step b9 may include the following situations:

[0181] In one case, in response to determining that the representation state corresponding to the character signal is a non-responsive state, the takeover of the first integrated circuit bus between the master device and the slave device is exited, and the interaction between the master device and the slave device based on the first integrated circuit bus is terminated.

[0182] The non-response state is used to indicate that the slave device does not process the target data sent by the master device.

[0183] In some embodiments, in response to determining that the representation state corresponding to the character signal is a non-responsive state, the complex programmable logic device exits the takeover of the first integrated circuit bus between the master device and the slave device, and the interaction between the master device and the slave device based on the first integrated circuit bus ends.

[0184] It should be noted that, in response to determining that the character signal corresponds to a non-responsive state, the takeover of the first integrated circuit bus between the master and slave devices is terminated, and interaction between the master and slave devices based on the first integrated circuit bus ends. During the process of the complex programmable logic device taking over the first integrated circuit bus between the master and slave devices, no short pulses are generated on the first serial clock line signal corresponding to the master device or the second serial clock line signal corresponding to the slave device, thereby ensuring normal communication between the master and slave devices. This ensures the stability of the interaction on the first integrated circuit bus without changing the original hardware connection architecture, thereby increasing the continuity and stability of the BMC (master device) in the server to manage peripherals.

[0185] In another case, in response to determining that the representation state corresponding to the character signal is a response state, the highest bit of the next byte sent by the master device to the slave device is obtained; and the highest bit of the next byte is recorded in the serial data line register, wherein the response state is used to represent that the slave device processes the target data sent by the master device; the highest bit of the next byte is sent to the slave device; and it is detected again whether the slave device enters the clock stretch state; until the communication between the master device and the slave device is completed, the transparent transmission mode is returned.

[0186] In some embodiments, in response to determining that the character signal corresponds to a response state, the complex programmable logic device obtains the most significant bit of the next byte sent by the master device to the slave device and records the most significant bit of the next byte to the serial data line register. The complex programmable logic device then sends the most significant bit of the next byte to the slave device, thereby enabling normal communication between the master and slave devices.

[0187] The complex programmable logic device again detects whether the slave device has entered the clock stretch state. For the detection process, please refer to the above embodiment. In response to the slave device entering the clock stretch state, the complex programmable logic device actively controls the master device to enter the clock stretch state, pulling down the first serial clock line signal corresponding to the master device to put the master device into a waiting state. At the same time, a timeout counter is started to determine whether the slave device is in an abnormal state. For the steps, please refer to the above embodiment. In response to the slave device not entering the clock stretch state or having exited the clock stretch state, the complex programmable logic device pulls up the second serial clock line signal corresponding to the slave device and sends the highest bit of the next byte to the slave device. This cycle continues until the communication between the master and slave devices ends and returns to the transparent transmission mode.

[0188] It should be noted that, in response to determining that the characterization state corresponding to the character signal is the response state, the highest bit of the next byte sent by the master device to the slave device is obtained; and the highest bit of the next byte is recorded in the serial data line register, so that the highest bit of the next byte can be obtained. Then, the highest bit of the next byte is sent to the slave device, ensuring normal communication between the master device and the slave device. It is again detected whether the slave device has entered the clock extension state; until the communication between the master device and the slave device is completed, the transparent transmission mode is returned. In the process of the complex programmable logic device taking over the first integrated circuit bus between the master device and the slave device, no short pulses are generated on the first serial clock line signal corresponding to the master device and the second serial clock line signal corresponding to the slave device, ensuring normal communication between the master device and the slave device. The stability of the interaction of the first integrated circuit bus is achieved without changing the original hardware connection architecture, which increases the continuity and stability of the BMC in the server, that is, the master device managing peripherals.

[0189] The clock stretching processing method provided by the embodiments of the present application in the integrated circuit bus transparent transmission mode is based on the second integrated circuit bus between the complex programmable logic device and the master device. It controls the master device to enter the clock stretching state and pulls down the first serial clock line signal corresponding to the master device to put the master device into a waiting state. This prevents the master device from sending the confirmation character bit state to the slave device, thereby preventing the first serial clock line signal corresponding to the master device from generating pulses that affect normal communication between the master and slave devices.

[0190] Then, the second serial clock line signal corresponding to the slave device is continuously pulled high, and a third serial clock line signal corresponding to the confirmation character bit is sent to the slave device. Whether the second serial clock line signal corresponding to the slave device is at a high level is detected, and a second detection result is obtained, thereby ensuring the accuracy of the second detection result. In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, it is determined that the slave device has not entered the clock stretch state or the slave device has exited the clock stretch state, and the first detection result is obtained, thereby ensuring the accuracy of the result that the slave device has not entered the clock stretch state or the slave device has exited the clock stretch state. In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, it is determined that the slave device has entered the clock stretch state, and the first detection result is obtained, thereby ensuring the accuracy of the result that the slave device has entered the clock stretch state.

[0191] In response to determining that the first detection result is that the slave device has entered a clock stretch state, a timeout counter is started. Continuously detecting whether the second serial clock line signal corresponding to the slave device has changed to a high level within a preset time period to obtain a fourth detection result, thereby ensuring the accuracy of the fourth detection result. In response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device has changed to a high level within the preset time period, it is determined that the time the slave device has entered the clock stretch state has not exceeded the preset time period, thereby obtaining a third detection result, thereby ensuring the accuracy of the result that the time the slave device has entered the clock stretch state has not exceeded the preset time period. In response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device has not changed to a high level within the preset time period, it is determined that the time the slave device has entered the clock stretch state has exceeded the preset time period, thereby obtaining a third detection result, thereby ensuring the accuracy of the result that the slave device has entered the clock stretch state has exceeded the preset time period.

[0192] In response to determining that the third detection result is that the time for the slave device to enter the clock stretch state exceeds a preset time length, it is determined that the slave device is in an abnormal state. Based on the third integrated circuit bus between the complex programmable logic device and the master device, a high impedance is output to the master device, and the first serial clock line signal corresponding to the master device is pulled high, thereby disconnecting the transparent transmission mode between the master device and the slave device, and preventing the slave device in the abnormal state from affecting other devices on the integrated circuit bus.

[0193] In response to determining that the third detection result is that the time for the slave device to enter the clock stretch state does not exceed the preset time length, when it is determined that the slave device is in a normal state, wait for the slave device to exit the clock stretch state, thereby ensuring normal communication between the master device and the slave device.

[0194] In response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, the second serial clock line signal corresponding to the slave device is pulled high so that the slave device can return a confirmation character signal to the master device. The confirmation character signal returned by the slave device to the master device is recorded in the confirmation character register corresponding to the slave device, so that the confirmation character signal returned by the slave device to the master device can be obtained. The first serial clock line signal corresponding to the master device is pulled high to release the clock stretch state corresponding to the master device, thereby causing the master device to exit the waiting state and put the master device into a normal communication state. Based on the second integrated circuit bus between the complex programmable logic device and the master device, the confirmation character signal is treated as a confirmation character bit and returned to the master device, so that the master device can receive the confirmation character signal returned by the slave device, thereby ensuring the next step of communication between the master device and the slave device.

[0195] A character signal is identified; based on the identification result, a corresponding character state is determined, ensuring the accuracy of the character state corresponding to the determined character signal. In response to determining that the corresponding character state is a non-responsive state, the master device exits the takeover of the first integrated circuit bus between the master and the slave device, terminating interaction between the master and the slave device based on the first integrated circuit bus. During the process of the complex programmable logic device taking over the first integrated circuit bus between the master and the slave device, no short pulses are generated on the first serial clock line signal corresponding to the master device or the second serial clock line signal corresponding to the slave device, thereby ensuring normal communication between the master and the slave device. This ensures stable interaction on the first integrated circuit bus without changing the existing hardware connection architecture, thereby increasing the continuity and stability of the BMC (master device) managing peripherals in the server. In response to determining that the corresponding character state is a responsive state, the master device obtains the most significant bit of the next byte sent to the slave device; the most significant bit of the next byte is recorded in a serial data line register, thereby obtaining the most significant bit of the next byte. The most significant bit of the next byte is then sent to the slave device, ensuring normal communication between the master and the slave device. The slave device is then checked again to see if it has entered the clock stretching state; communication between the master and slave devices ends, returning to transparent transmission mode. During the process of the complex programmable logic device taking over the first integrated circuit bus between the master and slave devices, no short pulses are generated on the first serial clock line signal corresponding to the master device or the second serial clock line signal corresponding to the slave device, ensuring normal communication between the master and slave devices. This ensures stable interaction on the first integrated circuit bus without changing the existing hardware connection architecture, increasing the continuity and stability of the server's BMC, the master device's management of peripherals.

[0196] To better describe the method for processing clock stretching in an integrated circuit bus transparent transmission mode provided in an embodiment of the present application, an embodiment of the present application provides a flowchart of the method for processing clock stretching in an integrated circuit bus transparent transmission mode, which can be used in the above-mentioned complex programmable logic device. As shown in FIG5 , the flowchart includes the following steps:

[0197] Step 301: Acquire target data transmitted from a master device to a slave device based on a first integrated circuit bus.

[0198] Step 302: Detect, based on the target data, whether the master device has completed sending one byte of data to the slave device.

[0199] Step 303 : In response to determining that the master device has completed sending one byte of data to the slave device, confirming that the master device is about to send an acknowledgement character bit to the slave device, taking over the first integrated circuit bus between the master device and the slave device.

[0200] Step 304 : Based on the second integrated circuit bus between the complex programmable logic device and the master device, control the master device to enter a clock stretching state, pull down the first serial clock line signal corresponding to the master device, and put the master device into a waiting state.

[0201] Step 305: continuously pull up the second serial clock line signal corresponding to the slave device, and send a third serial clock line signal corresponding to the confirmation character bit to the slave device.

[0202] Step 306 , detecting whether the second serial clock line signal corresponding to the slave device is at a high level, and obtaining a second detection result.

[0203] Step 307 , in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, determining that the slave device has not entered the clock stretch state or has exited the clock stretch state, obtaining the first detection result, and executing step 315 .

[0204] Step 308 : In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, determining that the slave device enters a clock stretching state, and obtaining the first detection result, and then executing step 309 .

[0205] Step 309 : In response to determining that the first detection result indicates that the slave device has entered a clock stretch state, start a timeout counter.

[0206] Step 310: Continuously detect whether the second serial clock line signal corresponding to the slave device changes to a high level within a preset time period to obtain a fourth detection result.

[0207] In step 311 , in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes high within the preset time period, and determining that the time for the slave device to enter the clock stretching state does not exceed the preset time period, step 313 is executed.

[0208] Step 312 , in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device does not become a high level within the preset time period, it is determined that the time for the slave device to enter the clock stretching state exceeds the preset time period, and step 314 is executed.

[0209] Step 313 : In response to determining that the third detection result is that the time the slave device enters the clock stretch state does not exceed the preset time period, and determining that the slave device is in a normal state, wait for the slave device to exit the clock stretch state.

[0210] Step 314, in response to determining that the third detection result is that the time for the slave device to enter the clock stretch state exceeds the preset time period, it is determined that the slave device is in an abnormal state; based on the third integrated circuit bus between the complex programmable logic device and the master device, a high impedance is output to the master device to pull up the first serial clock line signal corresponding to the master device.

[0211] Step 315: In response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, pull up the second serial clock line signal corresponding to the slave device, and record the confirmation character signal returned by the slave device to the master device in the confirmation character register corresponding to the slave device.

[0212] Step 316: pull up the first serial clock line signal corresponding to the master device to release the clock stretching state corresponding to the master device.

[0213] Step 317 : Based on the second integrated circuit bus between the complex programmable logic device and the host device, the confirmation character signal is treated as a confirmation character bit and returned to the host device.

[0214] Step 318: Recognize the determined character signal.

[0215] Step 319: Determine the character state corresponding to the character signal based on the recognition result. In response to determining that the character state corresponding to the character signal is the non-responsive state, execute step 320. In response to determining that the character state corresponding to the character signal is the responsive state, execute step 321.

[0216] Step 320: exit the takeover of the first integrated circuit bus between the master device and the slave device, and the interaction between the master device and the slave device based on the first integrated circuit bus ends.

[0217] Step 321: Obtain the MSB of the next byte sent by the master device to the slave device and record the MSB of the next byte in the serial data line register. Send the MSB of the next byte to the slave device and again check whether the slave device has entered the clock stretch state. This process continues until communication between the master and slave devices is complete, returning to transparent transmission mode.

[0218] In some embodiments, a device for processing clock stretching in an integrated circuit bus transparent transmission mode is also provided. The device is used to implement the above-mentioned embodiments, and the details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0219] Some embodiments provide a clock stretching processing device in an integrated circuit bus transparent transmission mode, which is applied to a complex programmable logic device. As shown in FIG6 , the device includes:

[0220] An acquisition module 401 is configured to acquire target data transmitted by a master device to a slave device based on a first integrated circuit bus;

[0221] A detection module 402 is used to detect whether the master device has completed sending one byte of data to the slave device based on the target data;

[0222] Confirmation module 403, configured to confirm that the master device is about to send a confirmation character bit to the slave device when the master device has completed sending a byte of data to the slave device;

[0223] The takeover module 404 takes over the first integrated circuit bus between the master device and the slave device, turns off the transparent transmission mode between the master device and the slave device, and controls the master device and / or the slave device.

[0224] In some embodiments, the takeover module 404 is used to control the master device to be in a waiting state based on a second integrated circuit bus between the complex programmable logic device and the master device; detect whether the slave device enters a clock stretching state based on a third integrated circuit bus between the complex programmable logic device and the slave device to obtain a first detection result; and control the master device and / or the slave device based on the first detection result.

[0225] In some embodiments, the takeover module 404 is used to control the master device to enter a clock stretching state based on a second integrated circuit bus between the complex programmable logic device and the master device, and to pull down the first serial clock line signal corresponding to the master device to put the master device into a waiting state.

[0226] In some embodiments, the takeover module 404 is used to continuously pull up the second serial clock line signal corresponding to the slave device, and send a third serial clock line signal corresponding to the confirmation character bit to the slave device; detect whether the second serial clock line signal corresponding to the slave device is a high level, and obtain a second detection result; based on the second detection result, determine whether the slave device enters the clock stretching state, and obtain a first detection result.

[0227] In some embodiments, the takeover module 404 is used to determine that the slave device has not entered the clock stretch state or has exited the clock stretch state in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, thereby obtaining the first detection result.

[0228] In some embodiments, the takeover module 404 is configured to determine that the slave device enters a clock stretching state in response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, thereby obtaining the first detection result.

[0229] In some embodiments, the takeover module 404 is used to start a timeout counter in response to determining that the first detection result is that the slave device enters a clock extension state; a preset duration is set in the timeout counter; based on the timeout timer, it is detected whether the time for the slave device to enter the clock extension state exceeds the preset duration to obtain a third detection result; based on the third detection result, the master device and / or the slave device is controlled.

[0230] In some embodiments, the takeover module 404 is used to continuously detect whether the second serial clock line signal corresponding to the slave device becomes a high level within a preset time period to obtain a fourth detection result; based on the fourth detection result, determine whether the time for the slave device to enter the clock stretch state exceeds the preset time period to obtain a third detection result.

[0231] In some embodiments, the takeover module 404 is used to respond to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes a high level within a preset time period, and determine that the time for the slave device to enter the clock stretching state does not exceed the preset time period, to obtain a third detection result.

[0232] In some embodiments, the takeover module 404 is used to determine that the time for the slave device to enter the clock stretching state exceeds the preset time length in response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device has not become a high level within the preset time length, and obtain a third detection result.

[0233] In some embodiments, the takeover module 404 is used to determine that the slave device is in an abnormal state in response to determining that the third detection result is that the time for the slave device to enter the clock stretch state exceeds a preset time period; based on the third integrated circuit bus between the complex programmable logic device and the master device, output high impedance to the master device and pull up the first serial clock line signal corresponding to the master device.

[0234] In some embodiments, the takeover module 404 is configured to wait for the slave device to exit the clock stretch state in response to determining that the third detection result is that the time the slave device enters the clock stretch state does not exceed a preset time period and that the slave device is in a normal state.

[0235] In some embodiments, the takeover module 404 is used to, in response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, pull up the second serial clock line signal corresponding to the slave device, and record the determination character signal returned by the slave device to the master device in the determination character register corresponding to the slave device; control the master device to exit the waiting state; based on the second integrated circuit bus between the complex programmable logic device and the master device, use the determination character signal as a confirmation character bit and return it to the master device.

[0236] In some implementations, the takeover module 404 is configured to pull up a first serial clock line signal corresponding to the master device, thereby releasing a clock stretching state corresponding to the master device.

[0237] In some embodiments, the takeover module 404 is used to identify a certain character signal; determine a representation state corresponding to the character signal based on the identification result; the representation state includes a response state and a non-response state; and process the first integrated circuit bus between the master device and the slave device based on the representation state corresponding to the determined character signal.

[0238] In some embodiments, the takeover module 404 is used to exit the takeover of the first integrated circuit bus between the master device and the slave device in response to determining that the representation state corresponding to the character signal is a non-responsive state, and the interaction between the master device and the slave device based on the first integrated circuit bus ends; the non-responsive state is used to indicate that the slave device does not process the target data sent by the master device.

[0239] In some embodiments, the takeover module 404 is used to obtain the highest bit of the next byte sent by the master device to the slave device in response to determining that the representation state corresponding to the character signal is a response state; and record the highest bit of the next byte to the serial data line register; the response state is used to represent that the slave device processes the target data sent by the master device; sends the highest bit of the next byte to the slave device; detects again whether the slave device enters the clock stretch state; until the communication between the master device and the slave device is completed, and returns to the transparent transmission mode.

[0240] The clock stretching processing device provided in the integrated circuit bus transparent transmission mode of the present application obtains target data transmitted by a master device to a slave device via a first integrated circuit bus, and then, based on the target data, detects whether the master device has completed sending a byte of data to the slave device. The accuracy of the result obtained by detecting whether the master device has completed sending a byte of data to the slave device is ensured. In response to determining that the master device has completed sending a byte of data to the slave device, the device confirms that the master device is about to send an acknowledgment character bit to the slave device, thereby ensuring the accuracy of the result confirming that the first integrated circuit bus is about to enter the acknowledgment character bit state. The device takes over the first integrated circuit bus between the master and slave devices, disables the transparent transmission mode between the master and slave devices, and controls the master and / or slave devices to prevent short pulses from being generated on the first serial clock line signal corresponding to the master device and the second serial clock line signal corresponding to the slave device after the master device sends the acknowledgment character bit to the slave device, thereby affecting normal communication between the master and slave devices. This ensures the stability of the first integrated circuit bus interaction without changing the existing hardware connection architecture, thereby increasing the continuity and stability of the server's BMC (master device) management of peripherals.

[0241] In some embodiments, the clock stretching processing device in the integrated circuit bus transparent transmission mode is presented in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0242] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0243] The present application also provides a complex programmable logic device (CPLD) having a clock stretching processing device in the integrated circuit bus transparent transmission mode as shown in FIG6 . The CPLD may be as shown in FIG7 .

[0244] An embodiment of the present application further provides an electronic device, which may be a server or a mobile terminal, and includes the complex programmable logic device shown in FIG7 .

[0245] Please refer to Figure 8, which is a structural diagram of an electronic device provided in an embodiment of the present application. As shown in Figure 8, the electronic device includes: one or more processors 10, a memory 20 associated with one or more processors 10, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 takes a processor 10 as an example.

[0246] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware module. The hardware module may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device (PLD) may be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general purpose array logic (GAL), or any combination thereof.

[0247] The memory 20 stores computer-readable instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to implement the method shown in the above embodiment.

[0248] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created based on the use of an electronic device presented by a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 20 includes a memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0249] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0250] The electronic device further includes a communication interface 30 for the electronic device to communicate with other devices or a communication network.

[0251] The embodiments of the present application also provide a non-volatile computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0252] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A method for processing clock extension in an integrated circuit bus transparent transmission mode, characterized in that: Applied to a complex programmable logic device, the method comprises: Acquire target data transmitted by the master device to the slave device based on the first integrated circuit bus; According to the target data, detecting whether the master device has completed sending one byte of data to the slave device; In response to determining that the master device has completed sending the one byte of data to the slave device, confirming that the master device is about to send a confirmation character bit to the slave device; and Taking over the first integrated circuit bus between the master device and the slave device, turning off the transparent transmission mode between the master device and the slave device, and controlling the master device and / or the slave device.

2. The method according to claim 1, characterized in that The taking over the first integrated circuit bus between the master device and the slave device, turning off the transparent transmission mode between the master device and the slave device, and controlling the master device and / or the slave device includes: Based on a second integrated circuit bus between the complex programmable logic device and the master device, controlling the master device to be in a waiting state; Based on a third integrated circuit bus between the complex programmable logic device and the slave device, detecting whether the slave device enters a clock stretching state to obtain a first detection result; and The master device and / or the slave device is controlled according to the first detection result.

3. The method according to claim 2, characterized in that The controlling the master device to be in a waiting state based on a second integrated circuit bus between the complex programmable logic device and the master device comprises: Based on the second integrated circuit bus between the complex programmable logic device and the master device, the master device is controlled to enter a clock stretching state, and a first serial clock line signal corresponding to the master device is pulled low to put the master device in a waiting state.

4. The method according to claim 2, characterized in that: The detecting, based on a third integrated circuit bus between the complex programmable logic device and the slave device, whether the slave device enters a clock stretching state to obtain a first detection result includes: Continuously pulling up the second serial clock line signal corresponding to the slave device, and sending a third serial clock line signal corresponding to a confirmation character bit to the slave device; Detecting whether the second serial clock line signal corresponding to the slave device is at a high level, and obtaining a second detection result; and According to the second detection result, it is determined whether the slave device enters the clock stretching state to obtain the first detection result.

5. The method according to claim 4, characterized in that The step of determining, according to the second detection result, whether the slave device enters the clock stretching state to obtain the first detection result includes: In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a high level, determining that the slave device has not entered the clock stretch state or the slave device has exited the clock stretch state, the first detection result is obtained.

6. The method according to claim 5, characterized in that Determining whether the slave device enters the clock stretching state according to the second detection result, and obtaining the first detection result includes: In response to determining that the second detection result is that the second serial clock line signal corresponding to the slave device is at a low level, determining that the slave device enters the clock stretching state, and obtaining the first detection result.

7. The method according to claim 2, characterized in that The controlling the master device and / or the slave device according to the first detection result includes: In response to determining that the first detection result is that the slave device enters the clock stretching state, starting a timeout counter; a preset time length is set in the timeout counter; Based on the timeout timer, detecting whether the time for the slave device to enter the clock stretch state exceeds the preset duration, to obtain a third detection result; and The master device and / or the slave device is controlled according to the third detection result.

8. The method according to claim 7, characterized in that The detecting, based on the timeout timer, whether the time for the slave device to enter the clock stretch state exceeds the preset time length, and obtaining a third detection result includes: Continuously detecting whether the second serial clock line signal corresponding to the slave device changes to a high level within the preset time period to obtain a fourth detection result; and According to the fourth detection result, it is determined whether the time for the slave device to enter the clock stretch state exceeds the preset duration to obtain the third detection result.

9. The method according to claim 8, characterized in that The determining, according to the fourth detection result, whether the time for the slave device to enter the clock stretch state exceeds the preset duration to obtain the third detection result includes: In response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device becomes a high level within the preset time length, determining that the time for the slave device to enter the clock stretching state does not exceed the preset time length, the third detection result is obtained.

10. The method according to claim 9, characterized in that The determining, according to the fourth detection result, whether the time for the slave device to enter the clock stretch state exceeds the preset duration to obtain the third detection result includes: In response to determining that the fourth detection result is that the second serial clock line signal corresponding to the slave device does not become a high level within the preset time length, it is determined that the time for the slave device to enter the clock stretching state exceeds the preset time length, and the third detection result is obtained.

11. The method according to claim 7, characterized in that The controlling the master device and / or the slave device according to the third detection result includes: In response to determining that the third detection result is that the time for the slave device to enter the clock stretching state exceeds the preset time length, determining that the slave device is in an abnormal state; and Based on the third integrated circuit bus between the complex programmable logic device and the master device, a high impedance is output to the master device, and a first serial clock line signal corresponding to the master device is pulled high.

12. The method according to claim 11, characterized in that The controlling the master device and / or the slave device according to the third detection result includes: In response to determining that the third detection result is that the time for the slave device to enter the clock stretch state does not exceed the preset time length, when it is determined that the slave device is in a normal state, waiting for the slave device to exit the clock stretch state.

13. The method according to claim 7, characterized in that The controlling the master device and / or the slave device according to the first detection result includes: In response to determining that the first detection result is that the slave device has not entered the clock stretch state or has exited the clock stretch state, pulling up a second serial clock line signal corresponding to the slave device, and recording a determination character signal returned by the slave device to the master device in a determination character register corresponding to the slave device; Controlling the master device to exit the waiting state; and Based on the second integrated circuit bus between the complex programmable logic device and the host device, the determined character signal is The confirmation character bit is returned and output to the master device.

14. The method according to claim 13, characterized in that The controlling the master device to exit the waiting state comprises: The first serial clock line signal corresponding to the master device is pulled high to release the clock stretching state corresponding to the master device.

15. The method according to claim 13, characterized in that After the determination character signal is regarded as the confirmation character bit and returned to the master device based on the second integrated circuit bus between the complex programmable logic device and the master device, the method further includes: Recognizing the determined character signal; According to the recognition result, determining the representation state corresponding to the determined character signal; the representation state includes a response state and a non-response state; and The first integrated circuit bus between the master device and the slave device is processed according to the representation state corresponding to the determined character signal.

16. The method according to claim 15, characterized in that The processing of the first integrated circuit bus between the master device and the slave device according to the characterization state corresponding to the determined character signal includes: In response to determining that the representation state corresponding to the character signal is the unresponsive state, the takeover of the first integrated circuit bus between the master device and the slave device is exited, and the interaction between the master device and the slave device based on the first integrated circuit bus is terminated; the unresponsive state is used to characterize that the slave device does not process the target data sent by the master device.

17. The method according to claim 16, characterized in that The method further comprises: In response to determining that the character state corresponding to the character signal is the response state, obtaining the highest bit of the next byte sent by the master device to the slave device; and recording the highest bit of the next byte to the serial data line register; the response state is used to represent that the slave device processes the target data sent by the master device; Send the highest bit of the next byte to the slave device; detecting again whether the slave device enters the clock stretching state; and Until the communication between the master device and the slave device is completed, the transparent transmission mode is returned.

18. A processing device for clock extension in an integrated circuit bus transparent transmission mode, characterized in that: Applied to a complex programmable logic device, the device comprises: An acquisition module, used for acquiring target data transmitted by the master device to the slave device based on the first integrated circuit bus; A detection module, used for detecting whether the master device has completed sending one byte of data to the slave device according to the target data; a confirmation module, configured to confirm that the master device is about to send a confirmation character bit to the slave device in response to determining that the master device has completed sending the one byte of data to the slave device; and The takeover module is used to take over the first integrated circuit bus between the master device and the slave device, turn off the transparent transmission mode between the master device and the slave device, and control the master device and / or the slave device.

19. An electronic device, characterized in that: include: A complex programmable logic device, used to execute the clock stretching processing method in the integrated circuit bus transparent transmission mode described in any one of claims 1 to 17.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the clock stretching processing method in the integrated circuit bus transparent transmission mode according to any one of claims 1 to 17.

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