Display panel and manufacturing method therefor, and display device

Abstract

Embodiments of the present disclosure provide a display panel and a manufacturing method therefor, and a display device. The display panel comprises a backplane and a light-emitting unit layer arranged on the backplane. The light-emitting unit layer comprises a first electrode layer, a pixel defining layer, a light-emitting function layer, and a second electrode layer which are arranged in sequence. The first electrode layer comprises first electrodes and an auxiliary electrode which are electrically insulated from each other. The pixel defining layer comprises first openings formed corresponding to the first electrodes and a second opening formed corresponding to the auxiliary electrode; the first openings expose at least parts of the first electrodes, and the second opening exposes at least part of the auxiliary electrode. The light-emitting function layer comprises a third opening communicated with the second opening, and the second electrode layer is electrically connected to the auxiliary electrode by means of the third opening and the second opening which are communicated. The auxiliary electrode, the second opening, and the third opening are all located in a display area.

Description

Display panel and manufacturing method thereof, and display device

[0001] This application claims priority to Chinese patent application No. 202311726936.8 filed on December 14, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) has been widely used in the display field due to its advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed and flexible display.

[0004] Summary of the Invention

[0005] On the one hand, a display panel is provided. The display panel includes a backplane and a light-emitting unit layer arranged on the backplane. The light-emitting unit layer includes a first electrode layer, a pixel defining layer, a light-emitting functional layer, and a second electrode layer arranged in sequence in a direction away from the backplane. The first electrode layer includes a plurality of first electrodes and an auxiliary electrode, and the plurality of first electrodes are electrically insulated from the auxiliary electrode. The pixel defining layer includes a plurality of first openings arranged corresponding to the plurality of first electrodes, and a second opening arranged corresponding to the auxiliary electrode; each first opening exposes at least a portion of a first electrode, and the second opening exposes at least a portion of the auxiliary electrode. The light-emitting functional layer includes a third opening, the third opening is connected to the second opening, and the second electrode layer is electrically connected to the auxiliary electrode through the third opening and the second opening. The auxiliary electrode, the second opening, and the third opening are all located in the display area.

[0006] In some embodiments, in an orthographic projection onto the back plate, the third opening falls within the range of the auxiliary electrode, and a distance exists between a boundary of the third opening and a boundary of the auxiliary electrode.

[0007] In some embodiments, the interval between adjacent first electrodes and auxiliary electrodes is W1, and W1 is ≥ 2 μm.

[0008] In some embodiments, the light-emitting functional layer covers sidewalls of the second opening.

[0009] In some embodiments, the display panel includes a plurality of sub-pixels located within a display area, each sub-pixel including a first electrode, a light-emitting functional layer, and a portion of the second electrode layer corresponding to the first electrode. The second opening and the third opening are located between two adjacent sub-pixels and are spaced apart from each other.

[0010] In some embodiments, the light-emitting functional layer includes a plurality of third openings, and the plurality of third openings are evenly distributed in the display area.

[0011] In some embodiments, in an orthographic projection onto the back plate, the third opening falls within the range of the second opening; a distance between a center of the third opening and a boundary of the third opening is W2, where W2 ≥ 8 μm.

[0012] In some embodiments, the centers of the second opening and the third opening coincide with each other, and a distance between the center of the second opening and a boundary of the auxiliary electrode is W3, where W3 is ≥9.5 μm.

[0013] In some embodiments, a backplane includes: a base substrate, a first source-drain conductive layer, and a first planarization layer. The first source-drain conductive layer is disposed between the base substrate and the first electrode layer; the first source-drain conductive layer includes a first conductive pattern located in the display area. The first planarization layer is disposed between the first source-drain conductive layer and the first electrode layer; the planarization layer includes a fourth opening, through which the auxiliary electrode is electrically connected to the first conductive pattern.

[0014] In some embodiments, the backplane further comprises: a gate conductive layer disposed between the first source-drain conductive layer and the base substrate, wherein the gate conductive layer comprises a second conductive pattern located in the display area, and the second conductive pattern is electrically connected to the first conductive pattern.

[0015] In some embodiments, the backplane further comprises: a second source-drain conductive layer disposed between the first planar layer and the first electrode layer, and a second planar layer disposed between the second source-drain conductive layer and the first electrode layer. The second source-drain conductive layer includes a third conductive pattern located in the display area, the second planar layer includes a fifth opening, the auxiliary electrode is electrically connected to the third conductive pattern through the fifth opening, and the third conductive pattern is electrically connected to the first conductive pattern through a fourth opening.

[0016] In some embodiments, at least one of the first conductive pattern, the second conductive pattern, and the third conductive pattern is a VSS auxiliary signal line.

[0017] In some embodiments, the display panel pixel density is greater than or equal to 450 PPI.

[0018] In another aspect, a display device is provided, comprising: a display panel according to any one of the above embodiments and a circuit board, wherein the circuit board is electrically connected to the display panel.

[0019] In another aspect, a method for manufacturing a display panel is provided, wherein the method comprises the following steps.

[0020] A first electrode layer is formed on the back plate; the first electrode layer includes a plurality of first electrodes and an auxiliary electrode, and the plurality of first electrodes are electrically insulated from the auxiliary electrode.

[0021] A pixel defining layer is formed on the first electrode layer; the pixel defining layer includes a plurality of first openings corresponding to the plurality of first electrodes, and a second opening corresponding to the auxiliary electrodes; each first opening exposes at least a portion of a first electrode, and each second opening exposes at least a portion of the auxiliary electrode.

[0022] A light-emitting functional layer is formed on the pixel defining layer, and a portion of the light-emitting functional layer is removed by a laser etching process to form a third opening in the light-emitting functional layer that penetrates the second opening.

[0023] A second electrode layer is formed on the light-emitting functional layer. The second electrode layer is electrically connected to the auxiliary electrode through the third opening and the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of a display device according to some embodiments;

[0026] FIG2 is a planar structural diagram of a display device according to some embodiments;

[0027] FIG3 is a cross-sectional structural diagram of a display panel according to some embodiments, obtained along the cross-sectional line CC in FIG2 ;

[0028] FIG4 is a cross-sectional structural diagram of a display panel according to some embodiments, obtained along the cross-sectional line DD in FIG2 ;

[0029] FIG5 is a flow chart of a method for manufacturing a display panel according to some embodiments;

[0030] FIG6 is a cross-sectional structural diagram corresponding to steps A1 and A2 of the preparation method shown in FIG5 ;

[0031] FIG7 is a cross-sectional structural diagram corresponding to step A3 of the preparation method shown in FIG5 ;

[0032] FIG8 is a cross-sectional structural diagram corresponding to step A4 of the preparation method shown in FIG5 ;

[0033] FIG9 is a cross-sectional structural diagram corresponding to step A5 of the preparation method shown in FIG5 ;

[0034] FIG10 is a flow chart of a method for manufacturing a display panel according to some other embodiments;

[0035] FIG11 is a cross-sectional structural diagram corresponding to steps S1 and S2 of the preparation method shown in FIG10 ;

[0036] FIG12 is a cross-sectional structural diagram corresponding to step S3 of the preparation method shown in FIG10 ;

[0037] FIG13 is a cross-sectional structural diagram corresponding to step S4 of the preparation method shown in FIG10 ;

[0038] FIG14 is a cross-sectional structural diagram of a display panel according to some embodiments, obtained along the cross-sectional line CC in FIG2 ;

[0039] FIG15 is a partially enlarged structural diagram of a display area of ​​a display panel according to some embodiments;

[0040] FIG16 is an enlarged structural diagram of area F in FIG13 ;

[0041] FIG17 is a cross-sectional structural diagram of a display panel according to some other embodiments, obtained along the cross-sectional line CC in FIG2 ;

[0042] FIG18 is a cross-sectional structural diagram of a display panel according to still other embodiments, obtained along the cross-sectional line CC in FIG2 ;

[0043] FIG19 is a cross-sectional structural diagram of a display panel according to some further embodiments, obtained along the cross-sectional line CC in FIG2 ;

[0044] FIG. 20 is a planar structural diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0055] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any device that displays, whether in motion (e.g., video), stationary (e.g., still images), text, or images. More specifically, it is contemplated that the embodiments described herein can be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0058] The display device 1000 includes a display panel 100 and a circuit board 200, wherein the display panel 100 is electrically connected to the circuit board 200. The display device 1000 may further include a frame and other electronic components, wherein the display panel 100 may be disposed within the frame, for example.

[0059] The circuit board 200 is configured to send a driving signal, such as a display driving signal and / or a touch driving signal, to the display panel 100. Driven by the circuit board 200, the display panel 100 displays images and / or implements touch operations.

[0060] The circuit board 200 includes but is not limited to a PCB (Printed Circuit Board) or an FPC (Flexible Printed Circuit).

[0061] The display panel 100 includes but is not limited to an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel or a micro light emitting diode (Micro LED) display panel, etc., and the present disclosure does not make any specific limitations on this.

[0062] The display panel 100 may be of various types and may be selected according to actual needs. Hereinafter, some embodiments of the present disclosure will be described by taking the display panel 100 as an OLED display panel as an example.

[0063] In some embodiments, as shown in FIG2 , the display panel 100 includes a display area AA and a peripheral area AN located at least on one side of the display area AA. The peripheral area AN includes a bonding area BB located on a side of the display panel 100 for connecting to the circuit board 200. The circuit board 200 is electrically connected to the display panel 100 within the bonding area BB.

[0064] The peripheral area AN may be located on one side of the display area AA, or on two adjacent or opposite sides of the display area AA, or surround the display area AN, etc., and may be adaptively designed according to needs, which is not limited in the present disclosure.

[0065] Based on this, in some examples, as shown in FIG2 , the display panel 100 includes a display area AA and a peripheral area AN surrounding the display area AA, the binding area BB and the circuit board 200 are located on the same side of the display area AA, and the circuit board 200 is electrically connected to the display panel 100 within the binding area BB. In other examples, the display panel 100 includes a peripheral area AN located on one side of the display area AA, at least a portion of the peripheral area AN serves as the binding area BB, and the circuit board 200 is electrically connected to the display panel 100 within the binding area BB.

[0066] In some embodiments, as shown in FIG. 2 , a plurality of pixels are disposed in the display area AA, and each pixel includes at least three sub-pixels P of different colors.

[0067] Based on this, in some examples, as shown in FIG2 , each subpixel P includes at least a first color subpixel, a second color subpixel, and a third color subpixel, where the first color, the second color, and the third color are three primary colors, such as red, green, and blue. In other examples, the subpixel P also includes a fourth color subpixel, such as white.

[0068] The structure of the sub-pixel P is exemplarily described below.

[0069] As shown in FIG3 , each sub-pixel P includes, for example, a light-emitting unit 201. Each light-emitting unit 201 includes a first electrode 211, a light-emitting portion 221, and a second electrode 231, which are stacked in a direction away from the backplane 10. Each light-emitting unit 201 can emit light of a single color, such as red, green, or blue. The first electrode 211 is an anode, and correspondingly, the second electrode 231 is a cathode; alternatively, the first electrode 211 is a cathode, and correspondingly, the second electrode 231 is an anode.

[0070] Each sub-pixel P further includes a pixel driving circuit coupled to the light-emitting unit 201. The pixel driving circuit is configured to drive the light-emitting unit 201 connected thereto to emit light. The pixel driving circuit includes a transistor T, wherein one electrode (the first electrode S or the second electrode D) of the transistor T other than the control electrode is electrically connected to the first electrode 211 of the light-emitting unit 201.

[0071] The film layer structure of the display panel 100 is exemplarily described below.

[0072] In some embodiments, as shown in FIG3 , the display panel 100 includes a backplane 10 , which includes a base substrate 11 , a semiconductor layer, a first gate insulating layer GI1 , a gate conductive layer Gate, a second gate insulating layer GI2 , and a first source / drain conductive layer SD1 stacked in sequence.

[0073] For example, the substrate 11 may be made of a rigid substrate and / or a flexible substrate. Rigid substrate materials include, but are not limited to, rigid materials such as glass, quartz, and plastic. Flexible substrate materials include, but are not limited to, flexible materials such as FPC and PI (Polyimide) film, PC (Polycarbonate), or PVC (Polyvinyl Chloride).

[0074] It should be noted that the material selection of the base substrate 11 is related to the specific design of the display panel 100 and can be selected according to actual needs. It is only used as an example here and does not limit the present disclosure.

[0075] For example, as shown in FIG3 , the semiconductor layer includes an active layer 12 of each transistor T. Transistor T may be a low-temperature polysilicon thin-film transistor, i.e., the semiconductor layer is made of low-temperature polysilicon. Transistor T may also be an oxide thin-film transistor, i.e., the semiconductor layer is made of a metal oxide, such as indium gallium zinc oxide or indium gallium tin oxide.

[0076] Exemplarily, as shown in FIG3 , the gate conductive layer Gate includes a gate conductive pattern. The gate conductive pattern overlaps with the orthographic projection of the active layer 12 on the base substrate 11 . The overlapping portion of the gate conductive pattern and the active layer 12 serves as the control electrode G of each transistor T. The first electrode S and the second electrode D of the transistor T are located in the first source-drain conductive layer SD1 .

[0077] In some embodiments, as shown in FIG. 3 , the backplane 10 further includes a PI layer 14 disposed on the base substrate 11 .

[0078] When glass is selected as the material of the base substrate 11, by forming a PI layer on the glass substrate, the stress on the glass substrate in the subsequent preparation process of the backplane 10 can be effectively reduced, thereby avoiding cracks, breakage and other problems of the glass substrate due to stress during the preparation of the display panel 100, thereby improving the preparation yield of the display panel 100.

[0079] In some embodiments, as shown in FIG. 3 , the backplane 10 further includes a buffer layer 13 disposed on the base substrate 11 .

[0080] For example, the buffer layer 13 may be disposed on the base substrate 11 and adhered to the base substrate 11 , or the buffer layer 13 may be disposed on a side of the PI layer 14 away from the base substrate 11 .

[0081] By setting the buffer layer 13, during the subsequent preparation process of the display panel 100, for example, when forming film layer structures such as the semiconductor layer, the gate conductive layer Gate and the first source and drain conductive layer SD1, the stress on the glass substrate in the subsequent preparation process of the backplane 10 can be effectively reduced, thereby avoiding problems such as cracks and breakage of the glass substrate due to stress during the preparation process of the display panel 100, thereby improving the preparation yield of the display panel 100.

[0082] In some embodiments, as shown in FIG. 3 , the back plate 10 further includes an interlayer dielectric layer ILD (Inter Layer Dielectric) disposed between the gate conductive layer Gate and the first source and drain conductive layer SD1 .

[0083] By way of example, the material of the interlayer dielectric layer ILD includes, but is not limited to, silicon oxide.

[0084] By forming an interlayer dielectric layer ILD between the gate conductive layer Gate and the first source and drain conductive layer SD1, electrical isolation is formed between the control electrode G of the transistor T and the first electrode S and the second electrode D, which can effectively reduce the parasitic capacitance between the conductive material and the substrate 11 and improve the parasitic field effect transistor formed by the conductive material spanning different regions.

[0085] Based on this, in some embodiments, as shown in FIG3 , the display panel 100 further includes a light-emitting unit layer 20 disposed on the backplane 10 . The light-emitting unit layer 20 is used to form a plurality of light-emitting units 201 in the plurality of sub-pixels P. The light-emitting unit layer 20 includes a first electrode layer 21 , a pixel defining layer (PDL), a light-emitting functional layer 22 , and a second electrode layer 23 , which are sequentially disposed in a direction away from the backplane 10 .

[0086] 3 , multiple first electrodes 211 are located in the first electrode layer 21 and are separated from each other. Multiple light-emitting portions 221 are located in the light-emitting functional layer 22 and are separated from each other. Multiple second electrodes 231 are located in the second electrode layer 23.

[0087] The multiple second electrodes 231 located in the second electrode layer 23 means that the second electrode layer 22 includes multiple second electrodes 231, and the multiple second electrodes 231 are connected to each other; or, as shown in FIG3 , the second electrode layer 23 is a single film structure, and the portion of the second electrode layer 23 within the area defined by each light-emitting unit 201 serves as the second electrode 231 of the sub-pixel P. The first electrode layer 21 is an anode layer, and accordingly, the second electrode layer 22 is a cathode layer; or, the first electrode layer 21 is a cathode layer, and accordingly, the second electrode layer 22 is an anode layer.

[0088] As shown in FIG3 , the pixel defining layer PDL includes a plurality of first openings K1 corresponding to the plurality of first electrodes 211 . Each first opening K1 exposes at least a portion of a first electrode 211 , and at least a portion of each light emitting portion 221 is located within a first opening K1 .

[0089] Exemplarily, as shown in FIG. 3 , the back plate 10 further includes: a first planar layer PLN1 , disposed between the first source-drain conductive layer SD1 and the light-emitting unit layer 20 .

[0090] By setting the first flat layer PLN1, the surface of the back panel 10 can be filled and flat, so that the film thickness of each part of the back panel 10 is basically consistent, which is beneficial for the subsequent formation of the light-emitting unit layer 20. The thickness of each film layer structure included in the light-emitting unit layer 20 can be basically consistent, thereby ensuring the display uniformity of the display panel 100.

[0091] The following description takes the second electrode layer 23 as an example of a film structure of a whole layer. It should be noted that, in order to facilitate the description of the specific structure of the display panel 100, the portion of the second electrode layer 23 corresponding to the sub-pixel P is referred to as the second electrode 231 of the sub-pixel P.

[0092] 4 , the backplane 10 includes a VSS bus 101 disposed on the base substrate 11. The VSS bus 101 is disposed in the peripheral area AN. The VSS bus 101 is disposed on at least one side of the display area AA and extends into the bonding area BB.

[0093] Exemplarily, when the backplane 10 is a single SD structure, that is, the backplane 10 includes a source-drain conductive layer: a first source-drain conductive layer SD1, the VSS bus 101 can be located in the first source-drain conductive layer SD1 and / or in the gate conductive layer G.

[0094] In the case where the first electrode layer 21 is an anode layer and the second electrode layer 23 is a cathode layer, the second electrode layer 23 covers the display area AA and extends into the peripheral area AN and is electrically connected to the VSS bus 101. For example, as shown in FIG4 , the second electrode layer 23 is connected to the VSS bus 101 in the backplane 10 through a perforation in the peripheral area AN.

[0095] The following is an exemplary description of the configuration of the VSS bus 101 based on the case where the peripheral area AN surrounds the display area AA. It should be noted that the following is only an exemplary description for a better understanding of the technical solution of the present disclosure and is not intended to limit the present disclosure.

[0096] The VSS bus 101 may be disposed on one side of the display area AA and adjacent to the binding area BB, with the end of the VSS bus 101 near the binding area BB extending into the binding area BB. Alternatively, the VSS bus 101 may surround the remaining sides of the display area AA except for the portion used to bind the circuit board 200, with both ends of the VSS bus 101 extending from both sides of the binding area BB into the binding area BB. Alternatively, on the side where the display panel 100 is bound to the circuit board 200, the width of the peripheral area AN is greater than the width of the binding area BB, and the VSS bus 101 may surround the display area AA and extend into the binding area BB on the side of the display area AA near the binding area BB.

[0097] Since the distances between the second electrodes 231 and the VSS bus 101 of each sub-pixel P in the display panel 100 are not exactly the same, when the display panel 100 emits light, the driving current I of each light-emitting unit 201 is the same. The greater the distance between the second electrode 231 and the VSS bus 101, the longer the transmission distance of the VSS signal transmitted from the VSS bus 101 to the second electrode 231. Along the transmission path of the VSS signal, the greater the resistance R between the VSS bus 101 and the second electrode 231, the significantly lower the driving voltage U1 applied to the light-emitting unit 201 corresponding to the second electrode 231; wherein, U1 = U0 - IR, U0 is the target driving voltage applied to the light-emitting unit 201, and U1 is the driving voltage actually applied to the light-emitting unit 201.

[0098] It can be seen that as the size of the display panel 100 increases, the IR Drop problem in the display panel 100 becomes more obvious, the display uniformity of the display panel 100 becomes worse, and the display effect becomes worse.

[0099] It should be noted that when the display panel 100 is large, for example, when the display panel 100 is greater than or equal to 16 inches, the IR Drop problem in the display panel 100 can lead to poor display quality of the display panel 100. When the display panel 100 is smaller than 16 inches, the above problem may also occur in the display panel 100.

[0100] In addition, as the display brightness of the display panel 100 increases, for example, the peak brightness of the display panel 100 is greater than or equal to 800 nits, the driving current I required for the sub-pixel P to emit light also increases. In this way, the IR Drop problem of the display panel 100 becomes more obvious, and the display uniformity of the display panel 100 decreases.

[0101] To solve the above problems, embodiments of the present disclosure provide a display panel 100 and a method for manufacturing the same. The structure of the display panel 100 and the method for manufacturing the same are described below.

[0102] As shown in FIG5 , the preparation method includes steps A1 to A5.

[0103] A1. As shown in FIG6 , a first electrode layer 21 is formed on the backplane 10. The first electrode layer 21 includes a plurality of first electrodes 211 and an auxiliary electrode 212. The plurality of first electrodes 211 and the auxiliary electrode 212 are electrically insulated.

[0104] For example, the number of the auxiliary electrodes 212 may be one or more and may be adaptively designed according to actual needs.

[0105] A2. As shown in FIG6 , a pixel defining layer (PDL) is formed on the first electrode layer 21. The pixel defining layer (PDL) covers the auxiliary electrode 212 and includes a plurality of first openings K1 corresponding to the plurality of first electrodes 211. Each first opening K1 exposes at least a portion of a first electrode 211.

[0106] Exemplarily, the plurality of first electrodes 211 are separated from each other.

[0107] A3. As shown in FIG7 , a light emitting functional layer 22 is formed on the pixel definition layer PDL. The light emitting functional layer 22 includes a plurality of light emitting portions 221 corresponding to the plurality of first electrodes 211 , and at least a portion of each light emitting portion 221 is located within the first opening K1 .

[0108] Illustratively, the plurality of light emitting portions 221 are separated from each other.

[0109] Exemplarily, in addition to the portion of the light-emitting portion 221 located within the first opening K1, the light-emitting portion 221 also covers the sidewalls of the first opening K1 and extends to the upper surface of the pixel defining layer PDL. The upper surface of the pixel defining layer PDL refers to the side surface of the pixel defining layer PDL away from the backplane 10.

[0110] A4. As shown in FIG8 , a laser etching process is used to remove part of the light-emitting functional layer 22 and the pixel defining layer PDL to form a connection hole L that penetrates from the upper surface of the light-emitting functional layer 22 through the pixel defining layer PDL and reaches the auxiliary electrode 212 .

[0111] The upper surface of the light-emitting functional layer 22 refers to the surface of the light-emitting functional layer 22 away from the back plate 10 . The upper surface of the base substrate 11 refers to the surface of the base substrate 11 facing the light-emitting functional layer 22 .

[0112] Illustratively, the laser acts on the light-emitting functional layer 22 in a direction perpendicular to the upper surface of the base substrate 11. The laser first etches away a portion of the light-emitting functional layer 22 to form a third opening K3 corresponding to the auxiliary electrode 212 in the light-emitting functional layer 22; then, the laser etches away a portion of the pixel defining layer PDL to form a second opening K2 corresponding to the auxiliary electrode 212 in the pixel defining layer PDL; the intersecting third opening K3 and second opening K2 constitute a connecting hole L.

[0113] A5. As shown in FIG. 9 , a second electrode layer 23 is formed on the light-emitting functional layer 22 . The second electrode layer 23 is electrically connected to the auxiliary electrode 212 through the connection hole L.

[0114] Accordingly, as shown in FIG9 , in some embodiments, the display panel 100 is formed by the above-mentioned preparation method (steps A1 to A5). In the display panel 100, the first electrode layer 21 further includes at least one auxiliary electrode 212, and the first electrode 211 is electrically insulated from the auxiliary electrode 212. The pixel defining layer PDL further includes a second opening K2 corresponding to the auxiliary electrode 212, and the second opening K2 exposes at least a portion of the auxiliary electrode 212. The light-emitting functional layer 22 includes a third opening K3, and the third opening K3 is connected to the second opening K2. The second electrode layer 23 is electrically connected to the auxiliary electrode 212 through the third opening K3 and the second opening K2. The auxiliary electrode 212, the second opening K2, and the third opening K3 are all located in the display area AA. The second electrode layer 23 covers the sidewalls of the second opening K2 and the third opening K3.

[0115] The second electrode layer 23 is electrically connected to the auxiliary electrode 212 through the through openings on the light-emitting unit layer 22 and the pixel definition layer PDL, which can reduce the resistance of the second electrode layer 23, thereby reducing the power consumption of the display panel 100; it can also reduce the impact of the IR Drop problem in the display panel 100, thereby improving the display uniformity of the display panel 100.

[0116] By providing the auxiliary electrode 212 in the first electrode layer 21 , the auxiliary electrode 212 can be formed simultaneously with the first electrode 211 , thereby improving the display uniformity of the display panel 100 and reducing the power consumption of the display panel 100 without adding any additional steps to prepare the display panel 100 .

[0117] When the pixel density of the display panel 100 is relatively low, for example, the pixel density of the display panel 100 is less than 450 PPI, the display panel 100 may adopt the structure of the above embodiment and / or be manufactured using the manufacturing method of the above embodiment.

[0118] When the pixel density of the display panel 100 is high, for example, the pixel density of the display panel 100 is greater than or equal to 450PPI, when laser etching is used to form the connection hole L, the laser needs to etch through the light-emitting functional layer 22 and the pixel definition layer PDL in sequence from one direction. In this way, the laser etching depth is deep. During the laser etching process, the laser energy may cause damage to the light-emitting portion 221 adjacent to the connection hole L, thereby affecting the light-emitting effect of the light-emitting unit 201.

[0119] Based on this, an embodiment of the present disclosure provides another display panel 100 and a manufacturing method thereof. The structure of the display panel 100 and the manufacturing method thereof are introduced below.

[0120] As shown in FIG10 , the preparation method includes steps S1 to S4.

[0121] S1. As shown in FIG11 , a first electrode layer 21 is formed on the back plate 10. The first electrode layer 21 includes a plurality of first electrodes 211 and an auxiliary electrode 212. The plurality of first electrodes 211 and the auxiliary electrode 212 are electrically insulated.

[0122] S2. As shown in FIG11 , a pixel defining layer (PDL) is formed on the first electrode layer 21. The pixel defining layer (PDL) includes a plurality of first openings K1 corresponding to the plurality of first electrodes 211, and second openings K2 corresponding to the auxiliary electrodes 212. Each first opening K1 exposes at least a portion of a first electrode 211, and each second opening K2 exposes at least a portion of an auxiliary electrode 212.

[0123] For example, the second opening K2 and the first opening K1 can be formed simultaneously or separately. For example, a whole pixel definition layer (PDL) is first formed, and then the first opening K1 and the second opening K2 are formed on the pixel definition layer (PDL). The second opening K2 and the first opening K1 can be formed simultaneously using a photolithography process.

[0124] For example, the second opening K2 may be formed by laser etching. Thus, when the second opening K2 is formed by laser etching, the laser energy used may be small due to the small laser etching depth, thereby preventing the laser energy from damaging the adjacent light emitting portion 221 .

[0125] S3 . As shown in FIG. 12 , a light emitting functional layer 22 is formed on the pixel definition layer PDL. A portion of the light emitting functional layer 22 is removed by laser etching to form a third opening K3 in the light emitting functional layer 22 that penetrates the second opening K2 .

[0126] In step S3, the portion of the light-emitting functional layer 22 in contact with the auxiliary electrode 212 is removed by laser etching to expose the auxiliary electrode 212. In this way, the laser etching depth is small, so when the third opening K3 is formed by laser etching, the laser energy used can be small, thereby preventing the laser energy from damaging the adjacent light-emitting portion 221.

[0127] Exemplarily, the laser used in step S3 may be UV light, pulsed laser, fluorescent laser light, or the like.

[0128] Exemplarily, the light-emitting functional layer 22 covers the sidewalls of the second opening K2 .

[0129] Exemplarily, the third opening K3 may be formed by a photolithography process or a laser etching process.

[0130] S4. As shown in FIG. 13 , a second electrode layer 23 is formed on the light-emitting functional layer 22 . The second electrode layer 23 is electrically connected to the auxiliary electrode 212 through the third opening K3 and the second opening K2 .

[0131] Accordingly, as shown in FIG. 13 , in some embodiments, the display panel 100 is formed by the above-mentioned manufacturing method (steps S1 to S4 ).

[0132] The display panel 100 formed through steps S1 to S4 has the same beneficial effects as the display panel 100 formed through steps A1 to A5. Moreover, compared with the display panel 100 formed through steps A1 to A5, it can avoid laser energy damaging the light-emitting functional layer 22 during the preparation process of the display panel 100, thereby ensuring the display effect of the display panel 100.

[0133] Figure 15 is a partially enlarged structural diagram within the display area AA of the display panel 100 according to some embodiments. In order to clearly describe the relative position between the third opening K3 and the light-emitting unit 201, Figure 15 only shows the light-emitting parts 221 of multiple light-emitting units 201 and multiple third openings K3.

[0134] In some embodiments, as shown in Figure 13, the pixel definition layer (PDL) includes a plurality of first openings K1 corresponding to the plurality of first electrodes 211, and second openings K2 corresponding to the auxiliary electrodes 212. Each first opening K1 exposes at least a portion of a first electrode 211, and each second opening K2 exposes at least a portion of the auxiliary electrode 212. The light-emitting functional layer 22 includes a third opening K3 that intersects the second openings K2. The second electrode layer 23 is electrically connected to the auxiliary electrode 212 through the third opening K3 and the second opening K2. The auxiliary electrode 212, the second openings K2, and the third opening K3 are all located in the display area AA.

[0135] By adding an auxiliary electrode 212 in the first electrode layer 21, the second electrode layer 23 contacts the auxiliary electrode 212 after passing through the third opening K3 on the light-emitting functional layer 22 and the second opening K2 on the pixel definition layer PDL, thereby reducing the resistance of the second electrode layer 23, thereby reducing the power consumption of the display panel 100, and effectively reducing the impact of the IR Drop problem in the display panel 100, thereby improving the display uniformity of the display panel 100.

[0136] Before forming the light-emitting functional layer 22, a second opening K2 is already formed in the pixel definition layer PDL. The second opening K2 and the first opening K1 can be formed in the same step, eliminating the need for additional fabrication steps. Furthermore, before forming the second electrode layer 23, only the portion of the light-emitting functional layer 22 that contacts the auxiliary electrode 212 needs to be removed to achieve electrical contact between the second electrode layer 23 and the auxiliary electrode 212.

[0137] The third opening K3 can be formed using a photolithography process or a laser etching process, which provides greater manufacturing flexibility. Furthermore, since the light-emitting functional layer 22 is relatively thin, when the laser etching process is used to form the third opening K3, the laser energy used is also relatively low, which can prevent the laser energy from damaging the portion of the light-emitting functional layer 22 adjacent to the third opening K3, thereby ensuring the display effect of the display panel 100.

[0138] 14 , the display panel 100 further includes at least one third electrode 24 disposed on a side of the second electrode layer 23 away from the backplane 10 . The third electrode 24 may correspond to the first electrode 211 and / or the auxiliary electrode 212 .

[0139] By providing the third electrode 24 , the resistance of the second electrode layer 23 can be reduced, thereby reducing the power consumption of the display panel 100 .

[0140] FIG15 is a partial enlarged structural diagram of the display area AA of the display panel 100 . To clearly illustrate the distribution of the third openings K3 in the display area AA, FIG15 only shows the light emitting units 201 and the third openings K3 .

[0141] In some embodiments, as shown in FIG. 15 , the light-emitting functional layer 22 includes a plurality of third openings K3 , and the plurality of third openings K3 are evenly distributed in the display area AA.

[0142] The first electrode layer 21 includes a plurality of auxiliary electrodes 212. Thus, the light-emitting functional layer 22 includes a plurality of third openings K3, and the pixel defining layer PDL includes a plurality of second openings K2. The greater the number of auxiliary electrodes 212 connected to the second electrode layer 23, the greater the effect of reducing the resistance of the second electrode layer 23, and the greater the effect of reducing the power consumption of the display panel 100.

[0143] Moreover, the plurality of third openings K3 are evenly distributed in the display area AA, and correspondingly, the plurality of auxiliary electrodes 212 are also evenly distributed in the display area AA. In this way, the second electrode layer 23 can have a plurality of evenly distributed positions for reducing resistance in the display area AA, which can better achieve the effect of reducing the screen cross-voltage of the display panel 100, and the display uniformity of the display panel 100 is better, and the display effect is better.

[0144] It should be noted that the number of the auxiliary electrode 212 is at least one, and accordingly, the number of the third opening K3 and the second opening K2 is at least one. The second electrode layer 23 is in contact with the auxiliary electrode 212 through the third opening K3 and the second opening K2 to achieve electrical connection. Therefore, the more the number of auxiliary electrodes 212, the more the number of the third opening K3 and the second opening K2.

[0145] For example, when the display panel 100 includes a plurality of third openings K3 , the spacing distance between the centers of the plurality of third openings K3 is greater than or equal to 0.1 mm and less than or equal to 10 mm.

[0146] It should be noted that, in the case where the light-emitting functional layer 22 includes multiple third openings K3, the range of the intervals between the third openings K3 is not limited to the above range (0.1mm~10mm), and can also be smaller or larger. The adaptive design is carried out according to actual needs. The above is only an exemplary description and not a limitation of the present disclosure.

[0147] In some embodiments, Figure 16 is an enlarged structural diagram of region F in Figure 13. As shown in Figure 16, in the orthographic projection onto the back plate 10, the third opening K3 falls within the range of the auxiliary electrode 212, and there is a gap between the boundary of the third opening K3 and the boundary of the auxiliary electrode 212.

[0148] In this way, when the third opening K3 is formed, the third opening K3 only exposes at least a portion of the upper surface of the auxiliary electrode 212 , thereby ensuring effective connection between the second electrode layer 23 and the auxiliary electrode 212 .

[0149] In some embodiments, as shown in FIG. 16 , the interval between adjacent first electrodes 211 and auxiliary electrodes 212 is W1 , where W1 ≥ 2 μm.

[0150] By limiting the spacing between the first electrode 211 and the auxiliary electrode 212, the problem of short circuit caused by the first electrode 211 and the auxiliary electrode 212 being in contact with each other, which causes the first electrode layer 21 and the second electrode layer 23 to be conductive, can be effectively avoided. While reducing the power consumption of the display panel 100 and improving the display uniformity, it is also beneficial to achieve a high pixel density of the display panel 100 and improve the display quality.

[0151] The auxiliary electrode 212 is arranged in the same layer as the multiple first electrodes 211, that is, the auxiliary electrode 212 is arranged in the spacing area between the multiple first electrodes 211. The larger the spacing distance between the auxiliary electrode 212 and the first electrode 211, the larger the spacing between adjacent first electrodes 211, that is, the larger the spacing between adjacent light-emitting units 201, and the lower the pixel density of the display panel 100.

[0152] 16 , the third opening K3 falls within the range of the second opening K2 in the orthographic projection onto the back plate 10. The distance between the center of the third opening K3 and the boundary of the third opening K3 is W2, where W2 ≥ 8 μm.

[0153] The size of the third opening K3 is related to the contact area between the second electrode layer 23 and the auxiliary electrode 212 . Therefore, the size of the third opening K3 must at least meet the effective contact between the second electrode layer 23 and the auxiliary electrode 212 , thereby ensuring electrical connection between the second electrode layer 23 and the auxiliary electrode 212 .

[0154] By controlling the spacing between the center of the third opening K3 and the boundary of the third opening K3 , it is possible to ensure that the size of the third opening K3 can meet the requirements for effective connection between the second electrode layer 23 and the auxiliary electrode 212 .

[0155] In some embodiments, as shown in FIG. 16 , the centers of the second opening K2 and the third opening K3 coincide with each other, and the distance between the center of the second opening K2 and the boundary of the auxiliary electrode 212 is W3 , where W3 ≥ 9.5 μm.

[0156] By controlling the distance between the center of the second opening K2 and the boundary of the auxiliary electrode 212, it is possible to ensure that the position of the second opening K2 is within the range of the upper surface of the auxiliary electrode 212, thereby ensuring that the subsequently formed second electrode layer 23 can achieve effective connection with the auxiliary electrode 212, thereby avoiding the second electrode layer 23 from breaking in the second opening K2 and the third opening K3.

[0157] In combination with the above embodiments, it can be seen that the distance between the third opening K3 and the boundary of the auxiliary electrode 212 is W3-W2≥1.5μm, which can further ensure that the parts of the second electrode layer 23 located in the third opening K3 and the second opening K2 are both located on the auxiliary electrode 23, thereby ensuring effective connection between the second electrode layer 23 and the auxiliary electrode 212.

[0158] In some embodiments, as shown in FIG. 15 and FIG. 16 , the third opening K3 is located between two adjacent light emitting units 201 , and there is a gap j between the third opening K3 and the adjacent light emitting units 201 .

[0159] As shown in FIG15 , the plurality of light emitting units 201 include light emitting units 201 of at least three different colors. The sizes of the light emitting units 201 of different colors may be the same or different, and the interval between any two adjacent light emitting units 201 may be the same or different.

[0160] The interval between two adjacent light emitting units 201 mentioned here refers to the distance between the light emitting areas of the two adjacent light emitting units 201 . This distance may be the distance between two adjacent first openings K1 in the pixel defining layer PDL.

[0161] When the intervals between any two adjacent light-emitting units 201 are the same, the third opening K3 can be provided between any two adjacent light-emitting units 201. When the intervals between any two adjacent sub-pixels P are not completely the same, the second opening K2 and the third opening K3 can be provided between any two adjacent sub-pixels P, or between two adjacent sub-pixels P with a larger interval.

[0162] In some embodiments, as shown in FIG17 , a first source-drain conductive layer SD1 is disposed between the base substrate 11 and the first electrode layer 21. The first source-drain conductive layer SD1 also includes a first conductive pattern M1 located in the display area AA. A first planar layer PLN1 is disposed between the first source-drain conductive layer SD1 and the first electrode layer 21. The first planar layer PLN1 includes a fourth opening K4, through which the auxiliary electrode 212 is electrically connected to the first conductive pattern M1. The first electrode S and second electrode D of the transistor T are disposed in the same layer as the first conductive pattern M1. This further reduces the resistance of the second electrode layer 23 without adding additional fabrication steps, thereby further reducing the power consumption of the display panel 100 and improving the display uniformity of the display panel 100.

[0163] In some embodiments, as shown in FIG. 18 , the backplane 10 further includes: the gate conductive layer Gate includes a second conductive pattern M2 located in the display area AA, and the second conductive pattern M2 is electrically connected to the first conductive pattern M1 .

[0164] Exemplarily, the insulating dielectric layer ILD is provided with a via hole, and the second conductive pattern M2 and the first conductive pattern M1 are in contact with each other through the via hole on the insulating dielectric layer ILD to achieve electrical connection.

[0165] The control electrode of the transistor T is arranged in the same layer as the second conductive pattern M2. In this way, without adding additional preparation steps, the resistance of the second electrode layer 23 can be further reduced, thereby better reducing the power consumption of the display panel 100 and improving the display uniformity of the display panel 100.

[0166] In some embodiments, as shown in FIG19 , the backplane 10 further includes: a second source-drain conductive layer SD2 disposed between the first planar layer PLN1 and the first electrode layer 23, and a second planar layer PLN2 disposed between the second source-drain conductive layer SD2 and the first electrode layer 23. The second source-drain conductive layer SD2 includes a third conductive pattern M3 located in the display area AA, and the second planar layer PLN2 includes a fifth opening K5. The auxiliary electrode 212 is electrically connected to the third conductive pattern M3 through the fifth opening K5, and the third conductive pattern M3 is electrically connected to the first conductive pattern M1.

[0167] By providing the third conductive pattern M3, the second electrode layer 23 is electrically connected to the auxiliary electrode 212, the first conductive pattern M1 and the second conductive pattern M2, which can further reduce the resistance of the second electrode layer 23, thereby better reducing the power consumption of the display panel 100 and improving the display uniformity of the display panel 100.

[0168] It should be noted that when the backplane 10 is a single SD structure, that is, the backplane 10 includes a source-drain conductive layer: the first source-drain conductive layer SD1, the auxiliary electrode 212 directly contacts the first conductive pattern M1 through the fourth opening K4 on the first flat layer PLN1 to achieve electrical connection.

[0169] In the case where the backplane 10 has a dual SD structure, that is, the backplane 10 includes two source-drain conductive layers: a first source-drain conductive layer SD1 and a second source-drain conductive layer SD2, the auxiliary electrode 212 first contacts the third conductive pattern M3 located in the fourth opening K4 through the fifth opening K5 on the second flat layer PLN2 to achieve electrical connection; since the third conductive pattern M3 is electrically connected to the first conductive pattern M1, the auxiliary electrode 212 can be electrically connected to the first conductive pattern M1 through the third conductive pattern M3.

[0170] In some embodiments, as shown in FIG. 17 , FIG. 18 , FIG. 19 , and FIG. 20 , at least one of the first conductive pattern M1 , the second conductive pattern M2 , and the third conductive pattern M3 is a VSS auxiliary signal line.

[0171] Exemplarily, at least one of the first conductive pattern M1 , the second conductive pattern M2 , and the third conductive pattern M3 disposed in the display area AA is electrically connected to the VSS bus line 101 disposed in the peripheral area AN.

[0172] In this way, the conductive pattern M (at least one of the first conductive pattern M1, the second conductive pattern M2 and the third conductive pattern M3) that transmits the VSS signal transmits the VSS signal from the display area AA to the second electrode layer 23. While reducing the resistance of the second electrode layer 23, it can also reduce the transmission path length between the VSS signal and the second electrode 231, thereby reducing the voltage difference of the light-emitting unit 201 in the peripheral area of ​​the conductive pattern M, thereby reducing the impact of the IR Drop problem in the display panel 100, and thereby improving the display uniformity of the display panel 100.

[0173] The structure of the display panel 100 and the circuit board 200 shown in Figure 20 is a structural diagram of the display device 1000 during the process of binding the display panel 100 and the circuit board 200. In the actually formed display device 1000, the portion of the circuit board 200 that extends beyond the display panel 100 is bent to the other side of the display panel 100.

[0174] For example, during the preparation process of the display device 1000, one end of the circuit board 200 is first bound to the display panel 100 on the display side (the display side is the side of the display panel 100 on which the light-emitting unit layer is set, and the circuit board 200 can be electrically connected to the display panel 100 in the binding area BB on the display side), and then the other end of the circuit board 200 is bent to the other side of the display panel 100 opposite to the display side to obtain the display device 1000 as shown in Figure 2.

[0175] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: Comprising a display area, the display panel comprises: Back panel; a light-emitting unit layer disposed on the backplane; the light-emitting unit layer comprises a first electrode layer, a pixel defining layer, a light-emitting functional layer, and a second electrode layer, which are sequentially disposed in a direction away from the backplane; Wherein, the first electrode layer includes a plurality of first electrodes and an auxiliary electrode, and the plurality of first electrodes are electrically insulated from the auxiliary electrode; The pixel defining layer includes a plurality of first openings corresponding to the plurality of first electrodes, and a second opening corresponding to the auxiliary electrode; each of the first openings exposes at least a portion of one of the first electrodes, and the second openings expose at least a portion of the auxiliary electrode; The light-emitting functional layer includes a third opening, the third opening is connected to the second opening, and the second electrode layer is electrically connected to the auxiliary electrode through the third opening and the second opening; The auxiliary electrode, the second opening, and the third opening are all located in the display area.

2. The display panel according to claim 1, wherein: In an orthographic projection onto the back plate, the third opening falls within the range of the auxiliary electrode, and a distance exists between a boundary of the third opening and a boundary of the auxiliary electrode.

3. The display panel according to claim 1 or 2, wherein: The interval between adjacent first electrodes and the auxiliary electrodes is W1, and W1 is greater than or equal to 2 μm.

4. The display panel according to any one of claims 1 to 3, wherein: The light-emitting functional layer covers the sidewalls of the second opening.

5. The display panel according to any one of claims 1 to 4, wherein: The display panel includes a plurality of sub-pixels located in the display area, each of the sub-pixels includes a first electrode, the light-emitting functional layer, and a portion of the second electrode layer corresponding to the first electrode; The second opening and the third opening are located between two adjacent sub-pixels, and there is a gap between the second opening and the third opening and the adjacent sub-pixels.

6. The display panel according to any one of claims 1 to 5, wherein: The light-emitting functional layer includes a plurality of third openings, and the plurality of third openings are evenly distributed in the display area.

7. The display panel according to any one of claims 1 to 6, wherein: In an orthographic projection onto the back plate, the third opening falls within the range of the second opening; A distance between a center of the third opening and a boundary of the third opening is W2, and W2 ≥ 8 μm.

8. The display panel according to any one of claims 1 to 7, wherein: The centers of the second opening and the third opening coincide with each other, and a distance between the center of the second opening and a boundary of the auxiliary electrode is W3, where W3 is ≥9.5 μm.

9. The display panel according to any one of claims 1 to 8, wherein: The backplane comprises: substrate; a first source-drain conductive layer, disposed between the base substrate and the first electrode layer, the first source-drain conductive layer comprising a first conductive pattern located in the display area; The first planar layer is disposed between the first source-drain conductive layer and the first electrode layer; the planar layer includes a fourth opening, and the auxiliary electrode is electrically connected to the first conductive pattern through the fourth opening.

10. The display panel according to claim 9, wherein: The backplane further comprises: A gate conductive layer is provided between the first source-drain conductive layer and the base substrate; the gate conductive layer includes a second conductive pattern located in the display area, and the second conductive pattern is electrically connected to the first conductive pattern.

11. The display panel according to claim 10, wherein: The backplane further comprises: a second source-drain conductive layer, disposed between the first planar layer and the first electrode layer; the second source-drain conductive layer includes a third conductive pattern located in the display area; A second planar layer is arranged between the second source-drain conductive layer and the first electrode layer; the second planar layer includes a fifth opening, the auxiliary electrode is electrically connected to the third conductive pattern through the fifth opening, and the third conductive pattern is electrically connected to the first conductive pattern through the fourth opening.

12. The display panel according to claim 11, wherein: At least one of the first conductive pattern, the second conductive pattern, and the third conductive pattern is a VSS auxiliary signal line.

13. The display panel according to any one of claims 1 to 12, wherein: The pixel density of the display panel is greater than or equal to 450PPI.

14. A display device, characterized in that: include: The display panel according to any one of claims 1 to 13; A circuit board is electrically connected to the display panel.

15. A method for preparing a display panel, characterized in that: The preparation method comprises: forming a first electrode layer on the back plate; the first electrode layer comprises a plurality of first electrodes and an auxiliary electrode, wherein the plurality of first electrodes are electrically insulated from the auxiliary electrode; forming a pixel defining layer on the first electrode layer; the pixel defining layer comprising a plurality of first openings corresponding to the plurality of first electrodes, and a second opening corresponding to the auxiliary electrode; each of the first openings exposing at least a portion of one of the first electrodes, and each of the second openings exposing at least a portion of the auxiliary electrode; forming a light-emitting functional layer on the pixel defining layer, and removing a portion of the light-emitting functional layer by a laser etching process to form a third opening in the light-emitting functional layer that penetrates the second opening; A second electrode layer is formed on the light-emitting functional layer, and the second electrode layer is electrically connected to the auxiliary electrode through the third opening and the second opening.

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