Signal transmission method, related device and storage medium

Abstract

The present application provides a signal transmission method, which can be applied to an electronic system such as a computer device (such as a host) or a storage device (such as an SSD). The electronic system comprises an electronic device and one or more memories, and the electronic device is connected to the one or more memories by means of a parallel interface. The electronic device can configure different values for parameters used for the parallel interface to transmit signals by means of different links, thereby reducing the power consumption of the parallel interface while ensuring that the SI margin of the signal in each link meets requirements. The present application also provides a processing apparatus, a related device, and a computer-readable storage medium.

Description

Signal transmission method, related device and storage medium

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 22, 2023, with application number 202311795224.1 and application name “Signal Transmission Method, Related Equipment and Storage Medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a signal transmission method, related equipment and storage medium. Background Art

[0003] High-speed parallel buses are currently widely used in communications products, computers, and servers. For example, many wireless and data communications products utilize high-speed memories such as solid-state drives (SSDs) and double-data-rate synchronous dynamic random-access memory (DDR SDRAM). To ensure communication quality, parallel interfaces incorporate circuit designs that enhance signal integrity (SI), such as on-die termination (ODT). ODT reduces signal reflections between the transmitter and receiver, improving signal integrity.

[0004] As the operating frequency and transmission rate of parallel interfaces continue to increase, the signal integrity (SI) of the signals in the parallel bus continues to decline. To ensure that the SI margin meets the requirements, the resistance of the ODT in the parallel interface needs to be reduced accordingly. However, this will increase the power consumption of the parallel interface, thereby increasing chip heat generation and reducing reliability.

[0005] Summary of the Invention

[0006] The present application provides a signal transmission method, related equipment and storage medium, which are used to reduce the power consumption of a parallel interface while ensuring that the SI margin of the signal in the parallel bus meets the requirements, thereby helping to avoid increased heat generation and decreased reliability of the chip.

[0007] In a first aspect, the present application provides a signal transmission method in a communication system. The system includes an electronic device and one or more memories, wherein a parallel interface of the electronic device is connected to parallel interfaces of the one or more memories via multiple links. For ease of description, the parallel interface in the electronic device is referred to as a first parallel interface, and the parallel interfaces of the one or more memories are collectively referred to as a second parallel interface. The method may be performed by a processing device. The processing device may be provided in the electronic device. Optionally, the processing device may be connected to the first parallel interface.

[0008] The processing device may configure one or more parameters used by the target interface to transmit signals via at least two of the multiple links. For example, for a first link and a second link of the at least two links, the processing device may configure one or more parameters used by the target interface to transmit signals via the first link, and configure one or more parameters used by the target interface to transmit signals via the second link.

[0009] Afterwards, the processing device may control the first parallel interface to transmit multiple signals with the second parallel interface through the at least two links. The target interface includes the first parallel interface and / or the second parallel interface. When the target interface is the first parallel interface, the processing device may control the configured first parallel interface to transmit multiple signals with the second parallel interface through the at least two links. When the target interface is the second parallel interface, the processing device may control the first parallel interface to transmit multiple signals with the configured second parallel interface through the at least two links. When the target interface includes the first parallel interface and the second parallel interface, the processing device may control the configured first parallel interface to transmit multiple signals with the configured second parallel interface through the at least two links.

[0010] Through analysis, it is found that by adjusting the value of the parameter of the parallel interface transmitting the signal through the link, the SI of the signal in the link can be changed, and then the SI margin of the signal can be changed. In addition, the parameter configuration that makes the SI margin larger will usually increase the power consumption of the parallel interface. Conversely, the parameter configuration that makes the SI margin smaller can usually reduce the power consumption of the parallel interface. In addition, when the parameter configuration used for the parallel interface to transmit signals through different links is the same, although the power consumption of the parallel interface transmitting signals through these two links is the same or close, since different links generally have differences in wiring length, impedance consistency and crosstalk, the SI margin of the signal in different links is generally different. In this application, the link with a larger SI margin is referred to as a link with a better wiring condition.

[0011] Based on the above findings, the present application proposes that, for the first link and the second link in at least two links and the target parameters in the one or more parameters, the processing device can configure a first value for the target parameter used by the target interface to transmit the signal through the first link, and configure a second value for the target parameter used by the target interface to transmit the signal through the second link. Since the routing conditions of the first link and the second link are generally different, configuring the same value for the target parameters corresponding to the two will cause the SI margin of the link with better routing conditions to be much higher than the required threshold. By configuring different first values ​​and second values ​​for the target parameters corresponding to the two, it is beneficial to reduce the difference between the SI margin of the link with better routing conditions and the threshold, thereby helping to reduce the power consumption of the target interface in transmitting the signal through the two links while ensuring that the SI margins of the signals in the first link and the second link meet the requirements, thereby reducing the overall power consumption of the target interface, and helping to avoid increased heat generation and decreased reliability of the chip.

[0012] Assuming that after the processing device configures one or more parameters adopted by the target interface to transmit signals through a certain link according to a target parameter of a certain value, the SI margin of the signal in the link meets the requirements, this application refers to this value as the alternative value of the target parameter corresponding to the link. Among the multiple alternative values ​​of the target parameter corresponding to the link, this application refers to the alternative value that minimizes the power consumption of the target interface to transmit signals through the link as the optimal value of the target parameter corresponding to the link. Optionally, the processing device can determine the optimal value of the target parameter corresponding to each link, and then configure the target parameter adopted by the target interface to transmit signals through the corresponding link according to the optimal value of the target parameter corresponding to each link. Since the routing conditions of different links are usually different, the values ​​of the target parameters adopted by the configured target interface to transmit signals through any two of the at least two links can be different. In this way, it is beneficial to further reduce the overall power consumption of the target interface.

[0013] To reduce configuration complexity, the processing device may optionally determine at least one link group from the at least two links, where a single link group includes multiple links from the at least two links, and different link groups include different links. The processing device may configure the target parameters used by the target interface to transmit signals through each link in the same link group to have the same value. One of the at least one link group is a first link group that includes the first link. Accordingly, the first link group includes, in addition to the first link, other links other than the first link, and the processing device also configures the target parameters used by the target interface to transmit signals through the other links to have the first value.

[0014] Because the first link group includes a portion of at least two links (for example, the first link group does not include the second link), it is advantageous to assign all or a portion of the links other than the link with the worst routing condition (referred to as the worst link) to the first link group. This is advantageous, compared to configuring the same values ​​for the target parameters corresponding to the first link group and the target parameters corresponding to the worst link, in that manner, while ensuring that the SI margins of the signals in each link within the first link group meet the requirements, thereby reducing the power consumption of the target interface when transmitting signals through the first link group, thereby reducing the overall power consumption of the target interface and helping to avoid increased heat generation and reduced reliability of the chip.

[0015] Based on the above analysis, optionally, the processing device can divide multiple links with similar routing conditions into the first link group. This is conducive to the SI margin of the signal in each link in the first link group being close to the required threshold, thereby helping to reduce the power consumption of the target interface in transmitting signals through the first link group, thereby reducing the overall power consumption of the target interface, and helping to avoid increased heat generation and decreased reliability of the chip.

[0016] Signals can be transmitted between the first parallel interface and the second parallel interface through multiple channels. Since the routing conditions of each link in the same channel are generally close, the first link group can optionally include multiple links in the same channel, or in other words, the first link group is used to transmit signals (data) in the same channel.

[0017] The bit width of a single channel may include multiple bytes. Since the routing conditions of each link in the same byte are generally close, optionally, the first link group may include multiple links in the same byte, or in other words, the first link group is used to transmit signals (data) in the same byte.

[0018] Optionally, before the processing device configures one or more parameters used by the target interface to transmit signals through the first link and the second link respectively, the processing device may obtain a first value of the target parameter corresponding to the first link group from the firmware.

[0019] Optionally, before the processing device configures one or more parameters for the target interface to transmit signals via the first link and the second link, the processing device controls the target interface to transmit test signals via the first link group using multiple target parameters with different values. The processing device then determines the first value from the multiple different values ​​based on the SI margins of the multiple transmitted test signals. This facilitates ensuring that signals transmitted via the first link group using the target parameters with the first values ​​after the configuration meet SI margin requirements.

[0020] Assume that the multiple different values ​​include value 1, value 2, ..., value n. The processing device can control the target interface to use the target parameter with value 1 to transmit a test signal (recorded as test signal 1) through the first link group, control the target interface to use the target parameter with value 2 to transmit a test signal (recorded as test signal 2) through the first link group, ..., control the target interface to use the target parameter with value n to transmit a test signal (recorded as test signal n) through the first link group, where n is a positive integer greater than 1. Afterwards, the processing device can determine the first value from the multiple different values ​​according to SI margin 1 of test signal 1, SI margin 2 of test signal 2, ..., SI margin n of test signal n.

[0021] Optionally, the processing device may determine one or more values ​​from the multiple different values, where the SI margin of the test signal respectively transmitted by the target interface using the target parameters of the one or more values ​​is not less than a required threshold, and then, from the one or more values, determine the value with the lowest corresponding power consumption as the first value. This helps ensure that the SI margin of the signal in each link within the first link group meets the requirements, thereby reducing the power consumption of the target interface when transmitting the signal through the first link group, thereby reducing the overall power consumption of the target interface, and helping to avoid increased heat generation and reduced reliability of the chip.

[0022] Optionally, the first value may be the optimal value of the target parameter corresponding to the link with the worst routing condition in the first link group (referred to as the target link). Accordingly, the processing device may control the target interface to transmit test signals through the target link using multiple different values ​​of the target parameter, and then determine the first value from the multiple different values ​​based on the signal integrity (SI) margins of the multiple transmitted test signals.

[0023] This application does not limit the processing device to comparing the power consumption of signals transmitted by the target interface using different values ​​of the target parameter. Optionally, because the SI margin can not only be used to determine whether the SI margin of the signals in each link within the first link group meets the requirements, the processing device can evaluate the power consumption of the target interface transmitting signals according to the corresponding target parameter values ​​based on the SI margin of each test signal. Alternatively, the processing device can determine the power consumption of the target interface transmitting signals according to a certain target parameter value using a table or formula.

[0024] This application does not limit the type of the one or more parameters. Optionally, the one or more parameters include at least one of the following parameters: driving capability parameters, transmitting end equalization EQ parameters, on-chip termination ODT parameters and receiving end equalization EQ parameters. Among them, the receiving end equalization EQ parameters may include linear continuous time equalization CTLE parameters and / or decision feedback equalizer DFE parameters. The above parameters can not only affect the SI margin of the signal in the link, but also affect the power consumption of the parallel interface. By differentially configuring the above parameters corresponding to the first link and the second link, it is beneficial to reduce the power consumption of the parallel interface while ensuring the communication quality of the parallel interface.

[0025] Optionally, the multi-path signal is used to transmit data to be written to the one or more memories, and accordingly, the processing device can control the first parallel interface to send the multi-path signal to the second parallel interface through the at least two links. When the target interface is the first parallel interface, one or more parameters may include transmission parameters (for example, ODT parameters and / or transmission-end equalization EQ parameters). When the target interface is the second parallel interface, one or more parameters may include reception parameters (for example, drive capability parameters and / or reception-end equalization EQ parameters). When the target interface includes the first parallel interface and the second parallel interface, one or more parameters may include transmission parameters and reception parameters, and the processing device may configure the transmission parameters for the first parallel interface and configure the reception parameters for the second parallel interface.

[0026] Optionally, the multiplexed signals are used to transmit data read from the one or more memories, and accordingly, the processing device may control the first parallel interface to receive the multiplexed signals from the second parallel interface via the at least two links. When the target interface is the first parallel interface, the one or more parameters may include the aforementioned receive parameters. When the target interface is the second parallel interface, the one or more parameters may include the aforementioned send parameters. When the target interface includes the first parallel interface and the second parallel interface, the one or more parameters may include send parameters and receive parameters, and the processing device may configure send parameters for the second parallel interface and receive parameters for the first parallel interface.

[0027] In the optional solution described above, the processing device can configure one or more parameters used by the second parallel interface to transmit signals through the link. This application does not limit the specific configuration method. For example, the electronic device and the memory can be in a master-slave relationship, and the processing device can send a configuration signal to the parallel interface of the memory connected to the link, and the configuration signal is used to transmit configuration information, and the configuration information is used to determine the values ​​of one or more parameters, and the configuration signal is used to instruct the memory to configure its own parallel interface according to the values ​​indicated by the configuration information. The one or more parameters used by the signal transmitted through the link.

[0028] Optionally, the one or more memories include non-volatile flash memory (Nand Flash) and / or double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM). Accordingly, the first parallel interface and the second parallel interface can be a non-volatile flash memory interface (Nand Flash Interface, NFI) or a DDR SDRAM interface (referred to as DDR interface). The full name of "NAND" is "NOT AND", which stands for NAND gate.

[0029] This application does not limit the form of the memory. For example, multiple memories can be provided in dual inline memory modules (DIMMs), which are installed on the motherboard of the electronic device via DIMM connectors. Alternatively, the memory can be integrated with the electronic device on the same circuit board.

[0030] This application does not limit the type of processing device. For example, the processing device can be a hardware-implemented device. As an example, the processing device can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Alternatively, the processing device can be a software-implemented device.

[0031] This application does not limit the functions of the processing device. For example, the processing device may be a storage controller in a storage device, or the processing device may have more functions in addition to controlling the memory. For example, the processing device may also have at least one of the computing function and / or communication function.

[0032] In a second aspect, the present application provides a processing device, which is applied to an electronic device, wherein a first parallel interface of the electronic device is connected to a second parallel interface of one or more memories through multiple links, and the processing device includes a configuration module and a communication module. The configuration module is used to configure one or more parameters respectively adopted by the target interface for transmitting signals through at least two of the multiple links, the target interface includes the first parallel interface and / or the second parallel interface, the at least two links include a first link and a second link, the one or more parameters include a target parameter, and the values ​​of the target parameters respectively adopted by the configured target interface for transmitting signals through the first link and the second link are a first value and a second value respectively; the communication module is used to control the first parallel interface to transmit multiple signals with the second parallel interface through the at least two links.

[0033] Optionally, the at least two links include a first link group, the first link group includes the first link and other links, and the other links do not include the second link. The value of the target parameter used by the configured target interface to transmit signals through the other links is the first value.

[0034] Optionally, the first link group is used to transmit signals in the same channel, or to transmit signals in the same byte.

[0035] Optionally, the first link and the second link are used to transmit signals in different channels, or to transmit signals in different bytes of the same channel.

[0036] Optionally, the configuration module is also used to control the target interface to use multiple different values ​​of the target parameters to transmit test signals through the first link group respectively, and then determine the first value from the multiple different values ​​based on the signal integrity SI margin of the multiple transmitted test signals.

[0037] Optionally, the multiple different values ​​include one or more values, the SI margin of the test signal respectively transmitted by the target interface using the target parameters of the one or more values ​​is not lower than a threshold, the one or more values ​​include the first value, and, among the one or more values, the power consumption of the signal transmitted by the target interface using the target parameters of the first value is the smallest.

[0038] Optionally, the one or more parameters include at least one of the following parameters: a driving capability parameter, a transmitting-end equalization EQ parameter, an on-chip termination ODT parameter, and a receiving-end equalization EQ parameter.

[0039] Optionally, the multiplexed signals are used to transmit data to be written into the one or more memories, or to transmit data read from the one or more memories.

[0040] Optionally, the one or more memories include non-volatile flash memory and / or double data rate synchronous dynamic random access memory DDR SDRAM.

[0041] Since the processing device provided by the second aspect can be used to execute the method provided by the first aspect, the technical effects that can be obtained by the processing device provided by the second aspect and the specific functions of each module can refer to the corresponding content of the first aspect mentioned above, and will not be repeated here.

[0042] In a third aspect, the present application provides an electronic device, comprising a processing device and a parallel interface, wherein the processing device is connected to the parallel interface, the parallel interface is used to connect to one or more memories, and the processing device is used to execute the method described in the first aspect or any possible implementation method of the first aspect.

[0043] Optionally, the processing device includes a processor and a memory, the memory stores instructions, and the processor is used to execute the instructions so that the processing device executes the method described in the first aspect or any possible implementation of the first aspect.

[0044] Optionally, the processing device includes a logic circuit, and the logic circuit is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0045] Optionally, the processing device is a chip. Optionally, the parallel interface and the processing device can be integrated into the same chip.

[0046] Optionally, the electronic device is a computer device or a storage device.

[0047] In a fourth aspect, the present application provides an electronic system, comprising a processing device and one or more memories, wherein a first parallel interface of the processing device is connected to a second parallel interface of the one or more memories, and the processing device is used to execute the method described in the first aspect or any possible implementation method of the first aspect.

[0048] In a fifth aspect, the present application provides a computer-readable storage medium comprising instructions, which, when executed on a computer device, enables the computer device to execute the method described in the first aspect or any possible implementation of the first aspect.

[0049] In a sixth aspect, an embodiment of the present application further provides a computer program product, which, when executed on a computer device, enables the computer device to execute the method described in the first aspect or any possible implementation of the first aspect.

[0050] Since each device can be used to execute the method provided by the first aspect, the technical effects that can be obtained by each device and the technical details of implementing the above method can refer to the corresponding content of the first aspect mentioned above, and will not be repeated here.

[0051] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1 schematically illustrates an electronic system provided by the present application;

[0053] FIG2-1 schematically illustrates a storage device provided by the present application;

[0054] Figure 2-2 schematically illustrates a computer device provided by this application;

[0055] FIG3-1 is a schematic diagram showing a parallel interface of an electronic device connected to multiple memory chips via a single channel;

[0056] FIG3-2 is a schematic diagram showing an electronic device connected to a memory chip 1-1;

[0057] FIG3-3 is a schematic diagram showing an electronic device connected to a memory chip 1-1 and a memory chip 2-1 via the same data bus L0;

[0058] FIG4 schematically shows a possible equivalent circuit diagram of a transmitting module and a receiving module;

[0059] FIG5 schematically shows the high-level equivalent circuits, high-level amplitudes, and high-level static power consumption of three logic levels: SSTL / CTT, POD, and LVSTL / TTL;

[0060] FIG6 schematically shows the low-level equivalent circuits, low-level amplitudes, and low-level static power consumption of three logic levels: SSTL / CTT, POD, and LVSTL / TTL;

[0061] Figure 7-1 schematically shows the routing of part of the link between a processor and two DIMMs on a motherboard;

[0062] Figure 7-2 schematically shows the routing of part of the link between the main controller and two flash memory chips in an SSD;

[0063] Figure 8-1 schematically illustrates the configuration parameters of the parallel interface in the SSD controller (chip) and flash memory chips (chips).

[0064] FIG8-2 schematically illustrates the configuration parameters of the parallel interface in the processor and memory chip in FIG2-2;

[0065] FIG9A , FIG9B , FIG9C , and FIG9D schematically illustrate possible processes of the method provided in this application;

[0066] Figures 10 and 11 schematically illustrate possible values ​​of various parameters in the parallel interface;

[0067] FIG12 schematically illustrates a possible process of parameter training. DETAILED DESCRIPTION

[0068] First, the application scenario of this application is introduced.

[0069] As shown in Figure 1, the present application can be applied to any electronic system including an electronic device and one or more memories, where the electronic device can be connected to the one or more memories via a parallel interface. This application refers to the parallel interface of the electronic device as a first parallel interface, and the parallel interfaces of the one or more memories as a second parallel interface. Figure 1 schematically illustrates memories 1 and 2, and the electronic system can include a greater or lesser number of memories.

[0070] The first parallel interface and the second parallel interface are connected via multiple links. This application does not limit the number of links between the first parallel interface and the second parallel interface. This application refers to two of the multiple links as the first link and the second link, respectively. Figure 1 schematically illustrates the first link and the second link, and this application does not limit the positional relationship between the first link and the second link.

[0071] In this application, the port on the link used to connect the electronic device is referred to as the first port. The first port of the first link and the first port of the second link are connected to different pins of the first parallel interface for transmitting two signals.

[0072] The first parallel interface can be connected to the second parallel interface via multiple links. When the first parallel interface is connected to multiple memories, the second parallel interface can include the parallel interface of each memory. The first link and the second link can connect the parallel interface of the same memory or the parallel interfaces of different memories.

[0073] In this application, the port on the link used to connect to the memory is referred to as the second port. A single link can have one second port or multiple second ports, and different second ports can be used to connect to the same memory or different memories.

[0074] This application does not limit the type of memory. The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), and enhanced synchronous dynamic random access memory. In addition to including all current mainstream high-speed memories, the memory may also include future high-speed memories.

[0075] This application does not limit the type of parallel interface, as long as both communicating parties use the same parallel interface protocol for communication. The above-mentioned parallel interface can be a single-ended high-speed parallel bus interface. For example, the parallel interface can be the NFI interface mentioned above, the SDR interface, the non-volatile double data rate (NV-DDR) interface, the NV-DDR2 interface, or the NV-DDR3 interface.

[0076] This application does not limit the form of the memory. For example, multiple memories can be provided in dual inline memory modules (DIMMs), which are installed on the motherboard of the electronic device via DIMM connectors. Alternatively, the memory can be integrated on the motherboard of the electronic device.

[0077] As shown in Figure 1, the electronic device may include a processing device and a first parallel interface. This application does not limit the type of the processing device. The processing device may be a hardware-implemented device, for example, the processing device may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. Alternatively, the processing device may be a virtual device implemented by software, for example, the processing device may be a virtual device obtained by the processor when executing instructions in the memory.

[0078] This application does not limit the functions of the electronic device. For example, the electronic device may be a storage controller, or the electronic device may have more functions besides controlling the memory, such as computing functions and / or communication functions.

[0079] This application does not limit the type of electronic system. For example, the electronic system shown in FIG1 may be a storage device, and the electronic device may be a storage controller in the storage device. This application does not limit the type of storage device. Taking the storage device as a solid-state drive (SSD) as an example, FIG2-1 schematically illustrates a schematic diagram of the storage device.

[0080] An SSD is a storage device that primarily uses NAND flash as permanent memory. As shown in Figure 2-1, an SSD consists of NAND flash memory and a main controller (referred to as the main controller). NAND flash memory consists of multiple flash chips for data storage. A flash chip is a package of one or more die. Each die can include multiple panels, each panel can include multiple blocks, and each block can include one or more pages. The main controller is the brain of the SSD, responsible for complex tasks such as managing data storage and maintaining SSD performance and lifespan. The main controller is an embedded microchip that includes a processor, which acts as a command center, issuing all SSD operation requests. For example, the processor uses firmware in the buffer to perform functions such as reading and writing data, garbage collection, and wear leveling.

[0081] As shown in Figure 2-1, the SSD controller also includes a host interface and a parallel interface. The host interface is used to communicate with the host. The host here can refer to any device such as a server, personal computer, or array controller. The parallel interface can have multiple channels. Through the multiple channels of the parallel interface, the controller can operate multiple flash memory chips in parallel, thereby increasing the underlying bandwidth. Figure 2-1 schematically shows two memory channels, or channels for short, between the controller and the NAND flash memory. The controller can read and write data to the two flash memory chips in parallel through these two channels. The controller can connect to the NAND flash memory through a larger number of channels.

[0082] In addition to flash memory, the master controller can also connect to other types of memory, such as the memory shown in Figure 2-1.

[0083] In the storage device shown in FIG2-1 , the master controller and the flash memory chip can be connected via a parallel interface. FIG2-1 does not specifically show the parallel interface of each flash memory chip.

[0084] Optionally, the electronic device shown in FIG1 can be understood with reference to the main control in FIG2-1, and the memory shown in FIG1 can be understood with reference to the flash memory chip shown in FIG2-1.

[0085] Alternatively, for example, the electronic system shown in FIG1 may be a computer device, such as a server, workstation, smartphone, personal computer (PC), laptop, or communication device (e.g., switch). As shown in FIG2-2 , the computer device may include a motherboard, on which a processor is mounted. The processor has two channels, with two DIMMs (DIMMs) in each channel. Specifically, the processor is connected to DIMM 0 and DIMM 1 in channel 0 via channel 0, and to DIMM 0 and DIMM 1 in channel 1 via channel 1. The DIMMs contain multiple memory chips (or memory chips), which may be double data rate synchronous dynamic random access memory (DDR SDRAM). A memory rank is a group of memory chips that are arranged in parallel to meet the data bit width requirements of a channel. The memory chips in each DIMM may form one or more memory ranks. FIG2-2 schematically illustrates two memory ranks in each DIMM. In actual applications, a DIMM may have fewer or more memory ranks as needed. When a single link has multiple second ports, different second ports may connect to memory chips in different memory ranks.

[0086] Figure 2-2 uses a processor with two channels as an example. In actual applications, a processor can have more or fewer channels. Figure 2-2 uses a single channel with two DIMMs as an example. In actual applications, a single channel can have more or fewer DIMMs.

[0087] In the computer device shown in FIG2-2 , the processor and the memory chip may be connected via a parallel interface, which is not specifically shown in FIG2-2 .

[0088] The electronic device shown in FIG. 1 can be understood with reference to the processor shown in FIG. 2-2 , and the memory shown in FIG. 1 can be understood with reference to the memory chip or DIMM shown in FIG. 2-2 .

[0089] The computer device may include more modules. For example, the motherboard shown in FIG2-2 may be provided with more processors. Each processor may be connected to a greater or lesser number of DIMMs. The processor may also be connected to other forms of memory. The above description uses a DDR SDRAM chip as an example. This application does not limit the type of memory chip. For example, the memory chip may be a single data rate synchronous dynamic random access memory (SDR SDRAM), a compute express link (CXL) extended memory, or a storage class memory (SCM).

[0090] To ensure bandwidth performance, as mentioned above, a parallel interface can have multiple channels. Taking the NFI interface of a solid-state drive (SSD) as an example, the Hi18XX SSD controller has 17 channels, each with 1 byte. For a DDR interface, each channel can have multiple bytes. Taking the DDR interface of a Kunpeng server motherboard as an example, the CPU controller has 8 channels, each with 9 bytes. The following describes how electronic devices access memory through a single channel.

[0091] Figure 3-1 shows a schematic diagram of a parallel interface of an electronic device connecting multiple memory chips through a single channel. Figure 3-1 does not specifically show each parallel interface. Assume that the channel is channel 0 shown in Figure 2-2. As shown in Figure 3-1, channel 0 may include a control link for transmitting control signals (indicated by a dotted line with an arrow in Figure 3-1) and a data link for transmitting data signals (indicated by a solid line with an arrow in Figure 3-1). This application does not limit the type of link or transmission line. For example, the link may be a bus. The following text takes the link as a bus as an example.

[0092] Control signals are used to carry control information. This application does not limit the type of control signals. For example, control signals may include at least one of configuration signals, command signals, address signals, and clock signals. Channel 0 may include multiple control buses. For simplicity, Figure 3-1 shows all control buses as a single dashed line.

[0093] The data signal is used to carry data. A channel of a parallel interface has a certain bit width, and the bit width of the channel represents the bit width of the data that the parallel interface can transmit in parallel through a single channel. This application does not limit the bit width of a single channel. Figure 3-1 takes the data bit width of channel 0 as 4 bytes (byte), or 32 bits (bit) as an example. Accordingly, the channel includes at least 32 data buses to transmit 32 bits of data in parallel. Byte refers to the bit width of a byte of the parallel bus interface, generally including 8 bits of data from DQ0 to DQ7. For the sake of simplicity of the figure, Figure 3-1 shows 4 bold black solid lines in channel 0, representing 4 bytes of data buses respectively. The data bus of byte 1 includes 8 data buses for transmitting the first byte of channel 0, the data bus of byte 2 includes 8 data buses for transmitting the second byte in channel 0, the data bus of byte 3 includes 8 data buses for transmitting the third byte in channel 0, and the data bus of byte 4 includes 8 data buses for transmitting the fourth byte in channel 0.

[0094] As mentioned above, the processor can be connected to one or more memory blocks through a single channel. Figure 3-1 takes the example of an electronic device connecting memory block 1 and memory block 2 through channel 0. The present application does not limit the number of memory chips in the memory block. The number is generally related to the data bit width of the channel and the bit width of a single memory chip. The present application does not limit the bit width of a single memory chip. For example, the bit width of a single memory chip can be 4 bits, 8 bits, or 16 bits. Assuming that the data bit width of the channel is 32 bits and the bit width of a single memory chip is 8 bits, then a memory block includes at least 4 memory chips. A memory block can also include more memory chips. For example, in order to ensure the data integrity of the memory and recover memory errors, one or more memory chips can be added to a memory block to store error correction code (ECC). For example, for a DRAM interface, a channel typically includes a bit width of 64+8 bits.

[0095] Assuming that the bit width of memory chip 1-1 shown in Figure 3-1 is 8 bits and that memory chip 1-1 is connected to the data bus of byte 1, Figure 3-2 schematically illustrates an electronic device connected to memory chip 1-1. Figure 3-2 schematically illustrates data buses L0 through L7, each of which is used to transmit a data signal for one bit in byte 1. Figure 3-2 also schematically illustrates a control bus. Additional buses can be connected between the electronic device and the memory chip to transmit signals other than data signals, such as at least one of configuration signals, clock signals, command signals, and address signals.

[0096] Figure 3-2 uses the example of a single memory chip with a bit width equal to one byte. The bit width of a single memory chip can be less than one byte. In this case, the data bus connected to the single memory chip can be used to transmit data signals representing a portion of a single byte. Alternatively, the bit width of a single memory chip can be greater than one byte. In this case, the data bus connected to the single memory chip can be used to transmit data signals representing multiple bytes.

[0097] FIG3-2 also schematically shows possible structures of the electronic device and the memory chip 1-1.

[0098] As shown in FIG3-2 , the processing device in the electronic device may include a configuration module and a communication module, each of which is connected to a parallel interface. The configuration module can be used to configure the parameters of its own parallel interface and / or the parameters of the parallel interface of the connected memory. The communication module can be used to control the parallel interface to transmit signals across multiple connected links to access the connected memory, such as the storage medium of memory chip 1-1.

[0099] As shown in Figure 3-2, a memory chip may include a control device, a storage medium, and a parallel interface. The control device includes a configuration module and a communication module. The configuration module can be used to configure the parameters of its own parallel interface and / or the parameters of the parallel interface of the connected processing device. The communication module can be used to control the parallel interface to transmit signals through multiple connected links to receive data sent by an electronic device to be written to the storage medium or to send data read from the storage medium to an electronic device.

[0100] This application does not limit the implementation of each module in the control device. For example, each module can be implemented by software, hardware, or a combination of software and hardware. Figure 3-2 uses the configuration in which the control device and the parallel interface are independent of each other as an example. Optionally, referring to Figure 3-3, the control device can be integrated into the parallel interface.

[0101] As mentioned above, a single link can have multiple second ports, and different second ports can be used to connect different memory chips. An electronic device can connect multiple memory chips through a single link. Assuming that the memory chip 2-1 in the memory block 2 shown in Figure 3-1 is connected to the same data bus L0 as the memory chip 1-1 in the memory block 1, Figure 3-3 shows a schematic diagram of an electronic device connecting the memory chip 1-1 and the memory chip 2-1 respectively through the same data bus. As shown in Figure 3-3, the electronic device can connect the memory chip 1-1 and the memory chip 2-1 respectively through the data bus L0. The memory chip 1-1 and the memory chip 2-1 can also be connected to more data buses and control buses respectively. For the sake of simplicity of the figure, Figure 3-3 only schematically shows a single data bus between the electronic device and the memory chip. Other data buses between the electronic device and the memory chip can refer to Figure 3-3.

[0102] The electronic device may also connect multiple memories via the same control bus. For example, different memory chips in the same memory block may be connected to the same control bus to receive the same control signal (eg, chip select signal, etc.).

[0103] The parallel interface can be provided with input / output (IO) circuits for each connected bus. The IO circuits may include a transmitting module and / or a receiving module. The transmitting module is used to transmit electrical signals to the bus, and the receiving module is used to receive electrical signals from the bus. Figure 3-3 schematically illustrates the transmitting module and receiving module provided for data bus L0 by each parallel interface. The controller can send a signal to L0 via the transmitting module, and the memory chip 1-1 or the memory chip 2-1 can receive the signal from data bus L0 via its own receiving module. The memory chip 1-1 or the memory chip 2-1 can send a signal to data bus L0 via its own transmitting module, and the controller can receive the signal from data bus L0 via its own receiving module.

[0104] Since a parallel interface can connect more buses, the parallel interface shown in FIG3-3 can include more IO circuits.

[0105] Figure 4 schematically illustrates a possible equivalent circuit diagram of a transmitting module and a receiving module. As shown in Figure 4, the transmitting module may include a connected transmitting control unit and a transmitting unit, and the receiving module may include a connected receiving control unit and a receiving unit. The transmitting control unit is used to obtain information to be transmitted and input control instructions to the transmitting unit based on the information. The transmitting unit is used to input an electrical signal to the connected data bus L0 according to the control instructions. The parallel interface protocol specifies the type of logic level of the signal transmitted between the communicating parties, such as stub series terminated logic (SSTL) / center tapped termination (CTT), pseudo open-drain (POD), or low voltage series terminated logic (LVSTL) / low tapped termination (LTT). The receiving unit may receive an electrical signal from the data bus L0. The receiving control unit may sample the electrical signal received by the receiving unit based on the type of logic level and determine the sampled voltage (or level) based on a reference voltage (or decision level) to decode the information.

[0106] The sending module and receiving module shown in FIG4 can be respectively provided in the electronic device shown in FIG3-3 and a memory chip, so that the electronic device can write data to the memory. Alternatively, the sending module and receiving module shown in FIG4 can be respectively provided in a memory chip and the electronic device shown in FIG3-3, so that the electronic device can read data from the memory.

[0107] The IO circuit shown in Figures 3-3 and 4 is a possible structure divided according to function, rather than limiting the structure of the IO circuit. For example, the sending control unit of the sending module and the receiving control unit of the receiving module can be integrated into the same control unit (such as an interface control unit). Optionally, the control unit can integrate the sending control unit and the receiving control unit in the IO circuit of each link. The IO circuit can include more units. For example, the IO circuit can also include one or more registers, which can be used to store parameter configurations of the parallel interface.

[0108] As shown in Figure 4, the transmitting control unit can input control instructions to port Ps based on the data to be sent. The control instructions can change the switching states of the PU switch and the PD switch, thereby changing the voltage level of port Pr. The receiving control unit can sample the electrical signal of port Pr according to the type of logic level and judge the sampled voltage (or level) based on a reference voltage (or judgment level) to decode the data.

[0109] For example, the transmission control unit turns on the PU switch and turns off the PD switch in the transmission unit, thereby generating a high level at the port Pr2. The transmission control unit turns off the PU switch and turns on the PD switch in the transmission unit, thereby generating a low level at the port Pr2.

[0110] The transmitting module and receiving module shown in FIG4 can be used to transmit SSTL type electrical signals. Different designs of parallel interfaces can be used to generate different types of logic levels. FIG5 schematically shows the high-level equivalent circuit, high-level amplitude, and high-level static power consumption of the three logic levels of SSTL / CTT, POD, and LVSTL / TTL, and FIG6 schematically shows the low-level equivalent circuit, low-level amplitude, and low-level static power consumption of the three logic levels. Referring to FIG5 and FIG6, the transmitting control unit turns on the branch where Ron_pu is located in the transmitting unit and turns off the branch where Ron_pd is located through a control instruction, thereby generating a high level at port Pr; the transmitting control unit turns off the branch where Ron_pu is located in the transmitting unit and turns on the branch where Ron_pd is located through a control instruction, thereby generating a low level at port Pr.

[0111] As shown in Figure 3-3, a single data bus can connect the IO circuits of multiple memory chips. Accordingly, the high and low level amplitudes will also be related to the parameters of the IO circuits of more memory chips.

[0112] This application does not limit the specific circuit design of the parallel interface. Figure 4 is only used as an example. The ground level in the transmitting unit and the receiving unit can be replaced with a level of other magnitude. The single resistor shown in Figure 4 can be implemented by one or more components. For example, Rodt can be implemented by an ODT circuit. This application does not limit the type of components, as long as the one or more components can be equivalent to a resistor.

[0113] Electronic systems can optimize the signal integrity (SI) of signals in the link by adjusting the values ​​of the parameters of the parallel interface used to transmit signals through the link, thereby increasing the SI margin of the electrical signals received by the receiving end, thereby ensuring that the receiving end can correctly sample the electrical signals in the link.

[0114] SI margin can include voltage margin and / or timing margin. Voltage margin refers to the excess voltage of a signal beyond the receiver's high and low level requirements. Timing margin refers to the excess time of a signal beyond the receiver's setup and hold time requirements.

[0115] For ease of description, this application refers to the parameters used by a parallel interface to transmit signals through a link as interface parameters corresponding to the link. Since a link can connect multiple parallel interfaces (e.g., a first parallel interface and a second parallel interface), the interface parameters corresponding to the link may include parameters of at least one parallel interface connected to the link, for example, parameters used by a target interface to transmit signals through the link, where the target interface may include a first parallel interface and / or a second parallel interface. The parameters used by a parallel interface to transmit signals through a link may include one or more parameters, and accordingly, the interface parameters corresponding to the link may include one or more parameters of the parallel interface.

[0116] This application does not limit the specific types of the above parameters. For example, the parameters may include at least one of multiple parameters such as driving capability parameters, transmitter (transmitter, Tx) equalization (equalization, EQ) parameters, on-die termination (on-die termination, ODT) parameters and receiver (receiver, Rx) EQ parameters.

[0117] The parameters are described below.

[0118] The driving capability parameter can be used to determine the current size of the electrical signal sent by the sending module. Due to the loss of the electrical signal during transmission in the transmission line, if the driving capability is too small, the receiving end cannot correctly receive the signal. Optionally, the driving capability parameter can be used to indicate the size of the resistor in the sending unit, for example, to indicate Ron_pu and Ron_pd shown in Figure 4. This application does not limit the specific implementation method and parameter configuration method of Ron. In the following, the driving capability parameter is used to indicate the size of the resistor in the sending unit as an example. Under normal circumstances, by reducing the resistance indicated by the driving capability parameter, it is beneficial to increase the current of the electrical signal sent by the sending module, thereby enhancing the driving capability of the sending end, and then helping to improve the SI of the link.

[0119] On-die termination (ODT), or on-chip termination resistor, can improve signal integrity by reducing signal reflections between the transmitter and receiver. The equivalent resistance of ODT can refer to Rodt_pu and Rodt_Pd shown in Figure 4. This application does not limit the specific circuit design and parameter configuration method of ODT. ODT can reduce signal reflections by providing a terminator resistor that matches the impedance of the transmission line. ODT parameters can be used to indicate the size of the ODT resistance, such as Rodt_pu and Rodt_pd shown in Figure 4. Generally, reducing the size of the resistance indicated by the ODT parameters is beneficial to improving the SI of the link.

[0120] Equalization circuits are used at the transmitting or receiving end to compensate for channel imperfections and eliminate intersymbol interference (ISI), thereby reopening the eye diagram of the received signal. In the frequency domain, equalization compensates for the low-pass characteristics of the channel using a high-pass filter. In the time domain, equalization reshapes the pulse response, confining its energy within a time interval to avoid ISI.

[0121] The transmitting module can be equipped with a Tx EQ circuit. The Tx EQ circuit can compensate for the difference in attenuation between high and low frequencies through pre-emphasis or de-emphasis. Pre-emphasis maintains the low-frequency portion of the electrical signal while boosting the high-frequency portion. De-emphasis attenuates the low-frequency portion of the signal while maintaining the high-frequency portion. Both de-emphasis and pre-emphasis are applied at the transmitting end of the signal, aiming to balance the high-frequency and low-frequency components as much as possible and reduce bit errors caused by the transmission link attenuating the high-frequency component more than the low-frequency component. Tx EQ parameters can be pre-emphasis or de-emphasis. Pre-emphasis parameters can include the amplitude and time range of the signal attenuation at the edge of the signal transition. De-emphasis parameters can include the amplitude and time range of the signal attenuation. Generally, increasing the amplitude and time range of the pre-emphasis parameters improves the link SI. Increasing the amplitude and time range of the de-emphasis parameters also improves the link SI.

[0122] The receiving module may be equipped with a receiving equalization circuit. The parameters of the receiving equalization circuit (i.e., Rx EQ) may include a continuous time linear equalization (CTLE) circuit and / or a decision feedback equalizer (DFE). Taking the CTLE circuit as an example, the CTLE circuit can compensate for the attenuation difference between high and low frequencies by amplifying high-frequency signals in the receiving module or by reducing low-frequency signals. Generally, when high-speed digital signals are transmitted through lossy channels, the CTLE circuit is used to boost the high-frequency components of the signal to compensate for high-frequency channel losses. CTLE parameters can be used to indicate the frequency range and / or amplification ratio within which the CTLE circuit amplifies the received electrical signal. Generally, increasing the frequency range and / or amplification ratio indicated by the CTLE parameters helps improve the SI of the link. The DFE processes the error signal through equalization in the feedback and forward paths, thereby achieving signal recovery and optimization. Generally, a higher DFE order results in better SI.

[0123] The gear position can be used to measure the value of the equalization parameter. Generally speaking, the larger the gear position, the larger the amplitude and / or range indicated by the pre-emphasis parameter or de-emphasis parameter.

[0124] The processing device may read a single configuration information 1 (referred to as configuration information 1) from the firmware, and then configure the interface parameters corresponding to each link according to the configuration information 1. The configuration information 1 is used to indicate the values ​​of one or more parameters of the parallel interface.

[0125] Assuming a single link has a first port and a second port, and the interface parameters corresponding to the link include parameters of the first parallel interface and parameters of the second parallel interface, as an example, configuration information 1 can be write process configuration information, which can indicate that the Ron value of the first parallel interface is SOC_Ron1 and the ODT value of the second parallel interface is Rodt1; or, configuration information 1 can be read process configuration information, which can indicate that the Ron value of the second parallel interface is Ron1 and the ODT value of the first parallel interface is SOC_Rodt1; or, configuration information 1 can include the above-mentioned write process configuration information and read process configuration information. SOC_Ron1 and Ron1 can be the same or different. When they are the same, configuration information 1 can indicate the values ​​of the drive capability parameters of the transmitter and receiver through Ron1. SOC_Rodt1 and Rodt1 can be the same or different. When they are the same, configuration information 1 can indicate the values ​​of the ODT parameters of the transmitter and receiver through Rodt1.

[0126] Assume that a single link has a first port and multiple second ports, and the interface parameters corresponding to the link include parameters of the first parallel interface and parameters of the second parallel interface. Taking the memory as a DDR memory as an example, configuration information 1 can be write process configuration information. The scheme can indicate that the value of Ron of the first parallel interface is SOC_Ron1, and the ODT of the second parallel interface includes three sub-parameters, which are respectively recorded as rtt_park, rtt_nom and rtt_wr. The values ​​of these three sub-parameters are rtt_park1, rtt_nom1 and rtt_wr1 respectively; or, configuration information 1 can be read process configuration information. The scheme can indicate that the Ron of the second parallel interface is Ron1, the values ​​of the three sub-parameters in the ODT are rtt_park1 and rtt_nom1 respectively, and the ODT of the first parallel interface is SOC_Rodt1; or, configuration information 1 can include the above-mentioned write process configuration information and read process configuration information. As described above, SOC_Ron1 and Ron1 may be the same or different, the values ​​of any sub-parameter in SOC_Rodt1 and the ODT of the second parallel interface may be different, or the values ​​of at least one sub-parameter in SOC_Rodt1 and the ODT of the second parallel interface may be the same.

[0127] After obtaining the configuration information 1 , the processing device may configure the interface parameters corresponding to each link according to the configuration information 1 .

[0128] The following uses the processor in the SSD shown in Figure 2-1 as an example. Assuming the SSD topology type is H, and configuration information 1 indicates SOC_Ron1 = 25, SOC_Rodt1 = 75, Ron1 = 37.5, and Rodt = 50, as shown in Figure 8-1. Before reading or writing data, the processor configures the specific values ​​of the interface parameters corresponding to each link according to configuration information 1.

[0129] Referring to Figure 8-1, before writing data, the processor may configure, for each link, the Ron used by the first parallel interface to send data signals through the link to 25, and the Rodt used by the parallel interface of the flash memory chip (referred to as the particle) connected to the link to receive data signals through the link to 50. If a single link has multiple second ports, the second port that receives data signals may be referred to as the target second port, and the second port not used for receiving data signals may be referred to as the non-target second port. The processor may configure the Rodt used by the flash memory chip's parallel interface to receive data signals through the target second port to 50, or configure the Rodt used by the flash memory chip's parallel interface to receive data signals through the non-target second port to 50, or configure the Rodt used by the flash memory chip's parallel interface to receive data signals through both the target second port and the non-target second port to 50, respectively.

[0130] Referring to Figure 8-1 , before reading data, the processor may configure the Ron used by the flash memory chip's parallel interface to send data signals through the link to 37.5, and the Rodt used by the first parallel interface to receive data signals through the link to 75. If a single link has multiple second ports, the second port that sends data signals may be referred to as the target second port, and the second port not used for sending data signals may be referred to as the non-target second port. The processor may configure the Rodt corresponding to the non-target second port in the flash memory chip's parallel interface to 50, and disable the Rodt corresponding to the target second port in the second parallel interface.

[0131] The following uses the processor shown in Figure 2-2 as an example. Assuming SOC_Ron1 = 34, SOC_Rodt1 = 60, Ron1 = 34, rtt_park1 = 60, rtt_nom1 = 240, and rtt_wr1 = 240, and referring to Figure 8-2, describes how the processor configures the specific values ​​of the interface parameters corresponding to each link according to configuration information 1 before reading or writing data.

[0132] As shown in Figure 2-2, because the processor connects to four memory banks through a single channel, a single link has at least four second ports, referred to as second port 1 through second port 4. Assume that second port 1 is connected to the memory chip in D1R0, second port 2 is connected to the memory chip in D1R1, second port 3 is connected to the memory chip in D0R0, and second port 4 is connected to the memory chip in D0R1.

[0133] Referring to sub-table T1 corresponding to "Interface parameter configuration corresponding to each link in the process of writing D1R0" in Figure 8-2, before the processor writes data to D1R0, for each link, the processor can determine a set of configurations of interface parameters corresponding to the link according to configuration information 1 (recorded as configuration 1-1). The values ​​of the parameters indicated by configuration 1-1 can refer to the values ​​indicated by the black dots in sub-table T1. Then, the processor configures the interface parameters of the link according to configuration 1-1, and can configure the value of Ron used by the first parallel interface to send signals through the link to SOC_Ron1 (i.e., 34), configure the Rodt (denoted as D1R0-Rodt) used by the second parallel interface to receive signals through the second port 1 of the link to rtt_wr1 (i.e., 240), configure the Rodt (denoted as D1R1-Rodt) used by the second parallel interface to receive signals through the second port 2 of the link to rtt_nom1 (i.e., 240), configure the Rodt (denoted as D0R0-Rodt) used by the second parallel interface to receive signals through the second port 3 of the link to rtt_park1 (i.e., 60), and configure the Rodt (denoted as D0R1-Rodt) used by the second parallel interface to receive signals through the second port 4 of the link to rtt_park1 (i.e., 60).

[0134] Similarly, before the processor writes data to D1R1, for each link, the processor can determine configurations 1-2 of the interface parameters corresponding to the link according to configuration information 1, as shown by the values ​​indicated by the black dots in sub-table T2 of Figure 8-2. Similarly, before the processor writes data to D1R0, for each link, the processor can determine configurations 1-3 of the interface parameters corresponding to the link according to configuration information 1, as shown by the values ​​indicated by the black dots in sub-table T3 of Figure 8-2. Similarly, before the processor writes data to D0R1, for each link, the processor can determine configurations 1-4 of the interface parameters corresponding to the link according to configuration information 1, as shown by the values ​​indicated by the black dots in sub-table T4 of Figure 8-2.

[0135] Referring to sub-table T5 corresponding to "Interface parameter configuration corresponding to each link during reading D1R0" in Figure 8-2, before the processor reads data from D1R0, for each link, the processor can determine a set of configurations of interface parameters corresponding to the link according to configuration information 1 (recorded as configurations 1-5). The values ​​of the parameters indicated by configurations 1-5 can refer to the values ​​indicated by the black dots in sub-table T5. Then, the processor configures the interface parameters corresponding to the link according to configurations 1-5, and can configure the Rodt value used by the first parallel interface to receive signals through the link to SOC_Rodt1 (i.e., 60), configure the Ron (denoted as D1R0-Ron) used by the second parallel interface to send signals through the second port 1 of the link to Ron1 (i.e., 34), configure the Rodt (denoted as D1R1-Rodt) used by the second parallel interface to receive signals through the second port 2 of the link to rtt_nom1 (i.e., 240), configure the Rodt (denoted as D0R0-Rodt) used by the second parallel interface to receive signals through the second port 3 of the link to rtt_park1 (i.e., 60), and configure the Rodt (denoted as D0R1-Rodt) used by the second parallel interface to receive signals through the second port 4 of the link to rtt_park1 (i.e., 60).

[0136] Similarly, before the processor reads data from D1R1, for each link, the processor can determine configurations 1-6 of the interface parameters corresponding to the link according to configuration information 1, as indicated by the black dots in sub-table T6 of Figure 8-2. Similarly, before the processor reads data from D0R0, for each link, the processor can determine configurations 1-7 of the interface parameters corresponding to the link according to configuration information 1, as indicated by the black dots in sub-table T7 of Figure 8-2. Similarly, before the processor reads data from D0R1, for each link, the processor can determine configurations 1-8 of the interface parameters corresponding to the link according to configuration information 1, as indicated by the black dots in sub-table T8 of Figure 8-2.

[0137] With the development of information and communications technology (ICT), processor computing power continues to increase, placing higher demands on the signal transmission rate between processors and memory. To ensure SI margin requirements, it is necessary to adjust the parameters of the parallel interface to optimize the SI of the signal in the link.

[0138] However, the parameters of the parallel interface not only affect the SI margin of the signal in the link, but also affect the power consumption of the parallel interface. In addition, parameter values ​​that make the SI better tend to increase the power consumption of the parallel interface, while conversely, parameter values ​​that make the SI worse tend to reduce the power consumption of the parallel interface.

[0139] Figures 5 and 6 also schematically illustrate the static power consumption of the high and low levels of three logic levels: SSTL / CTT, POD, and LVSTL / TTL. As shown in Figures 5 and 6, for any logic level, the smaller the Ron value, the greater the power consumption; conversely, the larger the Ron value, the lower the power consumption; the smaller the ODT value, the greater the power consumption; conversely, the larger the ODT value, the lower the power consumption.

[0140] The larger the value indicated by the pre-emphasis parameter (such as the enhancement amplitude and / or time range), the greater the power consumption generally is. Conversely, the smaller the value indicated by the pre-emphasis parameter (such as the enhancement amplitude and / or time range), the smaller the power consumption generally is.

[0141] The larger the value indicated by the CTLE parameter (eg, frequency range and / or amplification ratio), the greater the power consumption generally. Conversely, the smaller the value indicated by the CTLE parameter (eg, frequency range and / or amplification ratio), the smaller the power consumption generally.

[0142] Similarly, the greater the equalization order indicated by the DFE parameter, the greater the power consumption generally is. Conversely, the smaller the equalization order indicated by the DFE parameter, the smaller the power consumption generally is.

[0143] Through the above analysis, it is found that for different values ​​of the same parameter, a value with a larger SI margin usually leads to greater power consumption.

[0144] With the rapid development of semiconductor technology and the increase in chip operating frequency, the power consumption of chips and systems has increased rapidly. This increase in power consumption will lead to increased chip heat generation and decreased reliability. Therefore, low power consumption has become a key consideration in digital products. As a core component of digital products, the low-power design and application of memory are of great significance for reducing the power consumption of the entire digital product. To ensure the communication quality between the processing device and memory and reduce the power consumption of the parallel interface, after configuring the interface parameters corresponding to each link according to configuration information 1, the SI threshold of the signal transmitted in each link must meet the requirements and minimize power consumption.

[0145] However, as the operating frequency and transmission rate of parallel interfaces continue to increase, the SI margin of the parallel bus continues to decrease. To ensure that the SI margin meets the requirements, the Ron and Rodt values ​​indicated by configuration information 1 are continuously reduced, and the equalization parameters of the transmitter and / or receiver are continuously increased. Consequently, the power consumption of the parallel interface continues to increase. This increase in power consumption will lead to increased chip heat generation and decreased reliability. Therefore, it is urgent to find a solution to reduce the power consumption of parallel interfaces while ensuring communication quality.

[0146] FIG7-1 schematically illustrates a processor in a computer device and two DIMMs connected to the processor, and also schematically illustrates the routing of some transmission lines between the processor and the DIMMs and the length of the routing. Specifically, FIG7-1 schematically illustrates the routing of a transmission line in channel 0_byte 1, the routing of a transmission line in channel 0_byte 4, the routing of a transmission line in channel 1_byte 1, and the routing of a transmission line in channel 1_byte 4. The processor and the memory chips in the DIMMs can be connected through a DDR interface. FIG7-2 schematically illustrates a processor and two flash memory chips in a storage device, and also schematically illustrates the routing of some transmission lines between the processor and the flash memory chips and the length of the routing. Specifically, FIG7-2 schematically illustrates the routing of a transmission line in channel 0 and the routing of a transmission line in channel 16. The processor and the flash memory chip can be connected through an NFI interface. This application does not limit the implementation method of the link. For example, the link can be implemented through routing in the circuit board and / or connecting lines outside the circuit board.

[0147] As shown in Figures 7-1 and 7-2, the trace lengths of transmission lines in different channels generally vary significantly. As shown in Figure 7-1, the trace lengths of transmission lines for different bytes within the same channel also generally vary significantly. For example, as shown in Figure 7-2, the trace length of the transmission line in channel 0 is 2.1 inches, while the trace length of the transmission line in channel 16 is 5.9 inches. After configuring the interface parameters corresponding to each link according to configuration information 1 and transmitting signals through each link, experimental analysis found that the eye diagrams of signals transmitted through the channels with longer traces in Figures 7-1 and 7-2 were worse than those transmitted through the channels with shorter traces. Furthermore, the eye diagram of signals transmitted through the longer transmission line in the same channel in Figure 7-1 was worse than that transmitted through the shorter transmission line. Although the SI margins of the signals on each link are all above the threshold, SI margins may vary due to differences in trace conditions and other aspects between links. For any two links configured according to the same configuration information, the application refers to the link with better SI as the link with better routing, and the link with worse SI as the link with worse routing. For the link with better routing, by adjusting the value of the corresponding interface parameter (called the target parameter), it is possible to sacrifice a higher SI margin to reduce the power consumption of the parallel interface while ensuring that the SI margin is higher than the threshold. The target parameter may include one or more parameters of the parallel interface. In other words, by performing differentiated configuration of the interface parameters corresponding to multiple links, it is beneficial to further reduce the power consumption of the parallel interface while ensuring that the SI margin of each link meets the requirements.

[0148] Based on the above analysis, this application provides a method that can be applied to the electronic system shown in Figure 1. By differentially configuring the interface parameters corresponding to different links, it is not only beneficial to ensure that the links of each channel or byte in the parallel interface meet the SI margin requirements, but also helps to reduce the power consumption of the parallel interface.

[0149] As previously described, the interface parameters corresponding to the link may include the parameters used by the target interface to transmit signals through the link. Accordingly, before the processing device controls the first parallel interface to transmit multiple signals to the second parallel interface through at least two of the multiple links, the processing device may configure one or more parameters for the target interface to transmit signals through the at least two links. Furthermore, there are at least two links (e.g., the first link and the second link) among the at least two links, and the processing device performs differentiated configurations for the interface parameters corresponding to the two links. This not only helps ensure that the links of each channel or byte in the parallel interface meet the SI margin requirements, but also helps reduce the power consumption of the parallel interface. For example, the value configured by the processing device for the target parameter used by the target interface to transmit signals through the first link may be different from the value configured for the target parameter used by the target interface to transmit signals through the second link.

[0150] Assuming that after the processing device configures the interface parameters corresponding to a certain link according to certain configuration information, the SI margin of the signal transmitted by the link meets the requirements, this application refers to the configuration information as the alternative configuration information corresponding to the link. Among the multiple alternative configuration information corresponding to the link, this application refers to the alternative configuration information that minimizes the power consumption of the target interface transmitting the signal through the link as the optimal configuration information corresponding to the link, and the minimum power consumption is referred to as the optimal power consumption corresponding to the link. The application also provides a method for determining the configuration information corresponding to each link and configuring the interface parameters corresponding to the corresponding link according to the configuration information corresponding to each link. In this way, it is beneficial to configure the corresponding link according to the optimal configuration information corresponding to each link, thereby ensuring that each link meets the SI margin requirements while achieving the optimal power consumption corresponding to each link, thereby achieving the optimal power consumption of the parallel interface.

[0151] For example, for three links with different routing conditions (referred to as link 1, link 2, and link 3), assuming that the routing condition of link 1 is the worst and the routing condition of link 3 is the best, the optimal configuration information corresponding to link 1 can be determined to be configuration information 1, the optimal configuration information corresponding to link 2 is configuration information 2, and the optimal configuration information corresponding to link 3 is configuration information 3. Subsequently, the interface parameters corresponding to link 1 can be configured according to configuration information 1, the interface parameters corresponding to link 2 can be configured according to configuration information 2, and the interface parameters corresponding to link 3 can be configured according to configuration information 3. This is beneficial for ensuring that each link meets the SI margin requirements while achieving optimal power consumption corresponding to each link, thereby facilitating optimal power consumption of the parallel interface.

[0152] Assuming that after the processing device configures the interface parameters corresponding to each link in a certain link group according to a certain configuration information, the SI margin of the signal transmitted by each link in the link group meets the requirements, this application refers to this configuration information as the alternative configuration information corresponding to the link group. Among the multiple alternative configuration information corresponding to the link group, this application refers to the alternative configuration information that minimizes the power consumption of the target interface transmitting the signal through the link group as the optimal configuration information corresponding to the link group, and the minimum power consumption is referred to as the optimal power consumption corresponding to the link group. Through analysis, it is found that the optimal configuration information corresponding to the link group is the optimal configuration information corresponding to the link with the worst routing condition in the link group.

[0153] Further analysis of the three links (Link 1, Link 2, and Link 3) reveals that, compared with configuring the interface parameters for Link 3 according to the optimal configuration information 1 corresponding to Link 1, configuring the interface parameters for Link 3 according to the optimal configuration information 2 corresponding to Link 2 results in the target interface's power consumption for signal transmission through Link 3 being closer to its own optimal power consumption, resulting in lower power consumption.

[0154] Based on the above findings, the present application also provides a method for dividing at least two links into multiple link groups, determining configuration information corresponding to each link group, and then configuring the interface parameters corresponding to each link in the corresponding group according to the configuration information corresponding to each link group. This facilitates configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to the link with the worst routing condition in each link group.

[0155] The configuration information 1 introduced above, which ensures that the SI thresholds of the signals transmitted in each link meet the requirements and that power consumption is minimized, is actually the optimal configuration information corresponding to the link with the worst routing condition (the worst link) among multiple links. For a link group that does not include the worst link, since the routing conditions of the links in this group are all better than the routing conditions of the worst link, configuring the interface parameters corresponding to each link in the group according to the optimal configuration information corresponding to the group, compared to configuring the interface parameters corresponding to each link in the group according to configuration information 1, results in lower power consumption for the target interface transmitting signals through the group of links. This is beneficial for both ensuring communication quality and reducing power consumption, and also for reducing the complexity of configuring the target interface.

[0156] As previously mentioned, the first parallel interface can have multiple channels. Through analysis, it was found that the differences in the routing conditions of different links in the same channel are generally smaller than the differences in the routing conditions of links in different channels. Optionally, links in different channels can be divided into different link groups. Links in the same channel can be divided into one link group. Accordingly, the optimal configuration information corresponding to each channel can be determined, and then the interface parameters corresponding to the links in the corresponding channels can be configured according to the optimal configuration information corresponding to each channel. As shown in Figure 2-1 or Figure 2-2, assuming that the first parallel interface has channel 0 and channel 1, the processing device can determine the optimal configuration information corresponding to channel 0 (denoted as CH0) and determine the optimal configuration information corresponding to channel 1 (denoted as CH1). Then, one or more interface parameters corresponding to each link in channel 0 are configured according to CH0, and the interface parameters corresponding to each link in channel 1 are configured according to CH1.

[0157] As previously mentioned, the bit width of a single channel of the first parallel interface can be multiple bytes. Through analysis, it is found that for different links in the same channel, the routing differences of different links in the same byte are generally smaller than the routing differences of links corresponding to different bytes. Optionally, the links corresponding to different bytes in the same channel can be divided into different link groups. Links in the same byte can be divided into one link group. Accordingly, the optimal configuration information corresponding to each byte can be determined, and then the interface parameters corresponding to the link in the corresponding byte are configured according to the optimal configuration information corresponding to each byte. As shown in Figure 3-1, assuming that the first parallel interface has channel 0 and channel 1, and the bit width of each channel is 4 bytes, the processing device can determine Then, the interface parameters corresponding to each link in byte 1 of channel 0 are configured according to CH0B1, the interface parameters corresponding to each link in byte 2 of channel 0 are configured according to CH0B2, ..., the interface parameters corresponding to each link in byte 4 of channel 1 are configured according to CH1B4.

[0158] The following text will use examples to illustrate how to determine the optimal configuration information corresponding to a link group, which will not be expanded here.

[0159] Through the above method, the parallel bus interface can be configured with differentiated parameters, which is conducive to realizing the selection of differentiated parameter configurations for different channels and / or bytes of the parallel bus interface according to the actual routing conditions of the link (including routing length, impedance consistency, crosstalk, etc.), thereby fully tapping the SI margin of each channel and / or byte, reducing the power consumption of the parallel interface in transmitting signals in each channel or byte, and thus reducing the overall power consumption of the parallel interface.

[0160] Taking the self-developed SSD XX platform as an example, the current optimal SI parameter configuration is Ron = 25Ω, ODT = 50Ω, and the total static power consumption of the NFI interface is P = 17 channels * 12 bits * 0.012W = 2.448W. According to the differentiated parameter solution, on average, half of the channels have better routing conditions, which can be configured with Ron = 25Ω and ODT = 100Ω. The total power consumption is P = 8 channels * 12 bits * 0.012W + 9 channels * 12 bits * 0.006W = 1.8W, and the overall static power consumption is improved by 0.648W.

[0161] Assume that the multiple links between the first parallel interface and the second parallel interface include M control buses and N data buses, where M and N are positive integers greater than 1. The following example describes a process in which an electronic device accesses one or more memories.

[0162] Assuming that the target interface is the first parallel interface, the following describes a process of writing data from an electronic device to one or more memories via the parallel interface. FIG9A schematically illustrates a possible flow of the method. As shown in FIG9A , the method may include S901A to S904A.

[0163] S901A, the processing device determines multiple configuration information;

[0164] The processing device may determine multiple configuration information. Optionally, referring to FIG3-2 , the configuration module in the processing device may determine multiple configuration information.

[0165] For example, the processing device may divide N data buses into P link groups, where a single link group may include one or more links, and different link groups may include different links. The processing device may then determine configuration information corresponding to each link group, i.e., determine P pieces of configuration information. P is a positive integer less than or equal to N.

[0166] This application does not limit the manner in which the processing device groups the N data buses. As previously described, the processing device may optionally group links in different channels into different link groups. Alternatively, the processing device may group links in different channels into different link groups, and group links of different bytes in the same channel into different link groups. When P equals N, it can be considered that the processing device determines the configuration information corresponding to each link.

[0167] Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group described above. For example, assuming the first parallel interface has channel 0 and channel 1, the processing device may determine CH0 and CH1, respectively. Assuming the first parallel interface has channel 0 and channel 1, and each channel has a bit width of 4 bytes, the processing device may determine CH0B1, CH0B2, CH0B3, CH0B4, CH1B1, CH1B2, CH1B3, and CH1B4, respectively.

[0168] As previously described, the configuration information can be used to indicate the values ​​of one or more parameters of the first parallel interface. For the data writing process, the configuration information can include at least the write process configuration information described above. The write process configuration information can be used to indicate the parameters used by the first parallel interface to transmit signals over the link, such as the value of Ron (denoted as SOC_Ron) and / or the value of Tx EQ (denoted as SOC_Tx EQ) of the first parallel interface.

[0169] In this application, two link groups in the multiple link groups are referred to as the first link group and the second link group, respectively. The configuration information corresponding to the first link group is referred to as the first configuration information, and the configuration information corresponding to the second link group is referred to as the second configuration information. Since the routing conditions of the links in different link groups are generally quite different, the values ​​of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information may be different. For example, the first configuration information may indicate SOC_Ron=34, and the value of SOC_Tx EQ is gear 0, while the second configuration information may indicate SOC_Ron=40, and the value of SOC_Tx EQ is gear 0. Accordingly, the target parameter is SOC_Ron.

[0170] S902A: The processing device configures one or more parameters used by the first parallel interface to send signals through the corresponding link group according to the values ​​indicated by each configuration information;

[0171] After determining the plurality of configuration information, the processing device may configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, referring to FIG3-2 , S902A may be performed by a configuration module in the processing device.

[0172] For example, after the processing device determines the P configuration information corresponding to P link groups, assuming that configuration information i corresponds to link group i, i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to link group 1 according to the value indicated by configuration information 1, configure the interface parameters corresponding to link group 2 according to the value indicated by configuration information 2,..., configure the interface parameters corresponding to link group P according to the value indicated by configuration information P.

[0173] The processing device configuring the interface parameters corresponding to link group i according to the values ​​indicated by configuration information i may mean that, for each link in link group i, the processing device may configure one or more parameters used by the first parallel interface to transmit signals through the link according to the values ​​indicated by configuration information i. For example, for each link in the first link group, the processing device may configure the Ron and Tx EQ used by the first parallel interface to transmit signals through the link to 34 and gear 0, respectively, according to the values ​​indicated by the first configuration information. For each link in the second link group, the processing device may configure the Ron and Tx EQ used by the first parallel interface to transmit signals through the link to 40 and gear 0, respectively, according to the second configuration information.

[0174] S903A: The processing device controls the configured first parallel interface to send N data signals to the second parallel interface via N data buses.

[0175] After the processing device configures the interface parameters corresponding to the N data buses, it can control the first parallel interface to transmit N data signals to the second parallel interface via the N data buses. These N data signals can carry data to be written to one or more memories. Optionally, referring to FIG. 3-2 , S903A can be performed by a communication module in the processing device.

[0176] Assuming that data bus j corresponds to data signal j, the processing device can control the configured first parallel interface to send data signal 1 to the second parallel interface through data bus 1, control the configured first parallel interface to send data signal 2 to the second parallel interface through data bus 2,..., control the configured first parallel interface to send data signal N to the second parallel interface through data bus N.

[0177] After configuration, the first parallel interface can send a corresponding data signal to the first port of the link according to the interface parameters corresponding to the link. Assuming that the first link group includes data bus 1, the first parallel interface uses an Ron value of 34 and a Tx EQ of gear 0 to send data signal 1 to the first port of data bus 1. Assuming that the second link group includes data bus 2, the first parallel interface uses an Ron value of 40 and a Tx EQ of gear 0 to send data signal 2 to the first port of data bus 2. As shown in Figures 5 and 6, the size of Ron affects the level of the signal in the link. Therefore, the level of data signal 1 is different from the level of data signal 2.

[0178] 3-2 , assuming that data bus 1 is L0 as shown in FIG3-2 , the processing device can control its own parallel interface to send data signal 1 to memory chip 1 - 1 through data bus 1 .

[0179] S904A: One or more memories store data transmitted by N data signals.

[0180] After the processing device controls the configured first parallel interface to send N data signals to the second parallel interface through N data buses, one or more memories can receive the N data signals through the second parallel interface, determine the data to be written by the processing device based on the N data signals, and write the data into their own storage media.

[0181] Referring to FIG3-2 , assuming data bus 1 is L0 as shown in FIG3-2 , a processing device can send data signal 1 to memory chip 1-1 via data bus 1. One or more memories storing the data carried by data signal 1 can mean that memory chip 1-1 receives data signal 1 via its own parallel interface and then writes the data carried by data signal 1 to its own storage medium. Alternatively, referring to FIG3-2 , a communication module in memory chip 1-1 can write the data to the storage medium.

[0182] The processing device configures one or more parameters for the first parallel interface to transmit signals through the corresponding link group according to the configuration information corresponding to each link group, which facilitates configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. The processing device then controls the configured first parallel interface to transmit multiple data signals to the second parallel interface, which facilitates reducing the power consumption of the first parallel interface while ensuring the signal quality of the multiple data signals, thereby facilitating reducing the power consumption of the processing device and, ultimately, the power consumption of the electronic system.

[0183] Assuming that the target interface is the first parallel interface, the following describes a process for an electronic device to read data from one or more memories via the parallel interface. FIG9B schematically illustrates a possible flow of the method. As shown in FIG9B , the method may include S901B to S904B.

[0184] S901B, the processing device determines multiple configuration information;

[0185] The processing device may determine multiple configuration information. Optionally, referring to FIG3-2 , the configuration module in the processing device may determine multiple configuration information.

[0186] Similar to S901A above, for example, the processing device may divide N data buses into P link groups. Afterwards, the processing device may determine the configuration information corresponding to each link group, that is, determine P configuration information. Wherein, P is a positive integer less than or equal to N. The present application does not limit the manner in which the processing device groups the N data buses. As previously mentioned, optionally, the processing device may divide the links in different channels into different link groups. Alternatively, the processing device may divide the links in different channels into different link groups, and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group introduced above. As previously introduced, the configuration information may be used to indicate the value of one or more parameters of the first parallel interface. In this application, two of the multiple link groups are referred to as the first link group and the second link group, respectively. The configuration information corresponding to the first link group is referred to as the first configuration information, and the configuration information corresponding to the second link group is referred to as the second configuration information. Because the routing of links in different link groups generally varies significantly, the value of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information can be different.

[0187] Unlike S901A described above, for the data read process, the configuration information may include at least the read process configuration information described above. The read process configuration information may be used to indicate the parameters used by the first parallel interface to receive signals via the link, such as the value of the first parallel interface's Rodt (denoted as SOC_Rodt) and / or the value of the Rx EQ (denoted as SOC_Rx EQ). For example, the first configuration information may indicate SOC_Rodt = 60 and the SOC_Rx EQ value as gear 0, while the second configuration information may indicate SOC_Rodt = 120 and the SOC_Tx EQ value as gear 0. Accordingly, the target parameter is SOC_Rodt.

[0188] S902B: The processing device configures one or more parameters used by the first parallel interface to receive signals through the corresponding link group according to the values ​​indicated by each configuration information;

[0189] Similar to S902A above, after the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, with reference to Figure 3-2, S902B can be executed by the configuration module in the processing device. For example, after the processing device determines P configuration information corresponding to P link groups, assuming that configuration information i corresponds to link group i, i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to link group 1 according to the values ​​indicated by configuration information 1, configure the interface parameters corresponding to link group 2 according to the values ​​indicated by configuration information 2, ..., configure the interface parameters corresponding to link group P according to the values ​​indicated by configuration information P.

[0190] During the data read process, unlike S902A described above, the processing device configuring the interface parameters corresponding to link group i according to the values ​​indicated by configuration information i may mean that, for each link in link group i, the processing device may configure one or more parameters used by the first parallel interface to receive signals through the link according to the values ​​indicated by configuration information i. For example, for each link in the first link group, the processing device may configure the Rodt and Rx EQ used by the first parallel interface to receive signals through the link to 60 and gear 0, respectively, according to the values ​​indicated by the first configuration information. For each link in the second link group, the processing device may configure the Rodt and Rx EQ used by the first parallel interface to receive signals through the link to 120 and gear 0, respectively, according to the second configuration information.

[0191] S903B: The processing device controls the configured first parallel interface to receive N data signals from the second parallel interface via N data buses;

[0192] After the processing device configures the interface parameters corresponding to the N data buses, one or more memories can control the second parallel interface to send N data signals to the first parallel interface through the N data buses in response to a read data request from the processing device. The processing device can control the first parallel interface to receive N data signals from the second parallel interface through the N data buses. The N data signals can carry data read from the one or more memories.

[0193] Assuming that data bus j corresponds to data signal j, the processing device can control the configured first parallel interface to receive data signal 1 from the second parallel interface through data bus 1, control the configured first parallel interface to receive data signal 2 from the second parallel interface through data bus 2,..., control the configured first parallel interface to receive data signal N from the second parallel interface through data bus N.

[0194] After configuration, the first parallel interface can receive a corresponding data signal from the first port of the link according to the interface parameters corresponding to the link. Assuming that the first link group includes data bus 1, the first parallel interface uses a Rodt value of 60 and an Rx EQ of gear 0 to receive data signal 1 from the first port of data bus 1. Assuming that the second link group includes data bus 2, the first parallel interface uses a Rodt value of 120 and an Rx EQ of gear 0 to receive data signal 2 from the first port of data bus 2. As shown in Figures 5 and 6, the size of Rodt affects the level of the signal in the link. Therefore, the level of data signal 1 is different from the level of data signal 2.

[0195] Referring to Figure 3-2, assuming that the data bus 1 is L0 shown in Figure 3-2, the memory chip 1-1 (or the communication module in the memory chip 1-1 shown in Figure 3-2) can send data signal 1 to L0 through the parallel interface according to the data stored in the storage medium, and the processing device (or the communication module in the processing device shown in Figure 3-2) can receive data signal 1 from the data bus 1 through the parallel interface.

[0196] S904B: The processing device obtains data stored in one or more memories from the N data signals.

[0197] After the processing device controls the configured first parallel interface to receive N data signals from the second parallel interface through N data buses, the processing device can receive the N data signals through the first parallel interface, and determine the data to be read from one or more memories based on the N data signals, and then process or transmit the data.

[0198] The processing device configures one or more parameters for the first parallel interface to receive signals through the corresponding link group according to the configuration information corresponding to each link group, which facilitates configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. The processing device then controls the configured first parallel interface to receive multiple data signals from the second parallel interface to read data from one or more memories. This facilitates reducing the power consumption of the first parallel interface while ensuring the signal quality of the multiple data signals, thereby facilitating reducing the power consumption of the processing device and, ultimately, the power consumption of the electronic system.

[0199] Assuming the target interface is the second parallel interface, the following describes a process for an electronic device to write data to one or more memories via the parallel interface. FIG9C schematically illustrates a possible flow of the method. As shown in FIG9C , the method may include S901C to S904C.

[0200] S901C: The processing device determines multiple configuration information;

[0201] The processing device may determine multiple configuration information. Optionally, referring to FIG3-2 , the configuration module in the processing device may determine multiple configuration information.

[0202] Similar to S901A above, for example, the processing device may divide N data buses into P link groups. Afterwards, the processing device may determine the configuration information corresponding to each link group, that is, determine P configuration information. Wherein, P is a positive integer less than or equal to N. The present application does not limit the manner in which the processing device groups the N data buses. As mentioned above, optionally, the processing device may divide the links in different channels into different link groups. Alternatively, the processing device may divide the links in different channels into different link groups, and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group introduced above.

[0203] Unlike S901A described above, the configuration information can be used to indicate the values ​​of one or more parameters of the second parallel interface. For the data writing process, the configuration information can include at least the write process configuration information described above. The write process configuration information can be used to indicate the parameters used by the second parallel interface to receive signals via the link, such as the Rodt value and / or the Rx EQ value of the second parallel interface.

[0204] Similar to S901A above, this application refers to two link groups in the multiple link groups as the first link group and the second link group, respectively. The configuration information corresponding to the first link group is referred to as the first configuration information, and the configuration information corresponding to the second link group is referred to as the second configuration information. Because the routing of links in different link groups generally varies significantly, the value of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information can be different.

[0205] Different from the above S901A, for example, the first configuration information may indicate Rodt=34 and the Rx EQ value is gear 0, while the second configuration information may indicate Rodt=48 and the Rx EQ value is gear 0. Accordingly, the target parameter is Rodt.

[0206] As mentioned above, when a single link has multiple second ports, the ODT of the second parallel interface includes three sub-parameters, which are respectively recorded as rtt_park, rtt_nom and rtt_wr. As an example, the values ​​of rtt_park, rtt_nom and rtt_wr indicated by the first configuration information can be 60, 240 and 240 respectively, and the values ​​of rtt_park, rtt_nom and rtt_wr indicated by the second configuration information can be 60, 120 and 120 respectively. Accordingly, the target parameter may include rtt_park. Alternatively, when the values ​​of at least one of rtt_park, rtt_nom and rtt_wr are different, it can be considered that the values ​​of Rodt are different. Therefore, it can also be considered that the values ​​of Rodt indicated by the first configuration information and the values ​​of Rodt indicated by the second configuration information are different.

[0207] S902C: The processing device configures one or more parameters used by the second parallel interface to receive signals through the corresponding link group according to the values ​​indicated by each configuration information;

[0208] Similar to S902A above, after the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, referring to FIG3-2 , S902C can be performed by a configuration module in the processing device.

[0209] After the processing device determines the P configuration information corresponding to the P link groups, assuming that configuration information i corresponds to link group i, i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to link group 1 according to the values ​​indicated by configuration information 1, configure the interface parameters corresponding to link group 2 according to the values ​​indicated by configuration information 2,..., configure the interface parameters corresponding to link group P according to the values ​​indicated by configuration information P.

[0210] Regarding configuring the write process parameters of the second parallel interface, unlike S902A above, the processing device configuring the interface parameters corresponding to link group i according to the values ​​indicated by configuration information i may mean that, for each link in link group i, the processing device may configure one or more parameters used by the second parallel interface to receive signals through the link according to the values ​​indicated by configuration information i. For example, for each link in the first link group, the processing device may configure the Rodt and Rx EQ used by the second parallel interface to receive signals through the link to 240 and gear 0, respectively, according to the values ​​indicated by the first configuration information. For each link in the second link group, the processing device may configure the Rodt and Rx EQ used by the second parallel interface to receive signals through the link to 120 and gear 0, respectively, according to the second configuration information.

[0211] This application does not limit the manner in which the processing device configures one or more parameters used by the second parallel interface to receive signals through the link.

[0212] For example, the processing device may send the aforementioned configuration signal to the memory connected to the second port of the link. The configuration signal is used to indicate the values ​​of one or more parameters used by the parallel interface of the memory to receive signals through the link. Assuming that the processing device sends the configuration signal to the memory according to the first configuration information, the configuration signal may instruct the memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 240 and gear 0, respectively.

[0213] When a link has multiple second ports, the processing device can send configuration signals to the memory connected to each second port of the link. Continuing with Figure 8-2 , assume that the link has second ports 1 through 4, with second port 1 connected to the memory chip in D1R0, second port 2 connected to the memory chip in D1R1, second port 3 connected to the memory chip in D0R0, and second port 4 connected to the memory chip in D0R1. The processing device can send configuration signals 1 through 4 to the memory connected to second ports 1 through 4, respectively. Assume that the processing device sends configuration signals 1 to 4 respectively according to the first configuration information, the first configuration information indicates that the values ​​of rtt_park, rtt_nom and rtt_wr are 60, 240 and 240 respectively, the value of Rx EQ is gear 0, and the memory connected to the second port 1 is a memory to which data is to be written. Then, configuration signal 1 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 240 and gear 0 respectively, configuration signal 2 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 240 and gear 0 respectively, configuration signal 3 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 60 and gear 0 respectively, and configuration signal 4 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 60 and gear 0 respectively.

[0214] S903C: The processing device controls the first parallel interface to send N data signals to the configured second parallel interface through N data buses;

[0215] After the processing device configures the parameters of the second parallel interface, the processing device can control the first parallel interface to send N data signals to the second parallel interface through N data buses. The N data signals can carry data to be written into one or more memories.

[0216] Assuming that data bus j corresponds to data signal j, the processing device can control the first parallel interface to send data signal 1 to the configured second parallel interface through data bus 1, control the first parallel interface to send data signal 2 to the configured second parallel interface through data bus 2,..., control the configured first parallel interface to send data signal N to the configured second parallel interface through data bus N.

[0217] After configuration, the second parallel interface can receive a corresponding data signal from the second port of the link according to the interface parameters corresponding to the link. Assuming that the first link group includes data bus 1, the second parallel interface can use a Rodt value of 240 and an Rx EQ of gear 0 to send data signal 1 from the second port of data bus 1. Assuming that the second link group includes data bus 2, the first parallel interface uses a Rodt value of 120 and an Rx EQ of gear 0 to receive data signal 2 from the second port of data bus 2. As shown in Figures 5 and 6, the size of Rodt affects the level of the signal in the link. Therefore, the level of data signal 1 is different from the level of data signal 2.

[0218] Referring to Figure 3-2, assuming that data bus 1 is L0 as shown in Figure 3-2, the processing device (or the communication module in the processing device shown in Figure 3-2) can control its own parallel interface to send data signal 1 to memory chip 1-1 through data bus 1.

[0219] S904C: One or more memories store data transmitted by the N data signals.

[0220] After the processing device controls the first parallel interface to send N data signals to the configured second parallel interface through N data buses, one or more memories can receive the N data signals through the configured second parallel interface, and determine the data to be written by the processing device based on the N data signals, and write the data into their own storage media.

[0221] Referring to FIG3-2 , assuming data bus 1 is L0 as shown in FIG3-2 , a processing device can send data signal 1 to memory chip 1-1 via data bus 1. One or more memories storing the data carried by data signal 1 can mean that memory chip 1-1 receives data signal 1 via its own parallel interface and then writes the data carried by data signal 1 to its own storage medium. Alternatively, referring to FIG3-2 , a communication module in memory chip 1-1 can write the data to the storage medium.

[0222] The processing device configures one or more parameters for the second parallel interface to receive signals through the corresponding link group according to the configuration information corresponding to each link group, which facilitates configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. The processing device then controls the first parallel interface to transmit multiple data signals to the configured second parallel interface, which facilitates reducing the power consumption of the second parallel interface while ensuring the signal quality of the multiple data signals, thereby facilitating reducing the power consumption of one or more memories, and ultimately reducing the power consumption of the electronic system.

[0223] Assuming that the target interface is the second parallel interface, the following describes the process of an electronic device reading data from one or more memories via the parallel interface. FIG9D schematically illustrates a possible process of the method. As shown in FIG9D , the method may include S901D to S904D.

[0224] S901D, the processing device determines multiple configuration information;

[0225] The processing device may determine multiple configuration information. Optionally, referring to FIG3-2 , the configuration module in the processing device may determine multiple configuration information.

[0226] Similar to S901A above, for example, the processing device may divide N data buses into P link groups. Afterwards, the processing device may determine the configuration information corresponding to each link group, that is, determine P configuration information. Wherein, P is a positive integer less than or equal to N. The present application does not limit the manner in which the processing device groups the N data buses. As mentioned above, optionally, the processing device may divide the links in different channels into different link groups. Alternatively, the processing device may divide the links in different channels into different link groups, and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group introduced above.

[0227] Unlike S901A described above, the configuration information can be used to indicate the values ​​of one or more parameters of the second parallel interface. For the data reading process, the configuration information can include at least the read process configuration information described above. The read process configuration information can be used to indicate the values ​​of parameters used by the second parallel interface to transmit signals over the link, such as the value of the second parallel interface's Ron and / or the value of Tx EQ.

[0228] Similar to S901A above, this application refers to two link groups in the multiple link groups as the first link group and the second link group, respectively. The configuration information corresponding to the first link group is referred to as the first configuration information, and the configuration information corresponding to the second link group is referred to as the second configuration information. Because the routing of links in different link groups generally varies significantly, the value of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information can be different.

[0229] Unlike the configuration information in S901A above, which indicates parameters on the controller side, the configuration information can indicate parameters on the memory side. For example, the first configuration information may indicate Ron = 34 and Tx EQ value is level 0 on the memory side, while the second configuration information may indicate Ron = 48 and Tx EQ value is level 0 on the memory side. Accordingly, the target parameter is Ron.

[0230] Optionally, the read process configuration information may also indicate the value of Rodt. As previously described, when a single link has multiple second ports (e.g., second port 1 to second port 4), assuming that the processing device reads data from the memory connected to the second port 1, the processing device may also configure the memory connected to the other second ports to correspond to the Rodt of the link. Accordingly, the read process configuration information may also be used to indicate the values ​​of rtt_park, rtt_nom, and rtt_wr, respectively. As an example, the values ​​of rtt_park, rtt_nom, and rtt_wr indicated by the first configuration information may be 60, 240, and 240, respectively, and the values ​​of rtt_park, rtt_nom, and rtt_wr indicated by the second configuration information may be 60, 120, and 120, respectively. Accordingly, the target parameter may include rtt_park. Alternatively, when the values ​​of at least one of rtt_park, rtt_nom, and rtt_wr are different, it can be considered that the values ​​of Rodt are different. Therefore, it can also be considered that the values ​​of Rodt indicated by the first configuration information and the values ​​of Rodt indicated by the second configuration information are different.

[0231] S902D: The processing device configures one or more parameters used by the second parallel interface to send signals through the corresponding link group according to the values ​​indicated by each configuration information;

[0232] Similar to S902A above, after the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, with reference to Figure 3-2, S902D can be executed by the configuration module in the processing device. For example, after the processing device determines P configuration information corresponding to P link groups, assuming that configuration information i corresponds to link group i, i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to link group 1 according to the values ​​indicated by configuration information 1, configure the interface parameters corresponding to link group 2 according to the values ​​indicated by configuration information 2, ..., configure the interface parameters corresponding to link group P according to the values ​​indicated by configuration information P.

[0233] Regarding configuring the read process parameters of the second parallel interface, unlike S902A above, the processing device configuring the interface parameters corresponding to link group i according to the values ​​indicated by configuration information i may mean that, for each link in link group i, the processing device may configure one or more parameters used by the second parallel interface to transmit signals through the link according to the values ​​indicated by configuration information i. For example, for each link in the first link group, the processing device may configure the Ron and Tx EQ used by the second parallel interface to transmit signals through the link to 34 and gear 0, respectively, according to the values ​​indicated by the first configuration information. For each link in the second link group, the processing device may configure the Rodt and Rx EQ used by the second parallel interface to receive signals through the link to 48 and gear 0, respectively, according to the second configuration information.

[0234] This application does not limit the manner in which the processing device configures one or more parameters used by the second parallel interface to receive signals through the link.

[0235] Similar to S902C, for example, the processing device may send the aforementioned configuration signal to the memory connected to the second port of the link. The configuration signal is used to instruct the parallel interface of the memory to use one or more parameter values ​​for transmitting signals via the link. Assuming that the processing device sends the configuration signal to the memory according to the first configuration information, the configuration signal may instruct the memory to configure the parallel interface's Ron and Tx EQ corresponding to the link to 34 and level 0, respectively.

[0236] When a link has multiple second ports, the processing device can send configuration signals to the memory connected to each second port of the link. Continuing with Figure 8-2 , assume that the link has second ports 1 through 4, with second port 1 connected to the memory chip in D1R0, second port 2 connected to the memory chip in D1R1, second port 3 connected to the memory chip in D0R0, and second port 4 connected to the memory chip in D0R1. The processing device can send configuration signals 1 through 4 to the memory connected to second ports 1 through 4, respectively. Assume that the processing device sends configuration signals 1 to 4 respectively according to the first configuration information, the first configuration information indicates that Ron is 34, the values ​​of rtt_park, rtt_nom and rtt_wr are 60, 240 and 240 respectively, the value of Tx EQ is gear 0, and the memory connected to the second port 1 is a memory for reading data, then, configuration signal 1 can instruct the corresponding memory to configure the Ron and Rx EQ of the parallel interface corresponding to the link to 34 and gear 0 respectively, configuration signal 2 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 240 and gear 0 respectively, configuration signal 3 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 60 and gear 0 respectively, and configuration signal 4 can instruct the corresponding memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 60 and gear 0 respectively.

[0237] S903D: The processing device controls the first parallel interface to receive N data signals from the configured second parallel interface through N data buses;

[0238] After the processing device configures the parameters of the second parallel interface, one or more memories can respond to a read data request from the processing device and control the configured second parallel interface to send N data signals to the first parallel interface via N data buses. The processing device can control the first parallel interface to receive N data signals from the second parallel interface via N data buses. The N data signals can carry data read from the one or more memories.

[0239] Assume that data bus j corresponds to data signal j, where j is a positive integer less than or equal to N. The configured second parallel interface sends data signal 1 to the first parallel interface via data bus 1, sends data signal 2 to the first parallel interface via data bus 2, ..., and sends data signal N to the first parallel interface via data bus N.

[0240] After configuration, the second parallel interface can send a corresponding data signal to the second port of the link according to the interface parameters corresponding to the link. Assuming that the first link group includes data bus 1, the second parallel interface can use an Ron value of 34 and a Tx EQ of gear 0 to send data signal 1 to the second port of data bus 1. Assuming that the second link group includes data bus 2, the second parallel interface uses an Ron value of 48 and a Tx EQ of gear 0 to send data signal 2 to the second port of data bus 2. As shown in Figures 5 and 6, the size of Ron affects the level of the signal in the link. Therefore, the level of data signal 1 is different from the level of data signal 2.

[0241] Referring to Figure 3-2, assuming that the data bus 1 is L0 shown in Figure 3-2, the memory chip 1-1 (or the communication module in the memory chip 1-1 shown in Figure 3-2) can send data signal 1 to L0 through the parallel interface according to the data stored in the storage medium, and the processing device (or the communication module in the processing device shown in Figure 3-2) can receive data signal 1 from the data bus 1 through the parallel interface.

[0242] S904D: The processing device obtains data stored in one or more memories from the N data signals.

[0243] After the processing device controls the first parallel interface to receive N data signals from the configured second parallel interface through N data buses, the processing device can receive the N data signals through the first parallel interface, and determine the data to be read from one or more memories based on the N data signals, and then process or transmit the data.

[0244] The processing device configures one or more parameters for the second parallel interface to transmit signals through the corresponding link group according to the configuration information corresponding to each link group, thereby facilitating configuration of interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. The processing device then controls the first parallel interface to receive multiple data signals from the configured second parallel interface, thereby facilitating reduction of power consumption of the second parallel interface while ensuring signal quality of the multiple data signals, thereby facilitating reduction of power consumption of one or more memories, and ultimately reducing power consumption of the electronic system.

[0245] In S902C and S902D above, the processing device may configure one or more parameters used by the memory connected to the link to transmit signals via the link according to the configuration information. The processing device may send a configuration signal to the memory via a control bus connected to the memory, where the configuration signal indicates values ​​of the one or more parameters used by the memory to transmit signals via the link, as determined according to the configuration information.

[0246] Optionally, the processing device may send a configuration signal to the memory before each reading or writing of data, where the configuration signal carries the values ​​of the one or more parameters.

[0247] Alternatively, to reduce the length of information carried by the configuration signal, the processing device may send a first configuration signal to the memory, where the first configuration signal carries the values ​​of parameters indicated by the configuration information. For example, the first configuration signal carries the values ​​of Ron, rtt_park, rtt_nom, and rtt_wr. Thereafter, before each data read or write, the processing device may send a second configuration signal to the memory, where the second configuration signal is used to determine the value of at least one parameter from the values ​​of the multiple parameters carried by the first configuration signal. The memory may then configure its own parallel interface according to the value of the at least one parameter.

[0248] For example, continuing to refer to FIG8-2 , before writing D1R0 , the processor may send a second configuration signal to the memory chip in D1R0 , where the second configuration signal instructs to configure Rodt according to the value of rtt_wr .

[0249] The parallel interface of the processor can send a configuration signal to a single memory chip through one or more pins, and the one or more pins can be connected to the control bus. When the parallel interface of the processor sends a configuration signal to the memory chip through multiple pins, optionally, one of the multiple pins can be used to transmit the signal of the above-mentioned ODT field, and the pin can refer to the "ODT pin" shown in Figure 8-2. When the second configuration signal "0" sent by the first parallel interface through the pin is "0", the memory chip can be instructed to configure the ODT according to the value of rtt_park. When the second configuration signal "1" sent by the first parallel interface through the pin is "1", the memory chip can be instructed to configure the ODT according to the value of rtt_nom.

[0250] In the above S901A, S901B, S901C and S901D, the processing device may determine the configuration information corresponding to each link group in the plurality of link groups. This application does not limit the manner in which the processing device determines the configuration information corresponding to the link group.

[0251] Optionally, the processing device may determine the configuration information corresponding to each of the multiple link groups using a static configuration method. For example, the processing device may obtain the configuration information corresponding to each of the multiple link groups from firmware (FW).

[0252] For example, by grouping multiple links by channel or byte, simulation and testing during the R&D phase can traverse the parameters of different channels or different bytes within each channel to evaluate a set of differentiated parameter combinations that meet SI margins and optimize power consumption. These differentiated parameter combinations are then written to the processor's firmware. During power-on initialization, the processor retrieves the values ​​configured for the parameters of the multiple links from the firmware and configures the corresponding registers based on these values.

[0253] Taking the parallel interface of the processing device having m channels and each channel having n bytes as an example, the multiple configuration information obtained by the processing device can be CHiBj represents the value of the link parameter in byte j of channel i, where m and n are positive integers greater than 1, i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n.

[0254] For example, if the parallel interface of the processing device has m channels, the multiple configuration information obtained by the processing device may be Para = [CH1 ... CHm]. CHi represents the value of the link parameter in channel i, where m is a positive integer greater than 1 and i is a positive integer less than or equal to m.

[0255] Taking the parallel interface of the processing device as an example, which has one channel and n bytes, the above differentiated parameter combination can be Para = [B1…Bn]. Bi represents the value of the link parameter in byte j. Where n is a positive integer greater than 1, and j is a positive integer less than or equal to n.

[0256] Alternatively, the processing device may adopt a dynamic configuration method to determine the configuration information corresponding to each link group in the plurality of link groups. For example, the processing device may determine the configuration information corresponding to each link group through a parameter training program.

[0257] The processing device can optimize the configuration information corresponding to each link group through parameter training to determine its optimal configuration information. For example, the processing device can configure the parameters used by the target interface to transmit signals through the link group according to multiple different configuration information, transmit test signals through the configured target interface, and record the configuration information that results in the SI margin of the test signals transmitted by each link in the link group exceeding a threshold as the candidate configuration information. The processing device can then select the candidate configuration information with the lowest power consumption from the multiple candidate configuration information as the optimal configuration information corresponding to the link group.

[0258] For example, the parallel interface of the processing device has m channels and each channel has n bytes. After power-on, the processing device can optimize the configuration information corresponding to each byte in each channel through a training algorithm, select a set of configuration information (i.e., a combination of parameter values) that meets the SI margin requirements and has the best power consumption for each byte link group, and then configure the registers corresponding to the links in each byte in the target parallel interface based on the differentiated configuration information. The multiple configuration information obtained by the processing device can be All links in the same byte can share the same parameter configuration. For example, the parameters of all links in byte 1 of channel 1 can be configured as CH1B1.

[0259] Taking the parallel interface of the processing device as an example, which has m channels, after power-on, the processing device can optimize the configuration information corresponding to the link of each channel through a training algorithm, select a set of configuration information (i.e., a combination of parameter values) for each channel link group that meets the SI margin requirements and optimizes power consumption, and then configure the registers corresponding to the links in each channel of the target parallel interface based on the differentiated configuration information. The multiple configuration information obtained by the processing device can be Para = [CH1…CHm]. All links in the same channel can share the same parameter configuration. For example, the parameters of all links in channel 1 can be configured as CH1.

[0260] Taking the parallel interface of a processing device with one channel and n bytes as an example, after power-on, the processing device can optimize the parameters of the link of each byte through a training algorithm, select a set of configuration information (i.e., a combination of parameter values) for each byte link group that meets the SI margin requirements and optimizes power consumption, and then configure the registers corresponding to the links in each byte of the target parallel interface based on the differentiated configuration information. The multiple configuration information obtained by the processing device can be Para = [B1…Bn]. All links in the same byte can share the same parameter configuration. For example, the parameters of all links in byte 1 can be configured as B1.

[0261] This application does not limit the way in which the processing device determines the power consumption. For example, the processing device can determine the power consumption corresponding to each configuration information through a table or formula, or can predict the power consumption by the size of the SI margin.

[0262] When the configuration information corresponding to the link group is used to indicate the value of each parameter in a plurality of parameters, the processing device may group the plurality of parameters, and then sequentially optimize the plurality of parameter combinations corresponding to the link group.

[0263] For example, assuming that the multiple parameters include Ron, ODT, transmitter pre-emphasis parameters, CTLE parameters and DFE parameters, the processing device can divide the multiple parameters into two parameter combinations, the first parameter combination can include Ron and ODT, and the second parameter combination can include transmitter pre-emphasis parameters, CTLE parameters and DFE parameters.

[0264] The processing device can determine multiple value combinations for each parameter combination. The parameter values ​​in the value combination are the possible values ​​of the parameter configured by the parallel interface. The protocol specifies the possible values ​​of each parameter, and multiple value combinations can be determined based on the protocol. Taking the processor shown in Figure 2-1 as the processing device, multiple value combinations of the parameter combination can be determined by referring to the relevant content of the NAND flash memory protocol. For example, the possible values ​​of Ron and ODT can be determined by referring to Table 4-11 and Table 4-56 in the NAND flash memory protocol: ONFI. Taking the processor shown in Figure 2-2 as the processing device, multiple value combinations of the parameter combination can be determined by referring to the relevant content of the DDR protocol. For example, the possible values ​​of Ron and ODT can be determined by referring to Table 136 and Table 110 in the DDR protocol: JESD79. Figures 10 and 11 schematically illustrate the possible values ​​of the above parameters. In actual applications, the possible values ​​of the parameters may differ from those in Figures 10 and 11. The multiple value combinations selected by the processing device may be all value combinations determined based on the possible values ​​of each parameter, or may be a preferred partial value combination. For example, in a DDR2 single-channel dual-DIMM (2DIMM per Channel, 2DPC) scenario, the values ​​of rtt_Wr and rtt_Nom may be preferably 240, and the value of rtt_Park may be preferably a value between 120 and 40.

[0265] After the processing device determines the multiple value combinations of the first parameter combination, it can scan the multiple value combinations of the first parameter combination corresponding to the link group to determine the optimal value combination. The optimal value combination may refer to a value combination that enables the link group to meet the SI margin requirements and has the best power consumption. Afterwards, after setting the first parameter combination according to the optimal value combination of the first parameter combination, the optimal value combination can be determined by scanning from the multiple values ​​of the second parameter combination. Thus, the processing device can determine the optimal value combination of the multiple parameters corresponding to the link group (i.e., Ron, ODT, transmitter pre-emphasis parameters, CTLE parameters, and DFE parameters), that is, the optimal configuration information corresponding to the link group.

[0266] 12 , an example is given below to illustrate how the processing device scans multiple different values ​​of a target parameter of a target link and determines the optimal value. The target link may be a single uplink or a downlink, and the target parameter may be a single parameter of a target interface or a combination of single parameters.

[0267] As shown in FIG12 , the method for the processing device to determine the optimal value combination of the target parameter combination corresponding to the link group i through the parameter training process may include S1201 to S1208 .

[0268] S1201: Determine a value combination sequence of a target parameter combination, where the value combination sequence includes multiple different value combinations of the target parameter combination;

[0269] Assume that the value combination sequence is {v1, v2, ..., vn}, where n is a positive integer.

[0270] S1202, selecting a value combination (denoted as vi) from the value combination sequence, so that the value combination v of the target parameter combination = vi;

[0271] S1203, configure the target interface using v, control the target interface to transmit a test signal through link group i, and detect the SI margin of the test signal;

[0272] S1204: Determine whether the SI margin meets the requirements, for example, whether the SI margin is not lower than the threshold. If so, execute S1205; if not, execute S1207.

[0273] S1205. Record the value of v;

[0274] S1206: Determine whether to traverse the value sequence. If not, execute S1207; if yes, execute S1208.

[0275] S1207, select the next value combination (denoted as vi+1) from the value combination sequence, so that the value combination v of the target parameter combination = vi+1, triggering S1203;

[0276] S1208 . Determine the optimal value combination for power consumption from all recorded value combinations of v, that is, the optimal value combination for the target parameter combination corresponding to the link group i.

[0277] This application does not limit the way in which the processing device determines the power consumption. For example, the processing device can determine the power consumption corresponding to each value combination through a table or formula, or can predict the power consumption by the size of the SI margin.

[0278] In the method described above, taking the example of the processing device configuring one or more parameters used by the target interface to transmit signals through the corresponding link group according to the values ​​indicated by each configuration information in multiple configuration information, this application does not limit the method of the processing device to differentially configure the interface parameters corresponding to different links or different link groups. For example, the processing device can call a machine learning model to configure one or more parameters used by the target interface to transmit signals through at least two links, and the machine learning model is used to predict the optimal configuration of the parameters used by the target interface to transmit signals through each link and configure the interface parameters corresponding to each link. Accordingly, the processing device may not need to determine multiple configuration information.

[0279] In the above, the processing device configures the parameters used by the target interface to transmit data signals via a data bus as an example. Optionally, the processing device can configure the parameters used by the target interface to transmit control signals via multiple control buses according to the above method, and the processing device configures different values ​​for the interface parameters corresponding to at least two control buses. Thereafter, the processing device can control the first parallel interface to transmit control signals to the second parallel interface via the multiple control buses. This application does not limit the specific type of control signal. For example, the control signal can include at least one of an address signal, a chip select signal, a synchronization signal, and a configuration signal.

[0280] In the above example, the processing device configures interface parameters corresponding to the target interface via N data buses. Alternatively, the processing device may configure interface parameters corresponding to a portion of the N data buses. Subsequently, the processing device may optionally control the first parallel interface to transmit data signals to the second parallel interface via the configured portion of the data buses.

[0281] In the above example, the processing device controls the first parallel interface to send N data signals to or receive N data signals from N data buses. Alternatively, the processing device may control the first parallel interface to send N1 data signals to N1 of the N data buses, and control the first parallel interface to receive N2 data signals from N2 of the N data buses. N1 and N2 are positive integers, and N1 + N2 is less than or equal to N.

[0282] Assume that the memory structure is as shown in memory chip 1-1 in Figure 3-2. That is, the memory may include a control device, a parallel interface, and a storage medium. The control device may be connected to the parallel interface and the storage medium, respectively. As previously described, the configuration module in the control device is used to configure the parameters of the parallel interface. The communication module controls the parallel interface and transmits signals with the first parallel interface of the processing device to send data from the storage medium to the processing device or receive data sent by the processing device to be written to the storage medium.

[0283] In the method described above, the processing device configures the parameters of the parallel interface of the memory. Optionally, the parallel interface of the memory may not be configured by the processing device, but the memory (or the configuration module in the memory) may configure its own parallel interface. Assuming that the parallel interface of the memory and the first parallel interface of the processing device are connected through multiple links, based on the above analysis ideas and solutions, the present application also provides a method, in which the memory (or the configuration module in the memory) can perform differentiated configuration on at least two links of the multiple links. The at least two links can both be used to transmit data signals or both be used to transmit control signals. For specific solutions and effects, please refer to the content of the differentiated configuration solution executed by the processing device described above.

[0284] For example, before the processing device controls the first parallel interface to transmit multiple signals to the parallel interface of the memory via at least two of the multiple links, the memory may configure one or more parameters for transmitting signals via the at least two links on its parallel interface. Furthermore, at least two of the at least two links (e.g., the first link and the second link) are present, and the memory differentially configures the interface parameters corresponding to the two links.

[0285] For example, the memory may determine configuration information corresponding to each link group, and configure interface parameters corresponding to the corresponding link group according to the configuration information corresponding to each link group.

[0286] For example, the memory may divide at least two links into multiple link groups, determine configuration information corresponding to each link group, and then configure interface parameters corresponding to each link in the corresponding group according to the configuration information corresponding to each link group.

[0287] For example, assuming that multiple links correspond to multiple channels of the first parallel interface, the memory may determine optimal configuration information corresponding to each channel, and then configure interface parameters corresponding to the links in the corresponding channels according to the optimal configuration information corresponding to each channel.

[0288] For example, assuming that multiple links correspond to one or more channels of the first parallel interface, and the bit width of a single channel is multiple bytes, the memory can determine the optimal configuration information corresponding to each byte, and then configure the interface parameters corresponding to the link in the corresponding byte according to the optimal configuration information corresponding to each byte.

[0289] For example, S901C and S902C may be executed by a memory instead of a processing device, and / or S901D and S902D may be executed by a memory instead of a processing device.

[0290] The above introduces the methods, devices and equipment provided by this application. This application also provides a computer-readable medium, which stores instructions. When the computer-readable medium is run on an electronic device (such as a computer), it enables the electronic device to execute the methods described in the above aspects.

[0291] An embodiment of the present application further provides a computer program product, which, when executed on an electronic device (eg, a computer), enables the electronic device (eg, a computer) to execute the methods described in the above aspects.

[0292] It should also be noted that the embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the modules mentioned in this application may be hardware circuits, modules that exist in the form of software, or modules implemented by a combination of hardware circuits and software. The components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which may be implemented as one or more communication buses or signal lines.

[0293] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate and are merely used to describe the manner in which objects with the same attributes are described in the embodiments of this application.

[0294] Those skilled in the art will appreciate that the aforementioned computer-readable storage media include various non-transitory machine-readable media that can store program codes, such as USB flash drives, mobile hard disks, magnetic disks, optical disks, RAM, SSDs, or non-volatile memories.

[0295] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, rather than to limit it.

Claims

1. A signal transmission method, characterized in that: The method is applied to an electronic system, the electronic system comprising an electronic device and one or more memories, a first parallel interface of the electronic device being connected to a second parallel interface of the one or more memories via a plurality of links, the method comprising: configuring one or more parameters respectively adopted by a target interface to transmit signals through at least two of the multiple links, the target interface comprising the first parallel interface and / or the second parallel interface, the at least two links comprising a first link and a second link, the one or more parameters comprising a target parameter, and the values ​​of the target parameter respectively adopted by the configured target interface to transmit signals through the first link and the second link are respectively a first value and a second value; The first parallel interface is controlled to transmit multiple signals with the second parallel interface through the at least two links.

2. The signal transmission method according to claim 1, characterized in that: The at least two links include a first link group, the first link group includes the first link and other links, and the other links do not include the second link. The value of the target parameter used by the configured target interface to transmit signals through the other links is the first value.

3. The signal transmission method according to claim 2, characterized in that: The first link group is used to transmit signals in the same channel, or to transmit signals in the same byte.

4. The signal transmission method according to any one of claims 1 to 3, characterized in that: The first link and the second link are used to transmit signals in different channels, or to transmit signals in different bytes of the same channel.

5. The signal transmission method according to any one of claims 2 to 4, characterized in that: The method further comprises: Controlling the target interface to use the target parameters with multiple different values ​​to transmit test signals through the first link group respectively; The first value is determined from the multiple different values ​​according to signal integrity SI margins of the multiple transmitted test signals.

6. The signal transmission method according to claim 5, characterized in that: The multiple different values ​​include one or more values, wherein the SI margin of the test signal respectively transmitted by the target interface using the target parameters of the one or more values ​​is not lower than a threshold, and the one or more values ​​include the first value, and among the one or more values, the power consumption of the signal transmitted by the target interface using the target parameters of the first value is minimal.

7. The signal transmission method according to any one of claims 1 to 6, characterized in that: The one or more parameters include at least one of the following parameters: Driving capability parameters, transmitter equalization EQ parameters, on-chip termination ODT parameters and receiver equalization EQ parameters.

8. The signal transmission method according to any one of claims 1 to 7, characterized in that: The multiplexed signals are used to transmit data to be written into the one or more memories, or to transmit data read from the one or more memories.

9. The signal transmission method according to any one of claims 1 to 8, characterized in that: The one or more memories include non-volatile flash memory and / or double data rate synchronous dynamic random access memory DDR SDRAM.

10. A processing device, characterized in that: The processing device is applied to an electronic device, wherein a first parallel interface of the electronic device is connected to a second parallel interface of one or more memories via multiple links, and the processing device comprises: a configuration module, used to configure one or more parameters respectively adopted by a target interface for transmitting signals through at least two of the multiple links, the target interface comprising the first parallel interface and / or the second parallel interface, the at least two links comprising a first link and a second link, the one or more parameters comprising a target parameter, and the values ​​of the target parameter respectively adopted by the configured target interface for transmitting signals through the first link and the second link are respectively a first value and a second value; The communication module is used to control the first parallel interface to transmit multiple signals with the second parallel interface through the at least two links.

11. An electronic device, characterized in that: The electronic device comprises a processing device and a parallel interface, the processing device is connected to the parallel interface, the parallel interface is used to connect to one or more memories, and the processing device is used to execute the method as claimed in any one of claims 1-9.

12. The electronic device according to claim 11, characterized in that: The processing device comprises a processor, and the processor is configured to execute instructions stored in a memory, so that the processing device performs the method according to any one of claims 1 to 9.

13. The electronic device according to claim 11, characterized in that: The processing device comprises a logic circuit for executing the method according to any one of claims 1 to 9.

14. An electronic system, characterized in that: The electronic system comprises an electronic device and one or more memories, wherein the electronic device and the one or more memories are connected via a parallel interface, and the electronic device is as described in any one of claims 11-13.

15. The electronic system according to claim 14, characterized in that: The electronic system is a computer device or a storage device.

16. A computer-readable storage medium, characterized in that: The method comprises instructions which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 9.

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