Transmission method and communication device

Abstract

A transmission method and a communication device, relating to the technical field of communications. In the method, a first device can superpose all bits of a first bit sequence and some bits of each second bit sequence among N second bit sequences to obtain a third bit sequence, and transmit the third bit sequence to a second device. Compared with a two-layer superposition transmission scheme (for example, superposing the first bit sequence and one second bit sequence to obtain a third bit sequence), the method effectively improves the decoding reliability of the bit sequence which is not correctly decoded among the N second bit sequences, avoids the problem of error propagation due to decoding errors, and will not result in a decrease in the reliability of the third bit sequence; and compared with a multi-layer superposition transmission scheme (for example, superposing the first bit sequence and the N second bit sequences to obtain a third bit sequence), the method can also effectively reduce the decoding difficulty of the third bit sequence.

Description

Transmission Method and Communication Device This application claims the priority of a Chinese patent application with the application number 202311763671.9 and the application title "Transmission Method and Communication Device" submitted to the China National Intellectual Property Administration on December 20, 2023. The entire content thereof is incorporated herein by reference in its entirety. Technical Field This application relates to the field of communication technologies, and more particularly, to a transmission method and a communication device. Background Art The superposition transmission technology is a coding scheme for packet Markov superposition transmission. The transmitting end can divide the transmission block to be transmitted into multiple sub-blocks, and encode the obtained sub-blocks by combining with a low density parity check (LDPC) coding scheme to obtain corresponding coded codewords. The transmitting end can perform a superposition operation on the obtained coded codewords. For example, a superposition operation of bitwise exclusive OR of the previous coded codeword and the current coded codeword is performed, and the coded codeword obtained after superposition is used as the actually transmitted coded codeword. When performing the superposition operation, the transmitting end usually adopts a two-layer superposition coding scheme, but this superposition coding scheme is prone to the problem of a single superposition failure, which is likely to cause an error propagation problem; if a multi-layer superposition coding scheme is directly adopted, iterative message passing decoding needs to be performed on the soft information of multiple layers, and the decoding complexity will also be increased. Therefore, how to simultaneously improve the decoding reliability of superposition transmission and reduce the decoding complexity is a technical problem to be solved urgently at present. Summary of the Invention This application provides a transmission method and a communication device, which can support simultaneously improving the decoding reliability of superposition transmission and reducing the decoding complexity. In a first aspect, a transmission method is provided, including: obtaining a first bit sequence and N second bit sequences, where N is a positive integer; outputting a third bit sequence, where the third bit sequence is obtained by superposing the first bit of each of the N second bit sequences with all the bits of the first bit sequence, and the first bit is a part of the second bit sequence. The execution subject of the solution in the first aspect can be a first device, or a module (such as a chip system, etc.) in the first device, or a logical node, logical module or software that can implement all or part of the functions of the first device, which is not limited herein. For the convenience of description, the first device is taken as an example for description hereinafter. It should be noted that the above N second bit sequences are the second bit sequences that need to be used. For example, 10 second bit sequences can be obtained, and 8 of the 10 second bit sequences are used. Correspondingly, the value of the foregoing N can be 8. In the above technical solution, the first device may obtain a third bit sequence by superimposing all bits of the first bit sequence and partial bits of each of the N second bit sequences. Compared with a two-layer superimposed transmission scheme (for example, the first device obtains a third bit sequence by superimposing all bits of the first bit sequence and all bits of a second bit sequence), since partial second bit sequences among the N second bit sequences can be used to form multiple bit sequences, this can effectively improve the decoding reliability of the bit sequences that are not correctly decoded among the N second bit sequences, and will not cause an error propagation problem due to decoding errors, nor will it cause a decrease in the reliability of the third bit sequence. Compared with a multi-layer superimposed transmission scheme (for example, the first device obtains a third bit sequence by superimposing all bits of the first bit sequence and all bits of each of the N second bit sequences), since the number of XOR operations performed on the bits in the first bit sequence is less than N, this can effectively reduce the decoding difficulty of the third bit sequence. In the first aspect, the method further includes: obtaining a fourth bit sequence; outputting a fifth bit sequence, where the fifth bit sequence is obtained by superimposing all bits of the fourth bit sequence and at least one of the following: the first bit of at least one second bit sequence among the N second bit sequences, the second bit of at least one second bit sequence among the N second bit sequences, the second bit is partial bits in the second bit sequence, and the second bit is different from the first bit; or, partial bits in the first bit sequence. When the first bit of at least one second bit sequence among the N second bit sequences is used to form not only the third bit sequence but also the fifth bit sequence, the possibility of successful decoding of the first bit of the at least one second bit sequence can be enhanced by decoding one or both of the third bit sequence and the fifth bit sequence. When the first bit of at least one second bit sequence among the N second bit sequences is used to form the third bit sequence, the at least one The second bit of the second bit sequence is used to form the fifth bit sequence, so that the transmission reliability of the at least one second bit sequence can be enhanced. When the first bit sequence is used to form not only the third bit sequence but also the fifth bit sequence, the possibility of successful decoding of the first bit sequence can be enhanced by decoding one or both of the third bit sequence and the fifth bit sequence. In the first aspect, the method further includes: sending first indication information, where the first indication information is used to indicate the generation rule of the bit sequence. Among them, outputting the third bit sequence includes: outputting the third bit sequence according to the generation rule of the bit sequence. In this way, the second device can obtain the generation rule of the bit sequence and can decode the third bit sequence according to the generation rule of the bit sequence, which is conducive to increasing the possibility of the second device successfully decoding the third bit sequence. In the first aspect, the method further includes: receiving second indication information for indicating the generation rule of the bit sequence. Among them, outputting the third bit sequence includes: outputting the third bit sequence according to the generation rule of the bit sequence. In this way, the first device can obtain the generation rule of the bit sequence and generate the third bit sequence according to the generation rule of the bit sequence. When the first device sends the third bit sequence generated according to the generation rule of the bit sequence to the second device, the possibility of the second device successfully decoding the third bit sequence can be improved. In a second aspect, a transmission method is provided, including: obtaining a third bit sequence, where the third bit sequence is obtained by superimposing the first bit of each of the N second bit sequences on all the bits of the first bit sequence, and the first bit is a partial bit of the second bit sequence; determining the first bit sequence and the bit sequences among the N second bit sequences that are not correctly decoded according to the third bit sequence. The execution subject of the solution in the second aspect may be the second device, or a module in the second device (such as a chip system, etc.), or a logical node, logical module or software that can implement all or part of the functions of the second device, which is not limited thereto. For ease of description, the second device is used as an example for description below. In the above technical solution, when the third bit sequence is obtained by superimposing all the bits of the first bit sequence and partial bits of each of the N second bit sequences to obtain the third bit sequence, compared with the existing two-layer superimposed transmission scheme (for example, obtaining the third bit sequence by superimposing all the bits of the first bit sequence and all the bits of a second bit sequence), the decoding reliability of the bit sequences among the N second bit sequences that are not correctly decoded can be effectively improved, and there will be no error propagation problem caused by decoding errors, and the reliability of the third bit sequence will not be reduced; compared with the multi-layer superimposed transmission scheme (for example, the first device obtains the third bit sequence by superimposing all the bits of the first bit sequence and all the bits of each of the N second bit sequences), the decoding difficulty of the third bit sequence can also be effectively reduced. In a second aspect, the method further includes: obtaining a fifth bit sequence, which is obtained by superimposing all bits of a fourth bit sequence and at least one of the following: the first bit of at least one of N second bit sequences, the second bit of at least one of N second bit sequences, where the second bit is a partial bit of the second bit sequence and is different from the first bit; or, a partial bit of the first bit sequence; and determining the fourth bit sequence according to the fifth bit sequence. When the first bit of at least one of N second bit sequences is used to form not only the third bit sequence but also the fifth bit sequence, when decoding, the likelihood of successful decoding of the first bit of the at least one second bit sequence can be enhanced by decoding one or both of the third bit sequence and the fifth bit sequence. When the first bit of at least one of N second bit sequences is used to form the third bit sequence, and the second bit of the at least one second bit sequence is used to form the fifth bit sequence, in this way, the transmission reliability of the at least one second bit sequence can be enhanced. When the first bit sequence is used to form not only the third bit sequence but also the fifth bit sequence, in this way, the likelihood of successful decoding of the first bit sequence can be enhanced by decoding one or both of the third bit sequence and the fifth bit sequence. In a second aspect, the method further includes: sending first indication information, where the first indication information is used to indicate the generation rule of the bit sequence. Among them, determining the first bit sequence and N second bit sequences according to the third bit sequence includes: outputting the first bit sequence and N second bit sequences according to the generation rule of the bit sequence. In this way, the first device can obtain the generation rule of the bit sequence and generate the third bit sequence according to the generation rule of the bit sequence. When the first device sends the third bit sequence generated according to the generation rule of the bit sequence to the second device, the likelihood of the second device successfully decoding the third bit sequence can be improved. In a second aspect, the method further includes: receiving second indication information, where the second indication information is used to indicate the generation rule of the bit sequence. Among them, determining the first bit sequence and N second bit sequences according to the third bit sequence includes: outputting the first bit sequence and N second bit sequences. In this way, the second device can obtain the generation rule of the bit sequence and can decode the third bit sequence according to the generation rule of the bit sequence, which is beneficial to increasing the likelihood of the second device successfully decoding the third bit sequence. Combined with the method described in any one of the first aspect and the second aspect, the generation rule of the bit sequence includes at least one of the following: the number of stacked layers, the stacking length, the stacking order, or the stacking type. In this way, the first device can generate the third bit sequence according to one or more of the above. Combined with the method described in any one of the first aspect and the second aspect, the stacking order includes at least one of the following: ordered stacking or disordered stacking. When the stacking order is ordered stacking, this can reduce the decoding difficulty of the bit sequence and enhance the decoding reliability of the bit sequence. When the stacking order is disordered stacking, this can enhance the decoding reliability of the bit sequence and reduce the decoding difficulty of the bit sequence. Combined with the method described in any one of the first aspect and the second aspect, the stacking type includes at least one of the following: exclusive stacking or repeated stacking. When the stacking type is repeated stacking, the first bit of a second bit sequence can be used to form multiple bit sequences, which can enhance the decoding performance of the first bit of the second bit sequence. For example, the possibility of successfully decoding the first bit of the second bit sequence can be enhanced through one or more of the multiple bit sequences. When the stacking type is exclusive stacking, a second bit sequence can be divided into multiple parts, and each part can be respectively stacked into different bit sequences, which can effectively reduce the influence of channel quality on the transmission of the second bit sequence. Combined with the method described in any one of the first aspect and the second aspect, the first bit sequence and the N second bit sequences are all bit sequences after channel coding. In this way, the first device can perform a stacking operation on the bit sequence obtained after completing channel coding. Combined with the method described in any one of the first aspect and the second aspect, the fourth bit sequence is a bit sequence after channel coding. In this way, the first device can perform a stacking operation on the bit sequence obtained after completing channel coding. In a third aspect, a communication device is provided. The communication device can be the first device, or a device or module for performing the functions of the first device, etc. In a possible implementation, the communication device may include modules or units corresponding one by one to the methods / operations / steps / actions described in the first aspect. The module or unit can be a hardware circuit, software, or a combination of hardware circuit and software. In a fourth aspect, a communication device is provided. The communication device can be the second device, or a device or module for performing the functions of the second device, etc. A possible implementation manner, the communication device may include modules or units corresponding one by one to the methods / operations / steps / actions described in the second aspect, and the modules or units may be hardware circuits, software, or a combination of hardware circuits and software. In a fifth aspect, a communication device is provided, the communication device includes: a processing unit, configured to obtain a first bit sequence and N second bit sequences, where N is a positive integer; a transceiver unit, configured to output a third bit sequence, the third bit sequence is obtained by superimposing the first bit of each of the N second bit sequences and all bits of the first bit sequence, and the first bit is a part of the bits in the second bit sequence. The above-mentioned communication device can also be used to execute the solutions of the methods described in the foregoing first aspect and any possible manner in the first aspect, which will not be elaborated here. In a sixth aspect, a communication device is provided, the communication device includes: a transceiver unit, configured to obtain a third bit sequence, the third bit sequence is obtained by superimposing the first bit of each of the N second bit sequences and all bits of the first bit sequence, and the first bit is a part of the bits in the second bit sequence; a processing unit, configured to determine, according to the third bit sequence, the first bit sequence and the bit sequences that are not correctly decoded in the N second bit sequences. The above-mentioned communication device can also be used to execute the solutions of the methods described in the foregoing second aspect and any possible manner in the second aspect, which will not be elaborated here. In a seventh aspect, a communication device is provided, including a processor, the processor is configured to, by executing a computer program or instruction, or by a logic circuit, cause the communication device to execute the method in any possible manner in the first aspect or the second aspect. A possible implementation manner, the communication device further includes a memory, which is configured to store the computer program or instruction. A possible implementation manner, the communication device further includes a communication interface, which is configured to input and / or output signals. In an eighth aspect, a communication device is provided, including a logic circuit and an input / output interface, the input / output interface is configured to input and / or output signals, and the logic circuit is configured to execute the method in any possible manner in the first aspect or the second aspect. In a ninth aspect, a computer-readable storage medium is provided, on which a computer program or instruction is stored, and when the computer program or the instruction runs on a computer, the method described in any possible manner in the first aspect or the second aspect is caused to be executed. In a tenth aspect, there is provided a computer program product including instructions which, when running on a computer, cause the method described in any possible manner of the first aspect or the second aspect to be executed. In an eleventh aspect, there is provided a chip system. The chip is connected to a memory and is configured to read and execute a software program stored in the memory to execute the method described in any possible manner of the first aspect or the second aspect above. In a twelfth aspect, there is provided a chip system. The chip system includes: a communication interface for communicating with other devices; and a processor for causing a communication device equipped with the chip system to execute the method described in any possible manner of the first aspect or the second aspect above. In a thirteenth aspect, there is provided a chip system. The chip system includes a processor, a memory, and an input / output port. The memory is configured to store a computer program; and the processor is configured to execute the computer program stored in the memory so that the processor executes the method described in any possible manner of the first aspect or the second aspect above. In a fourteenth aspect, there is provided a chip system applied to an electronic device. The chip system includes one or more processors configured to invoke computer instructions to cause the electronic device to execute the method described in any possible manner of the first aspect or the second aspect above. For the description of the beneficial effects of any one of the second aspect to the fourteenth aspect, reference may be made to the description of the beneficial effects of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are schematic diagrams of a communication system applicable to embodiments of the present application. FIG. 3 is a schematic diagram of two-layer superimposed transmission. FIG. 4 is an interaction flow diagram of a transmission method according to an embodiment of the present application. FIGS. 5 - 8 are schematic diagrams of multi-layer superimposed transmission according to embodiments of the present application. FIG. 9 is a schematic diagram of a superimposition order according to an embodiment of the present application. FIGS. 10 and 11 are schematic block diagrams of a communication device applicable to embodiments of the present application. DETAILED DESCRIPTION The technical solutions in the present application will be described below with reference to the accompanying drawings. To facilitate understanding of the embodiments of the present application, the following points are first explained. 1. In the present application, unless otherwise specified, "a plurality or at least two" means two or more. II. In each embodiment of the present application, if there is no special description and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be cross-referenced. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships. III. The various digital numbers involved in the present application are only for the convenience of description and do not limit the protection scope of the present application. The size of the serial numbers involved in the present application does not mean the order of execution. The execution order of each process should be determined by its function and internal logic. For example, the terms "first", "second", "third", "fourth" and other various term numbers (if any) in the specification, claims and drawings of the present application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. Among them, such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order other than that illustrated or described here. At the same time, any embodiment or design solution described in the present application as "exemplarily" or "for example" should not be construed as more preferred or more advantageous than other embodiments or design solutions. Exactly speaking, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific way for easy understanding. IV. The terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. V. In the present application, "for indicating" can be understood as "enabling", and "enabling" can include direct enabling and indirect enabling. When describing that a certain piece of information is used to enable A, it may include that the information directly enables A or indirectly enables A, and it does not mean that A must be carried in the information. The information enabled by the information is called the information to be enabled. Then, in the specific implementation process, there are many ways to enable the information to be enabled. For example, but not limited to, the information to be enabled can be directly enabled, such as the information to be enabled itself or the index of the information to be enabled, etc. It is also possible to indirectly enable the information to be enabled by enabling other information, where there is an association relationship between the other information and the information to be enabled. It is also possible to only enable a part of the information to be enabled, while the other parts of the information to be enabled are known or pre-agreed. For example, it is also possible to realize the enabling of specific information by relying on the arrangement order of each piece of information pre-agreed (such as protocol regulations), so as to reduce the enabling overhead to a certain extent. At the same time, it is also possible to identify the common parts of each piece of information and enable them uniformly to reduce the enabling overhead caused by enabling the same information separately. VI. In this application, "pre-configuration" may include predefined, for example, protocol definition. Among them, "predefined" can be implemented by pre-saving corresponding codes, tables or other means that can be used to indicate relevant information in devices (for example, including each network element). This application does not limit its specific implementation method. VII. The "storage" or "saving" involved in this application may refer to being stored in one or more memories. The one or more memories may be set separately, or integrated in an encoder, a decoder, a processor, or a communication device. The one or more memories may also be partially set separately and partially integrated in a decoder, a processor, or a communication device. The type of the memory may be any form of storage medium, and this is not limited. VIII. The "protocol" involved in this application may refer to standard protocols in the communication field. For example, it may include 4th generation (4G) network, 5th generation (5G) network protocol, new radio (NR) protocol, 5.5G network protocol, 6th generation (6 th generation, 6G) network protocol, and related protocols applied to future communication systems. This application does not limit this. IX. In the schematic diagrams in the attached drawings of the specification of this application, the arrows or boxes shown by dashed lines indicate optional steps or optional modules. X. In this application, unless otherwise specified, " / " means that the objects associated before and after are in an "or" relationship. For example, A / B may mean A or B; "and / or" in this application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A and B can be singular or plural. XI. In this application, indication includes direct indication (also called explicit indication) and implicit indication. Directly indicating information A means including this information A. Implicitly indicating information A means indicating information A through the correspondence between information A and information B and directly indicating information B. The correspondence between information A and information B can be predefined, pre-stored, pre-burned, or pre-configured. XII. In this application, information C is used for the determination of information D, which includes both the case where information D is determined only based on information C and the case where it is determined based on information C and other information. In addition, when information C is used for the determination of information D, there may also be an indirect determination case. For example, information D is determined based on information E, and information E is determined based on information C. 13. In the present application, “device A sends information A to device B” can be understood as the destination of the information A or the intermediate network element in the transmission path between the destination and the device B, which may include sending information to device B directly or indirectly. 14. In this application, "device B receives information A from device A" can be understood as the source of the information A or the intermediate network element in the transmission path between the source and the source is device A, which may include directly or indirectly receiving information from device A. The information may be processed as necessary between the source and the destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be understood similarly and will not be repeated here. First, a communication system to which the embodiments of the present application are applicable is described. FIG. 1 is a schematic diagram of a communication system applicable to an embodiment of the present application. As shown in FIG. 1 , the communication system includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (such as 110a and 110b in FIG. 1 , collectively referred to as 110) and at least one terminal device (such as 120a-120j in FIG. 1 , collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in FIG. 1 ). The terminal device 120 is connected to the RAN node 110 wirelessly. The RAN node 110 is connected to the core network 200 wirelessly or by wire. The core network device in the core network 200 and the RAN node 110 in the RAN 100 may be different physical devices, or may be the same physical device that integrates the core network logical functions and the radio access network logical functions. RAN 100 can be a third generation partnership project (3 rd The RAN 100 may be a cellular system related to a third generation partnership project (3GPP), such as a 4G or 5G mobile communication system, or a future evolution system (such as a 6G mobile communication system). The RAN 100 may also be an open access network (open RAN, O-RAN or ORAN), a cloud radio access network (cloud radio access network, CRAN), or a wireless fidelity (wireless fidelity, WiFi) system. The RAN 100 may also be a communication system that integrates two or more of the above systems. The RAN node 110, sometimes also referred to as an access network device, RAN entity, access node, etc., forms part of a communication system and is used to assist a terminal device in achieving wireless access. Multiple RAN nodes 110 in this communication system can be of the same type or different types. In some scenarios, the roles of the RAN node 110 and the terminal device 120 are relative. For example, in FIG. 1, the network element 120i can be a helicopter or a drone, which can be configured as a mobile base station. For those terminal devices 120j that access the RAN 100 through the network element 120i, the network element 120i is a base station; but for the base station 110a, the network element 120i is a terminal device. The RAN node 110 and the terminal device 120 are sometimes both referred to as communication devices. For example, the network elements 110a and 110b in FIG. 1 can be understood as communication devices with base station functions, and the network elements 120a - 120j can be understood as communication devices with terminal functions. In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a next generation base station in a sixth generation (6 th generation, 6G) mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc. The RAN node can be a macro base station (such as 110a in FIG. 1), a micro base station or an indoor station (such as 110b in FIG. 1), a relay node or a donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, a wearable device, a vehicle or an in-vehicle device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). All or part of the functions of the RAN node in this application can also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (such as a cloud platform). The RAN node in this application can also be a logical node, a logical module or software that can implement all or part of the RAN node functions. In another possible scenario, multiple RAN nodes cooperate to assist a terminal device in achieving wireless access, and different RAN nodes respectively implement some functions of a base station. For example, the RAN node may be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and the DU may be separately provided, or may also be included in the same network element, such as a baseband unit (BBU). The RU may be included in a radio frequency device or a radio frequency unit, such as being included in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, the CU (or CU-CP and CU-UP), DU, or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, the CU may also be referred to as an O-CU (open CU), the DU may also be referred to as an O-DU, the CU-CP may also be referred to as an O-CU-CP, the CU-UP may also be referred to as an O-CU-UP, and the RU may also be referred to as an O-RU. For ease of description, in this application, the CU, CU-CP, CU-UP, DU, and RU are used as examples for description. Any one of the CU (or CU-CP, CU-UP), DU, and RU in this application may be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. In the embodiments of this application, the terminal device is a device with wireless transceiver functions, and may refer to a user equipment (UE), an access terminal, a subscriber unit, a user station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user device. In the embodiments of the present application, the terminal device may also be a satellite phone, a cellular phone, a smart phone, a wireless data card, a wireless modem, a machine type communication device, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a customer-premises equipment (CPE), a smart point of sale (POS) machine, a handheld device with wireless communication function, a computing device or other processing devices connected to a wireless modem, a vehicle-mounted device, a communication device carried on a high-altitude aircraft, a wearable device, a drone, a robot, a terminal in device-to-device (D2D) communication, a terminal in vehicle-to-everything (V2X) communication, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, or a terminal device in a communication network evolved after 5G, etc., without limitation in this regard. In the embodiments of the present application, the terminal device may also be a device with communication function in a 6G communication system, without limiting the form or type of the terminal device in 6G and other future communication systems. In the embodiments of the present application, the communication device for implementing the functions of the terminal device may be the terminal device or a device capable of supporting the terminal device to implement the functions, such as a chip system. The device may be installed in the terminal device or used in matching with the terminal device. In the present application, the chip system may be composed of chips or may include chips and other discrete devices. Figure 2 is a schematic diagram of another communication system applicable to the embodiments of the present application. As shown in Figure 2, the communication system includes: a first device and a second device. There is data transmission between the first device and the second device. The first device may be a sending end, and the second device may be a receiving end. Alternatively, the first device may be a receiving end, and the second device may be a sending end, which is not limited. For ease of description, the following takes the first device as the sending end and the second device as the receiving end as an example for description. The first device may be the aforementioned terminal device, and the second device may be the aforementioned terminal device; or, the first device is the aforementioned terminal device, and the second device is the aforementioned network device; or, the first device is the aforementioned network device, and the second device is the aforementioned terminal device; or, the first device is the aforementioned network device, and the second device is the aforementioned network device, etc., which is not limited thereto. In the embodiments of the present application, the communication between the network device and the terminal device follows a certain protocol layer structure. For example, the control plane protocol layer structure may include functions of protocol layers such as radio resource control (RRC) layer, packet data convergence protocol (PDCP) layer, radio link control (RLC) layer, media access control (MAC) layer, and physical layer; the user plane protocol layer structure may include functions of protocol layers such as PDCP layer, RLC layer, MAC layer, and physical layer; in a possible implementation, a service data adaptation protocol (SDAP) layer may also be included above the PDCP layer. The network device may implement the functions of protocol layers such as RRC, PDCP, RLC, and MAC by one node, or may implement the functions of these protocol layers by multiple nodes. For example, in an evolved architecture, the network device includes a CU and a DU, and multiple DUs are centrally controlled by one CU. For example, the CU and the DU may be divided according to the protocol layers of the wireless network. For example, the functions of protocol layers above the PDCP layer are set in the CU, and the protocol layers below the PDCP layer, such as the RLC layer and the MAC layer, etc., are set in the DU. This division of protocol layers is merely an example, and it can also be divided at other protocol layers. For example, it can be divided at the RLC layer, where the functions of the RLC layer and the protocol layers above it are set in the CU, and the functions of the protocol layers below the RLC layer are set in the DU; or, it can be divided within a certain protocol layer. For example, some functions of the RLC layer and the functions of the protocol layers above the RLC layer are set in the CU, and the remaining functions of the RLC layer and the functions of the protocol layers below the RLC layer are set in the DU. In addition, it can also be divided in other ways. For example, it can be divided according to latency. The functions that require the processing time to meet the latency requirement are set in the DU, and the functions that do not need to meet this latency requirement are set in the CU. In addition, the radio frequency device can be independently integrated and not placed in the DU, or it can be integrated in the DU, or partially remote and partially integrated in the DU, and there is no restriction here. The network architecture and service scenarios described in this application are for more clearly explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by this application. Those of ordinary skill in the art know that with the evolution of the communication network architecture and the emergence of new service scenarios, the technical solutions provided by this application are equally applicable to similar technical problems. For example, this application can be applied to the V2X scenario. To better understand the embodiments of this application, first, a brief description of the terms involved in this application is given. Among them, these explanations are for making the embodiments of this application easier to understand, and should not be regarded as a limitation on the scope of protection required by the embodiments of this application. I. Superposition transmission Superposition transmission is a way to improve the reliability of data transmission. By superimposing at least two bit sequences together according to a certain order, a new bit sequence can be obtained. For specific descriptions, please refer to Figure 3. Figure 3 is a schematic diagram of two-layer superposition transmission. As shown in Figure 3, bit sequence 1, bit sequence 2, bit sequence 3, and bit sequence 4 are all bit sequences to be transmitted (which can be called original bit sequences) (the timing of bit sequence 1 is before the timing of bit sequence 2, the timing of bit sequence 2 is before the timing of bit sequence 3, and the timing of bit sequence 3 is before the timing of bit sequence 4). To improve the reliability of bit sequence 1, bit sequence 2, bit sequence 3, and bit sequence 4 during transmission, the superposition process can be performed on bit sequence 1, bit sequence 2, bit sequence 3, and bit sequence 4. For example, for bit sequence 1, no processing is done; for bit sequence 2, all bits of bit sequence 1 are superimposed on all bits of bit sequence 2 to obtain a new bit sequence; for bit sequence 3, all bits of bit sequence 2 are superimposed on all bits of bit sequence 3 to obtain a new bit sequence; for bit sequence 4, all bits of bit sequence 3 are superimposed on all bits of bit sequence 4 to obtain a new bit sequence. In the content described in FIG. 3, the bit lengths of each bit sequence are the same, but the bit lengths of different bit sequences can also be different. For example, the bit length of bit sequence 1 is longer than that of bit sequence 2, and the bit length of bit sequence 2 is longer than that of bit sequence 3, and so on. For ease of description, the following describes the case where the bit lengths of each bit sequence are the same, but it does not limit the application scenario where the bit lengths of each bit sequence are different. For the description of the superposition between bit sequences, reference can be made to Table 1 and Table 2. The content shown in Table 1 and Table 2 is only for example understanding and is not the final limitation. Table 1 As shown in Table 1, bit sequence 1 is [01001010], bit sequence 2 is [01101010]. By superimposing all the bits of bit sequence 1 on all the bits of bit sequence 2, bit sequence *[00100000] (which is the bitwise XOR value between [01001010] and [01101010]) can be obtained. Table 2 As shown in Table 2, bit sequence 1 is

[1010] , bit sequence 2 is

[1010] . By superimposing all the bits of bit sequence 1 on all the bits of bit sequence 2, bit sequence *

[11110] (which is the bitwise XOR value corresponding to the first four bits of

[1010] and

[1010] ) can be obtained. When performing data transmission, in order to improve the reliability of data transmission, the bit sequence to be transmitted can be transmitted by superposition. For example, a two-layer superposition transmission scheme (such as superimposing all the bits of bit sequence 1 on all the bits of bit sequence 2) or a multi-layer superposition transmission scheme (such as superimposing all the bits of bit sequence 1 and all the bits of bit sequence 2 on all the bits of bit sequence 3) can be adopted. However, if a two-layer superposition transmission scheme is adopted, there is likely to be a problem of a single superposition failure, which is likely to cause an error propagation problem, and the error propagation leads to performance loss; if a multi-layer superposition transmission scheme is directly adopted, iterative message passing decoding of multi-layer soft information is required, and the decoding complexity will also be increased. Therefore, how to improve the decoding reliability of superposition transmission and reduce the decoding complexity at the same time is a technical problem that needs to be solved urgently at present. In view of this, the present application provides a transmission method and a communication device, which can improve the decoding reliability of superposition transmission and reduce the decoding complexity at the same time. FIG. 4 is an interactive process schematic diagram of the transmission method according to an embodiment of the present application. As shown in FIG. 4, the method includes: S401. The first device obtains a first bit sequence and N second bit sequences, where N is a positive integer. In a possible implementation, the first bit sequence and the N second bit sequences can both be bit sequences after channel coding. For example, the first bit sequence and the N second bit sequences can both be codebooks (CBs), or both be transport blocks (TBs), or be other types of bit sequences, which is not limited herein. When the first bit sequence and the N second bit sequences are both bit sequences after channel coding, the first device can perform a superposition operation on the bit sequences after completing channel coding, so as to transmit the bit sequence obtained after the superposition operation, that is, the third bit sequence. The above-mentioned N second bit sequences are the second bit sequences that need to be used. For example, 10 second bit sequences can be obtained, and 8 of the 10 second bit sequences are used. Correspondingly, the value of N described above is 8. S402. The first device outputs the third bit sequence to the second device. Correspondingly, the second device obtains the third bit sequence. The first device outputting the third bit sequence to the second device can be understood as: the first device performs channel coding and superposition processing on the first bit sequence and the N second bit sequences to obtain the third bit sequence, then performs modulation and other processing to obtain the signal corresponding to the third bit sequence, and sends the signal corresponding to the third bit sequence to the second device. The second device obtaining the third bit sequence can be understood as: the second device receives the signal corresponding to the third bit sequence sent by the first device, demodulates the signal and other processing to obtain the third bit sequence, and restores the first bit sequence and the bit sequences that have not been correctly decoded among the N second bit sequences by performing channel decoding and other processing through combining the soft information of other relevant historical bit sequences. The above-mentioned third bit sequence is obtained by the first device by superposing the first bit of each second bit sequence among the N second bit sequences with all the bits of the first bit sequence. Wherein, the first bit is a part of the bits in the second bit sequence. The first bits of each second bit sequence can be the same (such as the same number of bits and the same position of the bits), or different (such as the same number of bits but different positions of the bits; or the same position of the bits but different numbers of bits, etc.), which is not limited herein. When N = 1, the third bit sequence is obtained by the first device by superposing a part of the bits of a second bit sequence with all the bits of the first bit sequence; When N = 2, the third bit sequence is obtained by the first device through superposition of partial bits of each of the two second bit sequences and all bits of the first bit sequence; When N = 3, the third bit sequence is obtained by the first device through superposition of partial bits of each of the three second bit sequences and all bits of the first bit sequence; When N is a positive integer greater than 3, the third bit sequence is obtained by the first device through superposition of partial bits of each of the N second bit sequences and all bits of the first bit sequence. In a possible implementation, the N second bit sequences are bit sequences sorted before the first bit sequence. For example, if there are K bit sequences to be transmitted, which are: bit sequence u1, bit sequence u2, bit sequence u3, bit sequence u4,..., bit sequence u K (The timing of bit sequence u1 is before the timing of bit sequence u2, the timing of bit sequence u2 is before the timing of bit sequence u3,..., the timing of bit sequence u K-1 is before the timing of bit sequence u K ) Then, superposition processing can be performed on the K bit sequences to be transmitted. Exemplarily, K = 5 and the number of superposition layers = 3. Then, the first bit sequence u1 can be directly transmitted without processing (which can be referred to as bit sequence c1); all bits or partial bits of the first bit sequence u1 are superposed on all bits of the second bit sequence u2 to obtain the corresponding bit sequence c2; partial bits of the first bit sequence u1 and partial bits of the second bit sequence u2 are superposed on the third bit sequence u3 to obtain the corresponding bit sequence c3, partial bits of the second bit sequence u2 and partial bits of the third bit sequence u3 are superposed on the fourth bit sequence u4 to obtain the corresponding bit sequence c4, partial bits of the third bit sequence u3 and partial bits of the fourth bit sequence u4 are superposed on the fifth bit sequence u5 to obtain the corresponding bit sequence c5, and bit sequences c1, c 2、 c3, c4, and c5 are transmitted. In this way, the superposition rule between bit sequences can be relatively simple, thereby reducing the decoding complexity. For the description of the generation process of the third bit sequence, reference can be made to FIG. 5. FIG. 5 is a schematic diagram of multi-layer superposition transmission according to an embodiment of the present application. As shown in FIG. 5: As shown in Fig. 5(a), the first bit sequence is bit sequence 4, N = 2, the first second bit sequence is bit sequence 2 (represented by cross texture), the second second bit sequence is bit sequence 3 (represented by diagonal texture). Part of the bits of bit sequence 2 (such as the first bit of bit sequence 2) and part of the bits of bit sequence 3 (such as the first bit of bit sequence 3) are superimposed on all the bits of bit sequence 4 to obtain the third bit sequence. As shown in Fig. 5(b), the first bit sequence is bit sequence 4, N = 3, the first second bit sequence is bit sequence 1 (represented by vertical texture), the second second bit sequence is bit sequence 2 (represented by cross texture), the third second bit sequence is bit sequence 3 (represented by diagonal texture). Part of the bits of bit sequence 1 (such as the first bit of bit sequence 1), part of the bits of bit sequence 2 (such as the first bit of bit sequence 2) and part of the bits of bit sequence 3 (such as the first bit of bit sequence 3) are jointly superimposed on all the bits of bit sequence 4 to obtain the third bit sequence. In Fig. 5(a), the sum value between the number of bits of the first bit of bit sequence 2 and the number of bits of the first bit of bit sequence 3 is equal to the bit length of bit sequence 4. However, the sum value between the number of bits of the first bit of bit sequence 2 and the number of bits of the first bit of bit sequence 3 can be less than or greater than the bit length of bit sequence 4, and this is not limited. For example, when the sum value between the number of bits of the first bit of bit sequence 2 and the number of bits of the first bit of bit sequence 3 is greater than or equal to the bit length of bit sequence 4, it is possible to superimpose all the bits of bit sequence 4. When the sum value between the number of bits of the first bit of bit sequence 2 and the number of bits of the first bit of bit sequence 3 is less than the bit length of bit sequence 4, it is possible to superimpose part of the bits of bit sequence 4. In Fig. 5(b), the sum value between the number of bits of the first bit of bit sequence 1, the number of bits of the first bit of bit sequence 2 and the number of bits of the first bit of bit sequence 3 is equal to the bit length of bit sequence 4. However, the sum value between the number of bits of the first bit of bit sequence 1, the number of bits of the first bit of bit sequence 2 and the number of bits of the first bit of bit sequence 3 can be less than or greater than the bit length of bit sequence 4, and this is not limited. For example, when the sum of the number of bits of the first bit of bit sequence 1, the number of bits of the first bit of bit sequence 2, and the number of bits of the first bit of bit sequence 3 is greater than or equal to the bit length of bit sequence 4, it is possible to superimpose all the bits of bit sequence 4. When the sum of the number of bits of the first bit of bit sequence 1, the number of bits of the first bit of bit sequence 2, and the number of bits of the first bit of bit sequence 3 is less than the bit length of bit sequence 4, it is possible to superimpose some bits of bit sequence 4. The number of bits included in the first bit of each second bit sequence may be the superimposition length of each second bit sequence. For example, the first bit of bit sequence 1 includes 100 bits, and the superimposition length of bit sequence 1 is 100; the first bit of bit sequence 2 includes 50 bits, and the superimposition length of bit sequence 2 is 50; the first bit of bit sequence 3 includes 50 bits, and the superimposition length of bit sequence 3 is 50. It should be noted that the content shown in FIG. 5 is only for example and is not an ultimate limitation. S403. The second device determines the sequences among the N second bit sequences that are not correctly decoded and the first bit sequence according to the third bit sequence. Specifically, after receiving the signal corresponding to the third bit sequence, the second device can perform processing such as demodulation on the signal corresponding to the third bit sequence to obtain the soft information of the third bit sequence, and can jointly decode and determine or obtain the sequences among the N second bit sequences that are not correctly decoded and the first bit sequence according to the soft information of the third bit sequence and the historical related bit sequence information. In summary, the first device can superimpose all the bits of the first bit sequence and some bits of each of the N second bit sequences to obtain the third bit sequence. Compared with the two-layer superimposed transmission scheme (for example, the first device superimposes all the bits of the first bit sequence and all the bits of one second bit sequence to obtain the third bit sequence), since some of the second bit sequences among the N second bit sequences can be used to form multiple bit sequences, this can effectively improve the decoding reliability of the bit sequences among the N second bit sequences that are not correctly decoded, and there will be no error propagation problem due to decoding errors, and the reliability of the third bit sequence will not be decreased; compared with the multi-layer superimposed transmission scheme (for example, the first device superimposes all the bits of the first bit sequence and all the bits of each of the N second bit sequences to obtain the third bit sequence), since the number of XOR operations on the bits in the first bit sequence is less than N, this can effectively reduce the decoding difficulty of the third bit sequence. In the embodiments of the present application, the first device can obtain other bit sequences in a similar manner. In a possible implementation, method 400 may further include: The first device obtains a fourth bit sequence; The first device outputs a fifth bit sequence to the second device. Correspondingly, the second device obtains the fifth bit sequence. For the description of the first device outputting the fifth bit sequence to the second device, reference may be made to the foregoing description of S402, which will not be elaborated here. Wherein, the fifth bit sequence is obtained by superimposing all the bits of the fourth bit sequence by the first device according to at least one of the following items: The first bit of at least one of the foregoing N second bit sequences. When the first bit of at least one of the N second bit sequences is used not only to form the third bit sequence but also to form the fifth bit sequence, when decoding, the possibility of successful decoding of the first bit of the at least one second bit sequence can be enhanced by decoding one or both of the third bit sequence and the fifth bit sequence. The second bit of at least one of the foregoing N second bit sequences. The second bit is part of the second bit sequence and is different from the first bit. When the first bit of at least one of the N second bit sequences is used to form the third bit sequence, the second bit of the at least one second bit sequence is used to form the fifth bit sequence, so that the transmission reliability of the at least one second bit sequence can be enhanced. Part of the bits in the first bit sequence. When the first bit sequence can be used not only to form the third bit sequence but also to form the fifth bit sequence, the possibility of successful decoding of the first bit sequence can be enhanced by decoding one or both of the third bit sequence and the fifth bit sequence. For the description of the superimposing process of the fifth bit sequence, reference may be made to FIG. 6. FIG. 6 is a schematic diagram of another multi-layer superimposed transmission according to an embodiment of the present application. As shown in FIG. 6: In Fig. 6(a), bit sequence 4 is the first bit sequence. The first bit of bit sequence 2 and the first bit of bit sequence 3 are superimposed on all bits of bit sequence 4 to obtain the third bit sequence; bit sequence 6 is the fourth bit sequence. The first bit of bit sequence 3 and the first bit of bit sequence 5 are superimposed on all bits of bit sequence 6 to obtain the fifth bit sequence. Among them, the first bit of bit sequence 3 is used not only to form the third bit sequence but also to form the fifth bit sequence. In this way, this can effectively improve the decoding performance of the first bit of bit sequence 3. For example, the possibility of successful decoding of the first bit of bit sequence 3 can be enhanced through one or both of the third bit sequence and the fifth bit sequence. In Fig. 6(b), bit sequence 4 is the first bit sequence. The first bit of bit sequence 2 and the first bit of bit sequence 3 are superimposed on all bits of bit sequence 4 to obtain the third bit sequence; bit sequence 6 is the fourth bit sequence. The second bit of bit sequence 3 and the first bit of bit sequence 5 are superimposed on all bits of bit sequence 6 to obtain the fifth bit sequence. Among them, the first bit of bit sequence 3 is used to form the third bit sequence, and the second bit of bit sequence 3 is used to form the fifth bit sequence. In this way, this can further enhance the reliability of relevant bit information and contribute to improving the decoding performance. In this way, by dividing bit sequence 3 into two parts and each part is superimposed on different bit sequences respectively, this can enhance the transmission reliability of bit sequence 3. For example, the influence of channel quality on the transmission of bit sequence 3 can be reduced. In Fig. 6(c), bit sequence 4 is the first bit sequence. The first bit of bit sequence 2 and the first bit of bit sequence 3 are superimposed on all bits of bit sequence 4 to obtain the third bit sequence; bit sequence 6 is the fourth bit sequence. The second bit of bit sequence 3 and the first bit of bit sequence 4 are superimposed on all bits of bit sequence 6 to obtain the fifth bit sequence. Among them, some bits of bit sequence 4 are used to form the fifth bit sequence. In this way, the possibility of successful decoding of bit sequence 4 can be enhanced through the decoding of one or two of the third bit sequence and the fifth bit sequence. Specifically, the first bit sequence includes the bit information of bit sequence 4, and the fifth bit sequence includes the bit information of bit sequence 4. Or rather, bit sequence 4 is superimposed on bit sequence 6 to form the fifth bit sequence. Bit sequence 6 can also be superimposed on the subsequent bit sequence. Therefore, by successive superposition (such as superimposing bit sequence 4 on bit sequence 6 and superimposing bit sequence 6 on the subsequent bit sequence), this can improve the decoding reliability. For example, decoding can be performed through one or both of the third bit sequence and the fifth bit sequence, thereby enhancing the possibility of successful decoding of bit sequence 4. The method shown in Fig. 4 will be further described below in conjunction with Figs. 7 and 8. Figure 7 is a schematic diagram of three - layer superposition transmission according to an embodiment of the present application. As shown in Figure 7, bit sequence 1, bit sequence 2, bit sequence 3, bit sequence 4, and bit sequence 5 are bit sequences to be transmitted. For bit sequence 1, no processing is performed; for bit sequence 2, all bits or some bits of bit sequence 1 are superimposed on all bits of bit sequence 2 to obtain the corresponding bit sequence; for bit sequence 3, some bits of bit sequence 1 and some bits of bit sequence 2 are superimposed on all bits of bit sequence 3 to obtain the corresponding bit sequence; for bit sequence 4, some bits of bit sequence 2 and some bits of bit sequence 3 are superimposed on all bits of bit sequence 4 to obtain the corresponding bit sequence; for bit sequence 5, some bits of bit sequence 3 and some bits of bit sequence 4 are superimposed on all bits of bit sequence 5 to obtain the corresponding bit sequence. In the content shown in Figure 7, bit sequence 1 can be the second bit sequence, and bit sequence 2 is the first bit sequence; bit sequence 1 and bit sequence 2 can be the second bit sequence, and bit sequence 3 is the first bit sequence; bit sequence 2 and bit sequence 3 can be the second bit sequence, and bit sequence 4 is the first bit sequence; bit sequence 3 and bit sequence 4 can be the second bit sequence, and bit sequence 5 is the first bit sequence. Figure 8 is a schematic diagram of four - layer superposition transmission according to an embodiment of the present application. As shown in Figure 8, bit sequence 1, bit sequence 2, bit sequence 3, bit sequence 4, and bit sequence 5 are bit sequences to be transmitted. For bit sequence 1, no processing is performed; for bit sequence 2, all bits or some bits of bit sequence 1 are superimposed on all bits of bit sequence 2 to obtain the corresponding bit sequence; for bit sequence 3, some bits of bit sequence 1 and some bits of bit sequence 2 are superimposed on all bits of bit sequence 3 to obtain the corresponding bit sequence; for bit sequence 4, some bits of bit sequence 1, some bits of bit sequence 2, and some bits of bit sequence 3 are superimposed on all bits of bit sequence 4 to obtain the corresponding bit sequence; for bit sequence 5, some bits of bit sequence 2, some bits of bit sequence 3, and some bits of bit sequence 4 are superimposed on all bits of bit sequence 5 to obtain the corresponding bit sequence. In the content shown in Figure 8, bit sequence 1 can be the second bit sequence, and bit sequence 2 is the first bit sequence; bit sequence 1 and bit sequence 2 can be the second bit sequence, and bit sequence 3 is the first bit sequence; bit sequence 1, bit sequence 2, and bit sequence 3 can be the second bit sequence, and bit sequence 4 is the first bit sequence; bit sequence 2, bit sequence 3, and bit sequence 4 can be the aforementioned second bit sequence, and bit sequence 5 is the first bit sequence. ​ In the foregoing content, in the embodiment of the present application, an example is described in which the first device superimposes all the bits of the first bit sequence and partial bits of each of the N second bit sequences to obtain a third bit sequence. However, the first device may generate the third bit sequence according to the generation rule of the bit sequence. In a possible implementation, the first device outputs a third bit sequence according to the second indication information. The second indication information is used to indicate the generation rule of the bit sequence. Further, the second indication information may be sent by the second device to the first device. In this way, the first device can obtain the generation rule of the bit sequence and generate the third bit sequence according to the generation rule of the bit sequence. When the first device sends the third bit sequence generated according to the generation rule of the bit sequence to the second device, the possibility that the second device successfully decodes the third bit sequence can be improved. Optionally, after the first device generates and outputs the third bit sequence according to the generation rule of the bit sequence, the first device may also send the first indication information to the second device. The first indication information is used to indicate the generation rule of the bit sequence. In this way, the second device can obtain the generation rule of the bit sequence and can decode the third bit sequence according to the generation rule of the bit sequence, which is beneficial to increasing the possibility that the second device successfully decodes the third bit sequence. In the embodiment of the present application, the above-mentioned generation rule of the bit sequence may include at least one of the following: The number of superimposed layers, the superimposed length, the superimposed order, or the superimposed type. In this way, the first device may generate the third bit sequence according to one or more of the above. When the generation rule of the bit sequence includes the number of superimposed layers, it is used to indicate the number of layers during superimposed transmission. For example, when the number of superimposed layers is 3, the first device superimposes all the bits of the first bit sequence and partial bits of each of the 2 second bit sequences to obtain a third bit sequence. For another example, when the number of superimposed layers is 3, the first device superimposes all the bits of the first bit sequence and partial bits of each of the 3 second bit sequences to obtain a third bit sequence. Therefore, the above-mentioned number of superimposed layers may be understood as the value of N + 1 or the value of N, and this is not limited. When the generation rule of the bit sequence includes the superimposed type, it is used to indicate one or both of exclusive superimposition and repeated superimposition. When the superimposed type is exclusive superimposition, for example, the first bit of bit sequence 3 is used to form the third bit sequence, and the second bit of bit sequence 3 is used to form the fifth bit sequence; when the superimposed type is repeated superimposition, for example, the first bit of bit sequence 3 is respectively used to form the third bit sequence and the fifth bit sequence. For the description of the superimposed type, reference may be made to FIG. 6. The content described in (a) of FIG. 6 is repeated superposition. The first bit of bit sequence 3 is superimposed on bit sequence 4, and the first bit of bit sequence 3 is superimposed on bit sequence 6. The content described in (b) of FIG. 6 is exclusive superposition. The first bit of bit sequence 3 is superimposed on a bit sequence, and the second bit of bit sequence 3 is superimposed on bit sequence 6. When the superposition type is repeated superposition, the first bit of a second bit sequence can be used to form multiple bit sequences, which can enhance the decoding performance of the first bit of this second bit sequence. For example, the possibility of enhancing the successful decoding of the first bit of this second bit sequence can be achieved through one or more of these multiple bit sequences. When the superposition type is exclusive superposition, a second bit sequence can be divided into multiple parts, and each part is respectively superimposed on different bit sequences, which can effectively reduce the influence of channel quality on the transmission of this second bit sequence. When the generation rule of the bit sequence includes a superposition length (or superposition ratio), it is used to indicate the bit length of the first bit of each of the N second bit sequences. For example, when the superposition length is 100, the first device performs superposition based on all the bits of the first bit sequence and partial bits (such as 100 bits) of each of the N second bit sequences to obtain a third bit sequence. When the generation rule of the bit sequence includes a superposition order, it is used to indicate the sorting between each of the N second bit sequences. For example, when the generation rule of the bit sequence is used to indicate ordered superposition, the first device performs superposition based on all the bits of the first bit sequence and partial bits of each of the N second bit sequences sorted in sequence or satisfying a certain sorting to obtain a third bit sequence; when the generation rule of the bit sequence is used to indicate disordered superposition, the first device performs superposition based on all the bits of the first bit sequence and partial bits of each of the N second bit sequences sorted in a disordered manner to obtain a third bit sequence. When the superposition order is ordered superposition, this can reduce the decoding difficulty of the bit sequence and enhance the decoding reliability of the bit sequence. When the superposition order is disordered superposition, this can enhance the decoding reliability of the bit sequence and reduce the decoding difficulty of the bit sequence. The description of the superposition order can be referred to in FIG. 9. Figure 9 is a schematic diagram of the stacking order according to the embodiments of the present application. As shown in FIG. 9(a), when the stacking order is an ordered stack, some bits of bit sequence 1, some bits of bit sequence 2, and some bits of bit sequence 3 are sequentially stacked onto bit sequence 4, and some bits of bit sequence 2, some bits of bit sequence 3, and some bits of bit sequence 4 are sequentially stacked onto bit sequence 5; as shown in FIG. 9(b), when the stacking order is a disordered stack, some bits of bit sequence 1, some bits of bit sequence 3, and some bits of bit sequence 2 are sequentially stacked onto bit sequence 4, and some bits of bit sequence 2, some bits of bit sequence 4, and some bits of bit sequence 3 are disorderedly stacked onto bit sequence 5. For the generation rules of the above-listed bit sequences, for example: For the number of stacking layers, it can be indicated by radio resource control (RRC) or downlink control information (DCI). Exemplarily, RRC or DCI adds a new field for indicating the number of stacking layers. Among them, RRC or DCI configures and adds a new field Superposed_Layer, which can be configured as {1, 2, 3, 4...}. When this field is not carried in the RRC or DCI, it can be defaultly indicated as two layers. When Superposed_Layer is configured as {1}, it can be used to indicate no stacking. For the stacking ratio, it can be indicated by RRC or DCI. Exemplarily, RRC or DCI adds a new field for indicating the stacking length. Among them, RRC or DCI configures and adds a new field Superposed_Fraction. Among them, this field can be used to indicate the length of the first bit of each second bit sequence among N second bit sequences, or it can be used to indicate a stacking length that applies to each second bit sequence among the N second bit sequences. Among them, when this field is not carried in the RRC or DCI, it can be defaultly indicated as 50% or other values, which is not limited thereto. For the stacking method, it can be indicated by RRC or DCI. Exemplarily, RRC or DCI adds a new field for indicating the stacking method. Among them, RRC or DCI configures and adds a new field Superposed_Rule, which can be represented by 1 bit and takes values of {0, 1}, and is used to indicate whether it is a repeated stack or an exclusive stack. Among them, when this field is not carried in the RRC or DCI, it can be defaultly indicated as a repeated stack or an exclusive stack, which is not limited thereto. For example, Superposed_Rule = 0 can indicate repeated superposition, and Superposed_Rule = 1 indicates exclusive superposition. By default, the exclusive superposition is sequential, or in a predefined order. Additionally, Superposed_Rule can be extended to multiple bits. When the least significant bit of Superposed_Rule = 0, only 1 bit is used for representation, and the remaining bits are reserved for other uses. Or when it is = 0, this field has only 1 bit. If the least significant bit of Superposed_Rule = 1, it indicates exclusive superposition, and the remaining bits represent the exclusive superposition rule. Among them, the above-mentioned superposition method can also be used in combination with the superposition order. For example, exclusive superposition includes different superposition orders (such as ordered superposition or disordered superposition). For the superposition order, it can be indicated by RRC or DCI. Exemplarily, RRC or DCI adds a new field for indicating the superposition order. Among them, RRC or DCI configures and adds a new field Superposed_Order, which can be represented by 1 bit, and its values are {0, 1}, used to indicate whether it is ordered superposition or disordered superposition. For example, Superposed_Order = 0 can indicate ordered superposition, and Superposed_Order = 1 indicates disordered superposition. Furthermore, when the generation rule of the bit sequence is used to indicate disordered superposition, the embodiments of the present application can further indicate the superposition order between N second bit sequences. When the generation rule of the bit sequence is used to indicate ordered superposition, the embodiments of the present application can further indicate the superposition order between N second bit sequences. In this way, the first device can generate the third bit sequence according to the indicated superposition order between N second bit sequences. Correspondingly, the second device can perform decoding of the third bit sequence according to the indicated superposition order between N second bit sequences for the third bit sequence. In the embodiments of the present application, when multiple bit sequences are superposed, the embodiments of the present application can also support interleaving processing of these multiple bit sequences. Exemplarily, in Figure 5(a), before superimposing the first bit of bit sequence 2 on bit sequence 4, the first bit of bit sequence 2 can be interleaved, and the interleaved first bit of bit sequence 2 is superimposed on bit sequence 4. In this way, it can further improve the reliability of data transmission. It should be noted that the above description takes obtaining N second bit sequences and using the first bit of each second bit sequence in the N second bit sequences as an example, but it is not limited to the application scenario where the first bit of some second bit sequences in the N second bit sequences can be used. For example, the first bit of each second bit sequence in N - 1 second bit sequences can be used, etc. Finally, the device embodiments of the present application are introduced. To implement each function in the method provided by the present application, both the first device and the second device may include a hardware structure and / or a software module, and implement the above functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. Whether a certain function among the above functions is executed in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module depends on the specific application and design constraints of the technical solution. FIG. 10 is a schematic block diagram of a communication device according to an embodiment of the present application. The communication device includes a processing circuit 1010 and a transceiver circuit 1020. The processing circuit 1010 and the transceiver circuit 1020 may be connected or coupled to each other, for example, connected to each other through a bus 1030. The communication device may be the first device or the second device. Optionally, the communication device may further include a memory 1040. The memory 1040 includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a compact disc read-only memory (CD-ROM). The memory 1040 is used for storing relevant instructions and data. The processing circuit 1010 may be all or part of the processing circuits in one or more processors, or one or more processors. Among them, the processor may be a central processing unit (CPU). When the processing circuit 1010 is a CPU, the CPU may be a single-core CPU or a multi-core CPU. Among them, the processing circuit 1010 may be a signal processor, a chip, or other integrated circuits that can implement the method of the present application, or a partial circuit for processing functions in the foregoing processor, chip, or integrated circuit. In addition, the transceiver circuit 1020 may also be a transceiver, or an input / output interface. The input / output interface is used for inputting or outputting signals or data, and may also be referred to as an input / output circuit. When the communication device is the first device, exemplarily, the processing circuit 1010 is used to perform the following operations: obtaining a first bit sequence and N second bit sequences; outputting a third bit sequence, etc. When the communication device is the second device, exemplarily, the processing circuit 1010 is used to perform the following operations: obtaining a third bit sequence; determining a first bit sequence and N second bit sequences according to the third bit sequence, etc. The above description is only for exemplary purposes. When the communication device is the first device or the second device, it will be responsible for executing the methods or steps related to the first device or the second device in the foregoing method embodiments. When the communication device is the first device or the second device, the transceiver circuit 1020 can be a transceiver. When the communication device is a chip for the first device or the second device, the transceiver circuit 1020 can be an input / output circuit. The above description is only for exemplary purposes. For specific content, reference can be made to the content shown in the foregoing method embodiments. The implementation of each operation in FIG. 10 can also be correspondingly referred to the corresponding description of the method embodiment shown in FIG. 4. FIG. 11 is a schematic block diagram of another communication device according to an embodiment of the present application. The communication device can be the first device or the second device and is used to implement the method involved in the foregoing embodiments. Among them, the communication device includes a transceiver unit 1110 and a processing unit 1120. The transceiver unit 1110 and the processing unit 1120 will be introduced exemplarily below. The transceiver unit 1110 can include a transmitting unit and a receiving unit. The transmitting unit is used to perform the transmitting action of the communication device, and the receiving unit is used to perform the receiving action of the communication device. For ease of description, in the embodiments of the present application, the transmitting unit and the receiving unit are combined into one transceiver unit. This is explained uniformly here and will not be repeated later. When the communication device is the first device, exemplarily, the transceiver unit 1110 is used to output a third bit sequence; the processing unit 1120 is used to obtain a first bit sequence and N second bit sequences. Among them, the processing unit 1120 is used to execute the content related to the processing, control, etc. steps of the first device. When the communication device is the second device, exemplarily, the transceiver unit 1110 is used to obtain a third bit sequence; the processing unit 1120 is used to determine a first bit sequence and N second bit sequences according to the third bit sequence. Among them, the processing unit 1120 is used to execute the content related to the processing, control, etc. steps of the second device. processing, control and other steps. When the communication device is the first device or the second device, it will be responsible for executing one or more of the methods or steps related to the first device or the second device in the foregoing method embodiments. Optionally, the communication device further includes a storage unit 1130, and the storage unit 1130 is used to store programs or codes for executing the foregoing methods. It should be noted that the transceiver unit in FIG. 11 can correspond to the transceiver circuit in FIG. 10, and the processing unit in FIG. 11 can correspond to the processing circuit in FIG. 10. The device embodiments shown in FIGS. 10 and 11 are used to implement the content described in FIG. 4. For the specific execution steps and methods of the devices shown in FIGS. 10 and 11, reference may be made to the content described in the foregoing method embodiments. This application also provides a chip, including a processor, which is used to call and run instructions stored in the memory, so that a communication device installed with the chip executes the methods in the above examples. The memory may be integrated within the chip or located outside the chip. This application also provides another chip, including: an input interface, an output interface, and a processing circuit. The input interface, the output interface, and the processor are connected through an internal connection path. The processing circuit is used to execute code in the memory. When the code is executed, the processing circuit is used to execute the methods in the above examples. Optionally, the chip further includes a memory, which is used to store computer programs or code. Among them, the input interface and the output interface may be independent of each other or may be integrated into an input / output interface. The processing circuit may be all or part of the processing circuits in one or more processors, or one or more processors. This application also provides a processor, which is used to be coupled with a memory and execute the methods and functions related to network devices or terminal devices in any one of the above embodiments. In another embodiment of this application, a computer program product containing instructions is provided. When the computer program product runs on a computer, the methods in the foregoing embodiments are implemented. This application also provides a computer program. When the computer program runs on a computer, the methods in the foregoing embodiments are implemented. In another embodiment of this application, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the methods described in the foregoing embodiments are implemented. It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include but not be limited to these and any other suitable types of memory. The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium may be any available medium that can be accessed by a computer or a server, data A central data storage device. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive. In various embodiments of the present application, the magnitudes of the sequence numbers of the above processes do not imply the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in an electrical, mechanical, or other form. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories, random access memories, magnetic disks, or optical discs. Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

Claims

1. A transmission method, characterized in that: include: Obtain a first bit sequence and N second bit sequences, where N is a positive integer; A third bit sequence is output, where the third bit sequence is obtained by superimposing the first bit of each second bit sequence in the N second bit sequences with all the bits of the first bit sequence, where the first bit is a partial bit in the second bit sequence.

2. The method according to claim 1, characterized in that The method further comprises: obtaining a fourth bit sequence; Output a fifth bit sequence, where the fifth bit sequence is obtained by superimposing all bits of the fourth bit sequence and at least one of the following: a first bit of at least one second bit sequence among the N second bit sequences, a second bit of at least one second bit sequence among the N second bit sequences, the second bit being part of the second bit sequence, and the second bit being different from the first bit; or Some bits in the first bit sequence.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: Sending first indication information, where the first indication information is used to indicate a generation rule of a bit sequence; The outputting a third bit sequence comprises: The third bit sequence is output according to the generation rule of the bit sequence.

4. The method according to claim 1 or 2, characterized in that: The method further comprises: receiving second indication information, where the second indication information is used to indicate a generation rule of a bit sequence; The outputting a third bit sequence comprises: The third bit sequence is output according to the generation rule of the bit sequence.

5. The method according to claim 3 or 4, characterized in that: The generation rule of the bit sequence includes at least one of the following: The number of stacking layers, stacking length, stacking order or stacking type.

6. The method according to claim 5, characterized in that The stacking sequence includes at least one of the following: Ordered or disordered superposition.

7. The method according to claim 5, characterized in that The overlay type includes at least one of the following: Repulsive superposition or repeated superposition.

8. The method according to any one of claims 1 to 7, characterized in that The first bit sequence and the N second bit sequences are both channel-coded bit sequences.

9. A communication device, characterized in that: include: A processing unit, configured to obtain a first bit sequence and N second bit sequences, where N is a positive integer; A transceiver unit is used to output a third bit sequence, where the third bit sequence is obtained by superimposing the first bit of each second bit sequence in the N second bit sequences with all the bits of the first bit sequence, and the first bit is a partial bit in the second bit sequence.

10. The device according to claim 9, characterized in that The processing unit is further used to obtain a fourth bit sequence; The transceiver unit is further configured to output a fifth bit sequence, where the fifth bit sequence is obtained by superimposing all bits of the fourth bit sequence and at least one of the following: a first bit of at least one second bit sequence among the N second bit sequences, a second bit of at least one second bit sequence among the N second bit sequences, the second bit being part of the second bit sequence, and the second bit being different from the first bit; or Some bits in the first bit sequence.

11. The device according to claim 9 or 10, characterized in that The transceiver unit is further used to send first indication information, where the first indication information is used to indicate a generation rule of a bit sequence; The transceiver unit is further configured to output the third bit sequence according to a generation rule of the bit sequence.

12. The device according to claim 9 or 10, characterized in that The transceiver unit is further used to receive second indication information, where the second indication information is used to indicate a generation rule of the bit sequence; The transceiver unit is further configured to output the third bit sequence according to a generation rule of the bit sequence.

13. The device according to claim 11 or 12, characterized in that The generation rule of the bit sequence includes at least one of the following: The number of stacking layers, stacking length, stacking order or stacking type.

14. The device according to claim 13, characterized in that The stacking sequence includes at least one of the following: Ordered or disordered superposition.

15. The device according to claim 13, characterized in that The overlay type includes at least one of the following: Repulsive superposition or repeated superposition.

16. The device according to any one of claims 9 to 15, characterized in that The first bit sequence and the N second bit sequences are both channel-coded bit sequences.

17. A communication device, characterized in that: The device comprises a processor, wherein the processor is configured to cause the communication device to execute the method according to any one of claims 1 to 8 by executing a computer program or instruction, or by a logic circuit.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program or instructions, and when the computer program or instructions are executed on a computer, the method according to any one of claims 1 to 8 is executed.

19. A computer program product, characterized in that The invention comprises instructions, which, when executed on a computer, enable the method according to any one of claims 1 to 8 to be executed.

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