LDPC code-based communication method and apparatus

Abstract

An LDPC code-based communication method and apparatus. Encoding or decoding can be performed on the basis of an LDPC base matrix, wherein the LDPC base matrix is determined on the basis of an LDPC storage matrix and an indicator sequence. The indicator sequence comprises x elements, one element among the x elements corresponds to one row in the LDPC storage matrix, the i-th element θ(i) among the x elements is related to the θ(i) row of the LDPC storage matrix, the LDPC storage matrix comprises at least one first row, and the first row is a multi-edge row. The LDPC memory matrix is a matrix comprising multi-edge rows. On the basis of the correlation between the element θ(i) in the indicator sequence and the θ(i) row of the LDPC storage matrix, a sending end device performs element elimination on multiple edges in the LDPC storage matrix to determine the LDPC base matrix, thereby reducing the complexity of the multi-edge LDPC, and improving the performance of LDPC encoding and decoding.

Description

A communication method and communication device based on LDPC code

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 18, 2023, with application number 202311760596.0 and invention name “A communication method and communication device based on LDPC code”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Current LDPC codes suffer from low orthogonality between rows in the LDPC basis matrix, which impacts decoding efficiency and performance. For example, new radio (NR) LDPC codes have high edge density in the high-rate portion, resulting in a lack of orthogonality between rows and supporting only parallel decoding of quasi-cyclic (QC) blocks. Summary of the Invention

[0004] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which help to improve the LDPC coding performance.

[0005] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or a module or unit in the transmitting device (e.g., a chip). The transmitting device can be a terminal device or a network device.

[0006] The method includes: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence; wherein the LDPC base matrix is ​​determined according to an LDPC storage matrix and an indicator sequence, the indicator sequence includes x elements, one element of the x elements corresponds to a row in the LDPC storage matrix, an i-th element θ(i) of the x elements is related to the θ(i)-th row of the LDPC storage matrix, the LDPC storage matrix includes at least one first row, and the first row is a row with multiple edges; and sending the LDPC codeword sequence.

[0007] It should be understood that the indication sequence in the present application can be used to indicate whether to split, eliminate, merge or puncture the rows corresponding to the elements in the sequence.

[0008] It should also be understood that the LDPC memory matrix in the present application includes rows with multi-edges, and the row with multi-edges can be used to indicate that the row includes columns with a column weight greater than or equal to 2.

[0009] It should also be understood that the i-th element θ(i) of the x elements in the indicator sequence is associated with the θ(i)-th row of the LDPC memory matrix. For example, the specific value of the i-th element θ(i) is associated with the expansion method of the θ(i)-th row of the LDPC memory matrix. The expansion method can be traditional expansion or split expansion.

[0010] According to the method provided in this application, the LDPC codeword sequence is determined based on an LDPC memory matrix and an indicator sequence. One of the x elements included in the indicator sequence corresponds to a row in the LDPC memory matrix. The LDPC memory matrix is ​​a matrix including rows with multiple edges. Based on the correlation between the element θ(i) in the indicator sequence and the row θ(i) of the LDPC memory matrix, the multiple edges in the LDPC memory matrix are eliminated to determine the LDPC basis matrix, thereby reducing the complexity of the multiple-edge LDPC and improving the LDPC coding performance.

[0011] In combination with the first aspect, in some possible implementations, the set consisting of column numbers of columns where non-zero elements included in at least one i-th row in the LDPC storage matrix are located belongs to at least one of the column numbers of columns where multiple edges included in the θ(i)-th row are located.

[0012] Based on the above technical solution, the θ(i)th row in the LDPC storage matrix can be regarded as being obtained by splitting and expanding at least one ith row, or it can be understood that the ith row is a child node and the θ(i)th row is a parent node, that is, the child node is obtained by splitting and expanding the parent node, or the parent node is obtained by eliminating the child node. The set of column numbers of the columns containing the non-zero elements included in the ith row includes at least one of the column numbers of the columns containing the multiple edges included in the θ(i)th row. That is, at least one of the column numbers of the columns of the multiple edges included in the θ(i)th row is in the set of column numbers of the columns containing the corresponding non-zero elements in the ith row.

[0013] In combination with the first aspect, in some possible implementations, the set consisting of column numbers of the columns where the non-zero elements included in the i-th row are located includes the set consisting of column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

[0014] It should be understood that the column numbers of the columns where the multiple edges included in the θ(i)th row are located are all included in the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located.

[0015] In combination with the first aspect, in some possible implementations, the i-th row is the row corresponding to the smallest index whose element value is θ(i) in the indicator sequence.

[0016] Among them, the i-th row is the row obtained by the first split of the θ(i)-th row.

[0017] It should be understood that the θ(i)th row is split for the first time to obtain the i-th row, and the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)th row are located; or, the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes at least one of the column numbers of the columns where the multiple edges included in the θ(i)th row are located.

[0018] In combination with the first aspect, in some possible implementations, the i-th row is a row corresponding to any number whose element value is θ(i) in the indicator sequence.

[0019] The i-th row is a row obtained by splitting the θ(i)-th row any number of times.

[0020] It should be understood that the θ(i)th row is split any number of times to obtain the i-th row. The i-th row can be the row obtained by splitting the θ(i)th row 2, 3, or 5 times. The number of splits is any positive integer.

[0021] It should also be understood that the i-th row is a row obtained by splitting the θ(i)-th row any number of times, and the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located; or, the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes at least one of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

[0022] In combination with the first aspect, in some possible implementations, the number of multiple edges included in the i-th row is smaller than the number of multiple edges included in the θ(i) row.

[0023] Based on the above technical solution, the i-th row is the row obtained by splitting the θ(i)-th row, or the row obtained by eliminating the i-th row. That is, the number of multi-edges in the i-th row is continuously decreasing, that is, the number of multi-edges in the i-th row is less than the number of multi-edges in the θ(i)-th row. During the splitting or elimination process, the number of multi-edges in the child node is less than the number of multi-edges in the parent node.

[0024] In combination with the first aspect, in some possible implementations, the multiplicity of the heavy edge included in the first position in the θ(i)th row is a, and the multiplicity of the heavy edge included in the first position in the i-th row is or or or or or a is a positive integer.

[0025] For example, the maximum value of the multiplicity of the heavy edges included in the i-th row is smaller than the maximum value of the multiplicity of the heavy edges included in the θ(i) row.

[0026] It should be understood that the multiplicity of the heavy edges included in the i-th row at the same position is less than the multiplicity of the heavy edges included in the θ(i)-th row. For example, the multiplicity of the heavy edges included in the first position of the i-th row is half, or one-third, or one-half rounded up or rounded down, or one-third rounded up or rounded down.

[0027] In combination with the first aspect, in some possible implementations, the i-th element of the x elements in the indicator sequence corresponds to row θ(i) in the LDPC storage matrix, and the j-th element of the x elements corresponds to row θ(j) in the LDPC storage matrix, i<j≤x, i and j are both positive integers,

[0028] The row θ(i) and the row θ(j) satisfy one or more of the following:

[0029] The number of multiple edges included in the row θ(i) is greater than or equal to the number of multiple edges included in the row θ(j);

[0030] The maximum value of the multiplicity of the heavy edges included in the row θ(i) is greater than or equal to the maximum value of the multiplicity of the heavy edges included in the row θ(j);

[0031] The row weight corresponding to the row θ(i) is greater than or equal to the row weight corresponding to the row θ(j);

[0032] The sum of the multiplicities of the multiple edges included in the row θ(i) is greater than or equal to the sum of the multiplicities of the multiple edges included in the row θ(j);

[0033] The average number of multiple edges corresponding to the row θ(i) is greater than or equal to the average number of multiple edges corresponding to the row θ(j);

[0034] The number of puncture column sets associated with the row θ(i) is greater than or equal to the number of puncture column sets associated with the row θ(j);

[0035] The number of multiple edges of the puncture column set associated with the row θ(i) is greater than or equal to the number of multiple edges of the puncture column set associated with the row θ(j);

[0036] The sum of the multiplicities of the heavy edges in the set of puncture columns associated with the row θ(i) is greater than or equal to the sum of the multiplicities of the heavy edges in the set of puncture columns associated with the row θ(j);

[0037] The maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(i) is greater than or equal to the maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(j).

[0038] Based on the above technical solution, the correlation condition between the row θ(i) of the LDPC storage matrix corresponding to the i-th element θ(i) in the indicator sequence and the row θ(j) of the LDPC storage matrix corresponding to the j-th element θ(j), i.e., the correlation characteristic between elements θ(i) and θ(j) in the indicator sequence, can further reduce complexity and improve coding performance. For example, the number of multiple edges included in row θ(i) is greater than or equal to the number of multiple edges included in row θ(j). In the indicator sequence, element θ(i) is the i-th element and element θ(j) is the j-th element, i.e., element θ(i) precedes element θ(j), and the number of multiple edges included in row θ(i) corresponding to element θ(i) is greater than or equal to that of row θ(j). In the LDPC storage matrix, the larger the row number, the lower the code rate. This ensures that as the code rate decreases, the number of multiple edges decreases faster, and the average complexity decreases faster.

[0039] In combination with the first aspect, in some possible implementations, the first matrix area is composed of the 1st to qth rows and the 1st to kth columns of the LDPC storage matrix, and the first matrix area is a matrix with q rows and k columns, where q and k are both positive integers greater than or equal to 2.

[0040] In combination with the first aspect, in some possible implementations, q is 4, k is 22, and the code rate of the first matrix area is greater than or equal to 11 / 12.

[0041] Based on the above technical solution, the first matrix region is the region from column 1 to column 22 and row 1 to row 4 in the LDPC storage matrix. The code rate of the first matrix region is greater than or equal to 11 / 12, that is, the first matrix region is a high code rate region of the LDPC storage matrix.

[0042] In combination with the first aspect, in some possible implementations, the at least one first row belongs to the row where θ(i) corresponds to the first character, and the row number of the row corresponding to the first character is the position of the first character in the indication sequence.

[0043] It should be understood that the at least one first row belongs to the row where θ(i) corresponds to the first character, that is, there are multiple edges in the row where θ(i) corresponds to the first character.

[0044] In combination with the first aspect, in some possible implementations, the at least one first row belongs to the row corresponding to the positive integer θ(i), and the row number of the row corresponding to the positive integer θ(i) is i.

[0045] It should be understood that the at least one first row belongs to the row corresponding to θ(i) being a positive integer, that is, the row corresponding to θ(i) being a positive integer has multiple edges.

[0046] In combination with the first aspect, in some possible implementations, the multiplicity of the heavy edges included in each of the at least one first row is 2, or the multiplicity of the heavy edges included in each of the at least one first row includes 2 and 3.

[0047] Based on the above technical solution, the multiplicity of the heavy edges included in each of the at least one first row includes 2, or 2 and 3. The complexity of the multiplicity of the heavy edges included in each of the at least one first row is relatively low, and the verification of each heavy edge can achieve the conversion of the heavy edge into a single edge through 1 to 2 splits. That is, when the multiplicity of the heavy edges included in each of the at least one first row includes 2, or 2 and 3, the complexity of LDPC coding can be reduced.

[0048] In combination with the first aspect, in some possible implementations, the difference in the number of multiple edges included in each row of the at least one first row is less than or equal to 1, or the difference in the sum of the multiple edge multiplicities included in each row of the at least one first row is less than or equal to 1, or the maximum value of the multiple edge multiplicities included in each row of the at least one first row is the same.

[0049] Based on the above technical solution, the number of heavy edges in each row in the at least one first row is close or the same, the sum of the heavy edge multiplicities is close or the same, and the maximum value of the heavy edge multiplicities is the same, thereby achieving a more uniform row weight distribution in each row in the at least one first row and improving the performance of the LDPC encoding and decoding.

[0050] In combination with the first aspect, in some possible implementations, the at least one first row includes 1 or 2 first rows.

[0051] Based on the above technical solution, the at least one first row includes 1 or 2 first rows, that is, there are 1 or 2 rows in the LDPC storage matrix with repeated edges, that is, the check of the repeated edges in each first row can be realized by 1 to 2 splits to convert the repeated edges into single edges, thereby further reducing the complexity of LDPC encoding and decoding.

[0052] In combination with the first aspect, in some possible implementations, the indication sequence includes: a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the second segment are composed of the first character, the third segment is composed of a positive integer, the fourth segment is composed of the first character and a positive integer, and the at least one first row belongs to the set of rows corresponding to the first segment, or the at least one first row belongs to the set of rows corresponding to the second segment, or the at least one first row belongs to the union of the set of rows corresponding to the first segment and the set of rows corresponding to the second segment, or the at least one first row belongs to the set of rows corresponding to the third segment.

[0053] In combination with the first aspect, in some possible implementations, the at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the third segment, where M is the number of rows corresponding to the core check matrix.

[0054] In combination with the first aspect, in some possible implementations, the indication sequence includes: a fifth segment, a sixth segment, and a seventh segment, wherein the fifth segment is composed of the first character, the sixth segment is composed of a positive integer, the seventh segment is composed of the first character and a positive integer, and the at least one first row belongs to the set of rows corresponding to the fifth segment, or the at least one first row belongs to the set of rows corresponding to the sixth segment.

[0055] In combination with the first aspect, in some possible implementations, the at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the fifth segment, where M is the number of rows corresponding to the core check matrix.

[0056] In combination with the first aspect, in some possible implementations, the at least one first row is located in a first matrix area in the LDPC storage matrix, the maximum row number corresponding to the rows included in the first matrix area is less than or equal to a first threshold, and θ(i) is related to the position of the at least one first row in the first matrix area.

[0057] It should be understood that the maximum row number of the rows corresponding to the first matrix region in the LDPC storage matrix is ​​less than or equal to the first threshold, or it can be understood that the code rate corresponding to the first matrix region is greater than or equal to a certain threshold (e.g., a second threshold). The first threshold can be understood as a row number threshold, and the second threshold can be understood as a code rate threshold.

[0058] Based on the above technical solution, the at least one first row is located in the first matrix area, that is, it can ensure that the rows with multiple edges are mainly distributed in the first matrix area of ​​the LDPC storage matrix, and the maximum row number of the rows corresponding to the first matrix area is less than or equal to the first threshold, that is, it is possible to use multiple edges to increase the degree of variable nodes in the area corresponding to the higher code rate in the LDPC storage matrix, thereby achieving a better degree distribution without increasing the complexity of medium and low code rates.

[0059] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving device or a module or unit in the receiving device (e.g., a chip). The receiving device can be a terminal device or a network device.

[0060] The method includes: receiving an LDPC codeword sequence; performing LDPC decoding on the LDPC codeword sequence according to an LDPC base matrix to obtain an information bit sequence; wherein the LDPC base matrix is ​​determined according to an LDPC storage matrix and an indicator sequence, the indicator sequence includes x elements, one element of the x elements corresponds to a row in the LDPC storage matrix, an i-th element θ(i) of the x elements is related to the θ(i)-th row of the LDPC storage matrix, the LDPC storage matrix includes at least one first row, and the first row is a row with multiple edges; and sending the information bit sequence.

[0061] According to the method provided in this application, the LDPC codeword sequence is determined based on an LDPC storage sequence and an indicator sequence. One of the x elements included in the indicator sequence corresponds to a row in an LDPC storage matrix. The LDPC storage matrix is ​​a matrix including rows with multiple edges. By determining the LDPC base matrix based on the correlation between the element θ(i) in the indicator sequence and the row θ(i) of the LDPC storage matrix, multiple edges in the LDPC storage matrix are eliminated, thereby reducing transmission delay and improving LDPC coding performance.

[0062] In combination with the second aspect, in some possible implementations, the set consisting of column numbers of the columns where the non-zero elements included in the i-th row are located includes the set consisting of column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

[0063] It should be understood that the column numbers of the columns where the multiple edges included in the θ(i)th row are located are all included in the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located.

[0064] In conjunction with the second aspect, in some possible implementations, the i-th row is the row corresponding to the smallest index whose element value is θ(i) in the indicator sequence.

[0065] Among them, the i-th row is the row obtained by the first split of the θ(i)-th row.

[0066] It should be understood that the θ(i)th row is split for the first time to obtain the i-th row, and the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)th row are located; or, the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes at least one of the column numbers of the columns where the multiple edges included in the θ(i)th row are located.

[0067] In combination with the second aspect, in some possible implementations, the i-th row is a row corresponding to any number whose element value is θ(i) in the indicator sequence.

[0068] The i-th row is a row obtained by splitting the θ(i)-th row any number of times.

[0069] It should be understood that the θ(i)th row is split any number of times to obtain the i-th row. The i-th row can be the row obtained by splitting the θ(i)th row 2, 3, or 5 times. The number of splits is any positive integer.

[0070] It should also be understood that the i-th row is a row obtained by splitting the θ(i)-th row any number of times, and the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located; or, the set consisting of the column numbers of the columns where the non-zero elements in the i-th row are located includes at least one of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

[0071] In combination with the second aspect, in some possible implementations, the number of multiple edges included in the i-th row is smaller than the number of multiple edges included in the θ(i) row.

[0072] Based on the above technical solution, the i-th row is the row obtained by splitting the θ(i)-th row, or the row obtained by eliminating the i-th row. That is, the number of multi-edges in the i-th row is continuously decreasing, that is, the number of multi-edges in the i-th row is less than the number of multi-edges in the θ(i)-th row. During the splitting or elimination process, the number of multi-edges in the child node is less than the number of multi-edges in the parent node.

[0073] In conjunction with the second aspect, in some possible implementations, the multiplicity of the heavy edge included in the first position in the θ(i)th row is a, and the multiplicity of the heavy edge included in the first position in the i-th row is or or or or or a is a positive integer.

[0074] It should be understood that the maximum value of the multiplicity of the heavy edges included in the i-th row is smaller than the maximum value of the multiplicity of the heavy edges included in the θ(i) row.

[0075] It should be understood that the multiplicity of the heavy edges included in the i-th row at the same position is less than the multiplicity of the heavy edges included in the θ(i)-th row. For example, the multiplicity of the heavy edges included in the first position of the i-th row is half, or one-third, or one-half rounded up or rounded down, or one-third rounded up or rounded down.

[0076] In conjunction with the second aspect, in some possible implementations, the i-th element of the x elements in the indicator sequence corresponds to row θ(i) in the LDPC storage matrix, and the j-th element of the x elements corresponds to row θ(j) in the LDPC storage matrix, i<j≤x, i and j are both positive integers,

[0077] The row θ(i) and the row θ(j) satisfy one or more of the following:

[0078] The number of multiple edges included in the row θ(i) is greater than or equal to the number of multiple edges included in the row θ(j);

[0079] The maximum value of the multiplicity of the heavy edges included in the row θ(i) is greater than or equal to the maximum value of the multiplicity of the heavy edges included in the row θ(j);

[0080] The row weight corresponding to the row θ(i) is greater than or equal to the row weight corresponding to the row θ(j);

[0081] The sum of the multiplicities of the multiple edges included in the row θ(i) is greater than or equal to the sum of the multiplicities of the multiple edges included in the row θ(j);

[0082] The average number of multiple edges corresponding to the row θ(i) is greater than or equal to the average number of multiple edges corresponding to the row θ(j);

[0083] The number of puncture column sets associated with the row θ(i) is greater than or equal to the number of puncture column sets associated with the row θ(j);

[0084] The number of multiple edges of the puncture column set associated with the row θ(i) is greater than or equal to the number of multiple edges of the puncture column set associated with the row θ(j);

[0085] The sum of the multiplicities of the heavy edges in the set of puncture columns associated with the row θ(i) is greater than or equal to the sum of the multiplicities of the heavy edges in the set of puncture columns associated with the row θ(j);

[0086] The maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(i) is greater than or equal to the maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(j).

[0087] Based on the above technical solution, the correlation condition between the row θ(i) of the LDPC storage matrix corresponding to the i-th element θ(i) in the indicator sequence and the row θ(j) of the LDPC storage matrix corresponding to the j-th element θ(j), i.e., the correlation characteristic between elements θ(i) and θ(j) in the indicator sequence, can further reduce complexity and improve coding performance. For example, the number of multiple edges included in row θ(i) is greater than or equal to the number of multiple edges included in row θ(j). In the indicator sequence, element θ(i) is the i-th element and element θ(j) is the j-th element, i.e., element θ(i) precedes element θ(j), and the number of multiple edges included in row θ(i) corresponding to element θ(i) is greater than or equal to that of row θ(j). In the LDPC storage matrix, the larger the row number, the lower the code rate. This ensures that as the code rate decreases, the number of multiple edges decreases faster, and the average complexity decreases faster.

[0088] In combination with the second aspect, in some possible implementations, the at least one first row is located in a first matrix area in the LDPC storage matrix, the maximum row number corresponding to the rows included in the first matrix area is less than or equal to a first threshold, and θ(i) is related to the position of the at least one first row in the first matrix area.

[0089] It should be understood that the maximum row number of the rows corresponding to the first matrix region in the LDPC storage matrix is ​​less than or equal to the first threshold, or it can be understood that the code rate corresponding to the first matrix region is greater than or equal to a certain threshold (e.g., a second threshold). The first threshold can be understood as a row number threshold, and the second threshold can be understood as a code rate threshold.

[0090] Based on the above technical solution, the at least one first row is located in the first matrix area, that is, it can ensure that the rows with multiple edges are mainly distributed in the first matrix area of ​​the LDPC storage matrix, and the maximum row number of the rows corresponding to the first matrix area is less than or equal to the first threshold, that is, it is possible to use multiple edges to increase the degree of variable nodes in the area corresponding to the higher code rate in the LDPC storage matrix, thereby achieving a better degree distribution without increasing the complexity of medium and low code rates.

[0091] In combination with the second aspect, in some possible implementations, the first matrix area is composed of the 1st to qth rows and the 1st to kth columns of the LDPC storage matrix, and the first matrix area is a matrix with q rows and k columns, where q and k are both positive integers greater than or equal to 2.

[0092] In combination with the first aspect, in some possible implementations, q is 4, k is 22, and the code rate of the first matrix area is greater than or equal to 11 / 12.

[0093] Based on the above technical solution, the first matrix region is the region from column 1 to column 22 and row 1 to row 4 in the LDPC storage matrix. The code rate of the first matrix region is greater than or equal to 11 / 12, that is, the first matrix region is a high code rate region of the LDPC storage matrix.

[0094] In combination with the second aspect, in some possible implementations, the at least one first row belongs to the row where θ(i) corresponds to the first character, and the row number of the row corresponding to the first character is the position of the first character in the indication sequence.

[0095] It should be understood that the at least one first row belongs to the row where θ(i) corresponds to the first character, that is, there are multiple edges in the row where θ(i) corresponds to the first character.

[0096] In combination with the second aspect, in some possible implementations, the at least one first row belongs to the row corresponding to the positive integer θ(i), and the row number of the row corresponding to the positive integer θ(i) is i.

[0097] It should be understood that the at least one first row belongs to the row corresponding to θ(i) being a positive integer, that is, the row corresponding to θ(i) being a positive integer has multiple edges.

[0098] In combination with the second aspect, in some possible implementations, the multiplicity of the heavy edges included in each of the at least one first row is 2, or the multiplicity of the heavy edges included in each of the at least one first row includes 2 and 3.

[0099] Based on the above technical solution, the multiplicity of the heavy edges included in each of the at least one first row includes 2, or 2 and 3. The complexity of the multiplicity of the heavy edges included in each of the at least one first row is relatively low, and the verification of each heavy edge can achieve the conversion of the heavy edge into a single edge through 1 to 2 splits. That is, when the multiplicity of the heavy edges included in each of the at least one first row includes 2, or 2 and 3, the complexity of LDPC coding can be reduced.

[0100] In combination with the second aspect, in some possible implementations, the difference in the number of multiple edges included in each row of the at least one first row is less than or equal to 1, or the difference in the sum of the multiple edge multiplicities included in each row of the at least one first row is less than or equal to 1, or the maximum value of the multiple edge multiplicities included in each row of the at least one first row is the same.

[0101] Based on the above technical solution, the number of heavy edges in each row in the at least one first row is close or the same, the sum of the heavy edge multiplicities is close or the same, and the maximum value of the heavy edge multiplicities is the same, thereby achieving a more uniform row weight distribution in each row in the at least one first row and improving the performance of the LDPC encoding and decoding.

[0102] In combination with the second aspect, in some possible implementations, the at least one first row includes 1 or 2 first rows.

[0103] Based on the above technical solution, the at least one first row includes 1 or 2 first rows, that is, there are 1 or 2 rows in the LDPC storage matrix with repeated edges, that is, the check of the repeated edges in each first row can be realized by 1 to 2 splits to convert the repeated edges into single edges, thereby further reducing the complexity of LDPC encoding and decoding.

[0104] In combination with the second aspect, in some possible implementations, the indication sequence includes: a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the second segment are composed of the first character, the third segment is composed of a positive integer, the fourth segment is composed of the first character and a positive integer, and the at least one first row belongs to the set of rows corresponding to the first segment, or the at least one first row belongs to the set of rows corresponding to the second segment, or the at least one first row belongs to the union of the set of rows corresponding to the first segment and the set of rows corresponding to the second segment, or the at least one first row belongs to the set of rows corresponding to the third segment.

[0105] In combination with the second aspect, in some possible implementations, the at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the third segment, where M is the number of rows corresponding to the core check matrix.

[0106] In combination with the second aspect, in some possible implementations, the indication sequence includes: a fifth segment, a sixth segment, and a seventh segment, wherein the fifth segment is composed of the first character, the sixth segment is composed of a positive integer, the seventh segment is composed of the first character and a positive integer, and the at least one first row belongs to the set of rows corresponding to the fifth segment, or the at least one first row belongs to the set of rows corresponding to the sixth segment.

[0107] In combination with the second aspect, in some possible implementations, the at least one first row belongs to the set of rows corresponding to values ​​of θ(i) of 1 to M in the fifth segment, where M is the number of rows corresponding to the core check matrix.

[0108] In a third aspect, a communication device is provided, configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0109] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0110] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0111] In a fourth aspect, a communication device is provided, comprising: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to perform the method provided by any one of the above aspects or its implementation.

[0112] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0113] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0114] In a fifth aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0115] In one implementation, the device further includes the memory.

[0116] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0117] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0118] In a seventh aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any one of the above aspects or its implementation.

[0119] In an eighth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0120] In a ninth aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0121] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0122] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0123] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0124] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0125] FIG1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0126] FIG2 is a schematic diagram of an LDPC check matrix H.

[0127] FIG3 is a Tanner graph of a check matrix H of an LDPC.

[0128] FIG4 is a schematic diagram of the structure of a check matrix.

[0129] FIG. 5 shows an example of a non-column-regularized grouping structure and a column-regularized grouping structure.

[0130] Figure 6 is an example of traditional expansion and split expansion.

[0131] FIG7 is a schematic diagram of a multi-edge LDPC code.

[0132] FIG8 is a schematic flowchart of a communication method based on LDPC codes provided in this application.

[0133] FIG9 is an example of a technical solution of an embodiment of the present application.

[0134] FIG10 is another example of the technical solution of an embodiment of the present application.

[0135] FIG11 is another example of the technical solution of an embodiment of the present application.

[0136] FIG12 is another example of the technical solution of an embodiment of the present application.

[0137] FIG13 is a schematic structural diagram of a device provided in an embodiment of the present application.

[0138] FIG14 is another schematic structural diagram of the device provided in an embodiment of the present application.

[0139] FIG15 is a schematic diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0140] To facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0141] "For indicating" or "indicating" can include direct indication and indirect indication, or "for indicating" or "indicating" can be explicitly and / or implicitly indicated. The various numerical numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device. This application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the communication field, for example, it may include the Long Term Evolution (LTE) protocol, the NR protocol and related protocols used in future communication systems. This application does not limit this. Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in this application should not be construed as being preferred or advantageous over other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "a plurality" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. Descriptions of network element A sending a message, information, or data to network element B, or network element B receiving a message, information, or data from network element A, are intended to clarify the network element to which the message, information, or data is sent, and do not limit whether the messages, information, or data are sent directly or indirectly through other network elements. Phrases such as "when," "under the circumstances," "if," and "if" all imply that the device will take appropriate action under certain objective circumstances. They do not specify a time limit, do not require the device to perform a judgment action, and do not imply any other limitations.

[0142] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0143] A communication system to which the embodiments of the present application can be applied is described below.

[0144] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0145] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0146] Exemplarily, FIG1 shows a schematic diagram of a network architecture to which an embodiment of the present application may be applied.

[0147] As shown in Figure 1, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0148] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0149] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0150] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0151] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0152] In addition, the embodiments of the present application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability and low-latency scenarios, or low-power scenarios. Among them, the high-throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, the high-reliability and low-latency scenario can be, for example, an URLLC (Ultra Reliable Low Latency Communication) scenario, and the low-power scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0153] To facilitate understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but this does not mean that the embodiments of the present application can only be applied to existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. The specific names of the concepts or terms (for example, concepts or terms involving functional descriptions) can be adjusted as future systems develop.

[0154] 1. LDPC Code

[0155] LDPC codes are linear block codes whose parity check matrices are sparse. The number of zero elements in an LDPC parity check matrix far outnumbers the number of nonzero elements. In other words, the row and column weights of the parity check matrix are very small compared to the LDPC code length. An LDPC code with an information bit sequence length equal to q and a code length equal to n can be uniquely identified by its parity check matrix.

[0156] In 1981, Tanner represented LDPC codewords using a graph, now called a Tanner graph. There is a one-to-one correspondence between a Tanner graph and a parity check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is called check nodes, representing check constraints. Each check node represents a check constraint. This is explained below with reference to Figures 2 and 3.

[0157] FIG2 is a schematic diagram of an LDPC check matrix H.

[0158] In Figure 2, {V i} represents the variable node (VN) set, {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, and each column represents a codeword bit, each codeword bit corresponds to a variable node. In Figure 2, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is connected between the variable node and the check node involved, resulting in a Tanner graph.

[0159] FIG3 is a Tanner graph of an LDPC check matrix H.

[0160] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle has one vertex in this group as both its starting and ending point, and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of the graph, also known as its size, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 4, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, which in turn corresponds to each codeword bit of the LDPC codeword. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, which in turn corresponds to each parity bit of the LDPC codeword. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as having a connection or edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0161] In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes, and edges connected end to end.

[0162] As mentioned above, LDPC is a linear block code. It divides the information sequence to be encoded into groups of q bits. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to form a codeword of length n = q + m. The mapping from q information bits to a codeword of length n is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence is generated to complete the encoding process. After the codeword sequence is transmitted over the channel, the receiving device decodes the received signal and determines the original information bits.

[0163] 2. QC-LDPC code

[0164] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the parity check matrix H of the LDPC code will be very large. Therefore, H is usually represented in blocks: the complete parity check matrix H is considered to be composed of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by an exponential matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called QC blocks.

[0165] Based on the exponential matrix H b And the improvement value Z c (lifting size), the exponential matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0166] For example, the exponential matrix H of the QC-LDPC code b As shown below:

[0167] It can be seen that the exponential matrix H b The size of the exponential matrix H is 4 rows and 24 columns. b Each element in represents a Z c square matrix of order, element represents the cyclic permutation matrix, i represents the cyclic shift value, and i is an integer. In addition, the exponential matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0168] For example, As shown below:

[0169] Optional, exponential matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0170] It should be noted that the above-mentioned exponential matrix can also be called a base graph (BG). In the embodiments of the present application, the base matrix will be used to describe the embodiments of the present application. It can be understood that the above-mentioned exponential matrix has corresponding characteristics.

[0171] 3. Non-zero elements and zero elements

[0172] In the check matrix, a zero element indicates that there is no connection between the variable node and the check node, and a non-zero element indicates that there is a connection between the variable node and the check node.

[0173] In the LDPC index matrix, the zero element represents Z c An all-zero square matrix of order, with non-zero elements representing Z c The identity matrix of order or based on Z c The circulant permutation matrix of the identity matrix of order , where the values ​​of the non-zero elements represent the circulant shift values ​​or offset values ​​(shifting value) relative to the identity matrix.

[0174] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the check matrix H shown in Figure 2, "0" is used to represent zero elements and "1" is used to represent non-zero elements. For another example, the exponential matrix H described above b In the , "-1" is used to represent zero elements, and "non-negative values" are used to represent non-zero elements.

[0175] For the convenience of description, "0" is used below to represent a zero element and "1" is used to represent a non-zero element.

[0176] 4. Column weight and row weight

[0177] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, as shown in Figure 2, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4. For another example, as described above, the exponential matrix H b The first column has a column weight of 4 and the first row has a row weight of 20.

[0178] 5. Structure of the check matrix

[0179] FIG4 is a schematic diagram of the structure of a check matrix.

[0180] As shown in Figure 4 (a), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B shown in Figure 4 (b). Part A corresponds to information bits (also known as information bits, systematic bits, etc.), and part B is a square matrix corresponding to core parity bits (also known as core check bits). The core check can be the check corresponding to the highest code rate, or a check with a degree greater than or equal to 2, or the check nodes corresponding to the set of rows with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4 (b), an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4 (b). The raptor-like region can correspond to part E in Figure 4 (b), a unit matrix corresponding to the parity bits for low-rate extension.

[0181] The parity check matrix of the LDPC code shown in Figure 4 employs a "raptor-like" structure, allowing for gradual expansion to lower code rates using a high-rate core matrix. In practice, as shown in Figure 4 (a), the first X rows and Y columns of the parity check matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the matrix area used also expands.

[0182] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0183] 6. Information column and check column

[0184] The columns of the LDPC basis matrix consist of information columns and check columns.

[0185] Information column: corresponds to the information bit (also called information bit, system bit, etc.), which is the column corresponding to part A.

[0186] Parity column: Corresponds to the parity bit (or check digit). It can include a core parity column and an extended parity column. The core parity column corresponds to part B, and the extended parity column corresponds to part C or part E. The extended parity column is also called a raptor-like column. The extended parity column corresponds to the extended node.

[0187] 7. Core rows, core columns, and core matrices

[0188] Core rows: The core rows of the LDPC matrix are the rows corresponding to the core parity bits. In other words, the core rows are the rows corresponding to the high-rate region, or the rows corresponding to Part A, Part B, or Part C.

[0189] Core columns: This includes all information columns and all core check columns. In other words, core columns are the columns corresponding to the high bitrate area, or the columns corresponding to part A + part B.

[0190] Kernel Matrix: This is the matrix region consisting of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is ​​the high-rate region of the LDPC base matrix, or the portion consisting of Part A and Part B.

[0191] 8. Information transmission process

[0192] Figure 5 is a schematic diagram of the information transmission process. As shown in Figure 5, information is sent by the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, and arrives at the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 5 (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in Figure 5.

[0193] 9. Traditional expansion and split expansion

[0194] Traditional expansion: also known as normal expansion, refers to a low-code rate expansion method based on the traditional method. In this method, the rows of the storage matrix are read as the rows of the LDPC basis matrix.

[0195] Split-and-expand: Unlike traditional expansion, this approach uses a row of the storage matrix as a newly added row of the LDPC base matrix. The newly added row is then used to eliminate a row in the LDPC base matrix preceding the newly added row. The eliminated row and the newly added row are orthogonal, excluding the expanded nodes. Alternatively, the eliminated row is split into the newly added row and the eliminated row; or, the eliminated row and the newly added row are orthogonal, excluding the expanded nodes; or, the eliminated row contains all rows in the newly added row except for the expanded check nodes. The eliminated row can correspond to the parent node, and the newly added row, or the eliminated row, can correspond to the child node.

[0196] Figure 6 is an example of traditional expansion and split expansion.

[0197] FIG6 takes the splitting and expansion of the second row as an example.

[0198] Figure 6 (a) is the matrix before expansion. Figure 6 (b) is the matrix after adding a row. The process from Figure 6 (a) to Figure 6 (b) is a traditional expansion. Figure 6 (c) is the matrix after eliminating row 2 using the added row. The process from Figure 6 (a) to Figure 6 (b) to Figure 6 (c) is a splitting expansion. The eliminated row and the newly added row are orthogonal, except for the last column.

[0199] Figure 7 is a schematic diagram of a multi-edge LCPC code. In current multi-edge LDPC codes, since each element in the base matrix BG can be an integer greater than or equal to 2, this means that the position can be expanded into multiple cyclic shift matrices, which are further added together to form a check matrix.

[0200] Among them, the number of multiple edges in this application is the sum of the positions where the value of BG is greater than or equal to 2, that is, as shown in Figure 7, there are 5 positions with multiple edges, namely: row 1 and column 1, row 1 and column 2, row 1 and column 3, row 1 and column 5, and row 2 and column 1, that is, the number of multiple edges included in the basis matrix shown in Figure 7 is 5.

[0201] The multiplicity of the heavy edge in this application is the specific value of the BG at a position. As shown in Figure 7, the multiplicity of the heavy edge in column 1, row 1 is 3; the multiplicity of the heavy edge in column 1, row 2 is 2; the multiplicity of the heavy edge in column 2, row 1 is 2; the multiplicity of the heavy edge in column 3, row 1 is 2; and the multiplicity of the heavy edge in column 5, row 1 is 2. In the multi-edge LDPC code shown in Figure 7, the maximum value of the heavy edge multiplicity is the maximum value of the above-mentioned heavy edge multiplicity, that is, 3.

[0202] It should be understood that multi-edge LDPC codes have a larger degree distribution design space than single-edge LDPC codes. The degree distribution of LDPC codes is used to indicate the column weight distribution of the parity check matrix. Currently, the design goal of LDPC codes is often to ensure an optimal decoding threshold. However, density evolution theory determines the column weight distribution, which is the most important factor affecting the decoding threshold. Therefore, the degree distribution of LDPC codes is a hot topic of research in code construction. While multi-edge LDPC codes have the same matrix size as single-edge LDPC codes, they support larger column weights, meaning that multi-edge LDPC codes have a more optimal decoding threshold.

[0203] Currently in wireless communication systems, since each QC block in the multi-edge LDPC code is associated with each other, compared with the architecture of single-edge LDPC code that is suitable for parallel decoding of QC blocks, the multi-edge LDPC code cannot be read, calculated and stored in parallel. It also has disadvantages such as high latency, low hardware utilization, and uneven hardware utilization, which affects the coding efficiency and performance of the LDPC code.

[0204] In response to the above-mentioned problems, the present application provides a communication method and a communication device for multiple-edge LDPC codes based on indicator sequences, in order to improve decoding efficiency and performance.

[0205] The following describes the method embodiments of the present application.

[0206] FIG8 is a schematic flowchart of a communication method based on LDPC codes provided in this application.

[0207] Method 800 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or receiving device itself, or can refer to a device that supports the transmitting device or receiving device to implement the function. For convenience of description, the following description uniformly uses the transmitting device and receiving device. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0208] Method 800 may include at least part of the following.

[0209] 801. A transmitting device obtains an information bit sequence.

[0210] That is, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0211] The transmitting end device obtaining the information bit sequence may refer to: the transmitting end device performing source coding on source symbols to generate the information bit sequence. The transmitting end device obtaining the information bit sequence may also refer to: the transmitting end device receiving the information bit sequence from other communication devices.

[0212] 802. The transmitting end device performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence.

[0213] The LDPC base matrix is ​​determined based on an LDPC storage matrix and an indicator sequence. The LDPC storage matrix may refer to a matrix stored in the transmitting device or a matrix predefined by the protocol. The indicator sequence may also refer to a matrix stored in the transmitting device or a sequence predefined by the protocol.

[0214] It should be understood that the indicator sequence includes x elements, where one element of the x elements corresponds to a row in the LDPC memory matrix. The i-th element θ(i) of the x elements is associated with the θ(i)-th row in the LDPC memory matrix. The rows of the LDPC memory matrix correspond one-to-one to the elements in the indicator sequence, so the number of rows in the LDPC memory matrix is ​​equal to the length of the indicator sequence.

[0215] It should be understood that the transmitting device can determine the LDPC base matrix based on the LDPC storage matrix and the indicator sequence, and use the LDPC base matrix to perform LDPC encoding on the information bit sequence to obtain the LDPC codeword sequence. Among them, the LDPC base matrix is ​​the matrix actually used by the transmitting end when performing LDPC encoding. In the process of obtaining the LDPC base matrix, the transmitting end reads the x rows corresponding to the x elements included in the indicator sequence from the LDPC storage matrix according to the x elements. Among them, the value θ corresponding to each element in the x elements is related to the expansion method of the θth row in the LDPC storage matrix. The expansion method can be split expansion or traditional expansion. The description of split expansion and traditional expansion can be referred to above and will not be described in detail here.

[0216] It should also be understood that the value of the element θ(i) in the indicator sequence can be the first character or a positive integer, and when the value of θ(i) is a positive integer, the θ(i) is less than i, that is, the value of θ(i) is less than the row number of the current row. The value of the element θ(i) in the indicator sequence represents the expansion method of the matrix. For example, when θ(i) is a positive integer, it means that the i-th row is split and expanded, that is, the i-th row needs to split the θ(i)-th row; when θ(i) is the first character, it means that the i-th row is expanded normally.

[0217] As an example, in the process of obtaining the LDPC base matrix, the transmitting end device may select corresponding rows in the LDPC storage matrix from the first element to the xth element for expansion based on the x elements included in the indicator sequence. The transmitting end device determines the expansion mode of the i-th row based on the value of the element θ(i) corresponding to the i-th row being the first character or a positive integer, such as split expansion or normal expansion.

[0218] It should be noted that the rows of the matrices involved in this application are all counted from row 1, and the columns are all counted from column 1, that is, the first character in this application can be 0. If the rows of the matrix are counted from row 0 and / or the columns are counted from column 0, that is, the first character cannot be 0, and can be other characters, such as -1, -2, etc. The first character can be a number, a letter, or a symbol, etc., which is not limited in this application.

[0219] In one possible implementation, the LDPC memory matrix includes at least one first row, where the at least one first row is a row having multiple edges. Next, the LDPC memory matrix will be exemplarily introduced:

[0220] It should be understood that the LDPC storage matrix includes at least one row with multiple edges. The at least one first row is located in a first matrix region of the LDPC storage matrix, and the maximum row number corresponding to the rows included in the first matrix region is less than or equal to a first threshold. The specific value of the element θ(i) in the indicator sequence is related to the position of the at least one first row in the first matrix region. That is, the row with multiple edges is located in the first matrix region of the LDPC storage matrix, and the specific position of the row with multiple edges is related to the element θ(i) in the indicator sequence.

[0221] As an example, the first matrix region is composed of the 1st to qth rows and the 1st to kth columns in the LDPC memory matrix, that is, the first matrix region is a matrix with q rows and k columns. q and k are both positive integers greater than or equal to 2.

[0222] For example, the first threshold may be a row number threshold. Assume that the first threshold is 4, that is, the maximum row number corresponding to the rows included in the first matrix region is less than or equal to 4. Wherein, assuming that the maximum row number corresponding to the rows included in the first matrix region is 2, that is, q=2, that is, the rows included in the first matrix region are the 1st and 2nd rows in the LDPC storage matrix; assuming that the maximum row number corresponding to the rows included in the first matrix region is 3, that is, q=3, that is, the rows included in the first matrix region are the 1st, 2nd and 3rd rows in the LDPC storage matrix; assuming that the maximum row number corresponding to the rows included in the first matrix region is 4, that is, q=4, that is, the rows included in the first matrix region are the 1st, 2nd, 3rd and 4th rows in the LDPC storage matrix.

[0223] For example, the first threshold may be a row number threshold. Assuming that the first threshold is 8, that is, the maximum row number corresponding to the rows included in the first matrix region is less than or equal to 8, that is, q is less than or equal to 8. Assuming that the first threshold is 12, that is, the maximum row number corresponding to the rows included in the first matrix region is less than or equal to 12, that is, q is less than or equal to 12.

[0224] For example, the first matrix region is a matrix with 4 rows and 22 columns, that is, the first matrix region belongs to the matrix from row 1 to row 4 and column 1 to column 22 in the LDPC storage matrix. As shown in region A in Figure 4 above, the code rate supported by the first matrix region can be equal to 22 / (22+4-2)=11 / 12. When the code rate of the first matrix region is greater than 11 / 12, the code rate of the first matrix region can be increased by puncturing.

[0225] It can be seen that the first threshold limits the position of the first matrix region in the LDPC storage matrix through the row number threshold. That is, the smaller the first threshold, the higher the code rate corresponding to the first matrix region. The at least one first row is located within the first matrix region. It can be seen that increasing the degree of variable nodes in the high-code-rate matrix region through multiple edges can achieve a higher degree distribution and improve the performance of LDPC code. At the same time, the at least one first row is located within the first matrix region, which does not increase the complexity of the matrix region corresponding to medium and low code rates.

[0226] It should be understood that the specific position of the at least one first row in the first matrix area is related to the element θ(i) in the indication sequence corresponding to the at least one first row.

[0227] As an example, the specific position of the at least one first row is related to an element θ(i) in the indicator sequence. The at least one first row belongs to a row corresponding to θ(i) being the first character, and the row number of the row corresponding to the first character is the position of the first character in the indicator sequence. The at least one first row belongs to a row corresponding to θ(i) being the first character, that is, the at least one first row is located in the row corresponding to θ(i) being the first character within the first matrix region.

[0228] For example, if the first character is the number (0), assuming that the second element in the indicator sequence is θ(2)=0, the second row in the LDPC storage matrix corresponds to the element θ(2)=0, that is, the second row in the LDPC storage matrix is ​​a row with multiple edges; for example, if the first character is (*), assuming that the third element in the indicator sequence is θ(3)=*, the third row in the LDPC storage matrix corresponds to the element θ(3)=*, that is, the third row in the LDPC storage matrix is ​​a row with multiple edges.

[0229] As another example, the specific position of the at least one first row is related to an element θ(i) in the indicator sequence. The at least one first row belongs to a row corresponding to θ(i) being a positive integer, the row number of the row corresponding to θ(i) being the position of θ(i) in the indicator sequence, and the row number of the row corresponding to θ(i) being a positive integer being i. The at least one first row belongs to a row corresponding to θ(i) being a positive integer, that is, the at least one first row is located in a row corresponding to θ(i) being a positive integer within the first matrix region.

[0230] For example, assuming that the 4th element in the indicator sequence is θ(4)=2, the 4th row in the LDPC storage matrix corresponds to the element θ(4)=2, and θ(4) is a positive integer, that is, the 4th row in the LDPC storage matrix is ​​a row with multiple edges, and the row corresponding to the element θ(4) in the indicator sequence is row 4 in the LDPC storage matrix, and row 4 is a row with multiple edges; assuming that the 5th element in the indicator sequence is θ(5)=4, θ(5) is a positive integer, that is, the 5th row in the LDPC storage matrix is ​​a row with multiple edges, and the row corresponding to the element θ(5) in the indicator sequence is row 5 in the LDPC storage matrix, and row 5 is a row with multiple edges.

[0231] It should be understood that the first threshold is further determined based on the correlation between the specific position of the at least one first row and the element θ(i) in the indicator sequence and the value of the maximum row number corresponding to the rows included in the first matrix region.

[0232] Assuming that threshold #1 is less than threshold 2, and the maximum row number corresponding to the rows included in the first matrix region is less than or equal to threshold #1, the at least one first row may belong to the row corresponding to θ(i) as the first character in the first matrix region. The rows in regions other than the first matrix region of the LDPC storage matrix where θ(i) is the first character are all unilateral. Assuming that the maximum row number corresponding to the rows included in the first matrix region is less than or equal to threshold #2, the at least one first row may belong to the row in the first matrix region where θ(i) is a positive integer. The rows in regions other than the first matrix region of the LDPC storage matrix where θ(i) is a positive integer are all unilateral.

[0233] By dividing at least one first row belonging to a row corresponding to θ(i) being the first character and at least one first row belonging to a row corresponding to θ(i) being a positive integer into two different cases, different expansion methods are further distinguished, thereby more effectively controlling the complexity of LDPC encoding and decoding.

[0234] It should be understood that the multiplicity of the heavy edges included in each of the at least one first row is 2, or the multiplicity of the heavy edges included in each of the at least one first row includes 2 and 3. As shown in (1) and (2) in Figure 9, the size of the multiplicity of the heavy edges included in the at least one first row is limited, wherein the check of each heavy edge can obtain a single edge by splitting 1 to 2 times, thereby achieving low complexity of LDPC coding.

[0235] It should also be understood that the difference in the number of multiple edges included in each row of the at least one first row is less than or equal to 1, or the difference in the sum of the multiple edge multiplicities included in each row of the at least one first row is less than or equal to 1, or the maximum value of the multiple edge multiplicities included in each row of the at least one first row is the same. As shown in (1) in Figure 10, the at least one first row is the 1st row, the 2nd row and the 3rd row. Among them, the number of multiple edges included in the 1st row, the 2nd row and the 3rd row are all 1, that is, the number of multiple edges included in each row of the at least one first row is equal, that is, the difference in the number of multiple edges is only 0. Among them, the multiple edge multiplicities included in the 1st row, the 2nd row and the 3rd row are 2, 2, and 3 respectively, and the multiple edge multiplicities included in the 1st row and the 2nd row are equal, both 2. The multiple edge multiplicities included in the 3rd row are 3, which is only 1 different from the multiple edge multiplicities included in the 1st row and the 2nd row. As shown in (2) in Figure 10, the at least one first row is the 1st row, the 2nd row and the 3rd row. Among them, the number of multiple edges included in the first row, the second row and the third row is all 1, and the multiple edge multiplicity is all 2, that is, the maximum value of the multiple edge multiplicity included in at least one first row is equal.

[0236] It should also be understood that the at least one first row included in the LDPC memory matrix includes one or two first rows. One or two rows in the LDPC memory matrix have multiple edges, that is, the multiple edges in each first row can be verified by splitting them one or two times to convert the multiple edges into single edges, thereby further reducing the complexity of LDPC coding.

[0237] Based on the above introduction to the rows with multiple edges in the LDPC memory matrix, the following is an exemplary introduction to the relevant characteristics of the rows included in the LDPC memory matrix:

[0238] In one possible implementation, the set consisting of column numbers of columns where non-zero elements included in at least one i-th row in the LDPC storage matrix are located includes at least one of the column numbers of columns where multiple edges included in the θ(i)-th row are located.

[0239] It should be understood that in the split expansion method, the set consisting of the column numbers of the columns where the non-zero elements in any at least one row (for example, at least one i-th row) in the LDPC storage matrix are located includes at least one of the column numbers of all columns with multiple edges in the θ(i)-th row.

[0240] As an example, assuming that the fifth element in the exponential sequence is θ(5)=3, the fifth row in the LDPC storage matrix needs to split and expand the third row. The third row is equivalent to the parent node of the fifth row, and the fifth row is equivalent to the child node of the third row. The fifth row can be the row obtained by the first split of the third row, or the fifth row can be the row obtained by classifying the third row twice, three times or even more times. The third row is 2,1,3,0,1,0,1. It can be seen that the number of multiple edges in the third row is 2, the number of multiple edges with column number "1" is "2" and the number of multiple edges with column number "3" is "3". For example, the fifth row can be 1,0,2,0,0,1,1, and the column numbers of the columns where the non-zero elements included in the fifth row are located are 1, 2, 6 and 7, that is, the set of column numbers of the columns where the non-zero elements included in the fifth row are located includes the column numbers of the columns where the multiple edges included in the third row are located. For example, the 5th row can be 0, 0, 1, 0, 0, 1, 0, and the column numbers of the columns where the non-zero elements included in the 5th row are located are 3 and 6, that is, the set of column numbers of the columns where the non-zero elements included in the 5th row are located includes one of the column numbers of the columns where the multiple edges included in the 3rd row are located.

[0241] Among them, the 5th row can be the row obtained by splitting the 3rd row for the first time, that is, the 5th row can be "1,0,2,0,0,1,1" in the above example; the 5th row can be the row obtained by splitting the 3rd row any number of times (for example, 2 times), that is, the 5th row can be "0,0,1,0,0,1,0" in the above example.

[0242] It should be understood that the first position in the θ(i)th row includes a multiplicity of edges, and the first position in the i-th row includes a multiplicity of edges. or or or or or a is a positive integer. There is a certain relationship between the specific values ​​of the multiplicity of the same position in the θ(i)th row and the i-th row. For example, the multiplicity of the first position in the θ(i)th row is 4, and the multiplicity of the first position in the i-th row can be 2, or or or It should be understood that the multiplicity of the heavy edges included in the first position in the i-th row can also be determined by other calculation methods, which will not be introduced one by one in this application.

[0243] In one possible implementation, the set consisting of the column numbers of the columns where the non-zero elements included in the i-th row of the LDPC storage matrix are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

[0244] It should be understood that in the splitting and expanding manner, the θ(i)-th row is equivalent to the parent node of the i-th row, and the set of column numbers of the columns where the non-zero elements of its child nodes are located includes the set of column numbers of all columns with multiple edges in the parent node.

[0245] As an example, assume that the 4th element θ(4) = 2 in the exponential sequence. The 4th row in the LDPC storage matrix needs to split and expand the 2nd row, and the 2nd row is equivalent to the parent node of the 4th row, and the 4th row is equivalent to the child node of the 2nd row. As shown in Figure 11, child node #1 is obtained by splitting the parent node. The set of column numbers of the columns with multiple edges in this parent node is {1, 2, 3, 5}, and the set of column numbers of the columns where the non-zero elements in child node #1 are located is {1, 2, 3, 5, 8}. It can be seen that child node #1 will include all the columns corresponding to the multiple edges in its parent node. Child node #2 is the child node of child node #1, that is, child node #1 is the parent node of child node #2. The set of column numbers of the columns with multiple edges in child node #1 is {1}, and the set of column numbers of the columns where the non-zero elements in child node #2 are located is {1, 3, 8}. It can be seen that the set of column numbers of the columns where the non-zero elements in child node #2 are located includes the column numbers of all the columns corresponding to the multiple edges in child node #1. According to Figure 11 shown above, it can be seen that the child node includes all the columns corresponding to the multiple edges in its parent node.

[0246] It should be understood that assume the set of associated variables of the row i corresponding to the child node is N(i), the number of edges connected to the j-th column of the i-th row can be expressed as M(i, j), and the number of edges N(i) of its child node i can satisfy that for any variable node j ∈ N(i), the number of multiple edges of this child node is less than the number of multiple edges of its parent node: M(i, j) < M(θ(i), j). It can be seen that not all the multiple edges included in the parent node will appear in the child node, that is, the sum of the multiplicities of the multiple edges included in the parent node is greater than the sum of the multiplicities of the multiple edges included in the child node. By ensuring the reduction of the number of multiple edges through each splitting and expansion, the complexity of LDPC encoding and decoding can be further reduced.

[0247] It should also be understood that when the parent node (i1) is split for the first time, its child node (i2) includes all the columns corresponding to the multiple edges in the parent node. That is, the set {v ∈ N(i1)|M(i1, v) > 1} is a subset of N(i). Among them, the first split can identify the position of the first occurrence of this row number in the sequence. That is, for node i1, the position i2 of its first occurrence satisfies the condition θ(i2) = i1 and for any i′ < i2, θ(i′) ≠ i1. Among them, in this implementation method, for any node (i k ) and its first child node i k+1 , this child node i k+1 must include all the multiple edges of its parent node i kThe columns corresponding to all multiple edges in , k is any positive integer.

[0248] It should also be understood that the above description is based on the relationship between the i-th row and the θ(i)-th row. The first position in the θ(i)-th row has a multiplicity of edges, and the first position in the i-th row has a multiplicity of edges. or or or or or a is a positive integer. For specific examples, please refer to the above specific examples and will not be repeated here.

[0249] It should also be understood that, based on the aforementioned correlation characteristics of the rows included in the LDPC memory matrix, it is necessary to perform elimination / splitting on the multiple edges included in the multi-edge LDPC matrix, thereby splitting the multiple edges into single edges as quickly as possible. Regarding the aforementioned splitting of the multiple edges, the order of the splitting is related to the correlation characteristics of the elements θ(i) in the indicator sequence.

[0250] Next, the relevant characteristics of the element θ(i) in the indicator sequence are introduced as follows:

[0251] In one possible implementation, the i-th element among the x elements in the indicator sequence corresponds to the θ(i)-th row in the LDPC storage matrix, the j-th element among the x elements corresponds to the θ(j)-th row in the LDPC storage matrix, i<j≤x, i and j are both positive integers, and the θ(i)-th row and the θ(j)-th row satisfy one or more of the following:

[0252] (1) The number of multiple edges in the θ(i)th row is greater than or equal to the number of multiple edges in the θ(j)th row;

[0253] (2) The maximum value of the multiplicity of the heavy edges included in the θ(i)th row is greater than or equal to the maximum value of the multiplicity of the heavy edges included in the θ(j)th row;

[0254] (3) The row weight corresponding to the θ(i)th row is greater than or equal to the row weight corresponding to the θ(j)th row;

[0255] (4) The sum of the multiplicities of the edges in row θ(i) is greater than or equal to the sum of the multiplicities of the edges in row θ(j);

[0256] (5) The average number of multiple edges corresponding to the θ(i)th row is greater than or equal to the average number of multiple edges corresponding to the θ(j)th row;

[0257] (6) The number of puncture column sets associated with row θ(i) is greater than or equal to the number of puncture column sets associated with row θ(j);

[0258] (7) The number of multi-edges in the set of puncture columns associated with row θ(i) is greater than or equal to the number of multi-edges in the set of puncture columns associated with row θ(j);

[0259] (8) The sum of the multiplicity of the heavy edges in the set of puncture columns associated with row θ(i) is greater than or equal to the sum of the multiplicity of the heavy edges in the set of puncture columns associated with row θ(j);

[0260] (9) The maximum value of the multiplicity of heavy edges in the set of punctured columns associated with the θ(i)th row is greater than or equal to the maximum value of the multiplicity of heavy edges in the set of punctured columns associated with the θ(j)th row.

[0261] It should be understood that the i-th element θ(i) in the indicator sequence is located before the j-th element θ(j), that is, if splitting is required, the θ(i)-th row is splitted first compared to the θ(j)-th row.

[0262] Regarding (1) above, the number of heavy edges included in the θ(i)th row is greater than or equal to the number of heavy edges included in the θ(j)th row. For example, the number of heavy edges included in the θ(i)th row is 3, and the number of heavy edges included in the θ(j)th row is 2, and 3>2. The row number corresponding to the θ(i)th row is smaller than the row number corresponding to the θ(j)th row, which ensures that the number of heavy edges decreases as the bit rate decreases, reducing the complexity of LDCP encoding and decoding.

[0263] Regarding (2) above, the maximum value of the number of heavy edges included in the θ(i)th row is greater than or equal to the maximum value of the number of heavy edges included in the θ(j)th row. For example, the number of heavy edges included in the θ(i)th row is 2, 2, and 3, and the number of heavy edges included in the θ(j)th row is 2, 2, and 2. The maximum value of the number of heavy edges included in the θ(i)th row is 3, which is greater than the maximum value of the number of heavy edges included in the θ(j)th row, 2. The row number corresponding to the θ(i)th row is smaller than the row number corresponding to the θ(j)th row, which ensures that the maximum value of the number of heavy edges decreases as the bit rate decreases, reducing the complexity of LDCP encoding and decoding.

[0264] Regarding (3) above, the row weight corresponding to row θ(i) is greater than or equal to the row weight corresponding to row θ(j). For example, the row weight of row θ(i) is 5, and the row weight corresponding to row θ(j) is 4, where 5>4. The row number corresponding to row θ(i) is smaller than the row number corresponding to row θ(j), which ensures that the row weight decreases as the bit rate decreases, making the decoding threshold optimal.

[0265] It should be understood that the row weight can be the number of all variable nodes associated with the check row, or the number of core variable nodes associated with the check row, which is not limited in this application.

[0266] It should also be understood that the arrangement order of the elements in the indicator sequence can be sorted by sorting the row weights corresponding to the elements from large to small. First, the row set R with the largest row weight is filtered, and then the row set R is filtered according to the above (1) and / or (2), wherein the above (1) and (2) filtering methods are both from large to small.

[0267] As an example, the degree distribution is divided into at least two intervals [d1, d2], [d3, d4], ..., [d 2k-1 ,d 2k ], where d k The degree distribution is monotonically decreasing with k, and the degree within each interval is considered consistent when sorting. For example, if the degree distribution is divided into intervals [8,11], [4,7], [2,3], the sorting result is: the first segment of the indicator sequence includes elements corresponding to rows with row weights of 8 to 11, the second segment includes elements corresponding to rows with row weights of 4 to 7, and the third segment includes elements corresponding to rows with row weights of 2 to 3. This means that the degree distribution is divided into several sets / segments, and the ordering is based on the corresponding sets. For example, if the row set is divided into {8,9,10,11}, {4,5,7}, {2,3}, the sorting result is: the first segment of the indicator sequence includes elements corresponding to rows with row weights of {8,9,10,11}, the second segment includes elements corresponding to rows with row weights of {4,5,7}, and the third segment includes elements corresponding to rows with row weights of {2,3}.

[0268] For (4) above, the sum of the multiplicity of the heavy edges in the θ(i)th row is greater than or equal to the sum of the multiplicity of the heavy edges in the θ(j)th row. For example, the multiplicity of the heavy edges in the θ(i)th row is 2, 2, and 3, respectively, that is, the sum of the multiplicity of the heavy edges in the θ(i)th row (∑ v∈N(i) [M(i,v)-1]) is 7, and the multiplicity of the edges in the θ(i)th row is 2, 2, and 2, which is the sum of the multiplicity of the edges in the θ(j)th row (∑ v∈N(j) [M(j,v)-1]) is 6.

[0269] For (5) above, the average number of heavy edges corresponding to the θ(i)th row is greater than or equal to the average number of heavy edges corresponding to the θ(j)th row. For example, the θ(i)th row is: 2,2,1,0,0,0,0,3, that is, the average number of heavy edges in the θ(i)th row (∑ v∈N(i) [M(i,v)-1] / |N(j)) is 7 / 4, and the multiplicity of the heavy edges in the θ(i)th row is 2,2,1,0,0,0,1,2, that is, the sum of the multiplicity of the heavy edges in the θ(j)th row (∑ v∈N(j) [M(j,v)-1] / |N(j)) is 6 / 5.

[0270] Regarding (6), the number of punctured column sets associated with the θ(i)th row is greater than or equal to the number of punctured column sets associated with the θ(j)th row. For example, the number of punctured column sets corresponding to the θ(i)th row is 2, and the number of punctured column sets corresponding to the θ(j)th row is 1. The number of punctured column sets corresponding to the θ(i)th row is 2 > the number of punctured column sets corresponding to the θ(j)th row is 1. The row number corresponding to the θ(i)th row is smaller than the row number corresponding to the θ(j)th row, that is, the number of punctures is prioritized to decrease as the code rate decreases. The number of punctures is divided into multiple rows, thereby improving the convergence speed of LDPC decoding.

[0271] Regarding (7), the number of heavy edges of the puncture column set associated with the θ(i)th row is greater than or equal to the number of heavy edges of the puncture column set associated with the θ(j)th row. For example, the number of heavy edges associated with the puncture column corresponding to the θ(i)th row is 2, and the number of heavy edges associated with the puncture column corresponding to the θ(j)th row is 1. The number of heavy edges associated with the puncture column corresponding to the θ(i)th row is greater than the number of heavy edges of the puncture column set associated with the θ(j)th row. The row number corresponding to the θ(i)th row is less than the row number corresponding to the θ(j)th row, that is, the priority is to ensure that the number of heavy edges decreases as the code rate decreases, ensuring that the average complexity decreases faster.

[0272] For (8), the sum of the number of heavy edges in the set of puncturing columns associated with the θ(i)th row is greater than or equal to the sum of the number of heavy edges in the set of puncturing columns associated with the θ(j)th row. For example, the number of heavy edges associated with the puncturing columns corresponding to the θ(i)th row is 2 and 2, and the number of heavy edges associated with the puncturing columns corresponding to the θ(j)th row is 2. The sum of the number of heavy edges associated with the puncturing columns corresponding to the θ(i)th row is greater than the sum of the number of heavy edges in the set of puncturing columns associated with the θ(j)th row. The row number corresponding to the θ(i)th row is smaller than the row number corresponding to the θ(j)th row, that is, it is prioritized to ensure that the number of heavy edges decreases as the code rate decreases, ensuring that the average complexity decreases faster.

[0273] For (9), the maximum value of the number of heavy edges in the set of puncturing columns associated with the θ(i)th row is greater than or equal to the maximum value of the number of heavy edges in the set of puncturing columns associated with the θ(j)th row. For example, the number of heavy edges associated with the puncturing columns corresponding to the θ(i)th row is 2 and 3, and the number of heavy edges associated with the puncturing columns corresponding to the θ(j)th row is 2. The maximum value of the number of heavy edges associated with the puncturing columns corresponding to the θ(i)th row is greater than the maximum value of the number of heavy edges in the set of puncturing columns associated with the θ(j)th row. The row number corresponding to the θ(i)th row is smaller than the row number corresponding to the θ(j)th row, that is, the priority is to ensure that the number of heavy edges decreases as the code rate decreases, ensuring that the average complexity decreases faster.

[0274] It should be understood that for the above (6) to (9), as shown in (1) in FIG12 , it is assumed that the first column and the second column are punctured columns, that is, the punctured column set includes the first column and the second column. According to the above (6), the number of punch column sets associated with rows 1 to 4 is determined to be 2, 1, 1, 2, respectively, and they are sorted from large to small as row 1, row 4, row 3, and row 2; according to the above (7), the number of heavy edges associated with punch columns corresponding to rows 1 to 4 is determined to be 1, 1, 0, 0, respectively, and they are sorted from large to small as row 1, row 2, row 3, and row 4; according to the above (8), the number of heavy edges associated with punch columns corresponding to rows 1 to 4 is determined to be 4, 3, 0, 0, respectively, and they are sorted from large to small as row 1, row 2, row 3, and row 4; according to the above (9), the maximum value of the number of heavy edges associated with punch columns corresponding to rows 1 to 4 is determined to be 2, 3, 0, 0, respectively, and they are sorted from large to small as row 2, row 1, row 3, and row 4;

[0275] It should also be understood that the elements in the indicator sequence can be determined based on one or more of the above (1) to (9). For example, the rows are first sorted from largest to smallest according to the row weight indicated in (3), and a set R of rows with the largest row weight is determined. The rows in this set R are then determined based on one or more of the above (1) to (2), (4) to (9).

[0276] It should also be understood that for the puncturing principle in the multi-edge LDPC sequence, the specific address splitting principle of each puncturing column is similar to the splitting element in the above-mentioned LDPC storage matrix. For details, please refer to the relevant introduction of the splitting of the parent node by the child node, which will not be repeated here. Among them, combining puncturing and the above-mentioned splitting principle, according to the example in Figure 12, as shown in Figure 12 (2), the first row can prioritize reducing the multiple edges through the splitting principle, while dividing the number of puncturing columns as evenly as possible; or, as shown in Figure 12 (3), the first row prioritizes generating a row containing only one puncturing column, and on this basis further reduces the multiple edges; or, as shown in Figure 12 (4), the fourth row divides the number of puncturing columns as evenly as possible through the above-mentioned splitting principle.

[0277] Next, the segmentation features of the indicator sequence are introduced as follows:

[0278] In one possible implementation, the indication sequence includes: a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the second segment are composed of a first character, the third segment is composed of a positive integer, the fourth segment is composed of a first character and a positive integer, at least one first row belongs to a set of rows corresponding to the first segment, or at least one first row belongs to a set of rows corresponding to the second segment, or at least one first row belongs to the union of the set of rows corresponding to the first segment and the set of rows corresponding to the second segment, or at least one first row belongs to a set of rows corresponding to the third segment.

[0279] As an example, assuming that the first character is 0 and the core row of the core matrix is ​​denoted as M, the indicator sequence θ can be expressed as:

[0280] It can be seen that the indicator sequence is a four-segment piecewise function. Among them, the first segment 1, ..., M is the core segment, corresponding to the core matrix of the LDPC basis matrix (or the core check equation); the second segment 0 1×T is the traditional expansion segment, corresponding to the traditional expansion (or the traditional expansion check equation), the second segment is completely composed of the first character 0; the third segment p1(1,…,M+T), p2(1,…,2M+2T)… is the split expansion segment, corresponding to the split expansion, and is completely composed of row numbers (this segment must contain the row number of the core matrix); the fourth segment γ(0,p x ) is a mixed segmentation of split expansion and traditional expansion. The fourth segment represents interleaving the first character 0 with the previously appeared line number. Wherein, T is the length of the second segment, that is, the number of characters.

[0281] It should be understood that the at least one first row belongs to the set of rows corresponding to the above-mentioned first segment, that is, the core check matrix corresponding to the first segment includes rows with multiple edges, or, the at least one first row belongs to the set of rows corresponding to the second segment, that is, the check matrix corresponding to the second segment includes rows with multiple edges, or, the at least one first row belongs to the set of rows corresponding to the first segment and the rows corresponding to the second segment, or, the at least one first row belongs to the set of rows corresponding to the split extension segment corresponding to the third segment.

[0282] For example, a row with multiple edges and θ(i) being the first character belongs to the first segment, or the second segment, or the first segment and the second segment. For another example, a row with multiple edges and θ(i) being a positive integer belongs to the third segment. This row with multiple edges and θ(i) being a positive integer is located in region A in FIG4 , and the multiplicity of the multiple edges of the row is less than or equal to 2, and the row belongs to the set of rows in the third segment corresponding to θ(i) values ​​of 1 to M.

[0283] As another example, assuming that the first character is 0, the core row of the core matrix is ​​denoted as M, the indicator sequence θ can be expressed as:

[0284] It can be seen that the indicator sequence is a three-segment piecewise function. Among them, the fifth segment 1, ..., M is the core segment, corresponding to the core matrix of the LDPC basis matrix (or the core check equation); the sixth segment p1 (1, ..., M + T), p2 (1, ..., 2M + 2T) ... is the split expansion segment, corresponding to the split expansion, and is completely composed of row numbers (this segment must contain the row number of the core matrix); the seventh segment γ (0, p x ) is a mixed segmentation of split expansion and traditional expansion. The seventh segment represents interleaving the first character 0 with the row number that appeared previously. Wherein, T is the length of the fifth segment, that is, the number of characters.

[0285] It should be understood that the at least one first row belongs to the set of rows corresponding to the above-mentioned fifth segment, that is, the core check matrix corresponding to the fifth segment includes rows with multiple edges, or the at least one first row belongs to the set of rows corresponding to the sixth segment, that is, the core check matrix corresponding to the sixth segment includes rows with multiple edges.

[0286] For example, a row with multiple edges and θ(i) being the first character belongs to the fifth segment. Another example is a row with multiple edges and θ(i) being a positive integer belongs to the sixth segment. This row with multiple edges and θ(i) being a positive integer is located in region A in FIG4 , and the multiplicity of the multiple edges of this row is less than or equal to 2, and it belongs to the set of rows in the sixth segment corresponding to θ(i) values ​​of 1 to M.

[0287] 803 , the transmitting device sends an LDPC codeword sequence to the receiving device, or in other words, the receiving device receives the LDPC codeword sequence from the transmitting device.

[0288] It should be noted that since the LDPC codeword sequence may introduce channel noise signals during the transmission process, the LDPC codeword sequence output or sent by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0289] 804. The receiving end device decodes the LDPC codeword sequence according to the first LDPC base matrix and the indication information.

[0290] The LDCP base matrix used by the receiving device for decoding is the same as the LDCP base matrix used by the transmitting device for encoding, and both are determined based on the LDPC storage matrix and the indicator sequence. The relevant characteristics of the LDPC storage matrix and the indicator sequence can be specifically referred to the description on the transmitting device side and will not be described in detail here.

[0291] 805. The receiving end sends an information bit sequence to the transmitting end.

[0292] The receiving end decodes the LDPC codeword sequence according to the LDPC base matrix to obtain an information bit sequence, and sends the information bit sequence to the transmitting end.

[0293] The present invention is described in detail with reference to FIG8 to FIG12 , and the present invention is described below with reference to FIG13 to FIG15 .

[0294] It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 13 to 15 include hardware structures and / or software modules corresponding to the functions. Those skilled in the art should readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0295] Figures 13 and 14 are schematic diagrams of possible apparatuses provided in embodiments of the present application. These apparatuses can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0296] As shown in FIG13 , the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0297] When apparatus 10 is used to implement the functions of a transmitting device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting device, such as step 803, and processing unit 12 is used to execute the processing steps of the transmitting device, such as steps 801 and 802. When apparatus 10 is used to implement the functions of a receiving device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving device, such as steps 803 and 805, and processing unit 12 is used to execute the processing steps of the receiving device, such as step 804.

[0298] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0299] As shown in FIG14 , apparatus 20 includes a processing circuit 21. Processing circuit 21 is coupled to a memory 23, which is used to store instructions. When apparatus 20 is used to implement the method described above, processing circuit 21 is used to execute the instructions in memory 23 to implement the functions of processing unit 12 described above.

[0300] Optionally, the device 20 further includes a memory 23 .

[0301] Optionally, the apparatus 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It will be appreciated that the transceiver circuit 22 can be a transceiver or an input / output interface. When the apparatus 20 is used to implement the method described above, the processing circuit 21 is used to execute instructions to implement the functions of the processing unit 12, and the transceiver circuit 22 is used to implement the functions of the transceiver unit 11.

[0302] Optionally, the apparatus 20 may be a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be a transceiver.

[0303] Optionally, the apparatus 20 may be a chip applied to a transmitting end device or a receiving end device, and accordingly, the transceiver circuit may be an input / output interface.

[0304] Exemplarily, when apparatus 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above-described method embodiments. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to the transmitting device or the receiving device by other devices; or the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to other devices by the transmitting device or the receiving device.

[0305] 15 is a schematic diagram of a chip system 30 provided in an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0306] The logic circuit 31 may be a processing circuit in the chip system 30. The logic circuit 31 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 30 can implement the methods and functions of the various embodiments of the present application. The input / output interface 32 may be an input / output circuit in the chip system 30, outputting information processed by the chip system 30 or inputting data or signaling information to be processed into the chip system 30 for processing.

[0307] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0308] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiment; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiment.

[0309] The present application also provides a communication device, comprising a processing circuit coupled to a memory, the memory being used to store computer programs or instructions and / or data, and the processing circuit being used to execute the computer programs or instructions stored in the memory, or to read data stored in the memory, to perform the methods described in the above method embodiments. Optionally, there are one or more processing circuits. Optionally, the communication device includes a memory. Optionally, there are one or more memories. Optionally, the memory is integrated with the processing circuit or provided separately.

[0310] The present application also provides a chip including a processing circuit coupled to a memory, the memory being configured to store computer programs or instructions, and the processing circuit being configured to execute the computer programs or instructions stored in the memory to implement the methods performed by the transmitting or receiving device in each of the above method embodiments. The memory may be located within the chip or independently of the chip, external to the chip, without limitation herein.

[0311] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0312] The present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0313] The present application also provides a communication system, which includes at least one of the transmitting end device or the receiving end device in the above embodiments.

[0314] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0315] It is understood that the processing circuit in the embodiments of the present application can be a processor or a circuit in a processor for performing processing operations. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0316] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting device or a receiving device. Of course, the processor and storage medium can also be present in a transmitting device or a receiving device as discrete components.

[0317] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0318] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0319] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Obtaining an information bit sequence; According to an LDPC base matrix, LDPC encoding is performed on the information bit sequence to obtain an LDPC codeword sequence; wherein the LDPC base matrix is ​​determined according to an LDPC storage matrix and an indicator sequence, the indicator sequence includes x elements, one element of the x elements corresponds to a row in the LDPC storage matrix, an i-th element θ(i) of the x elements is related to a θ(i)-th row of the LDPC storage matrix, and the LDPC storage matrix includes at least one first row, and the first row is a row with multiple edges; The LDPC codeword sequence is sent.

2. The method according to claim 1, characterized in that The set consisting of the column numbers of the columns where the non-zero elements included in at least one i-th row in the LDPC storage matrix are located includes at least one of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

3. The method according to claim 2, characterized in that The set consisting of the column numbers of the columns where the non-zero elements included in the i-th row are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

4. The method according to claim 2 or 3, characterized in that: The i-th row is the row corresponding to the smallest number whose element value is θ(i) in the indicator sequence.

5. The method according to claim 2 or 3, characterized in that: The i-th row is a row corresponding to any number whose element value is θ(i) in the indicator sequence.

6. The method according to any one of claims 2 to 5, characterized in that The number of multiple edges included in the i-th row is less than the number of multiple edges included in the θ(i)-th row.

7. The method according to any one of claims 2 to 6, characterized in that The first position in the θ(i)th row includes a multiplicity of heavy edges, and the first position in the i-th row includes a multiplicity of heavy edges. or or or or or a is a positive integer.

8. The method according to any one of claims 1 to 7, characterized in that The i-th element of the x elements in the indicator sequence corresponds to row θ(i) in the LDPC storage matrix, and the j-th element of the x elements corresponds to row θ(j) in the LDPC storage matrix, i<j≤x, i and j are both positive integers, The row θ(i) and the row θ(j) satisfy one or more of the following: The number of multiple edges included in the row θ(i) is greater than or equal to the number of multiple edges included in the row θ(j); The maximum value of the multiplicity of the heavy edges included in the row θ(i) is greater than or equal to the maximum value of the multiplicity of the heavy edges included in the row θ(j); The row weight corresponding to the row θ(i) is greater than or equal to the row weight corresponding to the row θ(j); The sum of the multiplicities of the heavy edges included in the row θ(i) is greater than or equal to the sum of the multiplicities of the heavy edges included in the row θ(j); The average number of multiple edges corresponding to the row θ(i) is greater than or equal to the average number of multiple edges corresponding to the row θ(j); The number of puncture column sets associated with the row θ(i) is greater than or equal to the number of puncture column sets associated with the row θ(j); The number of multiple edges of the puncture column set associated with the row θ(i) is greater than or equal to the number of multiple edges of the puncture column set associated with the row θ(j); The sum of the multiplicities of the heavy edges in the set of puncturing columns associated with the row θ(i) is greater than or equal to the sum of the multiplicities of the heavy edges in the set of puncturing columns associated with the row θ(j); The maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(i) is greater than or equal to the maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(j).

9. The method according to any one of claims 1 to 8, characterized in that The at least one first row is located in a first matrix area in the LDPC storage matrix, the maximum row number corresponding to the rows included in the first matrix area is less than or equal to a first threshold, and θ(i) is related to the position of the at least one first row in the first matrix area.

10. The method according to claim 9, characterized in that The first matrix area is composed of the 1st to qth rows and the 1st to kth columns of the LDPC storage matrix. The first matrix area is a matrix with q rows and k columns, and q and k are both positive integers greater than or equal to 2.

11. The method according to claim 10, characterized in that The q is 4, the k is 22, and the code rate of the first matrix area is greater than or equal to 11 / 12.

12. The method according to any one of claims 9 to 11, characterized in that The at least one first row belongs to the row corresponding to the first character where θ(i), and the row number of the row corresponding to the first character is the position of the first character in the indication sequence.

13. The method according to any one of claims 9 to 11, characterized in that The at least one first row belongs to the row corresponding to the positive integer θ(i), and the row number of the row corresponding to the positive integer θ(i) is i.

14. The method according to any one of claims 1 to 13, characterized in that The multiplicity of the heavy edges included in each of the at least one first row is 2, or the multiplicity of the heavy edges included in each of the at least one first row includes 2 and 3.

15. The method according to any one of claims 1 to 14, characterized in that The difference between the number of heavy edges included in each row of the at least one first row is less than or equal to 1, or the difference between the sum of the multiplicity of heavy edges included in each row of the at least one first row is less than or equal to 1, or the maximum values ​​of the multiplicity of heavy edges included in each row of the at least one first row are the same.

16. The method according to any one of claims 1 to 15, characterized in that The at least one first row includes 1 or 2 first rows.

17. The method according to any one of claims 1 to 16, characterized in that The indication sequence includes: a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the second segment are composed of a first character, the third segment is composed of a positive integer, and the fourth segment is composed of the first character and a positive integer. The at least one first row belongs to the set of rows corresponding to the first segment, or the at least one first row belongs to the set of rows corresponding to the second segment, or the at least one first row belongs to the union of the set of rows corresponding to the first segment and the set of rows corresponding to the second segment, or the at least one first row belongs to the set of rows corresponding to the third segment.

18. The method according to claim 17, characterized in that The at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the third segment, where M is the number of rows corresponding to the core check matrix.

19. The method according to any one of claims 1 to 16, characterized in that The indication sequence includes: a fifth segment, a sixth segment and a seventh segment, wherein the fifth segment is composed of the first character, the sixth segment is composed of a positive integer, and the seventh segment is composed of the first character and a positive integer. The at least one first row belongs to a set of rows corresponding to the fifth segment, or the at least one first row belongs to a set of rows corresponding to the sixth segment.

20. The method according to claim 19, characterized in that The at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the sixth segment, where M is the number of rows corresponding to the core check matrix.

21. A communication method based on low-density parity check (LDPC) code, characterized in that: The method comprises: Receive an LDPC codeword sequence; According to an LDPC base matrix, LDPC decoding is performed on the LDPC codeword sequence to obtain an information bit sequence; wherein the LDPC base matrix is ​​determined according to an LDPC storage matrix and an indicator sequence, the indicator sequence includes x elements, one element of the x elements corresponds to a row in the LDPC storage matrix, an i-th element θ(i) of the x elements is related to a θ(i)-th row of the LDPC storage matrix, and the LDPC storage matrix includes at least one first row, and the first row is a row with multiple edges; The information bit sequence is sent.

22. The method according to claim 21, characterized in that The set consisting of the column numbers of the columns where the non-zero elements included in at least one i-th row in the LDPC storage matrix are located includes at least one of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

23. The method according to claim 22, characterized in that The set consisting of the column numbers of the columns where the non-zero elements included in the i-th row are located includes the set consisting of the column numbers of the columns where the multiple edges included in the θ(i)-th row are located.

24. The method according to claim 22 or 23, characterized in that The i-th row is the row corresponding to the smallest number whose element value is θ(i) in the indicator sequence.

25. The method according to claim 22 or 23, characterized in that The i-th row is a row corresponding to any number whose element value is θ(i) in the indicator sequence.

26. The method according to any one of claims 22 to 25, characterized in that The number of multiple edges included in the i-th row is less than the number of multiple edges included in the θ(i)-th row.

27. The method according to any one of claims 22 to 26, characterized in that The first position in the θ(i)th row includes a multiplicity of heavy edges, and the first position in the i-th row includes a multiplicity of heavy edges. or or or or or a is a positive integer.

28. The method according to any one of claims 21 to 27, characterized in that The i-th element of the x elements in the indicator sequence corresponds to row θ(i) in the LDPC storage matrix, and the j-th element of the x elements corresponds to row θ(j) in the LDPC storage matrix, i<j≤x, i and j are both positive integers, The row θ(i) and the row θ(j) satisfy one or more of the following: The number of multiple edges included in the row θ(i) is greater than or equal to the number of multiple edges included in the row θ(j); The maximum value of the multiplicity of the heavy edges included in the row θ(i) is greater than or equal to the maximum value of the multiplicity of the heavy edges included in the row θ(j); The row weight corresponding to the row θ(i) is greater than or equal to the row weight corresponding to the row θ(j); The sum of the multiplicities of the heavy edges included in the row θ(i) is greater than or equal to the sum of the multiplicities of the heavy edges included in the row θ(j); The average number of multiple edges corresponding to the row θ(i) is greater than or equal to the average number of multiple edges corresponding to the row θ(j); The number of puncture column sets associated with the row θ(i) is greater than or equal to the number of puncture column sets associated with the row θ(j); The number of multiple edges of the puncture column set associated with the row θ(i) is greater than or equal to the number of multiple edges of the puncture column set associated with the row θ(j); The sum of the multiplicities of the heavy edges in the set of puncturing columns associated with the row θ(i) is greater than or equal to the sum of the multiplicities of the heavy edges in the set of puncturing columns associated with the row θ(j); The maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(i) is greater than or equal to the maximum value of the multiplicity of heavy edges in the set of puncturing columns associated with the row θ(j).

29. The method according to any one of claims 21 to 28, characterized in that The at least one first row is located in a first matrix area in the LDPC storage matrix, the maximum row number corresponding to the rows included in the first matrix area is less than or equal to a first threshold, and θ(i) is related to the position of the at least one first row in the first matrix area.

30. The method according to claim 29, characterized in that The first matrix area is composed of the 1st to qth rows and the 1st to kth columns of the LDPC storage matrix. The first matrix area is a matrix with q rows and k columns, and q and k are both positive integers greater than or equal to 2.

31. The method according to claim 30, characterized in that The q is 4, the k is 22, and the code rate of the first matrix area is greater than or equal to 11 / 12.

32. The method according to any one of claims 29 to 31, characterized in that The at least one first row belongs to the row corresponding to the first character where θ(i), and the row number of the row corresponding to the first character is the position of the first character in the indication sequence.

33. The method according to any one of claims 29 to 31, characterized in that The at least one first row belongs to the row corresponding to the positive integer θ(i), and the row number of the row corresponding to the positive integer θ(i) is i.

34. The method according to any one of claims 22 to 33, characterized in that The multiplicity of the heavy edges included in each of the at least one first row is 2, or the multiplicity of the heavy edges included in each of the at least one first row includes 2 and 3.

35. The method according to any one of claims 22 to 34, characterized in that The difference between the number of heavy edges included in each row of the at least one first row is less than or equal to 1, or the difference between the sum of the multiplicity of heavy edges included in each row of the at least one first row is less than or equal to 1, or the maximum values ​​of the multiplicity of heavy edges included in each row of the at least one first row are the same.

36. The method according to any one of claims 22 to 35, characterized in that The at least one first row includes 1 or 2 first rows.

37. The method according to any one of claims 22 to 36, characterized in that The indication sequence includes: a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the second segment are composed of a first character, the third segment is composed of a positive integer, and the fourth segment is composed of the first character and a positive integer. The at least one first row belongs to the set of rows corresponding to the first segment, or the at least one first row belongs to the set of rows corresponding to the second segment, or the at least one first row belongs to the union of the set of rows corresponding to the first segment and the set of rows corresponding to the second segment, or the at least one first row belongs to the set of rows corresponding to the third segment.

38. The method according to claim 37, characterized in that The at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the third segment, where M is the number of rows corresponding to the core check matrix.

39. The method according to any one of claims 22 to 36, characterized in that The indication sequence includes: a fifth segment, a sixth segment and a seventh segment, wherein the fifth segment is composed of the first character, the sixth segment is composed of a positive integer, and the seventh segment is composed of the first character and a positive integer. The at least one first row belongs to a set of rows corresponding to the fifth segment, or the at least one first row belongs to a set of rows corresponding to the sixth segment.

40. The method according to claim 39, characterized in that The at least one first row belongs to a set of rows corresponding to values ​​of θ(i) of 1 to M in the sixth segment, where M is the number of rows corresponding to the core check matrix.

41. A communication device, characterized in that: The method comprises a module or a unit for executing the method according to any one of claims 1 to 40.

42. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 40 through logic circuits or executing code instructions.

43. The communication device according to claim 42, characterized in that The communication device is a chip or a chip system.

44. A computer-readable storage medium, characterized in that The storage medium stores a computer program or an instruction, and when the computer program or the instruction is executed by the communication device, the method according to any one of claims 1 to 40 is implemented.

45. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 40.

46. ​​A communication system, characterized in that: include: A sending end device for executing the method according to any one of claims 1 to 20; A receiving device for executing the method as claimed in any one of claims 21 to 40.

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