Pixel circuit and display device

Abstract

The present disclosure provides a pixel circuit and a display device. The pixel circuit comprises a driving circuit, a switch control circuit, a light-emitting element, a driving control circuit, and a first reset circuit; the driving circuit is electrically connected to the light-emitting element or a first voltage end by means of the switch control circuit; the switch control circuit is configured to control, under the control of the potential of a switch control end, the driving circuit to be connected to the light-emitting element or the first voltage end; and the driving control circuit writes, under the control of a first control signal, a light-emitting time control data voltage into the switch control end; and the first reset circuit writes, under the control of a set control signal, a set voltage into a second node, and a first electrode of the light-emitting element or a second electrode of the light-emitting element. According to the present disclosure, the pixel circuit is controlled on the basis of a driving current and a light-emitting duration, thereby improving the display effect of the light-emitting element.

Description

Pixel circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] Micro LEDs (micro light-emitting diodes) and Mini LEDs (mini light-emitting diodes) are expected to be widely used in future display applications due to their high brightness and reliability. As self-luminous devices, their luminous efficiency, brightness, and color coordinates vary with current density at low current densities. Therefore, to achieve grayscale display, Micro LEDs and Mini LEDs must operate at high current densities. Traditional current-controlled drive circuits cannot meet these grayscale display requirements.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a switch control circuit, a light-emitting element, a driving control circuit, and a first reset circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, and is used to generate a driving current for driving the light-emitting element under the control of the potential of the first node;

[0006] The driving circuit is electrically connected to the light-emitting element or the first voltage terminal through the switch control circuit, and the switch control circuit is electrically connected to the switch control terminal. The switch control circuit is used to control the connection between the driving circuit and the light-emitting element or the first voltage terminal under the control of the potential of the switch control terminal;

[0007] The driving control circuit is electrically connected to the first control terminal and the first data line respectively, and is used to write the light-emitting time control data voltage provided by the first data line into the switch control terminal under the control of the first control signal provided by the first control terminal;

[0008] The first reset circuit is used to write a set voltage into the second node, the first electrode of the light-emitting element, or the second electrode of the light-emitting element under the control of a set control signal provided by the set control terminal.

[0009] Optionally, the light-emitting element is an inorganic light-emitting diode, the aspect ratio of the transistor included in the switch control circuit is greater than 1, and the aspect ratio of the transistor included in the drive circuit is greater than 0.5.

[0010] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a storage circuit;

[0011] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is used to store electrical energy;

[0012] The first reset circuit is configured to write a set voltage into the second node under the control of the set control signal.

[0013] Optionally, the driving circuit is electrically connected to the first electrode of the light-emitting element through the switch control circuit, and the switch control circuit is used to control the connection between the driving circuit and the first electrode of the light-emitting element under the control of the potential of the switch control terminal; the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0014] The first reset circuit is used to write the set voltage into the first electrode of the light emitting element under the control of the set control signal during a reset period between the period for writing the display data voltage and the period for writing the luminous time control data voltage.

[0015] Optionally, the first electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0016] The driving circuit is electrically connected to the second electrode of the light-emitting element through the switch control circuit, and the switch control circuit is used to control the connection between the driving circuit and the first voltage terminal under the control of the potential of the switch control terminal;

[0017] The first reset circuit is used to write the set voltage into the second electrode of the light emitting element under the control of the set control signal during a reset period between the period for writing the display data voltage and the period for writing the luminous time control data voltage.

[0018] Optionally, the pixel circuit further includes a storage circuit;

[0019] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the first electrode of the light emitting element, and the energy storage circuit is used to store electrical energy;

[0020] The first end of the switch control circuit is electrically connected to the first voltage end, the second end of the switch control circuit is electrically connected to the first end of the drive circuit, the second end of the drive circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second voltage end; the switch control circuit is used to control the communication between the first voltage end and the first end of the drive circuit under the control of the potential of the switch control end; or the first end of the drive circuit is electrically connected to the first voltage end; the first end of the switch control circuit is electrically connected to the second end of the drive circuit, the second end of the switch control circuit is electrically connected to the first electrode of the light-emitting element, and the second end of the light-emitting element is electrically connected to the second voltage end; the switch control circuit is used to control the communication between the second end of the drive circuit and the first electrode of the light-emitting element under the control of the potential of the switch control end;

[0021] The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scan terminal and a first selection control terminal;

[0022] The compensation circuit is electrically connected to the scanning terminal, the first terminal of the light-emitting element, and the control node, respectively, and is used to control the communication between the first terminal of the light-emitting element and the control node under the control of the scanning signal provided by the scanning terminal; or the compensation circuit is electrically connected to the scanning terminal, the second terminal of the driving circuit, and the control node, respectively, and is used to control the communication between the second terminal of the driving circuit and the control node under the control of the scanning signal;

[0023] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is used to provide the set voltage written by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal.

[0024] Optionally, the pixel circuit further includes a storage circuit;

[0025] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second electrode of the light emitting element, and the energy storage circuit is used to store electrical energy;

[0026] The first pole of the light-emitting element is electrically connected to the first voltage terminal, the first terminal of the switch control circuit is electrically connected to the second pole of the light-emitting element, the second terminal of the switch control circuit is electrically connected to the first terminal of the drive circuit, and the second terminal of the drive circuit is electrically connected to the second voltage terminal; the switch control circuit is used to control the second pole of the light-emitting element to be connected to the first terminal of the drive circuit under the control of the potential of the switch control terminal; or the first pole of the light-emitting element is electrically connected to the first voltage terminal, and the second pole of the light-emitting element is electrically connected to the first terminal of the drive circuit; the first terminal of the switch control circuit is electrically connected to the second terminal of the drive circuit, and the second terminal of the switch control circuit is electrically connected to the second voltage terminal; the switch control circuit is used to control the second terminal of the drive circuit to be connected to the first pole of the light-emitting element under the control of the potential of the switch control terminal;

[0027] The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scan terminal and a first selection control terminal;

[0028] The compensation circuit is electrically connected to the scanning terminal, the second terminal of the light-emitting element, and the control node, respectively, and is used to control the second terminal of the light-emitting element to be connected to the control node under the control of the scanning signal; or the compensation circuit is electrically connected to the scanning terminal, the first terminal of the driving circuit, and the control node, respectively, and is used to control the first terminal of the driving circuit to be connected to the control node under the control of the scanning signal;

[0029] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is used to write the set voltage provided by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal.

[0030] Optionally, the drive control circuit is also electrically connected to the second control terminal and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the switch control terminal under the control of the second control signal provided by the second control terminal, and to maintain the potential of the switch control terminal.

[0031] Optionally, the first terminal of the driving circuit is electrically connected to the first voltage terminal;

[0032] The switch control circuit is electrically connected to the second terminal of the drive circuit and the first electrode of the light-emitting element respectively, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0033] The switch control circuit is used to control the connection between the second end of the driving circuit and the first end of the light emitting element under the control of the potential of the switch control end.

[0034] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit;

[0035] The switch control circuit is electrically connected to the first electrode of the light emitting element through the light emitting control circuit;

[0036] The light emitting control circuit is also electrically connected to the light emitting control terminal, and is used to control the connection between the switch control circuit and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal;

[0037] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end.

[0038] Optionally, the first electrode of the light-emitting element is electrically connected to the first voltage terminal, the switch control circuit is electrically connected to the second electrode of the light-emitting element and the first terminal of the drive circuit respectively, and the second terminal of the drive circuit is electrically connected to the second voltage terminal;

[0039] The switch control circuit is used to control the connection between the second electrode of the light-emitting element and the first end of the driving circuit under the control of the potential of the switch control end.

[0040] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit;

[0041] The switch control circuit is electrically connected to the first end of the drive circuit through the light emitting control circuit;

[0042] The light emitting control circuit is also electrically connected to the light emitting control terminal, and is used to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[0043] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the first end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal provided by the scanning end.

[0044] Optionally, the light-emitting element is an inorganic light-emitting diode, the aspect ratio of the transistor included in the switch control circuit is greater than 1, the aspect ratio of the transistor included in the light-emitting control circuit is greater than 1, and the aspect ratio of the transistor included in the drive circuit is greater than 0.5.

[0045] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit and a first control circuit;

[0046] The control terminal of the driving circuit is electrically connected to the first node;

[0047] The display data writing circuit is electrically connected to the scan terminal, the second data line and the second node respectively, and is used to write the display data voltage provided by the second data line into the second node under the control of the scan signal provided by the scan terminal;

[0048] The first control circuit is electrically connected to the light-emitting control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0049] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0050] The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0051] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third reset circuit;

[0052] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset period set between the time period for writing the display data voltage and the time period for writing the light-emitting time control data voltage.

[0053] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third reset circuit;

[0054] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the second electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset period set between the time period for writing the display data voltage and the time period for writing the light-emitting time control data voltage.

[0055] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing circuit;

[0056] The first end of the energy storage circuit is electrically connected to the control end of the drive circuit, the second end of the energy storage circuit is electrically connected to the first voltage end, and the energy storage circuit is used to store electrical energy;

[0057] The first end of the driving circuit is electrically connected to the first voltage end through the first light emitting control circuit;

[0058] The second end of the driving circuit is electrically connected to the switch control circuit through the second light emitting control circuit;

[0059] The first light emitting control circuit is further electrically connected to the light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[0060] The second light emitting control circuit is also electrically connected to the light emitting control terminal, and is used to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal;

[0061] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end;

[0062] The display data writing circuit is electrically connected to the scanning terminal, the second data line, and the first terminal of the driving circuit, respectively, and is configured to write the display data voltage provided by the second data line into the first terminal of the driving circuit under the control of the scanning signal. Optionally, the pixel circuit further includes a tank circuit, a first light-emitting control circuit, a second light-emitting control circuit, a compensation control circuit, and a display data writing circuit;

[0063] A first end of the energy storage circuit is electrically connected to the control end of the drive circuit, a second end of the energy storage circuit is electrically connected to the second voltage end, and the energy storage circuit is used to store electrical energy;

[0064] The first light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit, and the first terminal of the driving circuit, respectively, and is configured to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of a light emitting control signal provided by the light emitting control terminal;

[0065] The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit, and the second voltage terminal respectively, and is used to control the second terminal of the driving circuit to be electrically connected to the second voltage terminal under the control of the light emitting control signal;

[0066] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the first end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal provided by the scanning end;

[0067] The display data writing circuit is electrically connected to the scanning end, the second data line and the second end of the driving circuit respectively, and is used to write the display data voltage provided by the second data line into the second end of the driving circuit under the control of the scanning signal.

[0068] Optionally, the light-emitting element is an inorganic light-emitting diode, the aspect ratio of the transistor included in the switching control circuit is greater than 1, the aspect ratio of the transistor included in the first light-emitting control circuit is greater than 1, the aspect ratio of the transistor included in the second light-emitting control circuit is greater than 1, and the aspect ratio of the transistor included in the driving circuit is greater than 0.5.

[0069] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0070] The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0071] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing circuit;

[0072] The display data writing circuit is electrically connected to the scanning end, the second data line and the control end of the driving circuit respectively, and is used to write the display data voltage provided by the second data line into the control end of the driving circuit under the control of the scanning signal provided by the scanning end.

[0073] Optionally, the switch circuit is further connected to a second selection control terminal and a compensation terminal, and is configured to control the connection between the control node and the compensation terminal under the control of a second selection control signal provided by the second selection control terminal.

[0074] Optionally, the energy storage circuit includes a storage capacitor; the light emitting element is an inorganic light emitting diode;

[0075] The capacitance of the storage capacitor is greater than three times the gate-source capacitance of the transistor in the driving circuit.

[0076] Optionally, the drive control circuit includes a first transistor, a second transistor and a first capacitor;

[0077] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the switch control terminal;

[0078] The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the second initial voltage terminal, and the second electrode of the second transistor is electrically connected to the switch control terminal;

[0079] A first end of the first capacitor is electrically connected to the switch control end, and a second end of the first capacitor is electrically connected to the DC voltage end.

[0080] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor;

[0081] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first voltage terminal, and the second electrode of the driving transistor is electrically connected to the third node;

[0082] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor;

[0083] The gate of the third transistor is electrically connected to the switch control terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0084] A gate of the fifth transistor is electrically connected to the scan end, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third node.

[0085] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor;

[0086] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0087] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor; the first electrode of the driving transistor is electrically connected to the third node;

[0088] The gate of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second voltage terminal;

[0089] A gate of the fifth transistor is electrically connected to the scan end, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third node.

[0090] Optionally, the display data writing circuit includes a sixth transistor, and the first control circuit includes a seventh transistor;

[0091] The gate of the sixth transistor is electrically connected to the scanning end, the first electrode of the sixth transistor is electrically connected to the second data line, and the second electrode of the sixth transistor is electrically connected to the second node;

[0092] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the reference voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node.

[0093] Optionally, the first reset circuit includes an eighth transistor;

[0094] The gate of the eighth transistor is electrically connected to the set control terminal, the first electrode of the eighth transistor is electrically connected to the set voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node, the first electrode of the light-emitting element, or the second electrode of the light-emitting element;

[0095] The set voltage terminal is used to provide the set voltage.

[0096] Optionally, the second reset circuit includes a ninth transistor;

[0097] The gate of the ninth transistor is electrically connected to the first reset control terminal, the first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node.

[0098] Optionally, the third reset circuit includes a tenth transistor;

[0099] The gate of the tenth transistor is electrically connected to the second reset control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0100] Optionally, the third reset circuit includes a tenth transistor;

[0101] The gate of the tenth transistor is electrically connected to the second reset control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element.

[0102] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes an eleventh transistor; the second light-emitting control circuit includes a twelfth transistor; the switch control circuit includes a third transistor; the compensation control circuit includes a fifth transistor; and the display data writing circuit includes a sixth transistor;

[0103] A first terminal of the storage capacitor is electrically connected to the gate of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal;

[0104] The gate of the eleventh transistor is electrically connected to the light emitting control terminal, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor;

[0105] The gate of the twelfth transistor is electrically connected to the light emitting control terminal, the first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the third transistor;

[0106] The gate of the third transistor is electrically connected to the switch control terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0107] The gate of the fifth transistor is electrically connected to the scanning end, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor;

[0108] A gate of the sixth transistor is electrically connected to the scanning end, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor.

[0109] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes an eleventh transistor; the second light-emitting control circuit includes a twelfth transistor; the switch control circuit includes a third transistor; the compensation control circuit includes a fifth transistor; and the display data writing circuit includes a sixth transistor;

[0110] A first terminal of the storage capacitor is electrically connected to the gate of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second voltage terminal;

[0111] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the third transistor is electrically connected to the first electrode of the eleventh transistor;

[0112] The gate of the eleventh transistor is electrically connected to the light emitting control terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor;

[0113] The gate of the twelfth transistor is electrically connected to the light emitting control terminal, the first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal;

[0114] The gate of the fifth transistor is electrically connected to the scanning end, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor;

[0115] A gate of the sixth transistor is electrically connected to the scanning end, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor.

[0116] Optionally, the second reset circuit includes a ninth transistor;

[0117] The gate of the ninth transistor is electrically connected to the first reset control terminal, the first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node.

[0118] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor;

[0119] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;

[0120] The second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

[0121] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor;

[0122] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0123] The first electrode of the driving transistor is electrically connected to the first voltage terminal.

[0124] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor;

[0125] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the light-emitting element, the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0126] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor; the second electrode of the light-emitting element is electrically connected to the first electrode of the drive transistor;

[0127] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element.

[0128] Optionally, the display data writing circuit includes a sixth transistor;

[0129] A gate of the sixth transistor is electrically connected to the scan end, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the control end of the driving circuit.

[0130] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch;

[0131] A first end of the storage capacitor is electrically connected to the control end of the drive circuit, and a second end of the storage capacitor is electrically connected to the second end of the drive circuit;

[0132] The gate of the thirteenth transistor is electrically connected to the scanning terminal, the first electrode of the thirteenth transistor is electrically connected to the first electrode of the light-emitting element or the second terminal of the driving circuit, and the second electrode of the thirteenth transistor is electrically connected to the control node;

[0133] The control end of the first switch is electrically connected to the first selection control end, the first end of the first switch is electrically connected to the control node, and the second end of the first switch is electrically connected to the reference voltage end.

[0134] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch;

[0135] The first end of the storage capacitor is electrically connected to the control end of the drive circuit, and the second end of the storage capacitor is electrically connected to the first end of the drive circuit;

[0136] The gate of the thirteenth transistor is electrically connected to the scanning end, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the light-emitting element or the first end of the driving circuit, and the second electrode of the thirteenth transistor is electrically connected to the control node;

[0137] The control end of the first switch is electrically connected to the first selection control end, the first end of the first switch is electrically connected to the control node, and the second end of the first switch is electrically connected to the reference voltage end.

[0138] Optionally, the switching circuit further includes a second switch;

[0139] The control end of the second switch is electrically connected to the second selection control end, the first end of the second switch is electrically connected to the control node, and the second end of the second switch is electrically connected to the compensation end.

[0140] Optionally, the light-emitting element is an inorganic light-emitting diode.

[0141] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0142] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0143] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0144] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0145] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0146] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0147] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0148] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0149] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0150] FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0151] FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0152] FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0153] FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0154] FIG13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0155] FIG14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0156] FIG15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0157] FIG16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0158] FIG17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0159] FIG18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0160] FIG19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0161] FIG20 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0162] FIG21 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0163] FIG22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0164] FIG23 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0165] FIG24 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0166] FIG25 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0167] FIG26 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0168] FIG27 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0169] FIG28 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0170] FIG29 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0171] FIG30 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0172] FIG31 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0173] FIG32 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG31 ;

[0174] FIG33A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG31 during a first reset time period S11;

[0175] FIG33B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG31 during a first writing period S12;

[0176] FIG33C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG31 during a first light-emitting period S13;

[0177] FIG33D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG31 during a second reset period S21;

[0178] FIG33E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG31 during a second writing period S22;

[0179] FIG34A is a schematic diagram showing simulation results of high grayscale display of at least one embodiment of the pixel circuit shown in FIG31 ;

[0180] FIG34B is a schematic diagram showing simulation results of low grayscale display of at least one embodiment of the pixel circuit shown in FIG31 ;

[0181] FIG35 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG31 ;

[0182] FIG36 is a schematic diagram of the light emission timing of at least one embodiment of the pixel circuit shown in FIG31 during high grayscale light emission and low grayscale light emission;

[0183] FIG37 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0184] FIG38 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG37 ;

[0185] FIG39 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0186] FIG40 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG39 ;

[0187] FIG41A is a schematic diagram illustrating an operating state of at least one embodiment of the pixel circuit shown in FIG39 during a first reset period S11;

[0188] FIG41B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG39 during a first writing period S12;

[0189] FIG41C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG39 during a first light-emitting period S13;

[0190] FIG41D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG39 during a second writing period S22;

[0191] FIG41E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG39 during a second light-emitting period S23;

[0192] FIG42A is a schematic diagram showing simulation results of high grayscale display of at least one embodiment of the pixel circuit shown in FIG39 ;

[0193] FIG42B is a schematic diagram showing simulation results of low grayscale display of at least one embodiment of the pixel circuit shown in FIG39 ;

[0194] FIG43A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0195] FIG43B is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG43A of the present disclosure;

[0196] FIG43C is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG43A of the present disclosure;

[0197] FIG44 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0198] FIG45A is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG44 ;

[0199] FIG45B is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG44 ;

[0200] FIG46 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0201] FIG47A is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG46 of the present disclosure;

[0202] FIG47B is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG46 of the present disclosure;

[0203] FIG48A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG46 during a first reset period S11;

[0204] FIG48B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG46 during a first writing period S12;

[0205] FIG48C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG46 during the first light-emitting period S13;

[0206] FIG48D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG46 during a second writing period S22;

[0207] FIG48E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG46 during a second light-emitting period S23;

[0208] FIG49 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0209] FIG50A is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG49 ;

[0210] FIG50B is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG49 ;

[0211] FIG51 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0212] FIG52 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG51 ;

[0213] FIG53A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a first writing period S12 and a first light emitting period S22;

[0214] FIG53B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a second writing period S21 and a second light-emitting period S22;

[0215] FIG53C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a reset period SC1;

[0216] FIG53D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a compensation period SC2;

[0217] FIG53E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during an extraction period SC3;

[0218] FIG54A is a schematic diagram showing simulation results of high grayscale display during the display phase of at least one embodiment of the pixel circuit shown in FIG51 ;

[0219] FIG54B is a schematic diagram showing simulation results of low grayscale display during the display phase of at least one embodiment of the pixel circuit shown in FIG51 ;

[0220] FIG55 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0221] FIG56 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG55 ;

[0222] FIG57 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0223] FIG58 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG57 ;

[0224] FIG59 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0225] FIG60 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0226] FIG61 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0227] FIG62 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0228] FIG63 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0229] FIG64 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0230] FIG65 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0231] FIG66 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG65 ;

[0232] FIG67A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG65 during a first reset time period;

[0233] FIG67B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG65 during a first writing time period;

[0234] FIG67C is a schematic diagram illustrating an operating state of at least one embodiment of the pixel circuit shown in FIG65 during a first light-emitting period;

[0235] FIG67D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG65 during a second reset time period;

[0236] FIG67E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG65 during a second writing period;

[0237] FIG67F is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG65 during a second light-emitting period;

[0238] FIG68A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG66 when performing high grayscale display;

[0239] FIG68B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG66 when performing low grayscale display;

[0240] FIG69 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0241] FIG70 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG69 ;

[0242] FIG71 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0243] FIG72 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG71 ;

[0244] FIG73A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG71 when performing high grayscale display;

[0245] FIG73B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG71 when performing low grayscale display;

[0246] FIG74 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0247] FIG75 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG74 ;

[0248] FIG76A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG74 during a first reset time period;

[0249] FIG76B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG74 during a first writing time period;

[0250] FIG76C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG74 during a first light-emitting period;

[0251] FIG76D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG74 during a second reset time period;

[0252] FIG76E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG74 during a second writing time period;

[0253] FIG76F is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG74 during a second light-emitting period;

[0254] FIG77A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG74 when performing high grayscale display;

[0255] FIG77B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG74 when performing low grayscale display;

[0256] FIG78 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0257] FIG79 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG78 ;

[0258] FIG80 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0259] FIG81 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG80 ;

[0260] FIG82 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0261] FIG83 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG82 ;

[0262] FIG84A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG83 when performing high grayscale display;

[0263] FIG84B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG83 when performing low grayscale display;

[0264] FIG85 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0265] FIG86 is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG85 ;

[0266] FIG87 is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG85 ;

[0267] FIG88 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0268] FIG89 is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG88 ;

[0269] FIG90 is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG88 ;

[0270] FIG91A is a schematic diagram illustrating an operating state of at least one embodiment of the pixel circuit shown in FIG88 during a first reset period S11;

[0271] FIG91B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG88 during a first writing period S12;

[0272] FIG91C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG88 during a first light-emitting period S13;

[0273] FIG91D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG88 during a second writing period S22;

[0274] FIG91E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG88 during a second light-emitting period S23;

[0275] FIG92 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0276] FIG93 is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG92 ;

[0277] FIG94 is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG92 ;

[0278] FIG95 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0279] FIG96 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0280] FIG97 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0281] FIG98 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0282] FIG99 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0283] FIG100 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0284] FIG101 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0285] FIG102 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0286] FIG103 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0287] FIG104 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0288] FIG105 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0289] FIG106 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0290] FIG107 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG106 ;

[0291] FIG108A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG106 during a first reset time period;

[0292] FIG108B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG106 during a first writing time period;

[0293] FIG108C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG106 during a first light-emitting period;

[0294] FIG108D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG106 during a second reset time period;

[0295] FIG108E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG106 during a second writing period;

[0296] FIG108F is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG106 during a second light-emitting period;

[0297] FIG109A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG106 of the present disclosure during operation at low grayscale display;

[0298] FIG109B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG106 of the present disclosure during operation and high grayscale display;

[0299] FIG110 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG106 ;

[0300] FIG111 is a schematic diagram showing the light emission timing of at least one embodiment of the pixel circuit shown in FIG106 during high grayscale light emission and low grayscale light emission;

[0301] FIG112 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0302] FIG113 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG112 ;

[0303] FIG114 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0304] FIG115A is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG114 ;

[0305] FIG115B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG114 when performing high grayscale display;

[0306] FIG115C is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG114 when performing high grayscale display;

[0307] FIG116 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0308] FIG117 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG116 ;

[0309] FIG118 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0310] FIG119 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG118 ;

[0311] FIG120A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG118 during a first reset time period;

[0312] FIG120B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG118 during a first writing time period;

[0313] FIG120C is a schematic diagram illustrating an operating state of at least one embodiment of the pixel circuit shown in FIG118 during a first light-emitting period;

[0314] FIG120D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG118 during a second writing time period;

[0315] FIG120E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG118 during a second light-emitting period;

[0316] FIG121A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG118 when performing high grayscale display;

[0317] FIG121B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG118 when performing low grayscale display;

[0318] FIG122 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0319] FIG123 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG122 ;

[0320] FIG124A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG122 during a first reset period S11;

[0321] FIG124B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG122 during a first writing period S12;

[0322] FIG124C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG122 during a first light-emitting period S13;

[0323] FIG124D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG122 during a second writing period S22;

[0324] FIG124E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG122 during a second light-emitting period S23;

[0325] FIG125A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG122 when performing high grayscale display;

[0326] FIG125B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG122 when performing low grayscale display;

[0327] FIG126 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0328] FIG127 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG126 ;

[0329] FIG128 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0330] FIG129 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0331] FIG130 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0332] FIG131 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0333] FIG132 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0334] FIG133 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0335] FIG134 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0336] FIG135 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0337] FIG136 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0338] FIG137 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0339] FIG138 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0340] FIG139 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0341] FIG140 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0342] FIG141 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0343] FIG142 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0344] FIG143 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0345] FIG144 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0346] FIG145 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0347] FIG146 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0348] FIG147 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0349] FIG148 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0350] FIG149 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0351] FIG150 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0352] FIG151 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0353] FIG152 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG151 ;

[0354] FIG153A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a first reset period;

[0355] FIG153B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a first compensation period;

[0356] FIG153C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a first writing time period;

[0357] FIG153D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a second reset period;

[0358] FIG153E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a first light-emitting period;

[0359] FIG153F is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a third reset period;

[0360] FIG153G is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a second compensation period;

[0361] FIG153H is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a second writing period;

[0362] FIG153I is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a fourth reset period;

[0363] FIG153J is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG151 during a second light-emitting period;

[0364] FIG154A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG151 of the present disclosure when performing high grayscale display;

[0365] FIG154B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG151 of the present disclosure when performing low grayscale display;

[0366] FIG155 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0367] FIG156 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG155 ;

[0368] FIG157 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0369] FIG158 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG157 ;

[0370] FIG159 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0371] FIG160 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG159 ;

[0372] FIG161 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0373] FIG162 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG161 ;

[0374] FIG163 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0375] FIG164 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG163 ;

[0376] FIG165 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0377] FIG166 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG165 ;

[0378] FIG167 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG165 ;

[0379] FIG168 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0380] FIG169 is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG168 ;

[0381] FIG170 is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG168;

[0382] FIG171 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0383] FIG172 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG171 ;

[0384] FIG173A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a first reset period;

[0385] FIG173B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a first compensation period;

[0386] FIG173C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a first writing time period;

[0387] FIG173D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a first light-emitting period;

[0388] FIG173E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a second reset period;

[0389] FIG173F is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a second compensation period;

[0390] FIG173G is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a second writing time period;

[0391] FIG173H is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG171 during a second light-emitting period;

[0392] FIG174A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG171 when performing high grayscale display;

[0393] FIG174B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG171 when performing low grayscale display;

[0394] FIG175 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0395] FIG176 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG175 of the present disclosure;

[0396] FIG177 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0397] FIG178 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG177 of the present disclosure;

[0398] FIG179 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0399] FIG180 is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG179 of the present disclosure;

[0400] FIG181 is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG179 of the present disclosure;

[0401] FIG182 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0402] FIG183 is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG182 of the present disclosure;

[0403] FIG184 is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG182 of the present disclosure;

[0404] FIG185 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0405] FIG186 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG185 ;

[0406] FIG187A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG185 during a first reset period;

[0407] FIG187B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG185 during a first compensation period;

[0408] FIG187C is a schematic diagram illustrating an operating state of at least one embodiment of the pixel circuit shown in FIG185 during a first light-emitting period;

[0409] FIG187D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG185 during a third reset period;

[0410] FIG187E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG185 during a second compensation period;

[0411] FIG187F is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG185 during a second light-emitting period;

[0412] FIG188A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG185 when performing high grayscale display;

[0413] FIG188B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG185 when performing low grayscale display;

[0414] FIG189 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0415] FIG190 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG189 of the present disclosure;

[0416] FIG191 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0417] FIG192 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG191 of the present disclosure;

[0418] FIG193 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0419] FIG194 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0420] FIG195 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0421] FIG196 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0422] FIG197 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0423] FIG198 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0424] FIG199 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0425] FIG200 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0426] FIG201 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0427] FIG202 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0428] FIG203 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0429] FIG204 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG203 ;

[0430] FIG205A is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG203 during a first writing period;

[0431] FIG205B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG203 during a first light-emitting period;

[0432] FIG205C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG203 during a second writing time period;

[0433] FIG205D is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG203 during a second light-emitting period;

[0434] FIG205E is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG203 during a sensing reset period;

[0435] FIG205F is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG203 during a compensation period;

[0436] FIG205G is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG203 during an extraction period;

[0437] FIG206A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG203 when performing high grayscale display;

[0438] FIG206B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG203 when performing low grayscale display;

[0439] FIG207 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0440] FIG208 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG207 ;

[0441] FIG209A is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG207 during a first writing period;

[0442] FIG209B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG207 during a first light-emitting period;

[0443] FIG209C is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG207 during a second writing period;

[0444] FIG209D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG207 during a second light-emitting period;

[0445] FIG209E is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG207 during a sensing reset period;

[0446] FIG209F is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG207 during a compensation period;

[0447] FIG209G is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG207 during an extraction period;

[0448] FIG210A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG207 when performing high grayscale display;

[0449] FIG210B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG207 when performing low grayscale display;

[0450] FIG211 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0451] FIG212 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG211 ;

[0452] FIG213A is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG211 when performing high grayscale display;

[0453] FIG213B is a schematic diagram showing simulation results of at least one embodiment of the pixel circuit shown in FIG211 when performing low grayscale display;

[0454] FIG214 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0455] FIG215 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG214 ;

[0456] FIG216 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0457] FIG217 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG216 ;

[0458] FIG218 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0459] FIG219 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG218 ;

[0460] FIG220 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0461] FIG221 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG220 ;

[0462] FIG222 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0463] FIG223 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0464] FIG224 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG223 ;

[0465] FIG225 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0466] FIG226 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG225 ;

[0467] FIG227 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0468] FIG228 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG227 ;

[0469] FIG229A is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG227 during a first writing period;

[0470] FIG229B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG227 during a first light-emitting period;

[0471] FIG229C is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG227 during a second writing period;

[0472] FIG229D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG227 during a second light-emitting period;

[0473] FIG229E is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG227 during a sensing reset period;

[0474] FIG229F is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG227 during a compensation period;

[0475] FIG229G is a schematic diagram illustrating the operation of at least one embodiment of the pixel circuit shown in FIG227 during an extraction period;

[0476] FIG230 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0477] Figure 231 is a circuit diagram of a pixel circuit described in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0478] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0479] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0480] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0481] The pixel circuit according to the embodiment of the present disclosure includes a driving circuit, a switch control circuit, a light-emitting element, a driving control circuit and a first reset circuit;

[0482] The control terminal of the driving circuit is electrically connected to the first node, and is used to generate a driving current for driving the light-emitting element under the control of the potential of the first node;

[0483] The driving circuit is electrically connected to the light-emitting element or the first voltage terminal through the switch control circuit, and the switch control circuit is electrically connected to the switch control terminal. The switch control circuit is used to control the connection between the driving circuit and the light-emitting element or the first voltage terminal under the control of the potential of the switch control terminal;

[0484] The driving control circuit is electrically connected to the first control terminal and the first data line respectively, and is used to write the light-emitting time control data voltage provided by the first data line into the switch control terminal under the control of the first control signal provided by the first control terminal;

[0485] The first reset circuit is used to write a set voltage into the second node, the first electrode of the light-emitting element, or the second electrode of the light-emitting element under the control of a set control signal provided by the set control terminal.

[0486] In at least one embodiment of the present disclosure, the pixel circuit may include a driving circuit, a switch control circuit, a light-emitting element, a driving control circuit, and a first reset circuit; the driving control circuit writes a light-emission time control data voltage to the switch control terminal under the control of a first control signal; the first reset circuit writes a set voltage to a second node, a first electrode of the light-emitting element, or a second electrode of the light-emitting element under the control of a set control signal, so as to initialize the potential of the second node, the potential of the first electrode of the light-emitting element, or the potential of the second electrode of the light-emitting element before a light-emitting phase;

[0487] At least one embodiment of the present disclosure writes a luminous time control data voltage into a switch control terminal through the driving control circuit in a second data writing time period included in a second display stage provided after the first display stage, so as to control the luminous time of the light-emitting element according to the luminous time control data voltage during the luminous time period included in the second display stage, so as to delay writing the luminous time control data voltage into the pixel circuit, and control the pixel circuit with the driving current + luminous time length, thereby improving the display effect of the light-emitting element.

[0488] Optionally, the light-emitting element is an inorganic light-emitting diode, the aspect ratio of the transistor included in the switch control circuit is greater than 1, and the aspect ratio of the transistor included in the drive circuit is greater than 0.5.

[0489] In at least one embodiment of the present disclosure, the light-emitting element may be an inorganic light-emitting diode. For example, the light-emitting element may be a micro light-emitting diode or a mini light-emitting diode.

[0490] In a specific implementation, when the light-emitting element is an inorganic light-emitting diode, the width-to-length ratio of the driving transistor included in the driving circuit is greater than 0.5, and the width-to-length ratio of the transistor included in the switch control circuit is greater than 1.

[0491] Optionally, the light-emitting element may also be an organic light-emitting diode.

[0492] In at least one embodiment of the present disclosure, the aspect ratio of a transistor is a ratio of a channel width W to a channel length L of the transistor.

[0493] In at least one embodiment of the present disclosure, the set voltage may be a reference voltage, a first initial voltage, or a second initial voltage, but is not limited thereto.

[0494] Optionally, the set control terminal may be a reset control terminal, but is not limited thereto.

[0495] Optionally, the light-emitting element may be an OLED (organic light-emitting diode), a Mini LED (mini light-emitting diode) or a Micro-LED (micro light-emitting diode), but is not limited thereto.

[0496] Optionally, the first electrode of the light-emitting element may be an anode, and the second electrode of the light-emitting element may be a cathode.

[0497] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a storage circuit;

[0498] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is used to store electrical energy;

[0499] The first reset circuit is configured to write a set voltage into the second node under the control of the set control signal.

[0500] Optionally, the first voltage end may be a high voltage end, and the second voltage end may be a low voltage end, but the present invention is not limited thereto.

[0501] In at least one embodiment of the present disclosure, the energy storage circuit may include a storage capacitor; the light emitting element may be an inorganic light emitting diode;

[0502] The capacitance of the storage capacitor is greater than three times the gate-source capacitance of the transistor in the drive circuit. In a specific implementation, the capacitance of the storage capacitor is set to be greater than three times the gate-source capacitance of the transistor in the drive circuit so that when the source potential of the transistor in the drive circuit changes, the gate potential of the transistor in the drive circuit can be maintained, thereby ensuring display accuracy.

[0503] In at least one embodiment of the present disclosure, the gate-source capacitance of the transistor in the driving circuit may be a parasitic capacitance between the gate and the source of the transistor in the driving circuit, which may be calculated based on the facing area of ​​the gate and the source of the transistor in the driving circuit, and the dielectric constant, wherein the dielectric constant may be calculated based on the material and thickness of the insulating layer between the gate and the source of the transistor in the driving circuit.

[0504] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a storage circuit 10 , a driving circuit 11 , a switch control circuit 12 , a light emitting element E1 , a driving control circuit 13 and a first reset circuit 14 ;

[0505] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0506] The driving circuit 11 is electrically connected to the first electrode of the light emitting element E1 through the switch control circuit 12;

[0507] The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal V1;

[0508] The switch control circuit 12 is electrically connected to the switch control terminal N4, the second terminal of the drive circuit 11, and the first electrode of the light-emitting element E1, respectively. The switch control circuit is used to control the second terminal of the drive circuit 11 to communicate with the first electrode of the light-emitting element E1 under the control of the potential of the switch control terminal N4; the second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2;

[0509] The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[0510] The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the reference voltage terminal and the second node N2, and is used to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the reset control signal provided by the first reset control terminal RST1;

[0511] A first end of the energy storage circuit 10 is electrically connected to the first node N1 , and a second end of the energy storage circuit 10 is electrically connected to the second node N2 . The energy storage circuit 10 is used to store electrical energy.

[0512] As shown in FIG2 , the pixel circuit according to the embodiment of the present disclosure includes a storage circuit 10 , a driving circuit 11 , a switch control circuit 12 , a light emitting element E1 , a driving control circuit 13 and a first reset circuit 14 ;

[0513] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0514] The driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the switch control circuit 12;

[0515] The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0516] The switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the drive circuit 11, and the second electrode of the light-emitting element E1, respectively. The switch control circuit 12 is used to control the connection between the first terminal of the drive circuit 11 and the second electrode of the light-emitting element E1 under the control of the potential of the switch control terminal N4;

[0517] The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[0518] The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the reference voltage terminal and the second node N2, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first reset control signal provided by the first reset control terminal RST1;

[0519] A first end of the energy storage circuit 10 is electrically connected to the first node N1 , and a second end of the energy storage circuit 10 is electrically connected to the second node N2 . The energy storage circuit 10 is used to store electrical energy.

[0520] As shown in FIG3 , the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 11 , a switch control circuit 12 , a light emitting element E1 , a driving control circuit 13 and a first reset circuit 14 ;

[0521] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0522] The driving circuit 11 is electrically connected to the first voltage terminal V1 through the switch control circuit 12;

[0523] The control end of the switch control circuit 12 is electrically connected to the switch control end N4, the first end of the switch control circuit 12 is electrically connected to the first voltage end V1, and the second end of the switch control circuit 12 is electrically connected to the first end of the drive circuit 11. The switch control circuit 12 is configured to control the communication between the first voltage end V1 and the first end of the drive circuit 11 under the control of the potential of the switch control end N4;

[0524] The second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2;

[0525] The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[0526] The first reset circuit 14 is electrically connected to the first selection control terminal X1, the scan terminal G1, the reference voltage terminal, and the first electrode of the light-emitting element E1, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first selection control signal provided by the first selection control terminal X1 and the scan signal provided by the scan terminal G1;

[0527] A first electrode of the light emitting element E1 is electrically connected to the second node N2.

[0528] As shown in FIG4 , the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 11 , a switch control circuit 12 , a light emitting element E1 , a driving control circuit 13 and a first reset circuit 14 ;

[0529] The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal;

[0530] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0531] The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the drive circuit 11, the second terminal of the switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1, and the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2;

[0532] The switch control circuit 12 is used to control the connection between the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4;

[0533] The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[0534] The first reset circuit 14 is electrically connected to the first selection control terminal X1, the scan terminal G1, the reference voltage terminal, and the first electrode of the light-emitting element E1, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first selection control signal provided by the first selection control terminal X1 and the scan signal provided by the scan terminal G1;

[0535] The first electrode of the light emitting element E1 is electrically connected to the second node.

[0536] In at least one embodiment of the present disclosure, the driving circuit is electrically connected to the first electrode of the light-emitting element through the switch control circuit, and the switch control circuit is used to control the connection between the driving circuit and the first electrode of the light-emitting element under the control of the potential of the switch control terminal; the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0537] The first reset circuit is used to write the set voltage into the first electrode of the light emitting element under the control of the set control signal during a reset period between the period for writing the display data voltage and the period for writing the luminous time control data voltage.

[0538] In a specific implementation, the driving circuit can be electrically connected to the first pole of the light-emitting element through the switching control circuit. At this time, the first reset circuit can write the set voltage into the first pole of the light-emitting element under the control of the set control signal during the reset time period, so as to initialize the potential of the first pole of the light-emitting element before emitting light in each display cycle, clear the residual charge in the first pole of the light-emitting element, and improve the flicker phenomenon.

[0539] In at least one embodiment of the present disclosure, when the potential of the first electrode of the light-emitting element is initialized, the light-emitting element does not emit light.

[0540] When the pixel circuit according to at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are sequentially set; the first display phase may include a first reset time period, a first write time period, and a first light-emitting time period that are sequentially set; and the second display phase may include a second reset time period, a second write time period, and a second light-emitting time period that are sequentially set;

[0541] During the first reset period and the second reset period, the first reset circuit writes a set voltage into the first electrode of the light emitting element under the control of the set control signal;

[0542] In a first writing period, writing a display data voltage;

[0543] In a first light-emitting period, the driving circuit drives the light-emitting element to emit light according to the display data voltage;

[0544] In the second writing period, writing the light emitting time control data voltage;

[0545] In the second light-emitting period, the driving circuit controls the data voltage according to the light-emitting time to control whether the light-emitting element emits light.

[0546] The reset period provided between the period for writing the display data voltage and the period for writing the light emitting time control data voltage may be the second reset period.

[0547] Optionally, the first electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0548] The driving circuit is electrically connected to the second electrode of the light-emitting element through the switch control circuit, and the switch control circuit is used to control the connection between the driving circuit and the first voltage terminal under the control of the potential of the switch control terminal;

[0549] The first reset circuit is used to write a set voltage into the second electrode of the light-emitting element under the control of the set control signal.

[0550] In a specific implementation, the first pole of the light-emitting element can be electrically connected to the first voltage terminal, and the driving circuit can be electrically connected to the second pole of the light-emitting element through the switch control circuit. At this time, the first reset circuit can write the set voltage into the second pole of the light-emitting element under the control of the set control signal during the reset time period, so as to initialize the potential of the second pole of the light-emitting element before emitting light in each display cycle, clear the residual charge on the second pole of the light-emitting element, and improve the flicker phenomenon.

[0551] In at least one embodiment of the present disclosure, when the potential of the second electrode of the light-emitting element is initialized, the light-emitting element does not emit light.

[0552] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are set in sequence; the first display phase may include a first reset time period, a first write time period, and a first light-emitting time period that are set in sequence, and the second display phase may include a second reset time period, a second write time period, and a second light-emitting time period that are set in sequence.

[0553] During the first reset period and the second reset period, the first reset circuit writes a set voltage into the second electrode of the light-emitting element under the control of the set control signal;

[0554] In a first writing period, writing a display data voltage;

[0555] In a first light-emitting period, the driving circuit drives the light-emitting element to emit light according to the display data voltage;

[0556] In the second writing period, writing the light emitting time control data voltage;

[0557] In the second light-emitting period, the driving circuit controls the data voltage according to the light-emitting time to control whether the light-emitting element emits light.

[0558] The reset period provided between the period for writing the display data voltage and the period for writing the light emitting time control data voltage may be the second reset period.

[0559] In at least one embodiment of the present disclosure, the pixel circuit further includes a tank circuit;

[0560] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the first electrode of the light emitting element, and the energy storage circuit is used to store electrical energy;

[0561] The first end of the switch control circuit is electrically connected to the first voltage end, the second end of the switch control circuit is electrically connected to the first end of the drive circuit, the second end of the drive circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second voltage end; the switch control circuit is used to control the communication between the first voltage end and the first end of the drive circuit under the control of the potential of the switch control end; or the first end of the drive circuit is electrically connected to the first voltage end; the first end of the switch control circuit is electrically connected to the second end of the drive circuit, the second end of the switch control circuit is electrically connected to the first electrode of the light-emitting element, and the second end of the light-emitting element is electrically connected to the second voltage end; the switch control circuit is used to control the communication between the second end of the drive circuit and the first electrode of the light-emitting element under the control of the potential of the switch control end;

[0562] The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scan terminal and a first selection control terminal;

[0563] The compensation circuit is electrically connected to the scanning terminal, the first terminal of the light-emitting element, and the control node, respectively, and is used to control the communication between the first terminal of the light-emitting element and the control node under the control of the scanning signal provided by the scanning terminal; or the compensation circuit is electrically connected to the scanning terminal, the second terminal of the driving circuit, and the control node, respectively, and is used to control the communication between the second terminal of the driving circuit and the control node under the control of the scanning signal;

[0564] The switch circuit is respectively connected to the first selection control terminal, the control node and the set voltage terminal, and is used to provide the set voltage written by the set voltage terminal provided by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal.

[0565] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit further includes a tank circuit 10 and a first reset circuit;

[0566] The first end of the energy storage circuit 10 is electrically connected to the first node N1, and the second end of the energy storage circuit 10 is electrically connected to the first electrode of the light emitting element E1. The energy storage circuit 10 is used to store electrical energy;

[0567] The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scan terminal G1 and a first selection control terminal X1;

[0568] The compensation circuit 21 is electrically connected to the scanning terminal G1, the first electrode of the light-emitting element E1, and the control node N0, respectively, and is used to control the connection between the first electrode of the light-emitting element E1 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0569] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is used to provide the reference voltage Vref written in the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1.

[0570] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG4 , the pixel circuit further includes a tank circuit 10 and a first reset circuit;

[0571] The first end of the energy storage circuit 10 is electrically connected to the first node N1, and the second end of the energy storage circuit 10 is electrically connected to the first electrode of the light emitting element E1. The energy storage circuit 10 is used to store electrical energy;

[0572] The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scan terminal G1 and a first selection control terminal X1;

[0573] The compensation circuit 21 is electrically connected to the scanning terminal G1, the first electrode of the light-emitting element E1, and the control node N0, respectively, and is used to control the connection between the second terminal of the driving circuit 11 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0574] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is used to provide the reference voltage Vref provided by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1.

[0575] In at least one embodiment of the present disclosure, the pixel circuit further includes a tank circuit;

[0576] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second electrode of the light emitting element, and the energy storage circuit is used to store electrical energy;

[0577] The first electrode of the light-emitting element is electrically connected to the first voltage terminal, the first terminal of the switch control circuit is electrically connected to the second electrode of the light-emitting element, the second terminal of the switch control circuit is electrically connected to the first terminal of the drive circuit, and the second terminal of the drive circuit is electrically connected to the second voltage terminal; the switch control circuit is used to control the second electrode of the light-emitting element to be connected to the first terminal of the drive circuit under the control of the potential of the switch control terminal; or the first electrode of the light-emitting element is electrically connected to the first voltage terminal, and the second electrode of the light-emitting element is electrically connected to the first terminal of the drive circuit; the first terminal of the switch control circuit is electrically connected to the second terminal of the drive circuit, and the second terminal of the switch control circuit is electrically connected to the second voltage terminal; the switch control circuit is used to control the second terminal of the drive circuit to be connected to the first electrode of the light-emitting element under the control of the potential of the switch control terminal;

[0578] The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scan terminal and a first selection control terminal;

[0579] The compensation circuit is electrically connected to the scanning terminal, the second terminal of the light-emitting element, and the control node, respectively, and is used to control the second terminal of the light-emitting element to be connected to the control node under the control of the scanning signal; or the compensation circuit is electrically connected to the scanning terminal, the first terminal of the driving circuit, and the control node, respectively, and is used to control the first terminal of the driving circuit to be connected to the control node under the control of the scanning signal;

[0580] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is used to write the set voltage provided by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal.

[0581] As shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11 , a switch control circuit 12 , a light-emitting element E1 , a driving control circuit 13 , an energy storage circuit 10 , and a first reset circuit;

[0582] The first end of the energy storage circuit 10 is electrically connected to the first node N1, and the second end of the energy storage circuit 10 is electrically connected to the second electrode of the light emitting element E1. The energy storage circuit 10 is used to store electrical energy; the second electrode of the light emitting element E1 is electrically connected to the second node N2.

[0583] The first terminal of the light-emitting element E1 is electrically connected to the first voltage terminal V1, the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the light-emitting element E1, the second terminal of the switch control circuit 12 is electrically connected to the first terminal of the drive circuit 11, and the second terminal of the drive circuit 11 is electrically connected to the second voltage terminal V2;

[0584] The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the switch control circuit 12 is used to control the second electrode of the light-emitting element E1 to be connected to the first terminal of the drive circuit 11 under the control of the potential of the switch control terminal N4;

[0585] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0586] The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[0587] The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scan terminal G1 and a first selection control terminal;

[0588] The compensation circuit 21 is electrically connected to the scanning terminal G1, the second electrode of the light-emitting element E1, and the control node N0, respectively, and is used to control the connection between the second electrode of the light-emitting element E1 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0589] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1.

[0590] As shown in FIG8 , the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11 , a switch control circuit 12 , a light-emitting element E1 , a driving control circuit 13 , an energy storage circuit 10 , and a first reset circuit;

[0591] The first end of the energy storage circuit 10 is electrically connected to the first node N1, and the second end of the energy storage circuit 10 is electrically connected to the second electrode of the light emitting element E1. The energy storage circuit 10 is used to store electrical energy; the second electrode of the light emitting element E1 is electrically connected to the second node N2.

[0592] The first electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1, and the second electrode of the light-emitting element E1 is electrically connected to the first terminal of the driving circuit 11; the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the driving circuit 11, and the second terminal of the switch control circuit 12 is electrically connected to the second voltage terminal V2;

[0593] The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the switch control circuit 12 is used to control the second terminal of the drive circuit 11 to be connected to the first electrode of the light-emitting element E1 under the control of the potential of the switch control terminal N4;

[0594] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0595] The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[0596] The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scan terminal G1 and a first selection control terminal X1;

[0597] The compensation circuit 21 is electrically connected to the scanning terminal G1, the second electrode of the light-emitting element E1, and the control node N0, respectively, and is used to control the connection between the first terminal of the driving circuit 11 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0598] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1.

[0599] In at least one embodiment of the present disclosure, the drive control circuit is also electrically connected to the second control terminal and the second initial voltage terminal, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the switch control terminal under the control of the second control signal provided by the second control terminal, and to maintain the potential of the switch control terminal.

[0600] In a specific implementation, the drive control circuit may further write a second initial voltage into the switch control terminal and maintain the potential of the switch control terminal under the control of the second control signal.

[0601] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 1, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0602] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 2, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0603] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 5, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0604] As shown in Figure 12, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0605] As shown in Figure 13, based on at least one embodiment of the pixel circuit shown in Figure 7, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0606] As shown in Figure 14, based on at least one embodiment of the pixel circuit shown in Figure 8, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0607] Optionally, the first terminal of the driving circuit is electrically connected to the first voltage terminal;

[0608] The switch control circuit is electrically connected to the second terminal of the drive circuit and the first electrode of the light-emitting element respectively, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0609] The switch control circuit is used to control the connection between the second end of the driving circuit and the first end of the light emitting element under the control of the potential of the switch control end.

[0610] In a specific implementation, the switch control circuit can control the connection between the second end of the driving circuit and the first end of the light emitting element under the control of the potential of the switch control end.

[0611] The pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit;

[0612] The switch control circuit is electrically connected to the first electrode of the light emitting element through the light emitting control circuit;

[0613] The light emitting control circuit is also electrically connected to the light emitting control terminal, and is used to control the connection between the switch control circuit and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal;

[0614] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end.

[0615] In a specific implementation, the pixel circuit may further include a light-emitting control circuit and a compensation control circuit. The light-emitting control circuit, under the control of a light-emitting control signal, controls the connection between the switch control circuit and the first pole of the light-emitting element to perform light-emitting control; the compensation control circuit, under the control of a scanning signal, controls the connection between the control end of the driving circuit and the second end of the driving circuit to perform threshold voltage compensation.

[0616] Optionally, the light-emitting element is an inorganic light-emitting diode, the aspect ratio of the transistor included in the switch control circuit is greater than 1, the aspect ratio of the transistor included in the light-emitting control circuit is greater than 1, and the aspect ratio of the transistor included in the drive circuit is greater than 0.5.

[0617] In a specific implementation, the light-emitting element can be an inorganic light-emitting diode, the width-to-length ratio of the transistor included in the switch control circuit can be greater than 1, the width-to-length ratio of the transistor included in the light-emitting control circuit can be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit can be greater than 0.5.

[0618] As shown in FIG15 , based on at least one embodiment of the driving circuit shown in FIG9 , the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit 31 and a compensation control circuit 32 ( T5 );

[0619] The switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1 through the light emitting control circuit 31;

[0620] The light emitting control circuit E1 is also electrically connected to the light emitting control terminal EM, and is used to control the connection between the switch control circuit 12 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0621] The compensation control circuit 32 is electrically connected to the scanning end G1, the control end of the driving circuit 11 and the second end of the driving circuit 11 respectively, and is used to control the communication between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the scanning signal provided by the scanning end G1.

[0622] In at least one embodiment of the present disclosure, the first electrode of the light-emitting element is electrically connected to the first voltage terminal, the switch control circuit is electrically connected to the second electrode of the light-emitting element and the first terminal of the drive circuit respectively, and the second terminal of the drive circuit is electrically connected to the second voltage terminal;

[0623] The switch control circuit is used to control the connection between the second electrode of the light-emitting element and the first end of the driving circuit under the control of the potential of the switch control end.

[0624] The pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit;

[0625] The switch control circuit is electrically connected to the first end of the drive circuit through the light emitting control circuit;

[0626] The light emitting control circuit is also electrically connected to the light emitting control terminal, and is used to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[0627] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the first end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal provided by the scanning end.

[0628] In a specific implementation, the pixel circuit may further include a light-emitting control circuit and a compensation control circuit. The light-emitting control circuit, under the control of a light-emitting control signal, controls the connection between the switch control circuit and the first end of the driving circuit to perform light-emitting control; the compensation control circuit, under the control of a scanning signal, controls the connection between the control end of the driving circuit and the first end of the driving circuit to perform threshold voltage compensation.

[0629] As shown in FIG16 , based on at least one embodiment of the driving circuit shown in FIG10 , the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit 31 and a compensation control circuit 32 ( T5 );

[0630] The switch control circuit 12 is electrically connected to the first terminal of the driving circuit 11 through the light emitting control circuit 31; the second terminal of the driving circuit 11 is electrically connected to the second voltage terminal V2;

[0631] The light emitting control circuit 31 is also electrically connected to the light emitting control terminal EM, and is used to control the connection between the switch control circuit 12 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0632] The compensation control circuit 32 is electrically connected to the scanning end G1, the control end of the driving circuit 11 and the first end of the driving circuit 11 respectively, and is used to control the communication between the control end of the driving circuit 11 and the first end of the driving circuit 11 under the control of the scanning signal provided by the scanning end G1.

[0633] The pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit and a first control circuit;

[0634] The control terminal of the driving circuit is electrically connected to the first node;

[0635] The display data writing circuit is electrically connected to the scan terminal, the second data line and the second node respectively, and is used to write the display data voltage provided by the second data line into the second node under the control of the scan signal provided by the scan terminal;

[0636] The first control circuit is electrically connected to the light-emitting control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0637] In a specific implementation, the pixel circuit described in at least one embodiment of the present disclosure may further include a display data writing circuit and a first control circuit; the display data writing circuit writes the display data voltage provided by the second data line into the second node under the control of the scanning signal; the first control circuit writes the reference voltage into the second node under the control of the light emitting control signal.

[0638] As shown in FIG17 , based on at least one embodiment of the pixel circuit shown in FIG15 , the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit 41 and a first control circuit 42 ;

[0639] The control terminal of the driving circuit 11 is electrically connected to the first node N1;

[0640] The display data writing circuit 41 is electrically connected to the scan terminal G1, the second data line DI and the second node N2 respectively, and is used to write the display data voltage provided by the second data line DI into the second node N2 under the control of the scan signal provided by the scan terminal G1;

[0641] The first control circuit 42 is electrically connected to the light emitting control terminal EM, the reference voltage terminal and the second node N2 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM.

[0642] As shown in FIG18 , based on at least one embodiment of the pixel circuit shown in FIG16 , the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit 41 and a first control circuit 42 ;

[0643] The control terminal of the driving circuit 11 is electrically connected to the first node N1;

[0644] The display data writing circuit 41 is electrically connected to the scan terminal G1, the second data line DI and the second node N2 respectively, and is used to write the display data voltage provided by the second data line DI into the second node N2 under the control of the scan signal provided by the scan terminal G1;

[0645] The first control circuit 42 is electrically connected to the light emitting control terminal EM, the reference voltage terminal and the second node N2 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM.

[0646] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0647] The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal.

[0648] In a specific implementation, the pixel circuit may further include a second reset circuit; the second reset circuit writes a first initial voltage into the first node under the control of the first reset control signal.

[0649] As shown in FIG19 , based on at least one embodiment of the pixel circuit shown in FIG17 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit 51 ;

[0650] The second reset circuit 51 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal.

[0651] As shown in FIG20 , based on at least one embodiment of the pixel circuit shown in FIG19 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit 51 ;

[0652] The second reset circuit 51 is electrically connected to the first reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal.

[0653] The pixel circuit according to at least one embodiment of the present disclosure further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing circuit;

[0654] The first end of the energy storage circuit is electrically connected to the control end of the drive circuit, the second end of the energy storage circuit is electrically connected to the first voltage end, and the energy storage circuit is used to store electrical energy;

[0655] The first end of the driving circuit is electrically connected to the first voltage end through the first light emitting control circuit;

[0656] The second end of the driving circuit is electrically connected to the switch control circuit through the second light emitting control circuit;

[0657] The first light emitting control circuit is further electrically connected to the light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[0658] The second light emitting control circuit is also electrically connected to the light emitting control terminal, and is used to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal;

[0659] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end;

[0660] The display data writing circuit is electrically connected to the scanning end, the second data line and the first end of the driving circuit respectively, and is used to write the display data voltage provided by the second data line into the first end of the driving circuit under the control of the scanning signal.

[0661] In a specific implementation, the pixel circuit may further include a storage circuit, a first light-emitting control circuit, a second light-emitting control circuit, a compensation control circuit and a display data writing circuit; the first light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of a light-emitting control signal, and the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the switch control circuit under the control of the light-emitting control signal to perform light-emitting control; the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a scan signal to perform threshold voltage compensation; the display data writing circuit writes the display data voltage provided by the second data line into the first terminal of the driving circuit under the control of the scan signal to perform display data voltage writing.

[0662] In at least one embodiment of the present disclosure, the light-emitting element is an inorganic light-emitting diode, the width-to-length ratio of the transistor included in the switching control circuit is greater than 1, the width-to-length ratio of the transistor included in the first light-emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light-emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0663] In a specific implementation, the light-emitting element may be an inorganic light-emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, the width-to-length ratio of the transistor included in the first light-emitting control circuit may be greater than 1, the width-to-length ratio of the transistor included in the second light-emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5.

[0664] As shown in FIG21 , the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light-emitting element E1, a driving control circuit 13, a first reset circuit 14, a tank circuit 10, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a compensation control circuit 32, and a display data writing circuit 41.

[0665] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0666] The first reset circuit 14 is electrically connected to the first reset control terminal RST, the first initial voltage terminal I1, and the first electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST;

[0667] The first end of the energy storage circuit 10 is electrically connected to the control end of the drive circuit 11, and the second end of the energy storage circuit 10 is electrically connected to the first voltage end V1. The energy storage circuit 10 is used to store electrical energy;

[0668] The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal V1 through the first light emitting control circuit 61;

[0669] The second end of the driving circuit 11 is electrically connected to the switch control circuit 12 through the second light emitting control circuit 62;

[0670] The first light emitting control circuit 61 is also electrically connected to the light emitting control terminal EM, and is used to control the connection between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0671] The second light emitting control circuit 62 is also electrically connected to the light emitting control terminal EM, and is used to control the communication between the second terminal of the driving circuit 11 and the switch control circuit 12 under the control of the light emitting control signal;

[0672] The switch control circuit 12 is electrically connected to the switch control terminal N4, the second light-emitting control circuit 62, and the first electrode of the light-emitting element E1, respectively. The switch control circuit 12 is configured to control the second light-emitting control circuit 62 to communicate with the first electrode of the light-emitting element E1 under the control of the potential of the switch control terminal N4; the second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2;

[0673] The driving control circuit 13 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second initial voltage terminal I2, and the switch control terminal N4, respectively, and is configured to write the light-emission time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of a first control signal provided by the first control terminal GB, and write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of a second control signal provided by the second control terminal GA;

[0674] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the second terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0675] The display data writing circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the first terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal.

[0676] In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing circuit;

[0677] A first end of the energy storage circuit is electrically connected to the control end of the drive circuit, a second end of the energy storage circuit is electrically connected to the second voltage end, and the energy storage circuit is used to store electrical energy;

[0678] The first light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit, and the first terminal of the driving circuit, respectively, and is configured to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of a light emitting control signal provided by the light emitting control terminal;

[0679] The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit, and the second voltage terminal respectively, and is used to control the second terminal of the driving circuit to be electrically connected to the second voltage terminal under the control of the light emitting control signal;

[0680] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the first end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal provided by the scanning end;

[0681] The display data writing circuit is electrically connected to the scanning end, the second data line and the second end of the driving circuit respectively, and is used to write the display data voltage provided by the second data line into the second end of the driving circuit under the control of the scanning signal.

[0682] In a specific implementation, the pixel circuit may further include a storage circuit, a first light-emitting control circuit, a second light-emitting control circuit, a compensation control circuit and a display data writing circuit; the first light-emitting control circuit controls the connection between the switch control circuit and the first end of the driving circuit under the control of a light-emitting control signal; the second light-emitting control circuit controls the second end of the driving circuit to be electrically connected to the first pole of the light-emitting element under the control of the light-emitting control signal; the compensation control circuit controls the connection between the control end of the driving circuit and the first end of the driving circuit under the control of a scanning signal; the display data writing circuit writes the display data voltage provided by the second data line into the second end of the driving circuit under the control of the scanning signal.

[0683] As shown in FIG22 , the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light-emitting element E1, a driving control circuit 13, a first reset circuit 14, an energy storage circuit 10, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a compensation control circuit 32, and a display data writing circuit 41;

[0684] The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0685] The switch control circuit 12 is electrically connected to the switch control terminal N4, the first light control circuit 61, and the second electrode of the light-emitting element E1, respectively. The switch control circuit 12 is configured to control the connection between the second electrode of the light-emitting element E1 and the first light control circuit 61 under the control of the potential of the switch control terminal N4.

[0686] The driving control circuit 13 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second initial voltage terminal I2, and the switch control terminal N4, respectively, and is configured to write the light-emission time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of a first control signal provided by the first control terminal GB, and write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of a second control signal provided by the second control terminal GA;

[0687] The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1, and the second electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light-emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1, so as to clear the residual charge in the second electrode of the light-emitting element E1;

[0688] The first end of the energy storage circuit 10 is electrically connected to the control end of the drive circuit 11, and the second end of the energy storage circuit 10 is electrically connected to the second voltage end V2. The energy storage circuit 10 is used to store electrical energy;

[0689] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the switch control circuit 12, and the first terminal of the driving circuit 11, respectively, and is configured to control the communication between the switch control circuit 12 and the first terminal of the driving circuit 11 under the control of a light emitting control signal provided by the light emitting control terminal EM;

[0690] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11, and the second voltage terminal V2, respectively, and is used to control the second terminal of the driving circuit 11 to be electrically connected to the second voltage terminal V2 under the control of the light emitting control signal;

[0691] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the first terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0692] The display data writing circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal.

[0693] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0694] The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0695] In a specific implementation, the pixel circuit may further include a second reset circuit, and the second reset circuit writes the first initial voltage into the first node under the control of a reset control signal.

[0696] As shown in FIG23 , based on at least one embodiment of the pixel circuit shown in FIG21 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit 71 ;

[0697] The second reset circuit 71 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0698] As shown in FIG24 , based on at least one embodiment of the pixel circuit shown in FIG22 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit 71 ;

[0699] The second reset circuit 71 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0700] The pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit;

[0701] The display data writing circuit is electrically connected to the scanning end, the second data line and the control end of the driving circuit respectively, and is used to write the display data voltage provided by the second data line into the control end of the driving circuit under the control of the scanning signal provided by the scanning end.

[0702] In at least one embodiment of the present disclosure, the switch circuit is further connected to a second selection control terminal and a compensation terminal, and is configured to control the connection between the control node and the compensation terminal under the control of a second selection control signal provided by the second selection control terminal.

[0703] In a specific implementation, the switch circuit can control the connection between the control node and the compensation end under the control of the second selection control signal to transmit the potential of the control node to the compensation end, so as to perform threshold voltage compensation according to the potential of the compensation end.

[0704] As shown in FIG25 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit 41 ;

[0705] The display data writing circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0706] The switch circuit 22 is further connected to the second selection control terminal X2 and the compensation terminal SENS respectively, and is used to control the connection between the control node N0 and the compensation terminal SENS under the control of the second selection control signal provided by the second selection control terminal X2.

[0707] As shown in FIG26 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit 41 ;

[0708] The display data writing circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0709] The switch circuit 22 is further connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2.

[0710] As shown in FIG27 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit 41 ;

[0711] The display data writing circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0712] The switch circuit 22 is further connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2.

[0713] As shown in FIG28 , based on at least one embodiment of the pixel circuit shown in FIG8 , the pixel circuit according to at least one embodiment of the present disclosure further includes a display data writing circuit 41 ;

[0714] The display data writing circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0715] The switch circuit 22 is further connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2.

[0716] The pixel circuit according to at least one embodiment of the present disclosure may further include a third reset circuit;

[0717] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the reset control signal provided by the second reset control terminal during a reset period set between a period for writing the display data voltage and a period for writing the light-emitting time control data voltage.

[0718] As shown in FIG29 , based on at least one embodiment of the pixel circuit shown in FIG17 , the pixel circuit according to at least one embodiment of the present disclosure may further include a third reset circuit 81 ;

[0719] The third reset circuit 81 is electrically connected to the second reset control terminal RST2, the third initial voltage terminal I3 and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RST2.

[0720] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are set in sequence; the first display phase may include a first reset time period, a first write time period, and a first light-emitting time period that are set in sequence, and the second display phase may include a second reset time period, a second write time period, and a second light-emitting time period that are set in sequence.

[0721] During the first reset period and the second reset period, the third reset circuit writes a third initial voltage into the first electrode of the light emitting element under the control of the second reset control signal;

[0722] In a first writing period, writing a display data voltage;

[0723] In a first light-emitting period, the driving circuit drives the light-emitting element to emit light according to the display data voltage;

[0724] In the second writing period, writing the light emitting time control data voltage;

[0725] In the second light-emitting period, the driving circuit controls the data voltage according to the light-emitting time to control whether the light-emitting element emits light.

[0726] The reset period provided between the period for writing the display data voltage and the period for writing the light emitting time control data voltage may be the second reset period.

[0727] The pixel circuit according to at least one embodiment of the present disclosure may further include a third reset circuit;

[0728] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset period set between the time period for writing the display data voltage and the time period for writing the light-emitting time control data voltage.

[0729] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are set in sequence; the first display phase may include a first reset time period, a first write time period, and a first light-emitting time period that are set in sequence, and the second display phase may include a second reset time period, a second write time period, and a second light-emitting time period that are set in sequence.

[0730] During the first reset period and the second reset period, the third reset circuit writes a third initial voltage into the second electrode of the light-emitting element under the control of the second reset control signal;

[0731] In a first writing period, writing a display data voltage;

[0732] In a first light-emitting period, the driving circuit drives the light-emitting element to emit light according to the display data voltage;

[0733] In the second writing period, writing the light emitting time control data voltage;

[0734] In the second light-emitting period, the driving circuit controls the data voltage according to the light-emitting time to control whether the light-emitting element emits light.

[0735] The reset period provided between the period for writing the display data voltage and the period for writing the light emitting time control data voltage may be the second reset period.

[0736] As shown in FIG30 , based on at least one embodiment of the pixel circuit shown in FIG18 , the pixel circuit according to at least one embodiment of the present disclosure may further include a third reset circuit 81 ;

[0737] The third reset circuit 81 is electrically connected to the second reset control terminal RST2, the third initial voltage terminal I3 and the second electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the second electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RST2.

[0738] Optionally, the drive control circuit includes a first transistor, a second transistor and a first capacitor;

[0739] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the switch control terminal;

[0740] The gate of the second transistor is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the second initial voltage terminal, and the second electrode of the second transistor is electrically connected to the switch control terminal;

[0741] A first end of the first capacitor is electrically connected to the switch control end, and a second end of the first capacitor is electrically connected to the DC voltage end.

[0742] In at least one embodiment of the present disclosure, the DC voltage terminal may be, for example, a common electrode voltage terminal, a ground terminal, a high voltage terminal, or a low voltage terminal, but is not limited thereto.

[0743] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor;

[0744] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first voltage terminal, and the second electrode of the driving transistor is electrically connected to the third node;

[0745] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor;

[0746] The gate of the third transistor is electrically connected to the switch control terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0747] A gate of the fifth transistor is electrically connected to the scan end, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third node.

[0748] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor;

[0749] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0750] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor; the first electrode of the driving transistor is electrically connected to the third node;

[0751] The gate of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second voltage terminal;

[0752] A gate of the fifth transistor is electrically connected to the scan end, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third node.

[0753] Optionally, the display data writing circuit includes a sixth transistor, and the first control circuit includes a seventh transistor;

[0754] The gate of the sixth transistor is electrically connected to the scanning end, the first electrode of the sixth transistor is electrically connected to the second data line, and the second electrode of the sixth transistor is electrically connected to the second node;

[0755] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the reference voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second node.

[0756] Optionally, the first reset circuit includes an eighth transistor;

[0757] The gate of the eighth transistor is electrically connected to the set control terminal, the first electrode of the eighth transistor is electrically connected to the set voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node, the first electrode of the light-emitting element, or the second electrode of the light-emitting element;

[0758] The set voltage terminal is used to provide the set voltage.

[0759] Optionally, the second reset circuit includes a ninth transistor,

[0760] The gate of the ninth transistor is electrically connected to the first reset control terminal, the first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node.

[0761] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes an eleventh transistor; the second light-emitting control circuit includes a twelfth transistor; the switch control circuit includes a third transistor; the compensation control circuit includes a fifth transistor; and the display data writing circuit includes a sixth transistor;

[0762] A first terminal of the storage capacitor is electrically connected to the gate of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal;

[0763] The gate of the eleventh transistor is electrically connected to the light emitting control terminal, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor;

[0764] The gate of the twelfth transistor is electrically connected to the light emitting control terminal, the first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the twelfth transistor is electrically connected to the first electrode of the third transistor;

[0765] The gate of the third transistor is electrically connected to the switch control terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0766] The gate of the fifth transistor is electrically connected to the scanning end, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor;

[0767] A gate of the sixth transistor is electrically connected to the scanning end, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor.

[0768] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes an eleventh transistor; the second light-emitting control circuit includes a twelfth transistor; the switch control circuit includes a third transistor; the compensation control circuit includes a fifth transistor; and the display data writing circuit includes a sixth transistor;

[0769] A first terminal of the storage capacitor is electrically connected to the gate of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second voltage terminal;

[0770] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the third transistor is electrically connected to the first electrode of the eleventh transistor;

[0771] The gate of the eleventh transistor is electrically connected to the light emitting control terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor;

[0772] The gate of the twelfth transistor is electrically connected to the light emitting control terminal, the first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal;

[0773] The gate of the fifth transistor is electrically connected to the scanning end, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor;

[0774] A gate of the sixth transistor is electrically connected to the scanning end, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor.

[0775] Optionally, the second reset circuit includes a ninth transistor;

[0776] The gate of the ninth transistor is electrically connected to the first reset control terminal, the first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node.

[0777] Optionally, the third reset circuit includes a tenth transistor;

[0778] The gate of the tenth transistor is electrically connected to the second reset control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0779] Optionally, the third reset circuit includes a tenth transistor;

[0780] The gate of the tenth transistor is electrically connected to the second reset control terminal, the first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element.

[0781] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor;

[0782] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;

[0783] The second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

[0784] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor;

[0785] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0786] The first electrode of the driving transistor is electrically connected to the first voltage terminal.

[0787] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor;

[0788] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the light-emitting element, the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0789] Optionally, the switch control circuit includes a third transistor, and the drive circuit includes a drive transistor; the second electrode of the light-emitting element is electrically connected to the first electrode of the drive transistor;

[0790] The gate of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element.

[0791] Optionally, the display data writing circuit includes a sixth transistor;

[0792] A gate of the sixth transistor is electrically connected to the scan end, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the control end of the driving circuit.

[0793] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch;

[0794] A first end of the storage capacitor is electrically connected to the control end of the drive circuit, and a second end of the storage capacitor is electrically connected to the second end of the drive circuit;

[0795] The gate of the thirteenth transistor is electrically connected to the scanning terminal, the first electrode of the thirteenth transistor is electrically connected to the first electrode of the light-emitting element or the second terminal of the driving circuit, and the second electrode of the thirteenth transistor is electrically connected to the control node;

[0796] The control end of the first switch is electrically connected to the first selection control end, the first end of the first switch is electrically connected to the control node, and the second end of the first switch is electrically connected to the reference voltage end.

[0797] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch;

[0798] The first end of the storage capacitor is electrically connected to the control end of the drive circuit, and the second end of the storage capacitor is electrically connected to the first end of the drive circuit;

[0799] The gate of the thirteenth transistor is electrically connected to the scanning end, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the light-emitting element or the first end of the driving circuit, and the second electrode of the thirteenth transistor is electrically connected to the control node;

[0800] The control end of the first switch is electrically connected to the first selection control end, the first end of the first switch is electrically connected to the control node, and the second end of the first switch is electrically connected to the reference voltage end.

[0801] Optionally, the switching circuit further includes a second switch;

[0802] The control end of the second switch is electrically connected to the second selection control end, the first end of the second switch is electrically connected to the control node, and the second end of the second switch is electrically connected to the compensation end.

[0803] As shown in FIG31 , based on at least one embodiment of the pixel circuit shown in FIG17 , the light emitting element is a light emitting diode E0 ; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS;

[0804] The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0805] The gate of the first transistor T1 is electrically connected to the first control terminal GB, the source of the first transistor T1 is electrically connected to the first data line DT, and the drain of the first transistor T1 is electrically connected to the switch control terminal N4;

[0806] The gate of the second transistor T2 is electrically connected to the second control terminal GA, the source of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0807] A first end of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second end of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM;

[0808] The driving circuit includes a driving transistor T0, the switch control circuit includes a third transistor T3, the light emitting control circuit includes a fourth transistor T4, and the compensation control circuit includes a fifth transistor T5;

[0809] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the high voltage terminal VDD, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0810] The gate of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the source of the third transistor T3;

[0811] The gate of the third transistor T3 is electrically connected to the switch control terminal N4, and the drain of the third transistor T3 is electrically connected to the anode of the light emitting diode E0;

[0812] The gate of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source of the fifth transistor T5 is electrically connected to the first node N1, and the drain of the fifth transistor T5 is electrically connected to the third node N3;

[0813] The display data writing circuit includes a sixth transistor T6, and the first control circuit includes a seventh transistor T7;

[0814] The gate of the sixth transistor T6 is electrically connected to the scan terminal G1, the source of the sixth transistor T6 is electrically connected to the second data line DI, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0815] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the reference voltage terminal, and the drain of the seventh transistor T7 is electrically connected to the second node N2; the reference voltage terminal is used to provide a reference voltage Vref;

[0816] The first reset circuit includes an eighth transistor T8;

[0817] The gate of the eighth transistor T8 is electrically connected to the first reset control terminal RST1, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal, and the drain of the eighth transistor T8 is electrically connected to the second node N2;

[0818] The second reset circuit includes a ninth transistor T9,

[0819] The gate of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0820] The energy storage circuit includes a storage capacitor Cst;

[0821] A first end of the storage capacitor Cst is electrically connected to the first node N1 , and a second end of the storage capacitor Cst is electrically connected to the second node N2 .

[0822] In at least one embodiment of the pixel circuit shown in FIG. 31 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0823] In at least one embodiment of the pixel circuit shown in FIG31 , E0 may be an OLED (organic light emitting diode), a Mini LED (mini light emitting diode), or a Micro LED (micro light emitting diode), but is not limited thereto.

[0824] When working, at least one embodiment of the pixel circuit shown in Figure 31 of the present disclosure delays the writing of the luminous time control data voltage provided by the first data line DT into the pixel circuit to realize PAM (pulse amplitude modulation) + PWM (pulse width modulation) pixel driving.

[0825] In at least one embodiment of the pixel circuit shown in FIG31 of the present disclosure, Vi1 is less than Vdd+Vth, and when the second initial voltage Vi2 is written into N4, T3 can be turned on; wherein Vdd is the voltage value of the high voltage signal provided by VDD, and Vth is the threshold voltage of T0.

[0826] The values ​​of Vdata_I and Vref need to satisfy the driving current of E0 while Vref is less than or equal to Vdata_I to achieve grayscale display;

[0827] In high grayscale display, preferably, Vdata_T is equal to Vdata_I;

[0828] In low grayscale display, when Vdata_T is written into N4, T3 can be turned off.

[0829] As shown in FIG32 , when at least one embodiment of the pixel circuit shown in FIG31 of the present disclosure is in operation, a display cycle (the display cycle may be a frame display time) includes a first display stage S1 and a second display stage S2 that are sequentially arranged;

[0830] The first display stage S1 includes a first reset time period S11, a first writing time period S12, and a first light-emitting time period S13 that are set in sequence; the second display stage S2 includes a second writing time period S22 and a second light-emitting time period S23 that are set in sequence;

[0831] In the first reset period S11, RST provides a low voltage signal, as shown in FIG33A, T8 and T9 are turned on to write the reference voltage Vref into the second node N2 and the first initial voltage Vi1 provided by I1 into the first node N1;

[0832] In the first writing period S12, G1 provides a low voltage signal, as shown in FIG33B , T6 is turned on, DI provides the display data voltage Vdata_I to the second node N2, and T5 is turned on;

[0833] At the beginning of the first writing period S12, T0 is turned on to charge Cst through Vdata_I until the first node N1 becomes Vdd+Vth, and T0 is turned off to perform threshold voltage compensation; Vth is the threshold voltage of T0, and Vdd is the voltage value of the high voltage signal provided by VDD;

[0834] In the first writing period S12, the voltage signal provided by GA, T2 is turned on to write the second initial voltage Vi2 into the fourth node N4, and T3 is turned on;

[0835] In the first light-emitting period S13, EM provides a low voltage signal, as shown in FIG33C , T7 and T4 are turned on, T3 is turned on, and T0 drives E0 to emit light;

[0836] In the first light-emitting period S13, the potential of N2 is Vref. Due to capacitive coupling, the potential of N1 is Vdd+Vth+Vref-Vdata_I. The gate-source voltage Vgs of T0 is equal to Vth+Vref-Vdata_I; Id is equal to K×(Vref-Vdata_I). 2 ; K is the current coefficient of T0; Id is the driving current that T0 drives E0 to emit light;

[0837] In the second writing period S22, the first time t1 is delayed (the first time t1 is the light-emitting time required for the low grayscale), GB outputs a low voltage signal, as shown in FIG33D, T1 is turned on, and DT provides the light-emitting time control data voltage Vdata_T to N4; t1 is the duration of the first light-emitting period S13;

[0838] FIG33E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG31 during the second light-emitting period S23.

[0839] When Vdata_T is a high voltage signal, in the second light-emitting period S23, T3 is turned off, E0 does not emit light, and a short-term light-emitting period is achieved, and the light-emitting period is t1;

[0840] When Vdata_T is a low voltage signal, the optimal voltage value of Vdata_T is the same as the voltage value of Vi2, T3 is turned on, T0 drives E0 to emit light, E0 continues to emit light, and long-term light emission is achieved. The light emission duration is t1+t2, t2 is the second time, and t2 is the duration of the second write time period S22.

[0841] When at least one embodiment of the pixel circuit shown in Figure 31 is in operation, the second control signal provided by GA can be the same as the scanning signal provided by G1, or the second control signal provided by GA can be the same as the reset control signal provided by RST, that is, the second initial voltage Vi2 can be written into N4 in the first reset time period S11 or the first write time period S12, and GA can share the GOA (Gate On Array, a gate drive circuit arranged on the array substrate) circuit with G1 or RST; in addition, since Vi2 is a DC voltage signal, GA can also not use a shift register, and can be turned on for one frame time to reset the potential of N4 of all pixel circuits at once.

[0842] 34A is a schematic diagram showing simulation results of high grayscale display of at least one embodiment of the pixel circuit shown in FIG31 ; FIG34B is a schematic diagram showing simulation results of low grayscale display of at least one embodiment of the pixel circuit shown in FIG31 .

[0843] In at least one embodiment of the present disclosure, Id is the driving current generated at T0.

[0844] As shown in FIG34A , in high grayscale display, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vi2 is equal to -5V, Vdata_I is equal to 4V, Vref is equal to 2V, and Vdata_T is equal to -5V; where Vss is the voltage value of the low voltage signal provided by VSS;

[0845] As shown in FIG34B , in low grayscale display, Vdd is equal to 4.6V, Vss is equal to −3V, Vi1 is equal to −3V, Vi2 is equal to −5V, Vdata_I is equal to 4V, Vref is equal to 2V, and Vdata_T is equal to 5V.

[0846] As shown in FIG35 , when at least one embodiment of the pixel circuit shown in FIG31 is in operation, a display cycle (the display cycle may be one frame time) may include a first display phase and n second display phases arranged in sequence; during a writing period in the first display phase, a display data voltage is written in DI, and during a second display phase, a light emission time control data voltage is written in DT;

[0847] In FIG35 , the first display stage is labeled S1, the first second display stage is labeled S01, the n-1th first display stage is labeled S0n-1, and the nth first display stage is labeled S0n; n is an integer greater than 2;

[0848] The first display stage S1 includes a first reset period S11, a first writing period S12 and a first light-emitting period S13 which are set in sequence;

[0849] The first second display stage S01 includes a first second writing time period S012 and a first second light emitting time period S013 which are set successively;

[0850] The n-1th second display phase S0n-1 includes an n-1th second writing period S0n-12 and an n-1th second light emitting period S0n-13 which are arranged successively;

[0851] The n-th second display phase S0n includes an n-th second writing period S0n2 and an n-th second light-emitting period S0n3 which are arranged successively;

[0852] In the first reset period S11, RST provides a low voltage signal, T8 and T9 are turned on to write the reference voltage Vref into the second node N2 and write the first initial voltage Vi1 provided by I1 into the first node N1;

[0853] In the first writing period S12, G1 provides a low voltage signal, T6 is turned on, DI provides the display data voltage Vdata_I to the second node N2, and T5 is turned on to charge Cst until the first node N1 becomes Vdd+Vth; Vth is the threshold voltage of T0, and Vdd is the voltage value of the high voltage signal provided by VDD;

[0854] In the first writing period S12, the voltage signal provided by GA, T2 is turned on to write the second initial voltage Vi2 into the fourth node N4, and T3 is turned on;

[0855] In the first light-emitting period S13, EM provides a low voltage signal, T7 and T4 are turned on, T3 is turned on, and T0 drives E0 to emit light;

[0856] In the first light-emitting period S13, the potential of N2 is Vref. Due to capacitive coupling, the potential of N1 is Vdd+Vth+Vref-Vdata_I. The gate-source voltage Vgs of T0 is equal to Vth+Vref-Vdata_I; Id is equal to K×(Vref-Vdata_I). 2 ; K is the current coefficient of T0; Id is the driving current that T0 drives E0 to emit light;

[0857] In S012 , EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides a first light-emitting time control data voltage to N4 ;

[0858] When DT provides a low voltage signal at S012, T3 and T4 are turned on at S013, and T0 drives E0 to emit light;

[0859] When DT provides a high voltage signal at S012, T3 is turned off at S013 and E0 does not emit light;

[0860] At S0n-12, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides the n-1th light-emitting time control data voltage to N4;

[0861] When DT provides a low voltage signal at S0n-12, T3 and T4 are turned on at S0n-13, and T0 drives E0 to emit light;

[0862] When DT provides a high voltage signal at S0n-12, T3 is turned off at S0n-13, and E0 does not emit light;

[0863] At S0n2, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides the nth light-emitting time control data voltage to N4;

[0864] When DT provides a low voltage signal at S0n2, T3 is turned on at S0n3, T4 is turned on, and T0 drives E0 to emit light;

[0865] When DT provides a high voltage signal at S0n2, T3 is turned off at S0n3 and E0 does not emit light;

[0866] According to the light emitting time control data voltage provided by DT in each second writing period, it can be determined whether E0 emits light in each second light emitting period.

[0867] As shown in Figure 35, at least one embodiment of the pixel circuit shown in Figure 31, when working, writes the luminous time control data voltage multiple times within one frame time, writes the luminous time control data voltage at a high frequency, divides the low grayscale short-time luminescence into multiple segments of short-time luminescence, realizes low grayscale short-time high-frequency luminescence, reduces the continuous non-luminous time within one frame time, and thus reduces low grayscale flicker, realizes healthy display, and improves display performance.

[0868] In specific implementation, the high-frequency writing of the luminous time control data voltage can be input into multiple groups of first data lines, or a frame is divided into multiple sub-frames and a single first data line is input multiple times, or the second initial voltage and the luminous time control data voltage can be written alternately at high frequency.

[0869] FIG36 is a schematic diagram of the light emission timing of at least one embodiment of the pixel circuit shown in FIG31 during high grayscale light emission and low grayscale light emission;

[0870] As shown in Figure 36, n is equal to 5;

[0871] When performing high grayscale display, the light-emitting duration may be t1+t2+t3+t4+t5+t6;

[0872] When performing low grayscale display, the light emitting time may be t1+t3+t5;

[0873] t1 is the first time, t2 is the second time, t3 is the third time, t4 is the fourth time, t5 is the fifth time, and t6 is the sixth time;

[0874] t1 is the duration of the first light-emitting time period, t2 is the duration of the first second light-emitting time period, t3 is the duration of the second second light-emitting time period, t4 is the duration of the third second light-emitting time period, t5 is the duration of the fourth second light-emitting time period, and t6 is the duration of the fifth second light-emitting time period.

[0875] The difference between at least one embodiment of the pixel circuit shown in FIG37 and at least one embodiment of the pixel circuit shown in FIG31 is that T1 , T2 , T5 , T6 , T8 , and T9 are all NMOS transistors.

[0876] At least one embodiment of the pixel circuit shown in Figure 37 utilizes the low leakage current advantage of oxide thin film transistors to change T8, T6, T9, T5, T1, T2 or part of them into NMOS (N-type metal-oxide-semiconductor) transistors to reduce the leakage of N1, N2, and N4; utilizing the high mobility of PMOS transistors, T0, T3, T4, and T7 are set as PMOS transistors to meet threshold voltage compensation, current drive requirements, and reduce charging time, thereby further improving display performance.

[0877] FIG. 38 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 37 .

[0878] The difference between at least one embodiment of the pixel circuit shown in FIG39 and at least one embodiment of the pixel circuit shown in FIG37 is that all transistors are NMOS transistors.

[0879] At least one embodiment of the pixel circuit shown in FIG39 adopts NMOS TFT technology to implement a pixel circuit with current control + light emission duration control, which can be applied to oxide display products.

[0880] In at least one embodiment of the pixel circuit shown in FIG. 39 , E0 may be a Mini LED or a Micro LED, but is not limited thereto.

[0881] In at least one embodiment of the pixel circuit shown in FIG39 , Vi1 is greater than Vss+Vth, where Vss is the voltage value of the low voltage signal provided by VSS, and Vth is the threshold voltage of T0;

[0882] When Vi2 is written to N4, T3 can be turned on;

[0883] The values ​​of Vdata_I and Vref need to satisfy the driving current of E0 while Vref needs to be greater than or equal to Vdata_I to achieve grayscale display;

[0884] In high grayscale display, preferably, Vdata_T is equal to Vi2;

[0885] In low grayscale display, when Vdata_T inputs N4, T3 needs to be turned off.

[0886] FIG. 40 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 39 .

[0887] In FIG40 , the first display stage is designated as S1 and the second display stage is designated as S2;

[0888] The period marked S11 is a first reset period, the period marked S12 is a first write period, and the period marked S13 is a first light-emitting period;

[0889] The period labeled S22 is the second writing period, and the period labeled S23 is the second light-emitting period.

[0890] Figure 41A is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 39 in the first reset time period S11; Figure 41B is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 39 in the first write time period S12; Figure 41C is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 39 in the first light-emitting time period S13; Figure 41D is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 39 in the second write time period S22; Figure 41E is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 39 in the second light-emitting time period S23.

[0891] FIG42A is a schematic diagram showing simulation results of high grayscale display of at least one embodiment of the pixel circuit shown in FIG39 ; FIG42B is a schematic diagram showing simulation results of low grayscale display of at least one embodiment of the pixel circuit shown in FIG39 .

[0892] As shown in FIG42A , in high grayscale display, Vdd is equal to 7V, Vss is equal to 0V, Vi1 is equal to 8V, Vi2 is equal to 5V, Vdata_I is equal to 2V, Vref is equal to 6V, and Vdata_T is equal to 5V; wherein Vdd is the voltage value of the high voltage signal provided by VDD;

[0893] As shown in FIG42B , in low grayscale display, Vdd is equal to 7V, Vss is equal to 0V, Vi1 is equal to 8V, Vi2 is equal to 5V, Vdata_I is equal to 2V, Vref is equal to 6V, and Vdata_T is equal to −5V.

[0894] The difference between at least one embodiment of the pixel circuit shown in FIG43A and at least one embodiment of the pixel circuit shown in FIG31 is that: a third reset circuit is further included;

[0895] The third reset circuit includes a tenth transistor T10;

[0896] The gate of the tenth transistor T10 is electrically connected to the second reset control terminal RST2, the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the light emitting diode E0; the third initial voltage terminal I3 is used to provide a third initial voltage Vi3.

[0897] At least one embodiment of the pixel circuit shown in FIG. 43A of the present disclosure adds a tenth transistor T10 for resetting the potential of the anode of the light-emitting diode E0, thereby improving display contrast.

[0898] In at least one embodiment of the pixel circuit shown in FIG. 43A of the present disclosure, Vi3-Vss is smaller than Vled, ensuring that when Vi3 is written to the anode of E0, E0 does not emit light; wherein Vss is the voltage value of the low voltage signal provided by VSS, and Vled is the lighting voltage of E0.

[0899] FIG43B is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG43A of the present disclosure.

[0900] FIG43C is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG43A of the present disclosure.

[0901] In FIG43C , the first display stage is designated as S1 and the second display stage is designated as S2;

[0902] The period marked S11 is a first reset period, the period marked S12 is a first write period, and the period marked S13 is a first light-emitting period;

[0903] The period marked S21 is a second reset period, the period marked S22 is a second write period, and the period marked S23 is a second light-emitting period.

[0904] As shown in FIG43C , when at least one embodiment of the pixel circuit shown in FIG43A of the present disclosure is in operation, in the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal, and T11 is turned on to write the second initial voltage Vi2 provided by I2 into the anode of E0, so as to be able to clear the residual charge on the anode of E0 at high frequency and improve display flicker.

[0905] Based on at least one embodiment of the pixel circuit shown in Figure 37 and at least one embodiment of the pixel circuit shown in Figure 39, a third reset circuit can be added, and the third reset circuit can include a tenth transistor; the gate of the tenth transistor is electrically connected to the second reset control terminal, the source of the tenth transistor is electrically connected to the third initial voltage terminal, and the drain of the tenth transistor is electrically connected to the cathode of the light-emitting diode.

[0906] As shown in FIG44 , based on at least one embodiment of the pixel circuit shown in FIG23 , the light emitting element is a light emitting diode E0;

[0907] The driving circuit includes a driving transistor T0; the energy storage circuit includes a storage capacitor Cst; the first light-emitting control circuit includes an eleventh transistor T11; the second light-emitting control circuit includes a twelfth transistor T12; the switch control circuit includes a third transistor T3; the compensation control circuit includes a fifth transistor T5; and the display data writing circuit includes a sixth transistor T6;

[0908] A first end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor Cst is electrically connected to the high voltage terminal VDD; the gate of the driving transistor T0 is electrically connected to the first node N1;

[0909] The gate of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source of the eleventh transistor T11 is electrically connected to the high voltage terminal VDD, and the drain of the eleventh transistor T11 is electrically connected to the source of the driving transistor T0;

[0910] The gate of the twelfth transistor T12 is electrically connected to the light emitting control terminal EM, the source of the twelfth transistor T12 is electrically connected to the drain of the driving transistor T0, and the drain of the twelfth transistor T12 is electrically connected to the source of the third transistor T3;

[0911] The gate of the third transistor T3 is electrically connected to the switch control terminal N4, and the drain of the third transistor T4 is electrically connected to the anode of the light emitting diode E0;

[0912] The gate of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0, and the drain of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0;

[0913] The gate of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source of the sixth transistor T6 is electrically connected to the second data line DI, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor T0;

[0914] The first reset circuit includes an eighth transistor T8;

[0915] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal RST2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the light emitting diode E0; the third initial voltage terminal I3 is used to provide a third initial voltage Vi3;

[0916] The second reset circuit includes a ninth transistor T9;

[0917] The gate of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0918] The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0919] The gate of the first transistor T1 is electrically connected to the first control terminal GB, the source of the first transistor T1 is electrically connected to the first data line DT, and the drain of the first transistor T1 is electrically connected to the switch control terminal N4;

[0920] The gate of the second transistor T2 is electrically connected to the second control terminal GA, the source of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0921] A first end of the first capacitor C1 is electrically connected to the switch control terminal N4 , and a second end of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0922] In at least one embodiment of the pixel circuit shown in FIG. 44 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0923] In at least one embodiment of the pixel circuit shown in FIG44 , the contrast is improved and the display performance is enhanced by setting the eighth transistor to be reset by the potential of the anode of the light-emitting diode E0.

[0924] When at least one embodiment of the pixel circuit shown in Figure 44 is in operation, the second control signal provided by GA can be the same as the scanning signal provided by G1, or the second control signal provided by GA can be the same as the second reset control signal provided by RST2, that is, the second initial voltage Vi2 can be written into N4 in the first reset time period S11 or the first write time period S12, and GA can share the GOA (Gate On Array, a gate drive circuit arranged on the array substrate) circuit with G1 or RST; the number of control signals can be reduced, and the proportion of control signal writing time can be reduced.

[0925] As shown in FIG45A , when at least one embodiment of the pixel circuit shown in FIG44 is in operation, a display period (the display period may be one frame time) may include a first display phase S1 and a second display phase S2 that are sequentially arranged;

[0926] The first display stage S1 may include a first reset time period S11, a first writing time period S12, and a first light-emitting time period S13 that are set in sequence; the second display stage S2 may include a second writing time period S22 and a second light-emitting time period S23 that are set in sequence;

[0927] In the first reset period S11, RST1 provides a low voltage signal, RST2 provides a low voltage signal, T9 and T8 are turned on, and the anode of the first node N1 and E0 are reset;

[0928] In the first writing period S12, G1 provides a low voltage signal, T6 is turned on, DI writes the display data voltage to the first node N1, and T5 is turned on;

[0929] At the beginning of the first writing period S12, T0 is turned on and Cst is charged by the display data voltage until T0 is turned off and the gate voltage of T0 becomes Vdd+Vth, and threshold voltage compensation is performed; wherein Vdd is the voltage value of the high voltage signal provided by VDD, and Vth is the threshold voltage of T0;

[0930] In the first writing period S12, GA provides a low voltage signal, T2 is turned on, the second initial voltage Vi2 provided by I2 is written into N4, and T3 is turned on;

[0931] In the first light-emitting period S13, EM provides a low voltage signal, T11 and T12 are turned on, and T0 drives E0 to emit light;

[0932] In the second writing period S22, the first time t1 is delayed, GB provides a low voltage signal, T1 is turned on, and DT provides a light-emitting time control data voltage Vdata_T to N4; t1 is the duration of the first light-emitting period S13;

[0933] When Vdata_T is a high voltage signal, in the second light-emitting period S23, T3 is turned off, E0 does not emit light, and a short-term light-emitting period is achieved, and the light-emitting period is t1;

[0934] When Vdata_T is a low voltage signal, the optimal voltage value of Vdata_T is the same as the voltage value of Vi2. In the second luminous period S23, T3 is turned on, T0 drives E0 to emit light, and E0 continues to emit light to achieve long-term luminescence. The luminous duration is t1+t2, t2 is the second time, and t2 is the duration of the second luminous period S23.

[0935] FIG. 45B is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 44 .

[0936] In FIG45B , the period labeled S21 is the second reset period;

[0937] In the first reset period S11 and the second reset period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the anode of E0, so as to clear the residual charge of the anode of E0 at high frequency and improve display flicker.

[0938] As shown in FIG46 , based on at least one embodiment of the pixel circuit shown in FIG24 , the light emitting element is a light emitting diode E0;

[0939] The driving circuit includes a driving transistor T0; the energy storage circuit includes a storage capacitor Cst; the first light-emitting control circuit includes an eleventh transistor T11; the second light-emitting control circuit includes a twelfth transistor T12; the switch control circuit includes a third transistor T3; the compensation control circuit includes a fifth transistor T5; and the display data writing circuit includes a sixth transistor T6;

[0940] The anode of the light emitting diode E0 is electrically connected to the high voltage terminal VDD;

[0941] A first end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor Cst is electrically connected to the low voltage terminal VSS; the gate of the driving transistor T0 is electrically connected to the first node N1;

[0942] The gate of the third transistor T3 is electrically connected to the switch control terminal N4, the drain of the third transistor T3 is electrically connected to the cathode of the light emitting diode E1, and the source of the third transistor T3 is electrically connected to the drain of the eleventh transistor T11;

[0943] The gate of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, and the source of the eleventh transistor T11 is electrically connected to the drain of the driving transistor T0;

[0944] The gate of the twelfth transistor T12 is electrically connected to the light emitting control terminal EM, the drain of the twelfth transistor T12 is electrically connected to the source of the driving transistor T0, and the source of the twelfth transistor T12 is electrically connected to the low voltage terminal VSS;

[0945] The gate of the fifth transistor T5 is electrically connected to the scanning terminal G1, the drain of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0, and the drain of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0;

[0946] The gate of the sixth transistor T6 is electrically connected to the scanning terminal G1, the drain of the sixth transistor T6 is electrically connected to the second data line DI, and the source of the sixth transistor T6 is electrically connected to the source of the driving transistor T0;

[0947] The first reset circuit includes an eighth transistor T8;

[0948] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal RST2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the cathode of the light emitting diode E0;

[0949] The second reset circuit includes a ninth transistor T9;

[0950] The gate of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide a first initial voltage Vi1;

[0951] The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0952] The gate of the first transistor T1 is electrically connected to the first control terminal GB, the source of the first transistor T1 is electrically connected to the first data line DT, and the drain of the first transistor T1 is electrically connected to the switch control terminal N4;

[0953] The gate of the second transistor T2 is electrically connected to the second control terminal GA, the source of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0954] A first end of the first capacitor C1 is electrically connected to the switch control terminal N4 , and a second end of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0955] In at least one embodiment of the pixel circuit shown in FIG. 46 , all transistors are NMOS transistors, but the present invention is not limited thereto.

[0956] FIG. 47A is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 46 .

[0957] In FIG47A , the first display stage is designated as S1 and the second display stage is designated as S2;

[0958] The period marked S11 is a first reset period, the period marked S12 is a first write period, and the period marked S13 is a first light-emitting period;

[0959] The period labeled S22 is the second writing period, and the period labeled S23 is the second light-emitting period.

[0960] Figure 48A is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 46 in the first reset time period S11; Figure 48B is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 46 in the first write time period S12; Figure 48C is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 46 in the first light-emitting time period S13; Figure 48D is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 46 in the second write time period S22; Figure 48E is a schematic diagram of the working status of at least one embodiment of the pixel circuit shown in Figure 46 in the second light-emitting time period S23.

[0961] FIG. 47B is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 46 .

[0962] In FIG47B , the period labeled S21 is the second reset period;

[0963] In the first reset period S11 and the second reset period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the cathode of E0, so as to clear the residual charge of the cathode of E0 at high frequency and improve display flicker.

[0964] In at least one embodiment of the present disclosure, when the potential of the cathode of E0 is initialized, E0 does not emit light.

[0965] The difference between at least one embodiment of the pixel circuit shown in Figure 49 and at least one embodiment of the pixel circuit shown in Figure 44 is that T9, T8, T5, T6, T1 and T2 are NMOS TFTs, T9, T8, T5, T6, T1 and T2 are oxide TFTs, and T0, T11, T12 and T3 are PMOS TFTs.

[0966] At least one embodiment of the pixel circuit shown in Figure 49 adopts LTPO technology, taking advantage of the low leakage current of oxide TFT to reduce the leakage of the anode of the first node N1 and E0, and setting T9, T8, T5, T6, T1 and T2 as NMOS TFTs; taking advantage of the high mobility of PMOS TFT, setting T0, T11, T12 and T3 as PMOS TFTs, meeting the threshold voltage compensation and current driving requirements and reducing the charging time, thereby further improving the display performance.

[0967] FIG50A is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG49 . In FIG50 , S1 represents the first display phase, and S2 represents the second display phase.

[0968] The period marked S11 is a first reset period, the period marked S12 is a first write period, and the period marked S13 is a first light-emitting period;

[0969] The period labeled S22 is the second writing period, and the period labeled S23 is the second light-emitting period.

[0970] FIG50B is a second operation timing diagram of at least one embodiment of the pixel circuit shown in FIG49 ; in FIG50B , the period labeled S21 is a second reset period;

[0971] In the first reset period S11 and the second reset period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the anode of E0, so as to clear the residual charge of the anode of E0 at high frequency and improve display flicker.

[0972] As shown in FIG51 , based on at least one embodiment of the pixel circuit shown in FIG24 , the light emitting element is a light emitting diode E0;

[0973] The energy storage circuit includes a storage capacitor Cst, the compensation circuit includes a thirteenth transistor T13, the switch circuit includes a first switch K1; the drive circuit includes a drive transistor T0;

[0974] A first end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor Cst is electrically connected to the drain of the driving transistor T0; the gate of the driving transistor T0 is electrically connected to a first node N1; the drain of the driving transistor T0 is electrically connected to an anode of E0; and the anode of E0 is electrically connected to a second node N2;

[0975] The gate of the thirteenth transistor T13 is electrically connected to the scanning terminal G1, the source of the thirteenth transistor T13 is electrically connected to the anode of E0, and the drain of the thirteenth transistor T13 is electrically connected to the control node N0;

[0976] The control terminal of the first switch K1 is electrically connected to the first selection control terminal X1, the first terminal of the first switch K1 is electrically connected to the control node N0, and the second terminal of the first switch K1 is electrically connected to a reference voltage terminal; the reference voltage terminal provides a reference voltage Vref;

[0977] The switch circuit further includes a second switch K2;

[0978] a control end of the second switch K2 electrically connected to the second selection control end X2, a first end of the second switch K2 electrically connected to the control node N0, and a second end of the second switch K2 electrically connected to the compensation end SENS;

[0979] The display data writing circuit includes a sixth transistor T6;

[0980] The gate of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source of the sixth transistor T6 is electrically connected to the second data line DI, and the drain of the sixth transistor T6 is electrically connected to the gate of the driving transistor T0;

[0981] The switch control circuit includes a third transistor T3;

[0982] The gate of T3 is electrically connected to the switch control terminal N4, the source of T4 is electrically connected to the high voltage terminal VDD, the drain of T4 is electrically connected to the source of T0; the cathode of E0 is electrically connected to the low voltage terminal VSS;

[0983] The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1;

[0984] The gate of the first transistor T1 is electrically connected to the first control terminal GB, the source of the first transistor T1 is electrically connected to the first data line DT, and the drain of the first transistor T1 is electrically connected to the switch control terminal N4;

[0985] The gate of the second transistor T2 is electrically connected to the scanning terminal G1, the source of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is used to provide a second initial voltage Vi2;

[0986] A first end of the first capacitor C1 is electrically connected to the switch control terminal N4 , and a second end of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0987] In at least one embodiment of the pixel circuit shown in FIG. 51 , the second control end is the scanning end G1 , but the present invention is not limited thereto.

[0988] In at least one embodiment of the pixel circuit shown in FIG. 51 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0989] In at least one embodiment of the pixel circuit shown in FIG51 , T6 , K1 , and K2 constitute an extraction circuit for extracting Vth and Id.

[0990] As shown in FIG52 , when at least one embodiment of the pixel circuit shown in FIG51 of the present disclosure is in operation, a display cycle may include a display phase SX and a sensing phase SC;

[0991] The display stage SX includes a first writing time period S12, a first light emitting time period S13, a second writing time period S21 and a second light emitting time period S22 which are arranged in sequence;

[0992] The sensing phase SC includes a reset period SC1, a compensation period SC2 and an extraction period SC3 which are set in sequence;

[0993] In the first writing period S12, G1 provides a low voltage signal, T6 and T2 are turned on, DI provides the display data voltage Vdata_I, Vdata_I is written into the first node N1, T0 is turned on, the second initial voltage Vi2 provided by I2 is written into N4 through T2; T3 is turned on;

[0994] In the first light-emitting period S13, G1 provides a high voltage signal, T3 is turned on, and T0 drives E0 to emit light; the first light-emitting period S13 lasts for the first time t1;

[0995] In the second writing period S21, GB provides a low voltage signal, T1 is turned on, and DT provides a light emitting control data voltage;

[0996] As shown in FIG52 , in the second writing period S21 , the light emitting control data voltage provided by DT is a high voltage signal;

[0997] In the second lighting period S22, T3 is turned off and E0 is not illuminated, achieving short-duration lighting, with the lighting duration being t1;

[0998] When the light-emitting control data voltage provided by DT is a low voltage signal in the second writing period S21, T3 is turned on in the second light-emitting period S22, and T0 drives E0 to emit light, realizing long-time light emission. The light-emitting time is t1+t2, where t2 is the duration of the second light-emitting period S22;

[0999] As shown in FIG52 , in the reset period SC1 , G1 provides a low voltage signal, T13 , T0 , T6 , T3 , and T2 are turned on, K1 is turned on, and N2 is reset through Vref; DI provides a data voltage Vdata to the first node N1;

[1000] During the compensation period SC2, K1 is closed, Vref is less than Vdata, and Vdata is less than Vdd, where Vdd is the voltage value of the high voltage signal provided by VDD. When the potential of N2 is Vdata-Vth, the gate-source voltage of T0 is equal to Vth, where Vth is the threshold voltage of T0. T0 is turned off, and Vth is written into N2.

[1001] In the extraction period SC3, K2 is turned on and the IC (integrated circuit) extracts Vth through SENS.

[1002] As shown in FIG. 52 , in a period other than the second writing period, DT may provide the second initial voltage Vi2 , but is not limited thereto.

[1003] FIG53A is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a first writing period S12 and a first light emitting period S22;

[1004] FIG53B is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a second writing period S21 and a second light-emitting period S22;

[1005] FIG53C is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a reset period SC1;

[1006] FIG53D is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during a compensation period SC2;

[1007] FIG53E is a schematic diagram illustrating the operating state of at least one embodiment of the pixel circuit shown in FIG51 during the extraction time period SC3.

[1008] FIG54A is a schematic diagram showing simulation results of high grayscale display during the display phase of at least one embodiment of the pixel circuit shown in FIG51 ;

[1009] FIG. 54B is a schematic diagram showing simulation results of low grayscale display during the display phase of at least one embodiment of the pixel circuit shown in FIG. 51 .

[1010] The difference between at least one embodiment of the pixel circuit shown in FIG55 and at least one embodiment of the pixel circuit shown in FIG51 is that all transistors are NMOS TFTs to implement a pixel circuit with drive current control and light emission duration control.

[1011] At least one embodiment of the pixel circuit shown in FIG. 55 can be applied to oxide display products.

[1012] FIG56 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG55 .

[1013] The difference between at least one embodiment of the pixel circuit shown in Figure 57 and at least one embodiment of the pixel circuit shown in Figure 51 is that: T13, T1 and T2 are NMOS TFTs, T6, T0 and T3 are PMOS TFTs; the gate of T2 and the gate of T13 are both electrically connected to the second control terminal GA.

[1014] At least one embodiment of the pixel circuit shown in Figure 57 is an LTPO pixel circuit, which adopts LTPO technology and takes advantage of the low leakage current of oxide TFT and the high mobility of PMOS TFT. T13, T1 and T2 are set as NMOS TFT, and T6, T0 and T3 are set as PMOS TFT to meet the threshold voltage compensation, current drive and PPI (current density) requirements, thereby further improving the display performance.

[1015] FIG58 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG57 .

[1016] The pixel circuit according to the embodiment of the present disclosure includes a light-emitting element, a driving circuit, a first reset circuit and a data writing circuit;

[1017] The control terminal of the driving circuit is electrically connected to the first node, the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of the first node;

[1018] The data writing circuit is electrically connected to the writing control terminal and the writing node respectively, and is used to provide the display data voltage and the light emitting time control data voltage to the writing node in sequence under the control of the writing control signal provided by the writing control terminal;

[1019] The first reset circuit is electrically connected to a first reset control terminal, a first initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element under the control of a first reset control signal provided by the first reset control terminal during a reset period set between a period for writing the display data voltage and a period for writing the light-emitting time control data voltage.

[1020] When the pixel circuit according to the embodiment of the present disclosure is in operation, a display cycle (the display cycle may include one frame time) includes a first display phase and a second display phase that are set in sequence, wherein the first display phase includes a first writing time period; and the second display phase includes a reset time period and a second writing time period that are set in sequence;

[1021] During the first writing period, the data writing circuit provides a display data voltage to the writing node under the control of a writing control signal;

[1022] In the reset period, the first reset circuit writes the first initial voltage into the first electrode of the light emitting element under the control of the first reset control signal;

[1023] In the second writing period, the data writing circuit provides a light emitting time control data voltage to the writing node under the control of the writing control signal.

[1024] In a specific implementation, when the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a reset time period set between the time period for writing the display data voltage and the time period for writing the luminous time control data voltage, the first reset circuit, under the control of a first reset control signal, writes a first initial voltage to the first electrode of the light-emitting element to release the residual charge on the first electrode of the light-emitting element and improve display uniformity.

[1025] When the pixel circuit according to the embodiment of the present disclosure is in operation, the reset time period may be a second reset time period, and the first display phase may include a first reset time period set before the first writing time period;

[1026] In the first reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light-emitting element under the control of a first reset control signal to release residual charge in the first electrode of the light-emitting element and improve display uniformity.

[1027] When the pixel circuit described in the embodiment of the present disclosure is in operation, in the first reset time period and the second reset time period, the first reset circuit writes the first initial voltage into the first electrode of the light-emitting element under the control of the first reset control signal, so as to release the residual charge on the first electrode of the light-emitting element at a high frequency and improve the display uniformity.

[1028] In at least one embodiment of the present disclosure, the first end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the write node is electrically connected to the second end of the driving circuit; or, the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the write node is electrically connected to the first end of the driving circuit.

[1029] Optionally, the light-emitting element is an inorganic light-emitting diode, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[1030] In at least one embodiment of the present disclosure, the aspect ratio of a transistor is a ratio of a channel width W to a channel length L of the transistor.

[1031] In a specific implementation, the light emitting element may be an inorganic light emitting diode, and the aspect ratio of the transistor included in the driving circuit may be greater than 0.5.

[1032] In at least one embodiment of the present disclosure, the light-emitting element may be an inorganic light-emitting diode, but is not limited thereto; for example, the light-emitting element may be a micro light-emitting diode or a mini light-emitting diode.

[1033] In a specific implementation, the light emitting element may also be an organic light emitting diode.

[1034] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[1035] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second reset control signal provided by the second reset control terminal during the reset time period.

[1036] In a specific implementation, the driving circuit may further include a second reset circuit, and in the second reset time period, the second reset circuit writes a second initial voltage into the first node under the control of a second reset control signal;

[1037] The second reset circuit also writes a second initial voltage into the first node under the control of a second reset control signal during the first reset period;

[1038] The first display stage may further include a first light-emitting period set after the first writing period, and the second display stage may further include a second light-emitting period set after the second writing period, in which the driving circuit drives the light-emitting element to emit light according to the display data voltage in the first light-emitting period, and in which the driving circuit controls the data voltage according to the light-emitting time to drive the light-emitting element to emit light in the second light-emitting period;

[1039] At least one embodiment of the present disclosure resets the potential of the first node N1 before the first write time period and before the second write time period, so that when the display data voltage and the luminous time control data voltage have the same voltage value, the difference between the driving current generated by the driving circuit in the first luminous time period and the driving current generated by the driving circuit in the second luminous time period is reduced, thereby reducing the brightness difference between the first luminous time period and the second luminous time period in the same frame time.

[1040] Optionally, the first reset control end and the second reset control end may be the same reset control end, but the present invention is not limited thereto. In actual operation, the first reset control end and the second reset control end may be different reset control ends.

[1041] In at least one embodiment of the present disclosure, the write control terminal includes a first control terminal and a second control terminal, and the data write circuit is further electrically connected to the first data line and the second data line, respectively; the display cycle of the pixel circuit includes a first write time period and a second write time period set successively;

[1042] The data write circuit is used to write the display data voltage provided by the second data line to the write node under the control of the second control signal provided by the second control terminal during the first write time period, and is used to write the luminous time control data voltage provided by the first data line to the write node under the control of the first control signal provided by the first control terminal during the second write time period.

[1043] In a specific implementation, the write control end may include a first control end and a second control end. In the first write time period, the data write circuit writes the display data voltage provided by the second data line to the write node under the control of the second control signal. In the second write time period, the data write circuit writes the luminous time control data voltage provided by the first data line to the write node under the control of the first control signal.

[1044] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit, and a compensation control circuit;

[1045] The first light emitting control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is used to control the communication between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[1046] The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit, and the first electrode of the light emitting element, respectively, and is used to control the second terminal of the driving circuit to be connected to the first electrode of the light emitting element under the control of the light emitting control signal; the second electrode of the light emitting element is electrically connected to the second voltage terminal;

[1047] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end;

[1048] The first electrode of the light-emitting element is the first pole of the light-emitting element.

[1049] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, a second light-emitting control circuit and a compensation control circuit; the first light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of a light-emitting control signal; the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a scanning signal to perform threshold voltage compensation.

[1050] In at least one embodiment of the present disclosure, the light-emitting element is an inorganic light-emitting diode, the width-to-length ratio of the transistor included in the first light-emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light-emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[1051] In a specific implementation, the light-emitting element can be an inorganic light-emitting diode, the aspect ratio of the transistor included in the first light-emitting control circuit can be greater than 1, the aspect ratio of the transistor included in the second light-emitting control circuit can be greater than 1, and the aspect ratio of the transistor included in the driving circuit can be greater than 0.5.

[1052] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[1053] In at least one embodiment of the present disclosure, the pixel circuit may further include an energy storage circuit, wherein the energy storage circuit is electrically connected to the first node and is configured to store electrical energy.

[1054] Optionally, the energy storage circuit includes a storage capacitor; the light emitting element is an inorganic light emitting diode;

[1055] The capacitance of the storage capacitor is greater than three times the gate-source capacitance of the transistor in the driving circuit.

[1056] In a specific implementation, the energy storage circuit may include a storage capacitor; the light emitting element may be an inorganic light emitting diode;

[1057] The capacitance of the storage capacitor may be greater than three times the gate-source capacitance of the transistor in the driving circuit.

[1058] In a specific implementation, the capacitance value of the storage capacitor is set to be greater than 3 times the gate-source capacitance of the transistor in the driving circuit, so that when the source potential of the transistor in the driving circuit changes, the gate potential of the transistor in the driving circuit can be maintained to ensure display accuracy.

[1059] In at least one embodiment of the present disclosure, the gate-source capacitance of the transistor in the driving circuit may be a parasitic capacitance between the gate and the source of the transistor in the driving circuit, which may be calculated based on the facing area of ​​the gate and the source of the transistor in the driving circuit, and the dielectric constant, wherein the dielectric constant may be calculated based on the material and thickness of the insulating layer between the gate and the source of the transistor in the driving circuit.

[1060] As shown in FIG59 , the pixel circuit according to at least one embodiment of the present disclosure includes a light-emitting element E1, a tank circuit 10, a driving circuit 11, a first reset circuit 14, a data writing circuit 15, a second reset circuit 51, a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a compensation control circuit 32; the writing control terminal includes a first control terminal GB and a second control terminal GA;

[1061] The energy storage circuit 10 is electrically connected to the first node N1 and is used to store electrical energy;

[1062] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[1063] The data writing circuit 15 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second data line DI, and the first terminal of the driving circuit 11, respectively, and is used to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the second control signal provided by the second control terminal GA, and is used to write the light-emitting time control data voltage provided by the first data line DT into the first terminal of the driving circuit 11 under the control of the first control signal provided by the first control terminal GB;

[1064] The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1, and the first electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset period between a period for writing the display data voltage and a period for writing the light-emission time control data voltage.

[1065] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1, and the first terminal of the driving circuit 11, respectively, and is used to control the communication between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[1066] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11, and the first electrode of the light emitting element E1, respectively, and is used to control the second terminal of the driving circuit 11 to communicate with the first electrode of the light emitting element E1 under the control of the light emitting control signal; the second electrode of the light emitting element 31 is electrically connected to the second voltage terminal V2;

[1067] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the second terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[1068] The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the reset control signal provided by the reset control terminal RST during the reset time period.

[1069] In at least one embodiment of the present disclosure, the light-emitting element may be a light-emitting diode, the first electrode of the light-emitting element may be an anode of the light-emitting diode, and the second electrode of the light-emitting element may be a cathode of the light-emitting diode;

[1070] The light emitting diode may be an organic light emitting diode, a mini light emitting diode or a micro light emitting diode.

[1071] In at least one embodiment of the pixel circuit shown in Figure 59, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, the first electrode of the light-emitting element is the first pole of the light-emitting element, and the write node is electrically connected to the first end of the driving circuit, but is not limited to this.

[1072] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit, and a compensation control circuit;

[1073] The first electrode of the light emitting element is electrically connected to the first voltage terminal;

[1074] The first light emitting control circuit is electrically connected to the light emitting control terminal, the second electrode of the light emitting element, and the first terminal of the driving circuit, respectively, and is used to control the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[1075] The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit, and the second voltage terminal respectively, and is used to control the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal;

[1076] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the first end of the driving circuit respectively, and is used to control the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal provided by the scanning end.

[1077] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, a second light-emitting control circuit and a compensation control circuit; the first light-emitting control circuit controls the connection between the second pole of the light-emitting element and the first end of the driving circuit under the control of a light-emitting control signal; the second light-emitting control circuit controls the connection between the second end of the driving circuit and the second voltage end under the control of the light-emitting control signal; the compensation control circuit controls the connection between the control end of the driving circuit and the first end of the driving circuit under the control of a scanning signal to perform threshold voltage compensation.

[1078] As shown in FIG60 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1, a tank circuit 10, a driving circuit 11, a first reset circuit 14, a data writing circuit 15, a second reset circuit 51, a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a compensation control circuit 32; the writing control terminal includes a first control terminal GB and a second control terminal GA;

[1079] The energy storage circuit 10 is electrically connected to the first node N1 and is used to store electrical energy;

[1080] The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[1081] The control terminal of the driving circuit 11 is electrically connected to the first node N1. The driving circuit 11 is electrically connected to the second electrode of the light-emitting element E1 through the first light-emitting control circuit 61. The driving circuit 11 is configured to generate a driving current for driving the light-emitting element E1 under the control of the potential of the first node N1.

[1082] The data writing circuit 15 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second data line DI, and the second terminal of the driving circuit 11, respectively, and is used to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the second control signal provided by the second control terminal GA, and is used to write the light-emitting time control data voltage provided by the first data line DT into the second terminal of the driving circuit 11 under the control of the first control signal provided by the first control terminal GB;

[1083] The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1, and the second electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light-emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset period set between a period for writing the display data voltage and a period for writing the light-emission time control data voltage.

[1084] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second electrode of the light emitting element E1, and the first terminal of the driving circuit 11, respectively, and is configured to control the second electrode of the light emitting element E1 to communicate with the first terminal of the driving circuit 11 under the control of a light emitting control signal provided by the light emitting control terminal EM;

[1085] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11, and the second voltage terminal V2, respectively, and is used to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal;

[1086] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the first terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[1087] The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the reset control signal provided by the reset control terminal RST during the reset time period.

[1088] In at least one embodiment of the pixel circuit shown in Figure 60, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, the first electrode of the light-emitting element is the second electrode of the light-emitting element, and the write node is electrically connected to the second end of the driving circuit, but is not limited to this.

[1089] As shown in FIG61 , the pixel circuit according to at least one embodiment of the present disclosure includes a light-emitting element E1, a tank circuit 10, a driving circuit 11, a first reset circuit 14, a data writing circuit 15, a second reset circuit 51, a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a compensation control circuit 32; the writing control terminal includes a first control terminal GB and a second control terminal GA;

[1090] The energy storage circuit 10 is electrically connected to the first node N1 and is used to store electrical energy;

[1091] The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[1092] The data writing circuit 15 is electrically connected to the scanning terminal G1, the data line D0 and the first terminal of the driving circuit 11 respectively, and is used to write the display data voltage and the light-emitting time control data voltage provided by the data line D0 into the first terminal of the driving circuit 11 in sequence under the control of the scanning signal provided by the scanning terminal G1;

[1093] The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1, and the first electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset period between a period for writing the display data voltage and a period for writing the light-emission time control data voltage.

[1094] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1, and the first terminal of the driving circuit 11, respectively, and is used to control the communication between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[1095] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11, and the first electrode of the light emitting element E1, respectively, and is used to control the second terminal of the driving circuit 11 to communicate with the first electrode of the light emitting element E1 under the control of the light emitting control signal; the second electrode of the light emitting element 31 is electrically connected to the second voltage terminal V2;

[1096] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the second terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[1097] The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the reset control signal provided by the reset control terminal RST during the reset time period.

[1098] In at least one embodiment of the pixel circuit shown in Figure 61, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, and the first electrode of the light-emitting element is the second electrode of the light-emitting element.

[1099] As shown in FIG62 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1, a tank circuit 10, a driving circuit 11, a first reset circuit 14, a data writing circuit 15, a second reset circuit 51, a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a compensation control circuit 32; the writing control terminal includes a first control terminal GB and a second control terminal GA;

[1100] The energy storage circuit 10 is electrically connected to the first node N1 and is used to store electrical energy;

[1101] The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[1102] The control terminal of the driving circuit 11 is electrically connected to the first node N1. The driving circuit 11 is electrically connected to the second electrode of the light-emitting element E1 through the first light-emitting control circuit 61. The driving circuit 11 is configured to generate a driving current for driving the light-emitting element E1 under the control of the potential of the first node N1.

[1103] The data writing circuit 15 is electrically connected to the scanning terminal G1, the data line D0 and the second terminal of the driving circuit 11 respectively, and is used to write the display data voltage and the light-emitting time control data voltage provided by the data line D0 into the second terminal of the driving circuit 11 in sequence under the control of the scanning signal provided by the scanning terminal G1;

[1104] The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1, and the second electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light-emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset period set between a period for writing the display data voltage and a period for writing the light-emission time control data voltage.

[1105] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second electrode of the light emitting element E1, and the first terminal of the driving circuit 11, respectively, and is configured to control the second electrode of the light emitting element E1 to communicate with the first terminal of the driving circuit 11 under the control of a light emitting control signal provided by the light emitting control terminal EM;

[1106] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11, and the second voltage terminal V2, respectively, and is used to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal;

[1107] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the first terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[1108] The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the reset control signal provided by the reset control terminal RST during the reset time period.

[1109] In at least one embodiment of the pixel circuit shown in Figure 62, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, and the first electrode of the light-emitting element is the second electrode of the light-emitting element.

[1110] In at least one embodiment of the pixel circuit shown in FIG. 61 and FIG. 62 , the data writing circuit may include a tenth transistor;

[1111] The gate of the tenth transistor is electrically connected to the scan end, the first electrode of the tenth transistor is electrically connected to the data line, and the tenth transistor is electrically connected to the first end of the driving circuit or the second end of the driving circuit.

[1112] In at least one embodiment of the present disclosure, the write node includes a first write node and a second write node;

[1113] The first write node is electrically connected to the first end of the drive circuit; the pixel circuit also includes a switch control circuit; the second end of the drive circuit is electrically connected to the first electrode of the light-emitting element through the switch control circuit, and the switch control circuit is electrically connected to the switch control end, and the switch control circuit is used to control the connection between the second end of the drive circuit and the first electrode of the light-emitting element under the control of the potential of the switch control end; the second write node is electrically connected to the switch control end.

[1114] In at least one embodiment of the present disclosure, the write node includes a first write node and a second write node;

[1115] The first write node is electrically connected to the second end of the drive circuit; the pixel circuit also includes a switch control circuit; the first end of the drive circuit is electrically connected to the first electrode of the light-emitting element through the switch control circuit, and the switch control circuit is electrically connected to the switch control end, and the switch control circuit is used to control the connection between the first end of the drive circuit and the first electrode of the light-emitting element under the control of the potential of the switch control end; the second write node is electrically connected to the switch control end.

[1116] Optionally, the light-emitting element is an inorganic light-emitting diode, the aspect ratio of the transistor included in the switch control circuit is greater than 1, and the aspect ratio of the transistor included in the drive circuit is greater than 0.5.

[1117] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the aspect ratio of the transistor included in the switch control circuit may be greater than 1, and the aspect ratio of the transistor included in the drive circuit may be greater than 0.5.

[1118] In at least one embodiment of the present disclosure, the data writing circuit includes a first writing sub-circuit and a second writing sub-circuit; the writing control terminal includes a scanning terminal and a first control terminal;

[1119] The first writing sub-circuit is electrically connected to the first control terminal, the first data line and the second writing node respectively, and is used to write the light-emitting time control data voltage provided by the first data line into the second writing node under the control of the first control signal provided by the first control terminal;

[1120] The second writing sub-circuit is electrically connected to the scanning end, the second data line and the first writing node respectively, and is used to write the display data voltage provided by the second data line into the first writing node under the control of the scanning signal provided by the scanning end.

[1121] In a specific implementation, the data write circuit may include a first write sub-circuit and a second write sub-circuit. The first write sub-circuit, under the control of a first control signal, writes the luminous time control data voltage provided by the first data line into the second write node; the second write sub-circuit, under the control of the scan signal, writes the display data voltage provided by the second data line into the first write node.

[1122] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit, an initialization circuit, and a voltage maintenance circuit;

[1123] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of a second reset control signal provided by the second reset control terminal;

[1124] The initialization circuit is electrically connected to the second control terminal, the third initial voltage terminal and the second write node respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second write node under the control of the second control signal provided by the second control terminal;

[1125] The voltage maintaining circuit is electrically connected to the switch control terminal and is used to maintain the potential of the switch control terminal.

[1126] In a specific implementation, the pixel circuit may further include a second reset circuit and an initialization circuit; the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the first node under the control of a second reset control signal; the initialization circuit writes into the second write node under the control of a second control signal.

[1127] Optionally, the voltage maintaining circuit may include a second capacitor;

[1128] A first end of the second capacitor is electrically connected to the switch control end, and a second end of the second capacitor is electrically connected to the DC voltage end.

[1129] In at least one embodiment of the present disclosure, the DC voltage terminal may be a common electrode voltage terminal, a low voltage terminal, or a ground terminal, but is not limited thereto.

[1130] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit, and a compensation control circuit;

[1131] The first light emitting control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is used to control the communication between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal;

[1132] The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit, and the first terminal of the switch control circuit, respectively, and is configured to control the second terminal of the driving circuit to be connected to the first terminal of the switch control circuit under the control of the light emitting control signal;

[1133] The second terminal of the switch control circuit is electrically connected to the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the second voltage terminal; the switch control circuit is used to control the communication between the second light-emitting control circuit and the first electrode of the light-emitting element under the control of the potential of the switch control terminal;

[1134] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the connection between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end.

[1135] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, a second light-emitting control circuit and a compensation control circuit; the first light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal; the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first terminal of the switch control circuit under the control of the light-emitting control signal; the switch control circuit controls the connection between the second light-emitting control circuit and the first electrode of the light-emitting element under the control of the potential of the switch control terminal; the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal to perform threshold voltage compensation.

[1136] As shown in FIG63 , the pixel circuit according to at least one embodiment of the present disclosure includes a light-emitting element E1, a tank circuit 10, a driving circuit 11, a switch control circuit 12, a first reset circuit 14, a data writing circuit, a second reset circuit 51, an initialization circuit 50, a voltage maintaining circuit 103, a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a compensation control circuit 32.

[1137] The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1, and the first electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of a first reset control signal provided by the first reset control terminal RST1 during a reset period between a period for writing the display data voltage and a period for writing the light-emission time control data voltage.

[1138] The data writing circuit includes a first writing sub-circuit 151 and a second writing sub-circuit 152; the writing control terminal includes a scanning terminal G1 and a first control terminal GB;

[1139] The first writing sub-circuit 151 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is used to write the light-emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB;

[1140] The second writing sub-circuit 152 is electrically connected to the scanning terminal G1, the second data line DI and the first terminal of the driving circuit 11 respectively, and is used to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[1141] The second reset circuit 51 is electrically connected to the second reset control terminal RST2, the second initial voltage terminal I2 and the first node N1 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RST2;

[1142] The initialization circuit 50 is electrically connected to the second control terminal GA, the third initial voltage terminal I3, and the switch control terminal N4, respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA;

[1143] The voltage maintaining circuit 103 is electrically connected to the switch control terminal N4 and is used to maintain the potential of the switch control terminal N4;

[1144] The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1, and the first terminal of the driving circuit 11, respectively, and is used to control the communication between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[1145] The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11, and the first terminal of the switch control circuit 12, respectively, and is used to control the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal;

[1146] The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the second terminal of the switch control circuit 12 is electrically connected to the first electrode of the light-emitting element E1; the second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2; the switch control circuit 12 is used to control the communication between the second light-emitting control circuit 62 and the first electrode of the light-emitting element E1 under the control of the potential of the switch control terminal N4;

[1147] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11, and the second terminal of the driving circuit 11, respectively, and is used to control the communication between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[1148] The first electrode of the light-emitting element E1 is the first pole of the light-emitting element E1.

[1149] Optionally, the light-emitting element may be a light-emitting diode, and the first electrode of the light-emitting element may be an anode.

[1150] When at least one embodiment of the pixel circuit shown in FIG. 63 of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are arranged in sequence;

[1151] The first display stage includes a first reset time period, a first write time period, and a first light-emitting time period that are set in sequence, and the second display stage includes a second reset time period, a second write time period, and a second light-emitting time period that are set in sequence;

[1152] In the first reset period, the first reset circuit 14 writes a first initial voltage into the first electrode of the light-emitting element E1 under the control of a first reset control signal; the second reset circuit 51 writes a second initial voltage Vi2 into the first node N1 under the control of a second reset control signal;

[1153] During the first writing period, the second writing sub-circuit 152 writes the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scan signal; the initialization circuit 50 writes the third initial voltage Vi3 into the switch control terminal N4 under the control of the second control signal to control the switch control circuit 12 to be turned on under the control of the potential of the switch control terminal N4; and the compensation control circuit 32 controls the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scan signal.

[1154] In the first light-emitting period, the first light-emitting control circuit 61 is used to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light-emitting control signal; the second light-emitting control circuit 62 is used to control the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light-emitting control signal; the driving circuit 11 drives the light-emitting element E1 to emit light;

[1155] In the second reset time period, the first reset circuit 14 writes the first initial voltage into the first electrode of the light emitting element E1 under the control of the first reset control signal;

[1156] In the second writing period, the first writing sub-circuit 151 writes the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal;

[1157] In the second light-emitting time period, the first light-emitting control circuit 61 controls the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light-emitting control signal; the second light-emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light-emitting control signal; the driving circuit 11 controls whether the light-emitting element E1 emits light according to the light-emitting time control data voltage.

[1158] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light-emitting element under the control of a first reset control signal, so as to release the residual charge on the first electrode of the light-emitting element at a high frequency, thereby improving display uniformity.

[1159] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit, and a compensation control circuit;

[1160] The first electrode of the light emitting element is electrically connected to the first voltage terminal;

[1161] The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the first terminal of the switch control circuit is electrically connected to the second electrode of the light-emitting element, and the second terminal of the switch control circuit is electrically connected to the first light-emitting control circuit; the switch control circuit is used to control the connection between the second electrode of the light-emitting element and the first light-emitting control circuit under the control of the potential of the switch control terminal;

[1162] The first light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the switch control circuit, and the first terminal of the drive circuit, respectively, and is configured to control the second terminal of the switch control circuit to be connected to the first terminal of the drive circuit under the control of a light emitting control signal provided by the light emitting control terminal;

[1163] The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit, and the second voltage terminal, respectively, and is used to control the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal;

[1164] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the first end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal provided by the scanning end;

[1165] The first electrode of the light-emitting element E1 serves as the second electrode of the light-emitting element E1.

[1166] Optionally, the light-emitting element may be a light-emitting diode, and the second electrode of the light-emitting element may be a cathode.

[1167] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, a second light-emitting control circuit and a compensation control circuit; the switch control circuit controls the connection between the second pole of the light-emitting element and the first light-emitting control circuit under the control of the potential of the switch control end; the first light-emitting control circuit controls the connection between the second end of the switch control circuit and the first end of the drive circuit under the control of a light-emitting control signal; the second light-emitting control circuit controls the connection between the second end of the drive circuit and the second voltage end under the control of the light-emitting control signal; and the compensation control circuit controls the connection between the control end of the drive circuit and the first end of the drive circuit under the control of the scanning signal.

[1168] As shown in FIG64 , the pixel circuit according to at least one embodiment of the present disclosure includes a light-emitting element E1, a tank circuit 10, a driving circuit 11, a switch control circuit 12, a first reset circuit 14, a data writing circuit, a second reset circuit 51, an initialization circuit 50, a voltage maintaining circuit 103, a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a compensation control circuit 32.

[1169] The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1, and the second electrode of the light-emitting element E1, respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the second electrode of the light-emitting element E1 under the control of a first reset control signal pro...

Claims

1. A pixel circuit, comprising a driving circuit, a switching control circuit, a light-emitting element, a driving control circuit, and a first reset circuit; A control terminal of the driving circuit is electrically connected to a first node, and is configured to generate a driving current for driving the light-emitting element under the control of a potential of the first node; The driving circuit is electrically connected to the light-emitting element or a first voltage terminal through the switching control circuit, the switching control circuit is electrically connected to a switching control terminal, and the switching control circuit is configured to control connection between the driving circuit and the light-emitting element or the first voltage terminal under the control of a potential of the switching control terminal; The driving control circuit is respectively electrically connected to a first control terminal and a first data line, and is configured to write a light-emitting time control data voltage provided by the first data line into the switching control terminal under the control of a first control signal provided by the first control terminal; The first reset circuit is configured to write a set voltage into a second node, a first pole of the light-emitting element, or a second pole of the light-emitting element under the control of a set control signal provided by a set control terminal.

2. The pixel circuit according to claim 1, wherein, The light-emitting element is an inorganic light-emitting diode, an aspect ratio of a transistor included in the switching control circuit is greater than 1, and an aspect ratio of a transistor included in the driving circuit is greater than 0.

5.

3. The pixel circuit according to claim 1, wherein, It further comprises an energy storage circuit; A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is configured to store electrical energy; The first reset circuit is configured to write a set voltage into the second node under the control of the set control signal.

4. The pixel circuit according to claim 1, wherein, The driving circuit is electrically connected to a first pole of the light-emitting element through the switching control circuit, and the switching control circuit is configured to control connection between the driving circuit and the first pole of the light-emitting element under the control of a potential of the switching control terminal; a second pole of the light-emitting element is electrically connected to a second voltage terminal; The first reset circuit is configured to write a set voltage into the first pole of the light-emitting element under the control of the set control signal during a reset time period set between a time period for writing the display data voltage and a time period for writing the light-emitting time control data voltage.

5. The pixel circuit according to claim 1, wherein, The first pole of the light-emitting element is electrically connected to a first voltage terminal; The driving circuit is electrically connected to a second pole of the light-emitting element through the switching control circuit, and the switching control circuit is configured to control connection between the driving circuit and the first voltage terminal under the control of a potential of the switching control terminal; The first reset circuit is configured to write a set voltage into the second pole of the light-emitting element under the control of the set control signal during a reset time period set between a time period for writing the display data voltage and a time period for writing the light-emitting time control data voltage.

6. The pixel circuit according to claim 1, wherein, The pixel circuit further comprises an energy storage circuit; A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the first pole of the light-emitting element, and the energy storage circuit is configured to store electrical energy; The first end of the switch control circuit is electrically connected to the first voltage terminal, the second end of the switch control circuit is electrically connected to the first end of the driving circuit, the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the first voltage terminal and the first end of the driving circuit under the control of the potential of the switch control terminal; or, the first end of the driving circuit is electrically connected to the first voltage terminal; the first end of the switch control circuit is electrically connected to the second end of the driving circuit, the second end of the switch control circuit is electrically connected to the first pole of the light-emitting element, and the second end of the light-emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the potential of the switch control terminal; The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scan terminal and a first selection control terminal; The compensation circuit is respectively electrically connected to the scan terminal, the first pole of the light-emitting element and a control node, and is configured to control the connection between the first pole of the light-emitting element and the control node under the control of the scan signal provided by the scan terminal; or, the compensation circuit is respectively electrically connected to the scan terminal, the second end of the driving circuit and the control node, and is configured to control the connection between the second end of the driving circuit and the control node under the control of the scan signal; The switch circuit is respectively connected to the first selection control terminal, the control node and the set voltage terminal, and is configured to provide the set voltage written by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal.

7. The pixel circuit according to claim 1, wherein, The pixel circuit further includes an energy storage circuit; The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the second pole of the light-emitting element, and the energy storage circuit is configured to store electrical energy; The first pole of the light-emitting element is electrically connected to the first voltage terminal, the first end of the switch control circuit is electrically connected to the second pole of the light-emitting element, the second end of the switch control circuit is electrically connected to the first end of the driving circuit, and the second end of the driving circuit is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the second pole of the light-emitting element and the first end of the driving circuit under the control of the potential of the switch control terminal; or, the first pole of the light-emitting element is electrically connected to the first voltage terminal, the second pole of the light-emitting element is electrically connected to the first end of the driving circuit; the first end of the switch control circuit is electrically connected to the second end of the driving circuit, and the second end of the switch control circuit is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the potential of the switch control terminal; The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scan terminal and a first selection control terminal; The compensation circuit is electrically connected to the scanning terminal, the second pole of the light-emitting element, and the control node respectively, and is configured to control the connection between the second pole of the light-emitting element and the control node under the control of the scanning signal; or, The compensation circuit is electrically connected to the scanning terminal, the first end of the driving circuit, and the control node respectively, and is configured to control the connection between the first end of the driving circuit and the control node under the control of the scanning signal; The switching circuit is connected to the first selection control terminal, the control node, and the set voltage terminal respectively, and is configured to write the set voltage provided by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal.

8. The pixel circuit according to claim 1, wherein The drive control circuit is further electrically connected to the second control terminal and the second initial voltage terminal respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal to the switch control terminal under the control of the second control signal provided by the second control terminal, and is configured to maintain the potential of the switch control terminal.

9. The pixel circuit according to claim 8, wherein, The first end of the driving circuit is electrically connected to the first voltage terminal; The switch control circuit is electrically connected to the second end of the driving circuit and the first pole of the light-emitting element respectively, and the second pole of the light-emitting element is electrically connected to the second voltage terminal; The switch control circuit is configured to control the connection between the second end of the driving circuit and the first end of the light-emitting element under the control of the potential of the switch control terminal.

10. The pixel circuit according to claim 9, wherein, It further includes a light-emitting control circuit and a compensation control circuit; The switch control circuit is electrically connected to the first pole of the light-emitting element through the light-emitting control circuit; The light-emitting control circuit is further electrically connected to the light-emitting control terminal, and is configured to control the connection between the switch control circuit and the first pole of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit, and the second end of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning terminal.

11. The pixel circuit according to claim 8, wherein, The first pole of the light-emitting element is electrically connected to the first voltage terminal, the switch control circuit is electrically connected to the second pole of the light-emitting element and the first end of the driving circuit respectively, and the second end of the driving circuit is electrically connected to the second voltage terminal; The switch control circuit is configured to control the connection between the second pole of the light-emitting element and the first end of the driving circuit under the control of the potential of the switch control terminal.

12. The pixel circuit according to claim 11, wherein, It further includes a light-emitting control circuit and a compensation control circuit; The switch control circuit is electrically connected to the first end of the driving circuit through the light-emitting control circuit; The light-emitting control circuit is further electrically connected to the light-emitting control terminal, and is configured to control the connection between the switch control circuit and the first end of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit, and the first terminal of the driving circuit respectively, and is configured to control the connection between the control terminal and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

13. The pixel circuit according to claim 10 or 12, wherein, The light-emitting element is an inorganic light-emitting diode. The width-to-length ratio of the transistor included in the switch control circuit is greater than 1. The width-to-length ratio of the transistor included in the light-emitting control circuit is greater than 1. The width-to-length ratio of the transistor included in the driving circuit is greater than 0.

5.

14. The pixel circuit according to claim 8, wherein, It further includes a display data writing circuit and a first control circuit; The control terminal of the driving circuit is electrically connected to the first node; The display data writing circuit is electrically connected to the scanning terminal, the second data line, and the second node respectively, and is configured to write the display data voltage provided by the second data line into the second node under the control of the scanning signal provided by the scanning terminal. The first control circuit is electrically connected to the light-emitting control terminal, the reference voltage terminal, and the second node respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

15. The pixel circuit according to claim 14, wherein, It further includes a second reset circuit; The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal.

16. The pixel circuit according to claim 9, wherein, It further includes a third reset circuit; The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the first pole of the light-emitting element respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset period set between the period of writing the display data voltage and the period of writing the light-emitting time control data voltage.

17. The pixel circuit according to claim 11, wherein, It further includes a third reset circuit; The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the second pole of the light-emitting element respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the second pole of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset period set between the period of writing the display data voltage and the period of writing the light-emitting time control data voltage.

18. The pixel circuit according to claim 9, wherein, It further includes an energy storage circuit, a first light-emitting control circuit, a second light-emitting control circuit, a compensation control circuit, and a display data writing circuit; The first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit. The second terminal of the energy storage circuit is electrically connected to the first voltage terminal. The energy storage circuit is used for storing electrical energy. The first terminal of the driving circuit is electrically connected to the first voltage terminal through the first light-emitting control circuit; The second terminal of the driving circuit is electrically connected to the switch control circuit through the second light-emitting control circuit; The first light-emitting control circuit is also electrically connected to the light-emitting control terminal, and is configured to control the connection between the first voltage terminal and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control terminal; The second light-emitting control circuit is also electrically connected to the light-emitting control terminal, and is configured to control the connection between the second end of the driving circuit and the switch control circuit under the control of the light-emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit, and the second end of the driving circuit respectively and is configured to control the connection between the control terminal of the driving circuit and the second end of the driving circuit under the control of a scanning signal provided by the scanning terminal; The display data writing circuit is electrically connected to the scanning terminal, the second data line, and the first end of the driving circuit respectively, and is configured to write a display data voltage provided by the second data line into the first end of the driving circuit under the control of the scanning signal.

19. The pixel circuit according to claim 11, wherein, The pixel circuit further includes an energy storage circuit, a first light-emitting control circuit, a second light-emitting control circuit, a compensation control circuit, and a display data writing circuit; The first end of the energy storage circuit is electrically connected to the control terminal of the driving circuit, the second end of the energy storage circuit is electrically connected to the second voltage terminal, and the energy storage circuit is configured to store electrical energy; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the switch control circuit, and the first end of the driving circuit respectively, and is configured to control the connection between the switch control circuit and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control terminal; The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the second end of the driving circuit, and the second voltage terminal respectively, and is configured to control the connection between the second end of the driving circuit and the second voltage terminal under the control of the light-emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit, and the first end of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the first end of the driving circuit under the control of a scanning signal provided by the scanning terminal; The display data writing circuit is electrically connected to the scanning terminal, the second data line, and the second end of the driving circuit respectively, and is configured to write a display data voltage provided by the second data line into the second end of the driving circuit under the control of the scanning signal.

20. The pixel circuit according to claim 18 or 19, wherein The light-emitting element is an inorganic light-emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, the width-to-length ratio of the transistor included in the first light-emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light-emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.

5.

21. The pixel circuit according to claim 18 or 19, wherein A second reset circuit is further included; The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the first node respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

22. The pixel circuit according to claim 6 or 7, wherein, A display data writing circuit is further included; The display data writing circuit is electrically connected to the scanning terminal, the second data line, and the control terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the control terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

23. The pixel circuit according to claim 6 or 7, wherein, The switch circuit is further connected to a second selection control terminal and a compensation terminal, and is configured to control the connection between the control node and the compensation terminal under the control of the second selection control signal provided by the second selection control terminal.

24. The pixel circuit according to claim 3, 6, 7, 18 or 19, wherein The energy storage circuit includes a storage capacitor; the light-emitting element is an inorganic light-emitting diode; The capacitance value of the storage capacitor is greater than three times the gate-source capacitance of the transistor in the driving circuit.

25. The pixel circuit according to claim 8, wherein, The driving control circuit includes a first transistor, a second transistor, and a first capacitor; The gate of the first transistor is electrically connected to the first control terminal, the first pole of the first transistor is electrically connected to the first data line, and the second pole of the first transistor is electrically connected to the switch control terminal; The gate of the second transistor is electrically connected to the second control terminal, the first pole of the second transistor is electrically connected to the second initial voltage terminal, and the second pole of the second transistor is electrically connected to the switch control terminal; The first end of the first capacitor is electrically connected to the switch control terminal, and the second end of the first capacitor is electrically connected to the DC voltage terminal.

26. The pixel circuit according to claim 10, wherein, The driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light-emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor; The gate of the driving transistor is electrically connected to the first node, the first pole of the driving transistor is electrically connected to the first voltage terminal, and the second pole of the driving transistor is electrically connected to the third node; The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the first pole of the fourth transistor is electrically connected to the third node, and the second pole of the fourth transistor is electrically connected to the first pole of the third transistor; The gate of the third transistor is electrically connected to the switch control terminal, and the second pole of the third transistor is electrically connected to the first pole of the light-emitting element; The gate of the fifth transistor is electrically connected to the scanning terminal, the first pole of the fifth transistor is electrically connected to the first node, and the second pole of the fifth transistor is electrically connected to the third node.

27. The pixel circuit according to claim 12, wherein, The driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light-emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor; The gate of the third transistor is electrically connected to the switch control terminal, the first pole of the third transistor is electrically connected to the second pole of the light-emitting element, and the second pole of the third transistor is electrically connected to the first pole of the fourth transistor; The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the second pole of the fourth transistor is electrically connected to the first pole of the driving transistor; the first pole of the driving transistor is electrically connected to the third node; The gate of the driving transistor is electrically connected to the first node, and the second pole of the driving transistor is electrically connected to the second voltage terminal; The gate of the fifth transistor is electrically connected to the scan terminal, the first pole of the fifth transistor is electrically connected to the first node, and the second pole of the fifth transistor is electrically connected to the third node.

28. The pixel circuit according to claim 14, wherein, The display data writing circuit includes a sixth transistor, and the first control circuit includes a seventh transistor; The gate of the sixth transistor is electrically connected to the scan terminal, the first pole of the sixth transistor is electrically connected to the second data line, and the second pole of the sixth transistor is electrically connected to the second node; The gate of the seventh transistor is electrically connected to the light emission control terminal, the first pole of the seventh transistor is electrically connected to the reference voltage terminal, and the second pole of the seventh transistor is electrically connected to the second node.

29. The pixel circuit according to claim 1, wherein, The first reset circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the set control terminal, the first pole of the eighth transistor is electrically connected to the set voltage terminal, and the second pole of the eighth transistor is electrically connected to the second node, the first pole of the light emitting element, or the second pole of the light emitting element; The set voltage terminal is used to provide the set voltage.

30. The pixel circuit according to claim 15, wherein, The second reset circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the first reset control terminal, the first pole of the ninth transistor is electrically connected to the first initial voltage terminal, and the second pole of the ninth transistor is electrically connected to the first node.

31. The pixel circuit according to claim 16, wherein, The third reset circuit includes a tenth transistor; The gate of the tenth transistor is electrically connected to the second reset control terminal, the first pole of the tenth transistor is electrically connected to the third initial voltage terminal, and the second pole of the tenth transistor is electrically connected to the first pole of the light emitting element.

32. The pixel circuit according to claim 17, wherein, The third reset circuit includes a tenth transistor; The gate of the tenth transistor is electrically connected to the second reset control terminal, the first pole of the tenth transistor is electrically connected to the third initial voltage terminal, and the second pole of the tenth transistor is electrically connected to the second pole of the light emitting element.

33. The pixel circuit according to claim 18, wherein, The driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor, the first light emission control circuit includes an eleventh transistor, the second light emission control circuit includes a twelfth transistor, the switch control circuit includes a third transistor, the compensation control circuit includes a fifth transistor, and the display data writing circuit includes a sixth transistor; The first end of the storage capacitor is electrically connected to the gate of the driving transistor, and the second end of the storage capacitor is electrically connected to the first voltage terminal; The gate of the eleventh transistor is electrically connected to the light emission control terminal, the first pole of the eleventh transistor is electrically connected to the first voltage terminal, and the second pole of the eleventh transistor is electrically connected to the first pole of the driving transistor; The gate of the twelfth transistor is electrically connected to the light emission control terminal, the first pole of the twelfth transistor is electrically connected to the second pole of the driving transistor, and the second pole of the twelfth transistor is electrically connected to the first pole of the third transistor; The gate of the third transistor is electrically connected to the switch control terminal, and the second pole of the third transistor is electrically connected to the first pole of the light emitting element; The gate of the fifth transistor is electrically connected to the scan terminal, the first pole of the fifth transistor is electrically connected to the gate of the driving transistor, and the second pole of the fifth transistor is electrically connected to the second pole of the driving transistor; The gate of the sixth transistor is electrically connected to the scan terminal, and the first pole of the sixth transistor is electrically connected to the second data line, and the second pole of the sixth transistor is electrically connected to the first pole of the driving transistor.

34. The pixel circuit according to claim 19, wherein, The driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor, the first light emission control circuit includes an eleventh transistor, the second light emission control circuit includes a twelfth transistor, the switch control circuit includes a third transistor, the compensation control circuit includes a fifth transistor, and the display data writing circuit includes a sixth transistor; The first end of the storage capacitor is electrically connected to the gate of the driving transistor, and the second end of the storage capacitor is electrically connected to the second voltage terminal; The gate of the third transistor is electrically connected to the switch control terminal, the first pole of the third transistor is electrically connected to the second pole of the light emitting element, and the second pole of the third transistor is electrically connected to the first pole of the eleventh transistor; The gate of the eleventh transistor is electrically connected to the light emission control terminal, and the second pole of the eleventh transistor is electrically connected to the first pole of the driving transistor; The gate of the twelfth transistor is electrically connected to the light emission control terminal, the first pole of the twelfth transistor is electrically connected to the second pole of the driving transistor, and the second pole of the twelfth transistor is electrically connected to the second voltage terminal; The gate of the fifth transistor is electrically connected to the scan terminal, the first pole of the fifth transistor is electrically connected to the gate of the driving transistor, and the second pole of the fifth transistor is electrically connected to the first pole of the driving transistor; The gate of the sixth transistor is electrically connected to the scan terminal, the first pole of the sixth transistor is electrically connected to the second data line, and the second pole of the sixth transistor is electrically connected to the second pole of the driving transistor.

35. The pixel circuit according to claim 21, wherein, The second reset circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the first reset control terminal, the first pole of the ninth transistor is electrically connected to the first initial voltage terminal, and the second pole of the ninth transistor is electrically connected to the first node.

36. The pixel circuit according to claim 6, wherein, The switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; The gate of the third transistor is electrically connected to the switch control terminal, the first pole of the third transistor is electrically connected to the first voltage terminal, and the second pole of the third transistor is electrically connected to the first pole of the driving transistor; The second pole of the driving transistor is electrically connected to the first pole of the light emitting element.

37. The pixel circuit according to claim 6, wherein, The switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; The gate of the third transistor is electrically connected to the switch control terminal, the first pole of the third transistor is electrically connected to the second pole of the driving transistor, and the second pole of the third transistor is electrically connected to the first pole of the light emitting element; The first pole of the driving transistor is electrically connected to the first voltage terminal.

38. The pixel circuit according to claim 7, wherein, The switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; The gate of the third transistor is electrically connected to the switch control terminal, a first pole of the third transistor is electrically connected to a second pole of the light-emitting element, a second pole of the third transistor is electrically connected to a first pole of the driving transistor, and a second pole of the driving transistor is electrically connected to a second voltage terminal.

39. The pixel circuit according to claim 7, wherein, The switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a second pole of the light-emitting element is electrically connected to a first pole of the driving transistor; The gate of the third transistor is electrically connected to the switch control terminal, a first pole of the third transistor is electrically connected to a second pole of the driving transistor, and a second pole of the third transistor is electrically connected to a first pole of the light-emitting element.

40. The pixel circuit according to claim 22, wherein, The display data writing circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the scanning terminal, a first pole of the sixth transistor is electrically connected to the second data line, and a second pole of the sixth transistor is electrically connected to a control terminal of the driving circuit.

41. The pixel circuit according to claim 6, wherein, The energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch; A first end of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second end of the storage capacitor is electrically connected to a second end of the driving circuit; The gate of the thirteenth transistor is electrically connected to the scanning terminal, a first pole of the thirteenth transistor is electrically connected to a first pole of the light-emitting element or a second end of the driving circuit, and a second pole of the thirteenth transistor is electrically connected to the control node; The control terminal of the first switch is electrically connected to the first selection control terminal, a first end of the first switch is electrically connected to the control node, and a second end of the first switch is electrically connected to the reference voltage terminal.

42. The pixel circuit according to claim 7, wherein, The energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch; A first end of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second end of the storage capacitor is electrically connected to a first end of the driving circuit; The gate of the thirteenth transistor is electrically connected to the scanning terminal, a first pole of the thirteenth transistor is electrically connected to a second pole of the light-emitting element or a first end of the driving circuit, and a second pole of the thirteenth transistor is electrically connected to the control node; The control terminal of the first switch is electrically connected to the first selection control terminal, a first end of the first switch is electrically connected to the control node, and a second end of the first switch is electrically connected to the reference voltage terminal.

43. The pixel circuit according to claim 23, wherein, The switch circuit further includes a second switch; The control terminal of the second switch is electrically connected to the second selection control terminal, a first end of the second switch is electrically connected to the control node, and a second end of the second switch is electrically connected to the compensation terminal.

44. A display device, comprising the pixel circuit according to any one of claims 1 to 43.

Images