Signal adjusting apparatus, signal adjusting method, and display device

Abstract

A signal adjusting apparatus (100), a signal adjusting method, and a display device. The signal adjusting apparatus (100) comprises: a reset circuit (110), an adjusting circuit (120), a control circuit (130) and an output circuit (140), wherein the reset circuit (110) is configured to receive a first reset signal (Reset1) and reset the voltage of a target end (Q) of the reset circuit (110) on the basis of the first reset signal (Reset1), and the adjusting circuit (120), the control circuit (130) and the output circuit (140) are all connected to the target end (Q) of the reset circuit (110); the adjusting circuit (120) is configured to receive an adjusting signal (Datastep) and control a charging or discharging process of the target end (Q) at least on the basis of the adjusting signal (Datastep); the control circuit (130) is connected to the output circuit (140), and is configured to control, on the basis of the voltage of the target end (Q), a voltage applied to the output circuit (140); and the output circuit (140) is configured to control, on the basis of the voltage of the target end (Q) and the voltage applied by the control circuit (130), the voltage of an output signal from an output end (Output) of the output circuit (140).

Description

Signal conditioning device, signal conditioning method and display device Technical Field

[0001] Embodiments of the present disclosure relate to a signal conditioning apparatus, a signal conditioning method, and a display device. Background Art

[0002] Currently, active light-emitting diode (OLED) and Mini / Micro LED (Micro LED) displays generally use PAM (Pulse Amplitude Modulation) grayscale drive. As product resolution continues to increase and size continues to decrease, the shortcomings of PAM drive, such as high power consumption, high heat generation, and inability to achieve low grayscale, have become increasingly prominent. To address these issues, PWM (Pulse Width Modulation) grayscale drive has been introduced. However, the current PWM signal is provided by the chip, and the duty cycle cannot be adjusted, making it inconvenient to use.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a signal conditioning device, comprising: a reset circuit, a conditioning circuit, a control circuit, and an output circuit, wherein the reset circuit is configured to receive a first reset signal and reset the voltage of a target end of the reset circuit according to the first reset signal, wherein the conditioning circuit, the control circuit, and the output circuit are all connected to the target end of the reset circuit; the conditioning circuit is configured to receive a conditioning signal and control a charging or discharging process of the target end at least according to the conditioning signal; the control circuit is connected to the output circuit, and the control circuit is configured to control a voltage applied to the output circuit according to the voltage of the target end; the output circuit is configured to control the voltage of an output signal of an output end of the output circuit according to the voltage of the target end and the voltage applied by the control circuit.

[0005] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the control circuit includes a first control circuit and a second control circuit, the first end of the first control circuit is connected to the output circuit, the second end of the first control circuit is configured to receive a first voltage, and the third end of the first control circuit is connected to the target end; the first end of the second control circuit is connected to the first end of the first control circuit, and the second end of the second control circuit is configured to receive a second voltage; the first control circuit is configured to control the voltage difference between the first end of the first control circuit and the first voltage according to the voltage of the target end; and the second control circuit is configured to output the second voltage to the output circuit when the first control circuit is turned off.

[0006] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the first control circuit includes a first control transistor, the second control circuit includes a second control transistor, the gate of the first control transistor is connected to the target end, one of the source and the drain of the first control transistor is connected to the second control transistor, and the other receives a first voltage; one of the source and the drain of the second control transistor receives the second voltage, the other is connected to the first control transistor, and the gate of the second control transistor receives the second voltage; the first control transistor adjusts the degree of opening of the first control transistor according to the voltage of the target end, and the first control circuit is closed including the first control transistor being turned off; the second control transistor is configured to be turned on when the gate of the second control transistor receives the second voltage.

[0007] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the width-to-length ratio of the first control transistor is greater than the width-to-length ratio of the second control transistor.

[0008] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the output circuit includes a first output circuit and a second output circuit; the first end of the first output circuit is connected to the first end of the second output circuit, the second end of the first output circuit is configured to receive a third voltage, and the third end of the first output circuit is connected to the target end; the second end of the second output circuit is configured to receive a fourth voltage, and the third end of the second output circuit is connected to the control circuit; the output end of the output circuit is connected to the first end of the first output circuit and the first end of the second output circuit; the first output circuit is used to control the voltage difference between the voltage of the output end and the third voltage according to the voltage of the target end; the second output circuit is used to control the voltage difference between the voltage of the output end and the fourth voltage according to the voltage applied by the control circuit.

[0009] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the first output circuit includes a first output transistor, and the second output circuit includes a second output transistor; the gate of the first output transistor is connected to the target end, one of the gate and the drain of the first output transistor receives the third voltage, and the other is connected to the second output transistor; the gate of the second output transistor receives the voltage applied by the control circuit, one of the source and the drain of the second output transistor receives the fourth voltage, and the other is connected to the first output transistor; the first output transistor adjusts the conduction degree of the first output transistor according to the voltage of the target end, and the second output transistor adjusts the conduction degree of the second output transistor according to the voltage applied by the control circuit.

[0010] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the first end of the adjustment circuit is connected to the target end, the second end of the adjustment circuit receives the fifth voltage, and the third end of the adjustment circuit receives the adjustment signal; the adjustment circuit is configured to control the discharge or charging speed of the target end according to the adjustment signal.

[0011] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the adjustment circuit includes a first adjustment circuit, a first end of the first adjustment circuit is connected to the target end, a second end of the first adjustment circuit receives the fifth voltage, and a third end of the first adjustment circuit receives the adjustment signal; the first adjustment circuit is configured to control the discharge or charging speed of the target end according to the adjustment signal.

[0012] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the first adjustment circuit includes a first adjustment transistor, the gate of the first adjustment transistor receives the adjustment signal, one of the source and the drain of the first adjustment transistor is connected to the target end, and the other receives the fifth voltage; the first adjustment transistor is configured to adjust the conduction degree of the first adjustment transistor according to the voltage of the adjustment signal.

[0013] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the fourth terminal of the conditioning circuit is connected to the output terminal; the conditioning circuit is also configured to control the voltage change slope of the target terminal during the discharge or charging process according to the voltage of the output terminal.

[0014] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the adjustment circuit includes a first adjustment circuit and a second adjustment circuit; the first end of the first adjustment circuit and the first end of the second adjustment circuit are both connected to the target end, the second end of the first adjustment circuit and the second end of the second adjustment circuit are both configured to receive a fifth voltage, the third end of the first adjustment circuit receives the adjustment signal, and the first adjustment circuit is configured to control the discharge or charging speed of the target end according to the adjustment signal; the third end of the second adjustment circuit is connected to the output end, and the second adjustment circuit is configured to control the voltage change slope of the target end during the discharge or charging process according to the voltage of the output end.

[0015] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the first adjustment circuit includes a first adjustment transistor, the second adjustment circuit includes a second adjustment transistor, the gate of the first adjustment transistor receives the adjustment signal, one of the source and the drain of the first adjustment transistor is connected to the target end, and the other receives the fifth voltage; the gate of the second adjustment transistor is connected to the output end, one of the source and the drain of the second adjustment transistor is connected to the target end, and the other receives the fifth voltage; the first adjustment transistor is configured to adjust the conductivity of the first adjustment transistor according to the voltage of the adjustment signal; the second adjustment transistor is configured to adjust the conductivity of the second adjustment transistor according to the voltage of the output end.

[0016] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the signal conditioning device further includes a reset auxiliary circuit, which is connected between the first end of the conditioning circuit and the target end; the first end of the reset auxiliary circuit is connected to the first end of the conditioning circuit, the second end of the reset auxiliary circuit is connected to the target end, and the third end of the reset auxiliary circuit is configured to receive a second reset signal; the reset auxiliary circuit is opened or closed under the control of the second reset signal.

[0017] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the second reset signal is configured to control the reset auxiliary circuit to be closed when the reset circuit is opened, and to control the reset auxiliary circuit to be opened when the reset circuit is closed.

[0018] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the adjustment circuit includes a first adjustment circuit, a first end of the first adjustment circuit is connected to the first end of the reset auxiliary circuit, a second end of the first adjustment circuit receives the fifth voltage, and a third end of the first adjustment circuit receives the adjustment signal; the first adjustment circuit is configured to control the discharge or charging speed of the target end according to the adjustment signal.

[0019] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the first adjustment circuit includes a first adjustment transistor, the reset auxiliary circuit includes a reset auxiliary transistor, the gate of the first adjustment transistor receives the adjustment signal, one of the source and the drain of the first adjustment transistor is connected to the reset auxiliary transistor, and the other receives the fifth voltage; the gate of the reset auxiliary transistor receives the second reset signal, one of the source and the drain of the reset auxiliary transistor is connected to the first adjustment transistor, and the other is connected to the target end; the first adjustment transistor is configured to adjust the conduction degree of the first adjustment transistor according to the voltage of the adjustment signal; the reset auxiliary transistor is configured to be turned on or off under the control of the second reset signal.

[0020] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the adjustment circuit includes a first adjustment circuit and a second adjustment circuit, the first end of the first adjustment circuit and the first end of the second adjustment circuit are both connected to the first end of the reset auxiliary circuit, the second end of the first adjustment circuit and the second end of the second adjustment circuit are both configured to receive a fifth voltage, the third end of the first adjustment circuit receives the adjustment signal, and the first adjustment circuit is configured to control the discharge or charging speed of the target end according to the adjustment signal; the third end of the second adjustment circuit is connected to the output end, and the second adjustment circuit is configured to control the voltage change slope of the target end during the discharge or charging process according to the voltage of the output end.

[0021] For example, in the signal regulation device provided in at least one embodiment of the present disclosure, the first regulation circuit includes a first regulation transistor, the second regulation circuit includes a second regulation transistor, and the reset auxiliary circuit includes a reset auxiliary transistor. The gate of the first regulation transistor receives the regulation signal, one of the source and the drain of the first regulation transistor is connected to the second regulation transistor and the reset auxiliary transistor, and the other receives the fifth voltage; the gate of the second regulation transistor is connected to the output end, one of the source and the drain of the second regulation transistor is connected to the first regulation transistor and the reset auxiliary transistor, and the other is connected to the target end; the gate of the reset auxiliary transistor receives the second reset signal, one of the source and the drain of the reset auxiliary transistor is connected to the first regulation transistor and the second regulation transistor, and the other is connected to the target end; the first regulation transistor is configured to adjust the conduction degree of the first regulation transistor according to the voltage of the regulation signal; the second regulation transistor is configured to adjust the conduction degree of the second regulation transistor according to the voltage of the output end; and the reset auxiliary transistor is configured to be turned on or off under the control of the second reset signal.

[0022] For example, in the signal adjustment device provided in at least one embodiment of the present disclosure, the first end of the reset circuit is configured to receive a sixth voltage, and the second end of the reset circuit is configured to receive the first reset signal; the reset circuit is configured to use the sixth voltage to reset the voltage of the target end of the reset circuit under the control of the first reset signal; the adjustment circuit is configured to control the discharge or charging speed of the target end according to the adjustment signal after the voltage of the target end is reset.

[0023] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the reset circuit includes a reset transistor, the gate of the reset transistor receiving the first reset signal, one of the source and drain of the reset transistor receiving the sixth voltage, and the other being the target terminal; the reset transistor is configured to be turned on or off under the control of the first reset signal.

[0024] For example, in the signal conditioning device provided in at least one embodiment of the present disclosure, the signal conditioning device further includes a storage capacitor connected to the target terminal, and the storage capacitor is configured to store the voltage of the target terminal.

[0025] At least one embodiment of the present disclosure further provides a signal regulation method, which is used for the signal regulation device described in any embodiment of the present disclosure, the method comprising: applying the first reset signal to the reset circuit to control the reset circuit to reset the voltage of the target end to an initial voltage, wherein the control circuit applies a first control voltage to the output circuit according to the initial voltage, and the output circuit controls the output end to output a first output voltage according to the initial voltage and the first control voltage; applying the regulation signal to the regulation circuit to charge or discharge the target end through the regulation circuit, wherein, during the process of charging or discharging the target end, the voltage of the control signal applied by the control circuit to the output circuit changes from the first control voltage to the second control voltage, and the voltage of the output signal of the output end of the output circuit changes from the first output voltage to the second output voltage.

[0026] For example, the signal adjustment method provided in at least one embodiment of the present disclosure also includes: changing the voltage of the adjustment signal to change the duty cycle of the output signal; wherein the discharge or charging speed of the target end, the voltage change speed of the control signal and the voltage change speed of the output signal all change with the change of the voltage of the adjustment signal; wherein, the duty cycle of the output signal of the output end is related to the voltage change speed of the output signal.

[0027] At least one embodiment of the present disclosure further provides a display device, comprising the signal adjustment device described in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0029] FIG1 is a schematic diagram of a signal conditioning device provided by at least one embodiment of the present disclosure;

[0030] FIG2 is a signal timing diagram provided by at least one embodiment of the present disclosure;

[0031] FIG3 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0032] FIG4 is a schematic diagram of a signal waveform provided by at least one embodiment of the present disclosure;

[0033] FIG5 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0034] FIG6 is a schematic diagram of another signal waveform provided by at least one embodiment of the present disclosure;

[0035] FIG7 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0036] FIG8 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0037] FIG9 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0038] FIG10 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0039] FIG11 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0040] FIG12 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure;

[0041] FIG13 is a schematic diagram of another signal waveform provided by at least one embodiment of the present disclosure;

[0042] FIG14 is a schematic diagram of another signal waveform provided by at least one embodiment of the present disclosure;

[0043] FIG15 is a flowchart of a signal adjustment method provided by at least one embodiment of the present disclosure; and

[0044] FIG16 is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which the invention belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0047] The current PWM drive method is full-screen drive, or a PWM timing signal is introduced into the pixel drive circuit, combined with PAM drive to achieve low grayscale display. The current PWM timing signal is provided by an integrated circuit (IC), with a fixed frequency and duty cycle. It cannot be adjusted at any time according to actual needs, which increases the design difficulty and complexity of the adaptive signal.

[0048] At least one embodiment of the present disclosure provides a signal conditioning device, comprising: a reset circuit, a conditioning circuit, a control circuit, and an output circuit, wherein the reset circuit is configured to receive a first reset signal and reset the voltage of a target end of the reset circuit according to the first reset signal, wherein the conditioning circuit, the control circuit, and the output circuit are all connected to the target end of the reset circuit; the conditioning circuit is configured to receive the conditioning signal and control the charging or discharging process of the target end at least according to the conditioning signal; the control circuit is connected to the output circuit, and the control circuit is configured to control the voltage applied to the output circuit according to the voltage of the target end; the output circuit is configured to control the voltage of an output signal of an output end of the output circuit according to the voltage of the target end and the voltage applied by the control circuit.

[0049] At least one embodiment of the present disclosure further provides a signal conditioning method corresponding to the above-mentioned signal conditioning device.

[0050] The signal conditioning device provided by the embodiments of the present disclosure, through a reset circuit, a conditioning circuit, a control circuit, and an output circuit, can change the duty cycle of the output signal as the conditioning signal changes, thereby achieving adjustment of the duty cycle of the output signal. Furthermore, the control circuit determines the control voltage applied to the output circuit based on the target terminal voltage, and the output circuit controls the voltage of the output signal under the combined action of the control voltage and the target terminal voltage. Changes in the target terminal voltage can be quickly transmitted to the output signal, making the adjustment of the duty cycle of the output signal more sensitive and rapid.

[0051] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0052] FIG1 is a schematic diagram of a signal conditioning device provided by at least one embodiment of the present disclosure.

[0053] As shown in FIG. 1 , the signal conditioning device 100 includes a reset circuit 110 , a conditioning circuit 120 , a control circuit 130 and an output circuit 140 .

[0054] The reset circuit 110 is configured to receive a first reset signal Reset1 and reset the voltage of the target end (such as Q point) of the reset circuit according to the first reset signal Reset1, wherein the regulation circuit 120, the control circuit 130 and the output circuit 140 are all connected to the target end (Q point) of the reset circuit.

[0055] The regulating circuit 120 is configured to receive the regulating signal Datastep and control the charging or discharging process of the target terminal (Q point) at least according to the regulating signal Datastep.

[0056] The control circuit 130 is connected to the output circuit 140 , and the control circuit 130 is configured to control the voltage applied to the output circuit 140 according to the voltage of the target terminal (Q point).

[0057] The output circuit 140 is configured to control the voltage of an output signal at an output terminal Output of the output circuit according to the voltage of the target terminal (Q point) and the voltage applied by the control circuit.

[0058] For example, a first reset signal Reset1 is applied to reset circuit 110 to control reset circuit 110 to reset the voltage at the target terminal (point Q) to an initial voltage. Control circuit 130 applies a first control voltage to output circuit 140 based on the initial voltage. Output circuit 140 controls output terminal Output to output a first output voltage based on the initial voltage and the first control voltage. Then, a regulation signal Datastep is applied to regulation circuit 120 to charge or discharge the target terminal (point Q) through regulation circuit 120. During the charging or discharging process of the target terminal (point Q), the voltage of the control signal applied by control circuit 130 to output circuit 140 changes from the first control voltage to the second control voltage, and the voltage of the output signal at output terminal Output of output circuit 140 changes from the first output voltage to the second output voltage.

[0059] For example, when the duty cycle of the output signal needs to be changed, the voltage of the adjustment signal Datastep can be changed to change the duty cycle of the output signal. The speed of discharge or charge of the target terminal (Q point), the speed of voltage change of the control signal, and the speed of voltage change of the output signal all change with the change of the voltage of the adjustment signal Datastep. The duty cycle of the output signal at the output terminal Output is related to the speed of voltage change of the output signal.

[0060] For example, in some embodiments, the initial voltage may be a positive voltage. When the regulating circuit 120 is turned on by the regulating signal Datastep, the Q point may be discharged through the regulating circuit 120 , so that the Q point voltage gradually decreases.

[0061] For example, in some other embodiments, the initial voltage may be a negative voltage. When the regulating circuit 120 is turned on by the regulating signal Datastep, the Q point may be charged through the regulating circuit 120 , so that the Q point voltage gradually increases.

[0062] For example, the adjustment signal Datastep can control the degree of openness of the adjustment circuit 120. When the adjustment circuit 120 is open to a greater degree, the resistance of the adjustment circuit 120 is smaller, and the rate at which the Q point is discharged or charged through the adjustment circuit 120 is faster. When the adjustment circuit 120 is open to a lesser degree, the resistance of the adjustment circuit 120 is larger, and the rate at which the Q point is discharged or charged through the adjustment circuit 120 is slower. The rate at which the Q point is charged or discharged affects the rate at which the voltage of the control signal output by the control circuit 130 to the output circuit 140 changes, further affecting the rate at which the voltage of the output signal of the output circuit 140 changes, and thus affecting the duty cycle of the output signal. Therefore, the duty cycle of the output signal can be changed by changing the voltage of the adjustment signal Datastep, thereby achieving duty cycle adjustment.

[0063] For example, in an embodiment of the present disclosure, the charging or discharging speed of the Q point may refer to the time at which the voltage of the Q point changes from the voltage range of the initial voltage to the voltage range of the target voltage within a signal cycle. The target voltage of the Q point is the final voltage of the Q point discharge or charging process. The voltage range of the initial voltage may refer to the range from the initial voltage to the intermediate voltage (e.g., 0V), and the voltage range of the target voltage may refer to the range from the target voltage to the intermediate voltage (e.g., 0V). Accordingly, the changing speed of the output signal may refer to the time at which the output signal changes from the first voltage range to the second voltage range within a signal cycle. One of the first voltage range and the second voltage range may be a positive voltage, and the other may be a negative voltage. For example, the first voltage range is -12V to 0V, and the second voltage range is 0 to 12V. The duty cycle of the output signal may be the ratio of the duration of the output signal in the second voltage range within a cycle to the duration of the cycle. A fast changing speed of the output signal means that the voltage jump of the output signal is earlier within a cycle, the duration of the output signal in the second voltage range accounts for a large proportion of the cycle, and the duty cycle of the signal is large. On the contrary, the output signal changes slowly, which means that the voltage of the output signal jumps later in one cycle, and the duration of the output signal in the second voltage range accounts for a small proportion in one cycle, and the duty cycle of the signal is small.

[0064] FIG2 is a signal timing diagram provided by at least one embodiment of the present disclosure.

[0065] As shown in Figures 1 and 2, for example, during each cycle, a first reset signal Reset1 is applied to reset circuit 110 to reset the voltage at point Q to an initial voltage (e.g., 12V). Under the influence of the potential at point Q, control circuit 130 outputs a first control voltage to output circuit 140. Under the control of this first control voltage and the initial voltage at point Q, the output terminal Output of output circuit 140 outputs an output signal having a first output voltage (e.g., -12V). When a regulation signal Datastep is applied to regulation circuit 120, regulation circuit 120 is turned on, point Q begins to discharge, and the voltage at point Q gradually decreases. As the voltage at point Q decreases, the voltage of the control signal output by control circuit 130 to output circuit 140 increases. Under the influence of the voltage at point Q and the control signal voltage, the voltage of output signal Output of output circuit 140 increases. When point Q discharges to -12V, the voltage of output signal Output changes to 12V. If the output signal Output is active at a high level, the duty cycle of the output signal Output is the ratio of the duration of the high level in one cycle to the duration of the cycle.

[0066] For example, as shown in Figure 2, during time period T1, the voltage of the regulation signal Datastep is -11.1V. The regulation circuit is only slightly open, resulting in a high resistance. Consequently, discharge at point Q is slow, and accordingly, the voltage rise rate of the output signal Output is also slow. Near the end of the period, the output signal Output transitions to a high level, where it remains high for a short period. Consequently, the duty cycle of the output signal Output is low (e.g., 10.2%).

[0067] For example, during time period T2, the voltage of the regulation signal Datastep is -11.05V. Compared to time period T1, during time period T2, the regulation circuit is more open, and its resistance is reduced. Consequently, discharge at point Q is accelerated, and accordingly, the voltage rise rate of the output signal Output is also accelerated. The time at which the output signal Output transitions from a low level to a high level is shortened, and the duration of the high level within each cycle is prolonged. Consequently, the duty cycle of the output signal Output increases (for example, to 21.1%).

[0068] For example, during time period T3, the voltage of the adjustment signal Datastep is -10.95V. Compared to time period T2, during time period T3, the first opening degree of the adjustment circuit is further increased, and the resistance of the adjustment circuit is further reduced. Consequently, the Q-point discharge is further accelerated, and accordingly, the voltage rise rate of the output signal Output is also further accelerated. The time when the output signal Output changes from a low level to a high level is further shortened, and the high level duration within each cycle is further prolonged. Consequently, the duty cycle of the output signal Output is further increased (for example, to 44.7%).

[0069] Similarly, if the voltage of the adjustment signal Datastep during time period T4 is greater than the voltage during time period T3 (e.g., -10.95V), then the duty cycle of the output signal Output during time period T4 is greater than the duty cycle during time period T3. If the voltage of the adjustment signal Datastep during time period T5 is greater than the voltage during time period T4 (e.g., -10.7V), then the duty cycle of the output signal Output during time period T5 is greater than the duty cycle during time period T4. Therefore, by changing the voltage of the adjustment signal Datastep, the duty cycle of the output signal Output can be changed.

[0070] For example, when the initial voltage of the target terminal (Q point) is positive, the target terminal can start discharging after the regulating circuit 120 is turned on. When the initial voltage of the target terminal (Q point) is negative, the target terminal can start charging after the regulating circuit 120 is turned on.

[0071] According to the embodiments of the present disclosure, the duty cycle of the output signal can be changed as the adjustment signal Datastep changes through the reset circuit, the adjustment circuit, the control circuit and the output circuit, thereby achieving adjustment of the duty cycle of the output signal.

[0072] According to an embodiment of the present disclosure, a control circuit determines a control voltage applied to an output circuit based on a target terminal (Q-point) voltage. The output circuit controls the voltage of an output signal under the combined action of this control voltage and the target terminal (Q-point) voltage. Changes in the target terminal (Q-point) voltage can be quickly transmitted to the output signal, making the duty cycle of the output signal more sensitive and rapid to adjust.

[0073] For example, each of the reset circuit 110, the regulating circuit 120, the control circuit 130, and the output circuit 140 may include one or more transistors, such as thin film transistors (TFTs). TFTs include N-type and P-type TFTs. N-type TFTs can be turned on under high voltage, while P-type TFTs can be turned on under low voltage. In other embodiments, the reset circuit 110, the regulating circuit 120, the control circuit 130, and the output circuit 140 may also use other types of transistors.

[0074] In some of the following embodiments, description is made by taking as an example that the transistors included in the reset circuit 110 , the regulating circuit 120 , the control circuit 130 and the output circuit 140 are all N-type thin film transistors.

[0075] FIG3 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure.

[0076] As shown in FIG3 , for example, the control circuit 130 includes a first control circuit 131. A first terminal (point A) of the first control circuit 131 is connected to the output circuit 140. A second terminal of the first control circuit 131 is configured to receive a first voltage (e.g., VSS). A third terminal (point A) of the first control circuit 131 is connected to a target terminal (point Q). The first control circuit 131 is configured to control the voltage difference between the first terminal (point A) of the first control circuit 131 and the first voltage (e.g., VSS) based on the voltage at the target terminal (point Q). The voltage at the third terminal (point A) of the first control circuit 131 is the control voltage applied by the first control circuit 131 to the output circuit 140. To distinguish output signals from different embodiments, in the embodiment shown in FIG3 , the output signal is represented as Output1.

[0077] For example, the control circuit may further include a second control circuit 132, wherein a first terminal of the second control circuit 132 is connected to a first terminal of the first control circuit 131 (point A), and a second terminal of the second control circuit 132 is configured to receive a second voltage (e.g., VDD). The second control circuit 132 is configured to output the second voltage (VDD) to the output circuit 140 when the first control circuit 131 is turned off.

[0078] For example, the degree of openness of the first control circuit 131 varies with the voltage at the target terminal (point Q). At the beginning of the cycle, point Q is reset to an initial voltage (e.g., 12V), and the first control circuit 131 is opened (e.g., fully open) in response to the voltage at point Q. The second control circuit 132 can be in a closed state, or in an open state with a resistance greater than that of the first control circuit 131. The resistance of the first control circuit 131 is less than that of the second control circuit 132, so that the voltage at point A is biased toward the first voltage (VSS) received by the first control circuit 131. For example, the voltage at point A is at or near the first voltage (VSS), and the voltage difference between the voltage at point A and the first voltage is less than a threshold. For example, the first voltage is -12V, the second voltage is 12V, and the voltage at point A is at or near -12V. When the voltage at point A is the first voltage (VSS) or close to the first voltage and the voltage at point Q is the initial voltage, the output signal Output1 of the output circuit 140 is the first output voltage (eg, 12V).

[0079] For example, when the regulation circuit 120 is turned on by the regulation signal Datastep, point Q begins to discharge. As the voltage at point Q decreases, the opening degree of the first control circuit 131 decreases, the resistance of the first control circuit 131 increases, and the voltage difference between the voltage at point A and the first voltage (e.g., VSS) increases. When the first voltage (VSS) is negative, the voltage at point A gradually increases. When the voltage at point Q drops to a target voltage (e.g., -12V), the first control circuit 131 is turned off (e.g., fully closed). The resistance of the first control circuit 131 is much higher than the resistance of the second control circuit 132, and the voltage at point A deviates toward the second voltage (VDD) to which the second control circuit 132 is connected. The voltage difference between the voltage at point A and the second voltage (VDD) is less than a threshold value (e.g., the second voltage is 12V), and the voltage at point A is 12V or close to 12V. When the voltage at point A is at or near the second voltage (VDD) and the voltage at point Q is at the target voltage, output circuit 140 outputs signal Output1 at the second output voltage (e.g., 12V). Output circuit 140 maintains the second output voltage until the end of the current cycle. During the discharge process at point Q, the voltage at point A changes from the first voltage to the second voltage, and the voltage of the output signal changes from the first output voltage (e.g., -12V) to the second output voltage (e.g., 12V).

[0080] According to an embodiment of the present disclosure, the first control circuit controls the voltage difference between the voltage at point A and the first voltage according to the voltage at point Q to control the voltage applied to the output circuit. The circuit is simple, easy to implement, and highly reliable.

[0081] For example, the output circuit 140 includes a first output circuit 141 and a second output circuit 142. A first terminal of the first output circuit 141 is connected to a first terminal of the second output circuit 142. A second terminal of the first output circuit 141 is configured to receive a third voltage (e.g., VSS). A third terminal of the first output circuit 141 is connected to a target terminal (point Q). A second terminal of the second output circuit 142 is configured to receive a fourth voltage (e.g., VDD). A third terminal of the second output circuit 142 is connected to the control circuit 130. An output terminal, Output1, of the output circuit 140 is connected to a first terminal of the first output circuit 141 and a first terminal of the second output circuit. The first output circuit 141 is configured to control a voltage difference between the output terminal voltage and a third voltage (e.g., VSS) based on the voltage at the target terminal (point Q). The second output circuit 142 is configured to control a voltage difference between the output terminal voltage and a fourth voltage (e.g., VDD) based on a voltage applied by the control circuit 130 (the voltage at point A).

[0082] For example, as described above, when point Q is the initial voltage, the voltage at point A is at or near the first voltage, the second output circuit 142 is closed by the voltage at point A, and the first output circuit 141 is opened by the voltage at point Q. The resistance of the first output circuit 141 is smaller than the resistance of the second output circuit 142, and the voltage of the output signal Output1 of the output circuit 140 is biased toward the third voltage (VSS) received by the first output circuit 141. The voltage of the output signal Output1 (the first output voltage) is at or near the third voltage (VSS), meaning that the voltage difference between the output signal Output1 and the third voltage is less than the threshold.

[0083] For example, during the discharge process at point Q, the voltage at point A changes from the first voltage (VSS) to the second voltage (VDD). When point Q reaches the target voltage, the voltage at point A changes to the second voltage (or close to the second voltage). The second output circuit 142 is turned on by the voltage at point A, and the first output circuit 141 is turned off by the voltage at point Q. The resistance of the first output circuit 141 is greater than the resistance of the second output circuit 142, and the voltage of the output signal Output1 of the output circuit 140 is biased toward the fourth voltage (VDD) received by the second output circuit 142. The voltage of the output signal Output1 (the second output voltage) is at or close to the fourth voltage (VDD), i.e., the voltage difference between the voltage of the output signal Output1 and the fourth voltage (VDD) is less than the threshold.

[0084] According to the embodiment of the present disclosure, under the action of the voltage at point A and the voltage at point Q, the open and closed states of the second output circuit of the first output circuit are opposite, so that the output end can output different voltages. The circuit is simple, easy to implement, and has high reliability.

[0085] For example, the first control circuit 131 includes a first control transistor M6, and the second control circuit 132 includes a second control transistor M5. The gate of the first control transistor M6 is connected to the target terminal (point Q), one of the source and drain of the first control transistor M6 is connected to the second control transistor M5, and the other receives a first voltage (VSS). One of the source and drain of the second control transistor M5 receives a second voltage (VDD), and the other is connected to the first control transistor M5. The gate of the second control transistor M5 receives the second voltage (VDD). The first control transistor M6 adjusts the degree of opening of the first control transistor M6 according to the voltage of the target terminal (point Q). When the first control circuit 131 is turned off, the first control transistor M6 is turned off. The second control transistor is configured to turn on when the gate of the second control transistor receives the second voltage (e.g., VDD).

[0086] For example, the width-to-length ratio of the first control transistor M6 is greater than the width-to-length ratio of the second control transistor M5. For example, the width-to-length ratio W / L of the first control transistor M6 is 20 / 5, and the width-to-length ratio W / L of the second control transistor M5 is 5 / 5, so that the fully-on resistance of the first control transistor is smaller than the fully-on resistance of the second control transistor M5.

[0087] For example, the first output circuit 141 includes a first output transistor M8, and the second output circuit 142 includes a second output transistor M7. The gate of the first output transistor M8 is connected to the target terminal (point Q). One of the gate and drain of the first output transistor M8 receives a third voltage (e.g., VSS), and the other is connected to the second output transistor M7. The gate of the second output transistor M7 receives a voltage applied by the control circuit 130. One of the source and drain of the second output transistor M7 receives a fourth voltage (e.g., VDD), and the other is connected to the first output transistor M8. The first output transistor M8 adjusts its conduction level based on the voltage at the target terminal (point Q), and the second output transistor M7 adjusts its conduction level based on the voltage applied by the control circuit 130.

[0088] For example, the first control transistor M6, the second control transistor M5, the first output transistor M8, and the second output transistor M7 are all N-type thin-film transistors, which are turned on when a high level is applied and turned off when a low level is applied. The first voltage (VSS connected to M6) and the third voltage (VSS connected to M8) are both negative voltages (e.g., -12V), and the second voltage (VDD connected to M5) and the fourth voltage (VDD connected to M7) are both positive voltages (e.g., 12V). At the beginning of the cycle, point Q is reset to an initial voltage (e.g., 12V). The initial voltage drives the first control transistor M6 to turn on, and the second control transistor M5 is turned on by the second voltage (12V). However, because the fully-on resistance of the first control transistor M6 is less than the fully-on resistance of the second control transistor M5, the voltage at point A is at or close to the first voltage (12V). The first output transistor M8 is driven by the voltage at point Q (e.g., 12V) to turn on, and the second output transistor M7 is driven by the voltage at point A (e.g., 12V) to turn off. The voltage output by output terminal Output1 is a third voltage (e.g., -12V) or close to the third voltage. During the discharge process at point Q, the voltage at point Q gradually decreases, the degree of opening of the first control transistor M6 and the first output transistor M8 gradually decreases, the voltage at point A gradually increases, the degree of opening of the second output transistor M7 gradually increases, and the voltage at output terminal Output1 gradually increases. When the voltage at point Q drops to the target voltage (e.g., -12V), the second output transistor M7 turns on, the first output transistor M8 turns off, and the voltage at output terminal Output1 rises to a fourth voltage (e.g., 12V) and remains at the fourth voltage until the end of the current cycle, at which point the next cycle begins.

[0089] For example, in other embodiments, any one of the first control circuit, the second control circuit, the first output circuit, and the second output circuit may include two or more transistors, or may include other devices besides transistors, as long as each circuit can achieve the above functions.

[0090] For example, a first terminal of the regulation circuit 120 is directly or indirectly connected to the target terminal (Q point), a second terminal of the regulation circuit 120 receives a fifth voltage (e.g., VSS), and a third terminal of the regulation circuit receives the regulation signal Datastep. The regulation circuit 120 is configured to control the discharge or charge speed of the target terminal (Q point) based on the regulation signal Datastep. For example, according to the above embodiment, when the voltage of the regulation signal Datastep changes, the discharge or charge speed of the target terminal (Q point) increases or decreases accordingly, thereby increasing or decreasing the duty cycle of the output signal.

[0091] For example, a first terminal of the reset circuit 110 is configured to receive a sixth voltage (e.g., VDD), and a second terminal of the reset circuit is configured to receive a first reset signal Reset1. The reset circuit 110 is configured to reset the voltage at a target terminal (point Q) of the reset circuit using the sixth voltage (e.g., VDD) under the control of the first reset signal Reset1. The regulation circuit 120 is configured to control the discharge or charge speed of the target terminal (point Q) according to the regulation signal Datastep after the voltage at the target terminal (point Q) is reset.

[0092] For example, the reset circuit 110 includes a reset transistor M1. The gate of the reset transistor M1 receives a first reset signal Reset1. One of the source and drain of the reset transistor M1 receives a sixth voltage (e.g., VDD). The other is a target terminal (point Q). The reset transistor M1 is configured to be turned on or off under the control of the first reset signal.

[0093] For example, the high voltage of the first reset signal Reset1 may be 14V, and the low voltage may be -14V. The reset transistor M1 may be an N-type thin film transistor, which is turned on under the action of a high level and turned off under the action of a low level. The fifth voltage (VSS connected to M2) may be a negative voltage (such as -12V), and the sixth voltage (VDD connected to M1) may be a positive voltage (such as 12V). For example, when the cycle starts, a high voltage reset signal (such as 14V) is applied to the reset transistor M1 to turn on the reset transistor M1, and the sixth voltage (such as 12V) is applied to the target terminal (Q terminal) through the reset transistor M1 to reset the target terminal (Q terminal) to an initial voltage, which is the sixth voltage or close to the sixth voltage.

[0094] For example, the signal conditioning device further includes a storage capacitor C1 , which is connected to the target terminal (Q point). The storage capacitor C1 is configured to store the voltage of the target terminal (Q point).

[0095] For example, in other embodiments, the reset circuit 110 may include two or more transistors, or may include other devices in addition to transistors, as long as the reset circuit 110 can achieve the above functions.

[0096] For example, in some embodiments, the regulation circuit 120 includes a first regulation circuit, wherein a first terminal of the first regulation circuit is connected to the target terminal (Q point), a second terminal of the first regulation circuit receives a fifth voltage (e.g., VSS), and a third terminal of the first regulation circuit receives a regulation signal Datastep. The first regulation circuit 120 is configured to control the discharge or charge speed of the target terminal (Q point) based on the regulation signal Datastep.

[0097] For example, as shown in FIG3 , the first regulating circuit includes a first regulating transistor M2. The gate of the first regulating transistor M2 receives the regulating signal Datastep. One of the source and drain of the first regulating transistor M2 is connected to the target terminal (point Q), and the other receives a fifth voltage (e.g., VSS). The first regulating transistor M2 is configured to adjust the degree of conduction of the first regulating transistor M2 based on the voltage of the regulating signal Datastep.

[0098] For example, the first regulating transistor M2 can be an N-type thin-film transistor, which is turned on when a high voltage level is applied and turned off when a low voltage level is applied. The voltage of the regulating signal Datastep can be a negative voltage and greater than the cutoff voltage of the first regulating transistor M2. The voltage difference between the regulating signal Datastep and the cutoff voltage of the first regulating transistor M2 is less than a threshold. For example, the cutoff voltage of the first regulating transistor M2 can be -12V, and the voltage of the regulating signal Datastep can be around -11V or -10V. This allows the regulating signal Datastep to control the discharge speed of the Q point, preventing the Q point from discharging too quickly and thus failing to adjust the duty cycle of the output signal. The first regulating transistor M2 can be in a normally-on state, meaning that the regulating signal Datastep is always applied to the first regulating transistor M2 under normal circumstances. After the voltage at the Q point is reset to an initial voltage (e.g., -12V), the Q point begins to discharge through the first regulating transistor M2. In this embodiment, the higher the voltage of the regulating signal Datastep, the faster the Q point discharges and the greater the duty cycle of the output signal; the lower the voltage of the regulating signal Datastep, the slower the Q point discharges and the smaller the duty cycle of the output signal.

[0099] FIG4 is a schematic diagram of a signal waveform provided by at least one embodiment of the present disclosure.

[0100] As shown in FIG4 , the first reset signal Reset1 in the embodiment shown in FIG3 can be seen in the column “Reset1” in FIG4 . It can be seen that for each cycle, the first reset signal Reset1 is high for a short period of time after the start of the cycle, then jumps to a low level and maintains the low level until the end of the cycle. For example, if a cycle is 100 microseconds, the ratio of the high-level duration to the low-level duration of the first reset signal Reset1 is 5 / 95, that is, the high-level duration is 5 microseconds and the low-level duration is 95 microseconds. However, the present disclosure is not limited to this. The ratio of the high-level duration to the low-level duration of the first reset signal Reset1 can be a ratio between 1 / 99 and 10 / 90. In this way, the requirement of resetting the Q-point voltage can be met without taking up too much time for duty cycle adjustment. When reset transistor M1 is an N-type thin-film transistor, at the beginning of each cycle, the first reset signal Reset1 applies a high level to reset transistor M1, turning it on and resetting point Q. After point Q is reset, the first reset signal Reset1 applies a low level to reset transistor M1, turning it off. Reset transistor M1 remains off until the end of each cycle. The output signal Output1 in the embodiment shown in FIG3 can be found in the "Output1" column in FIG4 , and the voltage at point Q in the embodiment shown in FIG3 can be found in the "1-Q point" column in FIG4 . It can be seen that in the embodiment shown in FIG3 , as the voltage of the adjustment signal Datastep decreases, the degree of opening of the adjustment circuit decreases, the discharge rate at point Q slows down, and the duty cycle of the output signal Output1 decreases. For example, when the voltage of the adjustment signal Datastep is -10.6V, the Q-point voltage changes from positive to negative in the first half of the cycle. Correspondingly, the output signal Output1 changes from negative to positive in the first half of the cycle. During the cycle, the output signal Output1 spends a relatively large proportion of its voltage in the positive state, resulting in a large duty cycle (60.2%). When the voltage of the adjustment signal Datastep changes to -10.75V, the Q-point voltage changes from positive to negative in the second half of the cycle. Correspondingly, the output signal Output1 changes from negative to positive in the second half of the cycle. During the cycle, the output signal Output1 spends a relatively small proportion of its voltage in the positive state, resulting in a small duty cycle (34.4%). For example, when Datastep = [-10.6V, -10.7V, -10.71V, -10.72V, -10.75V], the duty cycle of the output signal (high voltage time / cycle length H) = [60.2%, 50.1%, 46.2%, 45.9%, 34.4%].

[0101] As can be seen from Figure 4, in the embodiment shown in Figure 3, the voltage change slope (or the slope of the signal transition edge) of various signals (such as the control signal and output signal) is relatively slow, and the signal transition edge is ramp-shaped, making it impossible to accurately calculate the duty cycle, affecting the practicality of the output signal. To address this problem, the following embodiment is provided.

[0102] FIG5 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure.

[0103] As shown in FIG5 , for example, the fourth terminal of the regulation circuit 120 is connected to the output terminal. The regulation circuit 120 is further configured to control the voltage change slope of the target terminal (Q point) during the discharge or charge process based on the voltage at the output terminal. To distinguish the output signals of different embodiments, in the embodiment shown in FIG4 , the output signal is represented as Output3.

[0104] For example, by connecting the regulation circuit 120 to the output end of the output circuit, the voltage at the output end can be used to affect the degree of opening of the regulation circuit 120, thereby adjusting the voltage change slope of each signal (such as the control signal, output signal, etc.), making the voltage change slope of the output signal steeper, and thus making the output signal closer to a square wave signal, thereby improving the practicality of the output signal.

[0105] For example, the regulation circuit 120 includes a first regulation circuit 121 and a second regulation circuit 122. A first terminal of the first regulation circuit 121 and a first terminal of the second regulation circuit 122 are both connected to a target terminal (Q point). A second terminal of the first regulation circuit 121 and a second terminal of the second regulation circuit 122 are both configured to receive a fifth voltage (e.g., VSS). A third terminal of the first regulation circuit 121 receives a regulation signal Datastep. The first regulation circuit 121 is configured to control the discharge or charge speed of the target terminal (Q point) based on the regulation signal Datastep. A third terminal of the second regulation circuit 122 is connected to an output terminal Output3. The second regulation circuit 122 is configured to control the voltage change slope of the target terminal (Q point) during the discharge or charge process based on the voltage of the output terminal Output3.

[0106] For example, the second regulating circuit 122 is in a closed state at the beginning of a cycle. When the voltage at the output terminal Output3 is higher than a certain value, the second regulating circuit 122 can be controlled to be open, thereby accelerating the discharge speed of point Q, causing the voltage at point Q to quickly jump to the target voltage (e.g., -12V), and thus causing the voltage of the output signal Output3 to quickly jump to the second output voltage (e.g., 12V). In this way, the transition slope of the output signal Output3 can be made steeper.

[0107] For example, the first regulation circuit 121 may include a first regulation transistor M2, and the second regulation circuit 122 may include a second regulation transistor M4. The gate of the first regulation transistor M2 receives the regulation signal Datastep, one of the source and drain of the first regulation transistor M2 is connected to the target terminal (Q point), and the other receives a fifth voltage (e.g., VSS). The gate of the second regulation transistor M4 is connected to the output terminal Output3, one of the source and drain of the second regulation transistor M4 is connected to the target terminal (Q point), and the other receives a fifth voltage (e.g., VSS). The first regulation transistor M2 is configured to adjust the conduction level of the first regulation transistor M2 based on the voltage of the regulation signal Datastep; the second regulation transistor M4 is configured to adjust the conduction level of the second regulation transistor M4 based on the voltage of the output terminal Output3.

[0108] For example, during the discharge process at point Q, as the voltage at point Q decreases, the first control transistor M6 and the first output transistor M8 gradually turn off, the voltage at point A gradually increases, the second output transistor M7 gradually turns on, and the output signal Output3 gradually increases. When the output signal Output3 voltage minus the VSS voltage exceeds the threshold voltage (Vth) of the second regulating transistor M4, the second regulating transistor M4 turns on, and point Q discharges rapidly, turning off the first control transistor M6 and the first output transistor M8. The voltage at point A rises rapidly, turning on the second output transistor M7, and the voltage of the output signal Output3 rises rapidly, quickly jumping from a low voltage to a high voltage.

[0109] FIG6 is a schematic diagram of another signal waveform provided by at least one embodiment of the present disclosure.

[0110] As shown in FIG6 , the first reset signal Reset1 in the embodiment shown in FIG5 can be found in the column “Reset1” in FIG6 . It can be seen that for each cycle, the first reset signal Reset1 is high for a short period of time after the start of the cycle (e.g., the high level duration accounts for 5 / 95 of the cycle), turning on the reset transistor M1 and resetting the Q point. Thereafter, the first reset signal Reset1 jumps to a low level and remains low until the end of the cycle, turning off the reset transistor M1 and maintaining the off state until the end of the cycle. The output signal Output3 in the embodiment shown in FIG5 can be found in the column “Output3” in FIG4 , and the Q point voltage in the embodiment shown in FIG5 can be found in the column “3-Q point” in FIG6 . It can be seen that, compared to the embodiment shown in FIG3 , after adding the second regulation circuit 122, the voltage change slope of the output signal Output3 becomes steeper, and the output signal is closer to a square wave signal, which is conducive to accurately calculating the duty cycle and improving the practicality of the output signal. FIG6 also shows that in the embodiment shown in FIG5 , as the voltage of the regulation signal Datastep increases, the degree of opening of the regulation circuit increases, the discharge rate of point Q increases, and the duty cycle of the output signal Output1 increases. For example, when Datastep = [-11.1V, -11.05V, -10.95V, -10.8V, -10.7V], the duty cycle of the output signal Output1 (high voltage time / cycle duration H) = [10.2%, 21.1%, 44.7%, 65.9%, 76.3%].

[0111] FIG. 7 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure.

[0112] As shown in FIG7 , compared to the embodiment shown in FIG3 , a reset assist circuit 150 is added to the signal conditioning device. Reset assist circuit 150 is connected between the first terminal of conditioning circuit 120 and the target terminal (point Q). A first terminal of reset assist circuit 150 is connected to the first terminal of conditioning circuit 120, a second terminal of reset assist circuit 150 is connected to the target terminal (point Q), and a third terminal of reset assist circuit 150 is configured to receive a second reset signal, Reset2. Reset assist circuit 150 is turned on or off under the control of second reset signal, Reset2. To distinguish output signals between different embodiments, in the embodiment shown in FIG7 , the output signal is designated as Output2.

[0113] For example, the second reset signal 150 is configured to control the reset assist circuit 150 to be turned off when the reset circuit 110 is turned on, and to control the reset assist circuit 150 to be turned on when the reset circuit 110 is turned off.

[0114] For example, when the reset circuit 110 is turned on, point Q is reset. If the reset assist circuit 150 is not provided and the regulation circuit 120 is normally open, point Q will leak current through the regulation circuit 120 during the reset process, affecting the reset of point Q and increasing power consumption and heat generation. In the disclosed embodiment, a reset assist circuit 150 is provided between the regulation circuit 120 and point Q. During the reset of point Q, the reset assist circuit 150 is turned off by the second reset signal 150. This prevents leakage current from point Q during the reset process, ensures that point Q is reset to the initial voltage, reduces power consumption, and avoids heat generation. After point Q is reset, the second reset signal 150 can control the reset assist circuit 150 to turn on, allowing point Q to discharge (or charge) through the reset assist circuit 150 and the regulation circuit 120.

[0115] For example, the regulation circuit 120 includes a first regulation circuit, a first terminal of the first regulation circuit being connected to a first terminal of the reset assist circuit 150, a second terminal of the first regulation circuit receiving a fifth voltage (e.g., VSS), and a third terminal of the first regulation circuit receiving a regulation signal Datastep. The first regulation circuit is configured to control a discharge or charge rate of a target terminal (Q point) based on the regulation signal Datastep.

[0116] For example, the first regulation circuit includes a first regulation transistor M2, and the reset assist circuit 150 includes a reset assist transistor M3. The gate of the first regulation transistor M2 receives the regulation signal Datastep, one of the source and drain of the first regulation transistor M2 is connected to the reset assist transistor M3, and the other receives a fifth voltage (e.g., VSS). The gate of the reset assist transistor M3 receives the second reset signal Reset2, one of the source and drain of the reset assist transistor M3 is connected to the first regulation transistor M2, and the other is connected to the target terminal (Q point). The first regulation transistor M2 is configured to adjust the degree of conduction of the first regulation transistor M2 based on the voltage of the regulation signal Datastep. The reset assist transistor M3 is configured to be turned on or off under the control of the second reset signal Reset2.

[0117] For example, when the reset transistor M1 and the reset auxiliary transistor M3 are the same type of transistors (for example, both are N-type transistors), the first reset signal Reset1 and the second reset signal Reset2 can be opposite signals, that is, when the first reset signal Reset1 is high, the second reset signal Reset2 is low; when the first reset signal Reset1 is low, the second reset signal Reset2 is high.

[0118] For example, in the embodiment shown in FIG7 , the waveform of the signal is shown in FIG4 . The first reset signal Reset1 in the embodiment shown in FIG7 can be seen in the “Reset1” column in FIG4 . It can be seen that for each cycle, the first reset signal Reset1 is high for a short period of time after the start of the cycle (e.g., the high level duration accounts for 5 / 95 of a cycle), so that the reset transistor M1 is turned on and the Q point is reset. Thereafter, the first reset signal Reset1 jumps to a low level and remains low until the end of a cycle, so that the reset transistor M1 is turned off and remains in the off state until the end of a cycle. The output signal Output2 in the embodiment shown in FIG7 can be seen in the “Output2” column in FIG4 . The waveform of the output signal Output2 can be the same as the waveform of the output signal Output1 in the embodiment shown in FIG3 , and will not be repeated here. The Q point voltage in the embodiment shown in FIG7 can be seen in the “2-Q point” column in FIG4 . The 2-Q point voltage can be the same as the 1-Q point voltage in the embodiment shown in FIG3 , and will not be repeated here. Compared with the embodiment shown in Figure 3, the embodiment shown in Figure 7 adds a second reset signal Reset2. The second reset signal Reset2 in the embodiment shown in Figure 7 can be found in the "Reset2" column in Figure 4. It can be seen that when the reset transistor M1 and the reset auxiliary transistor M3 are transistors of the same type (for example, both are N-type transistors), the level of the second reset signal Reset2 can be opposite to the first reset signal Reset1. The second reset signal Reset2 is low for a short period of time after the start of the cycle to turn off the reset auxiliary transistor M3 and avoid leakage current during the Q point reset process. After that, the second reset signal Reset2 jumps to a high level and maintains a high level until the end of one cycle, so that the reset auxiliary transistor M3 is turned on and remains in the on state until the end of one cycle. For example, one cycle is 100 microseconds, and the ratio of the low-level duration to the high-level duration of the second reset signal Reset2 is 5 / 95, the low-level duration is 5 microseconds, and the high-level duration is 95 microseconds, but the present disclosure is not limited to this. The ratio of the low-level duration to the high-level duration of the second reset signal Reset2 can be a ratio between 1 / 99 and 10 / 90.

[0119] For example, in other embodiments, the reset assist circuit may include two or more transistors, or may include other devices in addition to transistors, as long as the reset assist circuit can achieve the above functions.

[0120] FIG8 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure.

[0121] As shown in FIG8 , compared to the embodiment shown in FIG5 , a reset assist circuit 150 is added to the signal conditioning device. The conditioning circuit may include a first conditioning circuit and a second conditioning circuit. The first end of the first conditioning circuit and the first end of the second conditioning circuit are both connected to the first end of the reset assist circuit 150. The second end of the first conditioning circuit and the second end of the second conditioning circuit are both configured to receive a fifth voltage (e.g., VSS). The third end of the first conditioning circuit receives a conditioning signal, Datastep. The first conditioning circuit is configured to control the discharge or charge speed of the target terminal (Q point) based on the conditioning signal, Datastep. The third end of the second conditioning circuit is connected to the output terminal, Output4. The second conditioning circuit is configured to control the voltage change slope of the target terminal (Q point) during the discharge or charge process based on the voltage at the output terminal, Output4. To distinguish the output signals of different embodiments, in the embodiment shown in FIG8 , the output signal is represented as Output4.

[0122] For example, the first regulation circuit includes a first regulation transistor M2, the second regulation circuit includes a second regulation transistor M4, and the reset assist circuit 150 includes a reset assist transistor M3. The gate of the first regulation transistor M2 receives the regulation signal Datastep, one of the source and drain of the first regulation transistor M2 is connected to the second regulation transistor M4 and the reset assist transistor M3, and the other receives a fifth voltage (e.g., VSS). The gate of the second regulation transistor M4 is connected to the output terminal Output, one of the source and drain of the second regulation transistor M4 is connected to the first regulation transistor M2 and the reset assist transistor M3, and the other is connected to the target terminal (Q point). The gate of the reset assist transistor M3 receives the second reset signal Reset2, one of the source and drain of the reset assist transistor M3 is connected to the first regulation transistor M2 and the second regulation transistor M4, and the other is connected to the target terminal (Q point). The first regulation transistor M2 is configured to adjust the conduction level of the first regulation transistor M2 based on the voltage of the regulation signal Datastep. The second regulation transistor M4 is configured to adjust the conduction level of the second regulation transistor M4 based on the voltage of the output terminal Output4. The reset auxiliary transistor M3 is configured to be turned on or off under the control of the second reset signal Reset2 .

[0123] For example, in the embodiment shown in FIG8 , the waveform of the signal is shown in FIG6 . The first reset signal Reset1 in the embodiment shown in FIG8 can be seen in the column “Reset1” in FIG6 . It can be seen that for each cycle, the first reset signal Reset1 is high for a short period of time after the start of the cycle (for example, the high level duration accounts for 5 / 95 of a cycle), so that the reset transistor M1 is turned on and the Q point is reset. Thereafter, the first reset signal Reset1 jumps to a low level and remains low until the end of a cycle, so that the reset transistor M1 is turned off and remains in the off state until the end of a cycle. The output signal Output4 in the embodiment shown in FIG8 can be seen in the column “Output4” in FIG6 . The waveform of the output signal Output4 can be the same as the waveform of the output signal Output3 in the embodiment shown in FIG5 , and will not be repeated here. The Q point voltage in the embodiment shown in FIG8 can be seen in the column “4-Q point” in FIG6 . The 4-Q point voltage can be the same as the 3-Q point voltage in the embodiment shown in FIG5 , and will not be repeated here. Compared to the embodiment shown in FIG5 , the embodiment shown in FIG8 adds a second reset signal Reset2. The second reset signal Reset2 in the embodiment shown in FIG8 can be found in the "Reset2" column in FIG6 . It can be seen that the second reset signal Reset2 is low for a short period of time after the start of the cycle (for example, the low level duration accounts for 5 / 95 of a cycle) to turn off the reset auxiliary transistor M3 and avoid leakage current during the Q point reset process. After that, the second reset signal Reset2 jumps to a high level and maintains a high level until the end of a cycle, so that the reset auxiliary transistor M3 is turned on and remains in the on state until the end of a cycle. In the embodiment shown in FIG8 , not only can the Q point be reset to the initial voltage, but the output signal transition edge can also be made steeper, which is conducive to accurately calculating the duty cycle and improving the practicality of the output signal.

[0124] In the above embodiments, a detailed description is given using as an example an example where the transistors included in the reset circuit 110, the regulating circuit 120, the control circuit 130, and the output circuit 140 are all N-type thin film transistors. The following briefly describes a case where the transistors included in the reset circuit 110, the regulating circuit 120, the control circuit 130, and the output circuit 140 are all P-type thin film transistors.

[0125] FIG9 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure.

[0126] Compared to Figure 3 , the positions of the high-level VDD and low-level VSS are swapped in the example of Figure 9 . In Figure 3 , each transistor is N-type. The reset transistor M1 is connected to the high-level VDD to reset the Q point to the high-level VDD. The first control transistor M6 and the first output transistor M8 are turned on at the low level. The first regulating transistor M2 is connected to the low-level VSS to discharge the Q point. The first control transistor M6 is connected to the low-level VSS to apply a low level to the second output transistor M7 when the first control transistor M6 is turned on. The second control transistor M5 is connected to the high-level VDD to apply a high level to the second output transistor M7 when the first control transistor M6 is turned off. The first output transistor M8 is connected to the low-level VSS to cause the output terminal "Output" to output a low level when the first output transistor M8 is turned on and the second output transistor M7 is turned off. The second output transistor M7 is connected to the high-level VDD to cause the output terminal "Output" to output a high level when the first output transistor M8 is turned off and the second output transistor M7 is turned on. The duty cycle of the output signal may be the ratio of the duration during which the output signal maintains a high level to the total duration of the period within one cycle.

[0127] In contrast, in FIG9 , each transistor is P-type. The reset transistor M1 is connected to a low voltage VSS to reset the Q point to a low voltage VSS, and the first regulating transistor M2 is connected to a high voltage VDD to charge the Q point. The first control transistor M6 is connected to a high voltage VDD to apply a high voltage to the second output transistor M7 when the first control transistor M6 is on. The second control transistor M5 is connected to a low voltage VSS to apply a low voltage to the second output transistor M7 when the first control transistor M6 is off. The first output transistor M8 is connected to a high voltage VDD to cause the output terminal "Output" to output a high voltage when the first output transistor M8 is on and the second output transistor M7 is off. The second output transistor M7 is connected to a low voltage VSS to cause the output terminal "Output" to output a low voltage when the first output transistor M8 is off and the second output transistor M7 is on. The duty cycle of the output signal can be the ratio of the duration that the output signal remains low within a cycle to the total duration of the cycle.

[0128] FIG10 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure. Compared to FIG5 , in the example of FIG10 , the positions of the high level VDD and the low level VSS are swapped.

[0129] FIG11 is a schematic diagram of another signal conditioning device provided by at least one embodiment of the present disclosure. Compared to FIG7 , in the example of FIG11 , the positions of the high level VDD and the low level VSS are swapped.

[0130] FIG12 is a schematic diagram of another signal conditioning device according to at least one embodiment of the present disclosure. Compared to FIG8 , in the example of FIG12 , the positions of the high level VDD and the low level VSS are swapped.

[0131] For example, in the embodiments shown in Figures 9 to 12, the adjustment signal Datastep can be a positive voltage and less than the cut-off voltage of the first adjustment transistor M2. The voltage difference between the voltage of the adjustment signal Datastep and the cut-off voltage of the first adjustment transistor M2 is less than a threshold. For example, the cut-off voltage of the first adjustment transistor M2 can be 12V, and the voltage of the adjustment signal Datastep can be around 10V. In this way, the adjustment signal Datastep can control the charging speed of the Q point, preventing the Q point from charging too quickly and causing the duty cycle of the output signal to be unable to be adjusted.

[0132] FIG13 is a schematic diagram of another signal waveform provided by at least one embodiment of the present disclosure. FIG13 shows the waveforms of the signals in the examples shown in FIG9 and FIG11. It can be seen that when the reset transistor M1 is a P-type thin film transistor, for each cycle, the first reset signal Reset1 is at a low level for a short period of time after the start of the cycle (for example, the low level duration accounts for 5 / 95 of a cycle), so that the reset transistor M1 is turned on and the Q point is reset. Thereafter, the first reset signal Reset1 jumps to a high level and maintains the high level until the end of a cycle, so that the reset transistor M1 is turned off and remains in the off state until the end of a cycle. When the reset transistor M1 and the reset auxiliary transistor M3 are both P-type transistors, the level of the second reset signal Reset2 can be opposite to that of the first reset signal Reset1. The second reset signal Reset2 is high for a short period of time after the start of the cycle (for example, the high level duration accounts for 5 / 95 of a cycle) to turn off the reset auxiliary transistor M3 to avoid leakage current during the Q point reset process. After that, the second reset signal Reset2 jumps to a low level and maintains a low level until the end of a cycle, so that the reset auxiliary transistor M3 is turned on and remains in the on state until the end of a cycle.

[0133] For example, as shown in Figure 13, as the voltage of the regulation signal Datastep increases, the degree of opening of the regulation circuit decreases, the charging speed of the Q point (5-Q point or 6-Q point) slows down, and the duty cycle of the output signal (Output5 or Output6) decreases. For example, when the voltage of the regulation signal Datastep is 9.8V, the voltage at the Q point (5-Q point or 6-Q point) changes from negative to positive in the first half of the cycle. Correspondingly, the output signal (Output5 or Output6) changes from positive to negative in the first half of the cycle. Within a cycle, the output signal (Output5 or Output6) spends a large proportion of its voltage in the negative state, resulting in a large duty cycle (69.8%). When the voltage of the adjustment signal Datastep changes to 9.94V, the voltage at point Q (point 5-Q or point 6-Q) changes from negative to positive in the second half of the cycle. Correspondingly, the output signal (Output5 or Output6) changes from full voltage to negative in the second half of the cycle. The proportion of the output signal (Output5 or Output6) in a cycle that is negative is relatively small, and the duty cycle is small (39.7%). The voltage change slopes of the various signals in Figure 13 are relatively gentle, and the signal transition edges are ramp-shaped. For example, when the adjustment signal Datastep = [9.8V, 9.9V, 9.94V], the output signal Output duty cycle (low voltage time / cycle duration H) = [69.8%, 54.8%, 39.7%].

[0134] Figure 14 is a schematic diagram of another signal waveform provided by at least one embodiment of the present disclosure. Figure 14 shows the waveforms of the signals in the examples shown in Figures 10 and 12. For the description of the waveforms of the first reset signal Reset1 and the second reset signal Reset2 in Figure 14, please refer to the description of Figure 13, which will not be repeated here. Compared with the Q point (5-Q point or 6-Q point) voltage in Figure 13, it can be seen that after the second adjustment circuit is added, the Q point (7-Q point or 8-Q point) voltage shown in Figure 14 has a steeper transition edge. Accordingly, compared with the output signal (Output5 or Output6) in Figure 13, it can be seen that after the second adjustment circuit is added, the output signal (Output7 or Output8) shown in Figure 14 has a steeper transition edge, which can improve the practicality of the output signal. For example, when Datastep = [10.28V, 10.25V, 10.18V, 10V, 9.8V], the duty cycle of the output signal Output (low voltage time / cycle length H) = [9.9%, 22.5%, 45.6%, 74.9%, 85.3%].

[0135] For example, the output signal of the embodiment of the present disclosure can be connected to the pixel driving circuit of the display panel to achieve control of the display effect. In some embodiments, the output signal can be connected to the first voltage terminal ELVDD of the pixel driving circuit, and the overall brightness of the display panel can be controlled by controlling the working duration of the ELVDD signal. In other embodiments, the output signal can be connected to the gate of the data write transistor (DTFT) in the pixel driving circuit, acting as the gate drive signal of the data write transistor to adjust the pixel grayscale, and use the high grayscale to match the output signal to achieve low grayscale display. The above only illustrates some application directions of the signal adjustment device of the embodiment of the present disclosure. The actual use is not limited to this and can be flexibly adjusted according to actual conditions.

[0136] At least one embodiment of the present disclosure further provides a signal conditioning method, which is used in the signal conditioning device of any of the above embodiments. FIG15 is a flowchart of a signal conditioning method provided by at least one embodiment of the present disclosure. For example, as shown in FIG15 , the signal conditioning method includes steps S110 to S120.

[0137] Step 110: Apply a first reset signal to the reset circuit to control the reset circuit to reset the voltage of the target end to the initial voltage. The control circuit applies a first control voltage to the output circuit according to the initial voltage. The output circuit controls the output end to output a first output voltage according to the initial voltage and the first control voltage.

[0138] Step S120: Applying a regulating signal to the regulating circuit to charge or discharge the target end through the regulating circuit. During the charging or discharging process of the target end, the voltage of the control signal applied by the control circuit to the output circuit changes from the first control voltage to the second control voltage, and the voltage of the output signal at the output end of the output circuit changes from the first output voltage to the second output voltage.

[0139] For example, in some embodiments, the signal conditioning method may further include: changing the voltage of the conditioning signal to change the duty cycle of the output signal. The target terminal discharge or charge speed, the voltage change speed of the control signal, and the voltage change speed of the output signal all change with changes in the voltage of the conditioning signal. The duty cycle of the output signal at the output terminal is related to the voltage change speed of the output signal.

[0140] For specific embodiments of the signal conditioning method provided in the embodiments of the present disclosure, reference may be made to the above description of the signal conditioning device. For technical effects of the signal conditioning method provided in the embodiments of the present disclosure, reference may be made to the corresponding description of the signal conditioning device in the above embodiments, which will not be repeated here.

[0141] At least one embodiment of the present disclosure further provides an electronic device. FIG16 is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure. For example, as shown in FIG16 , the electronic device 1 includes a signal conditioning device 100 , such as the signal conditioning device 100 provided by any embodiment of the present disclosure.

[0142] For example, the electronic device 1 may further include other components such as a pixel driving circuit.

[0143] For example, the electronic device 1 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or a combination of any electronic device and hardware, which is not limited in the embodiments of the present disclosure.

[0144] It should be noted that for the sake of clarity and brevity, the embodiments of the present disclosure do not provide all components of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art may provide and configure other components not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0145] For the relevant description and technical effects of the electronic device 1 , reference may be made to the relevant description and technical effects of the frequency divider provided in the embodiments of the present disclosure, which will not be repeated here.

[0146] There are a few points to note:

[0147] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0148] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0149] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A signal conditioning device, comprising: A reset circuit, an adjustment circuit, a control circuit, and an output circuit, wherein, the reset circuit is configured to receive a first reset signal and reset the voltage at the target end of the reset circuit according to the first reset signal, wherein the adjustment circuit, the control circuit, and the output circuit are all connected to the target end of the reset circuit; the adjustment circuit is configured to receive an adjustment signal and control at least the charging or discharging process of the target end according to the adjustment signal; the control circuit is connected to the output circuit, and the control circuit is configured to control the voltage applied to the output circuit according to the voltage at the target end; the output circuit is configured to control the voltage of the output signal at the output end of the output circuit according to the voltage at the target end and the voltage applied by the control circuit.

2. The signal conditioning device according to claim 1, wherein, The control circuit includes a first control circuit and a second control circuit, a first end of the first control circuit is connected to the output circuit, a second end of the first control circuit is configured to receive a first voltage, and a third end of the first control circuit is connected to the target end; a first end of the second control circuit is connected to the first end of the first control circuit, and a second end of the second control circuit is configured to receive a second voltage; the first control circuit is configured to control the voltage difference between the first end of the first control circuit and the first voltage according to the voltage at the target end; the second control circuit is configured to output the second voltage to the output circuit when the first control circuit is turned off.

3. The signal conditioning device according to claim 2, wherein, The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor, a gate of the first control transistor is connected to the target end, and one of a source and a drain of the first control transistor is connected to the second control transistor, and the other receives the first voltage; one of a source and a drain of the second control transistor receives the second voltage, and the other is connected to the first control transistor, and a gate of the second control transistor receives the second voltage; the first control transistor adjusts the opening degree of the first control transistor according to the voltage at the target end, and the first control circuit being turned off includes the first control transistor being cut off; the second control transistor is configured to turn on when the gate of the second control transistor receives the second voltage.

4. The signal conditioning device according to claim 3, wherein, The aspect ratio of the first control transistor is greater than the aspect ratio of the second control transistor.

5. The signal conditioning device according to any one of claims 1-4, wherein, The output circuit includes a first output circuit and a second output circuit; a first end of the first output circuit is connected to a first end of the second output circuit, a second end of the first output circuit is configured to receive a third voltage, and a third end of the first output circuit is connected to the target end; a second end of the second output circuit is configured to receive a fourth voltage, and a third end of the second output circuit is connected to the control circuit; an output end of the output circuit is connected to the first end of the first output circuit and the first end of the second output circuit; the first output circuit is configured to control the voltage difference between the voltage at the output end and the third voltage according to the voltage at the target end; The second output circuit is configured to control the voltage difference between the voltage at the output terminal and the fourth voltage according to the voltage applied by the control circuit.

6. The signal conditioning device according to claim 5, wherein, The first output circuit includes a first output transistor, and the second output circuit includes a second output transistor; The gate of the first output transistor is connected to the target terminal, and one of the gate and the drain of the first output transistor receives the third voltage, and the other is connected to the second output transistor; The gate of the second output transistor receives the voltage applied by the control circuit, and one of the source and the drain of the second output transistor receives the fourth voltage, and the other is connected to the first output transistor; The first output transistor adjusts the conduction degree of the first output transistor according to the voltage at the target terminal, and the second output transistor adjusts the conduction degree of the second output transistor according to the voltage applied by the control circuit.

7. The signal conditioning device according to any one of claims 1-6, wherein, The first end of the adjustment circuit is connected to the target terminal, the second end of the adjustment circuit receives a fifth voltage, and the third end of the adjustment circuit receives the adjustment signal; The adjustment circuit is configured to control the discharging or charging speed of the target terminal according to the adjustment signal.

8. The signal conditioning device according to claim 7, wherein, The adjustment circuit includes a first adjustment circuit, The first end of the first adjustment circuit is connected to the target terminal, the second end of the first adjustment circuit receives the fifth voltage, and the third end of the first adjustment circuit receives the adjustment signal; The first adjustment circuit is configured to control the discharging or charging speed of the target terminal according to the adjustment signal.

9. The signal conditioning device according to claim 8, wherein, The first adjustment circuit includes a first adjustment transistor, the gate of the first adjustment transistor receives the adjustment signal, and one of the source and the drain of the first adjustment transistor is connected to the target terminal, and the other receives the fifth voltage; The first adjustment transistor is configured to adjust the conduction degree of the first adjustment transistor according to the voltage of the adjustment signal.

10. The signal conditioning device according to claim 7, wherein, The fourth end of the adjustment circuit is connected to the output terminal; The adjustment circuit is further configured to control the voltage change slope of the target terminal during the discharging or charging process according to the voltage at the output terminal.

11. The signal conditioning device according to claim 10, wherein, The adjustment circuit includes a first adjustment circuit and a second adjustment circuit; The first ends of the first adjustment circuit and the second adjustment circuit are both connected to the target terminal, the second ends of the first adjustment circuit and the second adjustment circuit are both configured to receive a fifth voltage, The third end of the first adjustment circuit receives the adjustment signal, and the first adjustment circuit is configured to control the discharging or charging speed of the target terminal according to the adjustment signal; The third end of the second adjustment circuit is connected to the output terminal, and the second adjustment circuit is configured to control the voltage change slope of the target terminal during the discharging or charging process according to the voltage at the output terminal.

12. The signal conditioning device according to claim 11, wherein, The first adjustment circuit includes a first adjustment transistor, and the second adjustment circuit includes a second adjustment transistor, The gate of the first adjustment transistor receives the adjustment signal, and one of the source and the drain of the first adjustment transistor is connected to the target terminal, and the other receives the fifth voltage; The gate of the second regulating transistor is connected to the output terminal, one of the source and the drain of the second regulating transistor is connected to the target terminal, and the other receives the fifth voltage; The first regulating transistor is configured to regulate the conduction degree of the first regulating transistor according to the voltage of the regulating signal; The second regulating transistor is configured to regulate the conduction degree of the second regulating transistor according to the voltage of the output terminal.

13. The signal conditioning device according to claim 7, wherein, The signal regulating device further includes a reset assist circuit, and the reset assist circuit is connected between the first end of the regulating circuit and the target terminal; The first end of the reset assist circuit is connected to the first end of the regulating circuit, the second end of the reset assist circuit is connected to the target terminal, and the third end of the reset assist circuit is configured to receive a second reset signal; The reset assist circuit is turned on or off under the control of the second reset signal.

14. The signal conditioning device according to claim 13, wherein, The second reset signal is configured to control the reset assist circuit to turn off when the reset circuit is turned on, and control the reset assist circuit to turn on when the reset circuit is turned off.

15. The signal conditioning device according to claim 13 or 14, wherein, The regulating circuit includes a first regulating circuit, the first end of the first regulating circuit is connected to the first end of the reset assist circuit, the second end of the first regulating circuit receives the fifth voltage, and the third end of the first regulating circuit receives the regulating signal; The first regulating circuit is configured to control the discharging or charging speed of the target terminal according to the regulating signal.

16. The signal conditioning device according to claim 15, wherein, The first regulating circuit includes a first regulating transistor, and the reset assist circuit includes a reset assist transistor, The gate of the first regulating transistor receives the regulating signal, one of the source and the drain of the first regulating transistor is connected to the reset assist transistor, and the other receives the fifth voltage; The gate of the reset assist transistor receives the second reset signal, and the reset assist crystal One of the source and the drain of the tube is connected to the first regulating transistor, and the other is connected to the target terminal; The first regulating transistor is configured to regulate the conduction degree of the first regulating transistor according to the voltage of the regulating signal; The reset assist transistor is configured to be turned on or off under the control of the second reset signal.

17. The signal conditioning device according to claim 13 or 14, wherein, The regulating circuit includes a first regulating circuit and a second regulating circuit, The first end of the first regulating circuit and the first end of the second regulating circuit are both connected to the first end of the reset assist circuit, the second end of the first regulating circuit and the second end of the second regulating circuit are both configured to receive the fifth voltage, The third end of the first regulating circuit receives the regulating signal, and the first regulating circuit is configured to control the discharging or charging speed of the target terminal according to the regulating signal; The third end of the second regulating circuit is connected to the output terminal, and the second regulating circuit is configured to control the voltage change slope of the target terminal during the discharging or charging process according to the voltage of the output terminal.

18. The signal conditioning device according to claim 17, wherein, The first regulating circuit includes a first regulating transistor, the second regulating circuit includes a second regulating transistor, and the reset assist circuit includes a reset assist transistor, The gate of the first adjustment transistor receives the adjustment signal, one of the source and drain of the first adjustment transistor is connected to the second adjustment transistor and the reset assist transistor, and the other receives the fifth voltage; The gate of the second adjustment transistor is connected to the output terminal, one of the source and drain of the second adjustment transistor is connected to the first adjustment transistor and the reset assist transistor, and the other is connected to the target terminal; The gate of the reset assist transistor receives the second reset signal, one of the source and drain of the reset assist transistor is connected to the first adjustment transistor and the second adjustment transistor, and the other is connected to the target terminal; The first adjustment transistor is configured to adjust the conduction degree of the first adjustment transistor according to the voltage of the adjustment signal; The second adjustment transistor is configured to adjust the conduction degree of the second adjustment transistor according to the voltage of the output terminal; The reset assist transistor is configured to be turned on or off under the control of the second reset signal.

19. The signal conditioning device according to any one of claims 1-18, wherein, The first end of the reset circuit is configured to receive a sixth voltage, and the second end of the reset circuit is configured to receive the first reset signal; The reset circuit is configured to reset the voltage of the target end of the reset circuit by using the sixth voltage under the control of the first reset signal; The adjustment circuit is configured to control the discharge or charge speed of the target end according to the adjustment signal after the voltage of the target end is reset.

20. The signal conditioning device according to claim 19, wherein, The reset circuit includes a reset transistor, the gate of the reset transistor receives the first reset signal, and one of the source and drain of the reset transistor receives the sixth voltage. The other is the target end; The reset transistor is configured to be turned on or off under the control of the first reset signal.

21. The signal conditioning device according to any one of claims 1-20, wherein, The signal adjustment device further includes a storage capacitor, the storage capacitor is connected to the target end, and the storage capacitor is configured to store the voltage of the target end.

22. A signal adjustment method for the signal adjustment device according to any one of claims 1-21, the method comprising: Applying the first reset signal to the reset circuit to control the reset circuit to reset the voltage of the target end to an initial voltage, wherein the control circuit applies a first control voltage to the output circuit according to the initial voltage, and the output circuit controls the output terminal to output a first output voltage according to the initial voltage and the first control voltage; Applying the adjustment signal to the adjustment circuit to charge or discharge the target end through the adjustment circuit, wherein during the charging or discharging of the target end, the voltage of the control signal applied by the control circuit to the output circuit changes from the first control voltage to a second control voltage, and the voltage of the signal output by the output terminal of the output circuit changes from the first output voltage to a second output voltage.

23. The signal adjustment method according to claim 22, further comprising: Changing the voltage of the adjustment signal to change the duty cycle of the output signal; Wherein, the discharging or charging speed of the target end, the voltage change speed of the control signal, and the voltage change speed of the output signal all change with the change of the voltage of the adjustment signal; Wherein, the duty cycle of the output signal of the output end and the voltage change speed of the output signal are related.

24. A display device, comprising the signal adjustment device according to any one of claims 1-21.

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