Array substrate, display panel, and display device

Abstract

The present invention provides an array substrate, a display panel, and a display device. The array substrate comprises a plurality of pixel driving circuits, and each pixel driving circuit comprises a first transistor (T1) and a driving transistor (T2). The array substrate comprises: a base (10); a semiconductor layer (30) located on one side of the base (10), the semiconductor layer (30) comprising a first active layer pattern (31) of the first transistor (T1) and a second active layer pattern (32) of the driving transistor (T2), and the first active layer pattern (31) and the second active layer pattern (32) being mirror-symmetrical; and a first metal layer (40) located on the side of the semiconductor layer (30) away from the base (10), the first metal layer (40) comprising a first gate layer pattern (41), and at least part of the first gate layer pattern (41) overlapping the first active layer pattern (31) and the second active layer pattern (32). According to the present invention, the first transistor (T1) and the driving transistor (T2) shares the first gate layer pattern (41) as a gate, thereby simplifying a pixel driving circuit preparation process.

Description

Array substrate, display panel and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) devices have many advantages, such as being fully solid-state, self-luminous, wide viewing angle, wide color gamut, fast response speed, high luminous efficiency, high brightness, high contrast, ultra-thin, ultra-light, low power consumption, wide operating temperature range, the ability to produce large-size and flexible panels, and simple manufacturing process. They can achieve truly flexible displays and have received increasing attention and attention in the market in recent years.

[0003] Organic light-emitting display devices use pixel driver circuits to illuminate the light-emitting pixels to achieve the corresponding image display. Figure 1 shows an equivalent schematic diagram of a pixel driver circuit. In the prior art, the pixel driver circuit configured on the display panel shown in Figure 1 has a complex layout structure and high manufacturing difficulty.

[0004] Summary of the Invention

[0005] In view of the problems in the prior art, an object of the present invention is to provide an array substrate, a display panel and a display device.

[0006] An embodiment of the present invention provides an array substrate, including a plurality of pixel driving circuits, wherein the pixel driving circuits include a first transistor and a driving transistor; the array substrate includes:

[0007] substrate;

[0008] a semiconductor layer located on one side of the substrate, the semiconductor layer comprising a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are mirror-symmetrical;

[0009] The first metal layer is located on a side of the semiconductor layer away from the substrate. The first metal layer includes a first gate layer pattern. At least a portion of the first gate layer pattern overlaps with the first active layer pattern and the second active layer pattern.

[0010] In some embodiments, the portion where the first gate layer pattern overlaps with the first active layer pattern is the first channel of the first transistor, the portion where the first gate layer pattern overlaps with the second active layer pattern is the second channel of the driving transistor, and the first channel and the second channel are bent.

[0011] In some embodiments, the first transistor and the driving transistor share a portion of a channel.

[0012] In some embodiments, the pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor;

[0013] The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor;

[0014] The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor;

[0015] The third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern, and the fifth gate layer pattern overlaps with the fifth active layer pattern.

[0016] In some embodiments, the pixel driving circuit further includes a reset transistor, a first light emission control transistor, and a second light emission control transistor;

[0017] The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light emission control transistor, and an eighth active layer pattern of the second light emission control transistor;

[0018] The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light emission control transistor, and an eighth gate layer pattern of the second light emission control transistor;

[0019] The sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

[0020] In some embodiments, the pixel driving circuit further includes a storage capacitor;

[0021] The array substrate further comprises a second metal layer located on a side of the first metal layer away from the substrate; the second metal layer comprises a second plate pattern of the storage capacitor, an initialization voltage signal line, and a reset voltage signal line;

[0022] The second electrode pattern overlaps with the first gate layer pattern, and the overlapping portion of the vertical projections of the first gate layer pattern and the second electrode pattern on the substrate forms the storage capacitor;

[0023] The semiconductor layer further includes a ninth active layer pattern and a tenth active layer pattern arranged along the first direction, and the initialization voltage signal line overlaps with the ninth active layer pattern;

[0024] The reset voltage signal line overlaps with the tenth active layer pattern.

[0025] In some embodiments, the device further includes a third metal layer arranged along the first direction and located on a side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line;

[0026] The first scanning signal line overlaps with the third gate layer pattern of the initialization transistor;

[0027] The second scanning signal line overlaps with the fourth gate layer pattern of the write transistor and the fifth gate layer pattern of the compensation transistor;

[0028] The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

[0029] In some embodiments, the third metal layer further includes a first positive power supply voltage signal line, and the first electrode plate of the storage capacitor overlaps with the first positive power supply voltage signal line.

[0030] In some embodiments, the method further includes a fourth metal layer disposed along the second direction and located on a side of the third metal layer away from the substrate.

[0031] In some embodiments, the fourth metal layer includes a data line and a second positive power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data write transistor; the second positive power supply voltage signal line overlaps with the first positive power supply voltage signal line.

[0032] An embodiment of the present invention further provides a display panel, comprising the array substrate described above.

[0033] An embodiment of the present invention further provides a display device, comprising the array substrate described above.

[0034] The array substrate, display panel, and display device provided by the present invention have the following advantages:

[0035] The array substrate includes multiple pixel driving circuits, each including a first transistor and a driving transistor. The array substrate includes: a substrate; a semiconductor layer located on one side of the substrate, the semiconductor layer including a first active layer pattern for the first transistor and a second active layer pattern for the driving transistor; the first active layer pattern and the second active layer pattern being mirror-image symmetrical; and a first metal layer located on a side of the semiconductor layer away from the substrate, the first metal layer including a first gate layer pattern, at least a portion of the first gate layer pattern overlapping with the first active layer pattern and the second active layer pattern. In the present invention, the first transistor and the driving transistor share the first gate layer pattern as a gate, simplifying the process of manufacturing the pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0037] FIG1 is an equivalent schematic diagram of a pixel driving circuit;

[0038] 2 is a schematic diagram showing a layout of a semiconductor layer and a first metal layer provided on an array substrate according to an embodiment of the present invention;

[0039] 3 is a schematic diagram of the layout of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0040] 4 is a schematic diagram of the layout of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0041] 5 is a schematic diagram of the layout of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0042] 6 is a schematic diagram of the layout of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0043] 7 is a schematic diagram of the layout of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0044] 8 is a schematic diagram of the layout of the first transistor and the driving transistor of the array substrate provided by another embodiment of the present invention;

[0045] 9 is a schematic diagram showing a layout of a semiconductor layer and a first metal layer provided on an array substrate according to another embodiment of the present invention;

[0046] 10 is a schematic diagram showing a layout of a semiconductor layer and a first metal layer provided on an array substrate according to another embodiment of the present invention;

[0047] 11 is a schematic diagram showing a layout of a semiconductor layer and a first metal layer provided on an array substrate according to another embodiment of the present invention;

[0048] 12 is a schematic diagram of the layout of an array substrate provided with a second metal layer according to an embodiment of the present invention;

[0049] 13 is a schematic diagram of the layout of an array substrate provided with a second metal layer according to another embodiment of the present invention;

[0050] 14 is a schematic diagram of the layout of an array substrate provided with a third metal layer according to an embodiment of the present invention;

[0051] 15 is a schematic diagram of the layout of an array substrate provided with a third metal layer according to an embodiment of the present invention;

[0052] 16 is a schematic diagram of the layout of an array substrate provided with a fourth metal layer according to an embodiment of the present invention;

[0053] FIG17 is a cross-sectional view taken along section line AA′ in FIG16 ;

[0054] FIG18 is a cross-sectional view taken along section line BB' in FIG16;

[0055] FIG19 is a cross-sectional view taken along line CC′ in FIG16 . DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, identical reference numerals denote identical or similar structures, and thus repetitive descriptions thereof will be omitted. The use of "or" and "either" in this specification may mean "and" or "or."

[0057] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied through different specific embodiments. The details in the present application can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present application. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0058] To address the problems in the prior art, an embodiment of the present invention provides an array substrate. Figure 1 shows an equivalent schematic diagram of a pixel driving circuit in an array substrate provided by an embodiment of the present invention. As shown in Figure 1, the pixel driving circuit includes a first transistor T1, a driving transistor T2, an initialization transistor T3, a data writing transistor T4, a compensation transistor T5, a reset transistor T6, a first emission control transistor T7, and a second emission control transistor T8.

[0059] The first transistor T1 and the driving transistor T2 are turned on and off in response to the potential of the first node n1 ; the control terminals of the first transistor T1 and the driving transistor T2 are electrically connected to the first node n1 .

[0060] The initialization transistor T3 transmits an initialization voltage to the first node n1 in response to the first scan signal. A first terminal of the initialization transistor T3 is electrically connected to the initialization voltage signal line Vint, a second terminal of the initialization transistor T3 is electrically connected to the first node n1, and a control terminal of the initialization transistor T3 is electrically connected to the first scan signal line Sn-1.

[0061] The data write transistor T4 and the compensation transistor T5 respond to the second scan signal to transmit the data voltage and the threshold voltage Vth of the first transistor T1 to the first node n1 and store them in the storage capacitor Cs. The control terminal of the data write transistor T4 is electrically connected to the second scan signal line Sn, the first terminal of the data write transistor T4 is electrically connected to the data line Data, and the second terminal of the data write transistor T4 is electrically connected to the first terminal of the first transistor T1. The control terminal of the compensation transistor T5 is electrically connected to the second scan signal line Sn, the first terminal of the compensation transistor T5 is electrically connected to the second terminal of the first transistor T1, and the second terminal of the compensation transistor T5 is electrically connected to the first node n1. Because the first transistor T1 and the drive transistor T2 have exactly the same size, the threshold voltage of the drive transistor T2 is the same as the threshold voltage of the first transistor T1. The first plate of the storage capacitor Cs is electrically connected to the first node n1, and the second plate of the storage capacitor Cs is electrically connected to the first power supply voltage signal line ELVDD.

[0062] Reset transistor T6 responds to the third scan signal to write a reference voltage to the first terminal of the light-emitting element OLED to reset the potential of the first terminal of the light-emitting element OLED. The control terminal of reset transistor T6 is electrically connected to the third scan signal line Sn+1, the first terminal of reset transistor T6 is electrically connected to the reset voltage signal line Vres, and the second terminal of reset transistor T6 is electrically connected to the anode of the light-emitting element OLED. Here, the anode of the light-emitting element OLED is the anode of the light-emitting element.

[0063] The first emission control transistor T7 and the second emission control transistor T8 respond to the emission control signal to drive the light-emitting element OLED to emit light. The control terminal of the first emission control transistor T7 is electrically connected to the emission control signal line En, the first terminal of the first emission control transistor T7 is electrically connected to the first power supply voltage signal line ELVDD, and the second terminal of the first emission control transistor T7 is electrically connected to the first terminal of the driving transistor T2. The control terminal of the second emission control transistor T8 is electrically connected to the emission control signal line En, the first terminal of the second emission control transistor T8 is electrically connected to the second terminal of the driving transistor T2, and the second terminal of the second emission control transistor T8 is electrically connected to the anode of the light-emitting element OLED.

[0064] It should be noted that in the circuits provided in the embodiments of the present application, nodes do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram. The control terminal of a transistor refers to the gate of the transistor, the first terminal of a transistor refers to one of the source or drain of the transistor, and the second terminal of the transistor refers to the other of the source or drain. Transistors include P-type transistors and N-type transistors. In this embodiment, a P-type transistor is used as an example for explanation.

[0065] The array substrate provided in the embodiment of the present invention includes multiple pixel driving circuits, but only the layout of one pixel driving circuit is taken as an example to describe the present invention in detail. The layouts of the remaining pixel driving circuits can be any of the ones described in the following embodiments.

[0066] Figures 2 to 19 illustrate the layout design of each layer of the pixel driving circuit in Figure 1 and schematic cross-sectional structures of some locations. In conjunction with Figures 2 to 19 , it can be seen that the array substrate provided by the embodiment of the present invention includes a substrate 10, with the pixel driving circuit located on one side of the substrate 10; the pixel driving circuit includes a first transistor T1 and a driving transistor T2, and the array substrate includes: a substrate 10, a semiconductor layer 30, and a first metal layer 40. The semiconductor layer 30 is located on one side of the substrate 10 and includes a first active layer pattern 31 for the first transistor T1 and a second active layer pattern 32 for the driving transistor T2; the first active layer pattern 31 and the second active layer pattern 32 are mirror-image symmetrical; the first metal layer 40 is located on the side of the semiconductor layer 30 away from the substrate 10 and includes a first gate layer pattern 41, at least a portion of which overlaps with the first active layer pattern 31 and the second active layer pattern 32. The portion where the first gate layer pattern 41 overlaps with the first active layer pattern 31 forms the first channel of the first transistor T1, while the portion where the first gate layer pattern 41 overlaps with the second active layer pattern 32 forms the second channel of the driving transistor T2. The first transistor T1 and the driving transistor T2 structurally have the same width-to-length ratio and therefore electrically have the same threshold voltage. The first transistor T1 and the driving transistor T2 share the first gate layer pattern 41 as the gate, simplifying the array substrate manufacturing process and improving the reliability of the pixel driving circuit.

[0067] It should be noted that the first metal layer 40 here forms the gate of the transistor in the pixel driving circuit, and the semiconductor layers located on both sides of the channel form the source or drain of the transistor in the pixel driving circuit.

[0068] The semiconductor layer 30 may be made of, but not limited to, low-temperature polysilicon. As shown in FIG17 to FIG19 , a buffer layer 20 is provided between the substrate 10 and the semiconductor layer 30 to ensure good contact between the substrate 10 and the semiconductor layer 30 .

[0069] In conjunction with Figure 1, the white lines shown in Figure 2 represent the light-emitting and charging paths. The path from the data writing transistor T4, the first transistor T1, the compensation transistor T5, to the first node n1 is the charging path; the path from the first light-emitting control transistor T7, the driving transistor T2, to the second light-emitting control transistor T8 is the light-emitting path. Because the first transistor T1 and the driving transistor T2 have identical length and width dimensions, the threshold voltage of the first transistor T1 is the same as the threshold voltage of the driving transistor T2. Therefore, compensating for the threshold voltage of the first transistor T1 in the charging path is equivalent to compensating for the threshold voltage of the driving transistor T2. This allows the threshold voltage of the driving transistor T2 to be written to the first node n1 during the charging phase, thereby improving the display unevenness caused by the different threshold voltages of the driving transistor T2.

[0070] As shown in Figures 3 to 8, in some embodiments, the first channel of the first transistor T1 and the second channel of the driving transistor T2 can be configured to have a meander shape. Since the brightness of the light-emitting element in the pixel is related to the drive current generated by the driving transistor T2, and the drive current is controlled by the data signal transmitted by the data line, increasing the channel length of the driving transistor T2 can increase the data voltage range of the data signal, improve the ability of the driving transistor T2 to control the light emission of the light-emitting element, and thus improve the display effect of the display panel.

[0071] Continuing to refer to Figures 3 to 5 , compared to Figure 3 , the area of ​​the first gate layer pattern 41 in Figures 4 and 5 is increased, namely, the area overlapping with the first active layer pattern 31 and the second active layer pattern 32 is increased, as specifically shown in the dashed boxes in Figures 4 and 5 . The increased area of ​​the first gate layer pattern 41 overlapping with the first active layer pattern 31 and the second active layer pattern 32 further increases the channel lengths of the first transistor T1 and the driving transistor T2, thereby improving the driving transistor T2's ability to control the light emission of the light-emitting element, thereby enhancing the display quality of the display panel.

[0072] As shown in Figures 6 to 8, the first transistor T1 and the driving transistor T2 can be designed to share part of the channel to increase the channel length of the transistor. Compared with the channel design in Figures 3 to 5, in the same layout space, the two transistors share part of the channel to increase their respective channel lengths. The design of the channel of the first transistor T1 and the driving transistor T2 is only for illustration and is not specifically limited here. Compared with Figure 6, the area of ​​the first gate layer pattern 41 in Figures 7 and 8 that overlaps with the first active layer pattern 31 and the second active layer pattern 32 is increased (the increased portion is shown in the dotted box shown in Figures 7 and 8), which can further increase the channel length of the first transistor T1 and the driving transistor T2.

[0073] 2 , the pixel driving circuit further includes an initialization transistor T3, a data writing transistor T4, and a compensation transistor T5; the semiconductor layer 30 further includes a third active layer pattern of the initialization transistor T3, a fourth active layer pattern of the data writing transistor T4, and a fifth active layer pattern of the compensation transistor T5;

[0074] The first metal layer 40 also includes a third gate layer pattern 43 of the initialization transistor T3, a fourth gate layer pattern 44 of the data writing transistor T4, and a fifth gate layer pattern 45 of the compensation transistor T5. The third gate layer pattern 43 overlaps with the third active layer pattern in a vertical projection on the substrate 10, and the overlapping portion on the third active layer pattern is the channel of the initialization transistor T3; the fourth gate layer pattern 44 overlaps with the fourth active layer pattern in a vertical projection on the substrate 10, and the overlapping portion on the fourth active layer pattern is the channel of the data writing transistor T4; the fifth active layer pattern overlaps with the fifth gate layer pattern 45 in a vertical projection on the substrate 10, and the overlapping portion on the fifth active layer is the channel of the compensation transistor T5.

[0075] The third gate layer pattern 43 of the initialization transistor T3 and the third active layer pattern have two unconnected overlapping portions. The design of the third gate layer pattern 43 and the third active layer pattern of the initialization transistor T3 is equivalent to designing the initialization transistor T3 as a dual-gate transistor, that is, the initialization transistor T3 includes a first sub-transistor T3a and a second sub-transistor T3b.

[0076] The fifth gate layer pattern 45 of the compensation transistor T5 and the fifth active layer pattern have two unconnected overlapping portions. The design of the fifth gate layer pattern 45 and the fifth active layer pattern of the compensation transistor T5 is equivalent to designing the compensation transistor T5 as a dual-gate transistor, that is, the compensation transistor T5 includes a third sub-transistor T5a and a fourth sub-transistor T5b.

[0077] Furthermore, the pixel driving circuit further includes a reset transistor T6, a first light emission control transistor T7, and a second light emission control transistor T8; the semiconductor layer 30 further includes a sixth active layer pattern of the reset transistor T6, a seventh active layer pattern of the first light emission control transistor T7, and an eighth active layer pattern of the second light emission control transistor T8;

[0078] The first metal layer 40 further includes a sixth gate layer pattern 46 of the reset transistor T6 , a seventh gate layer pattern 47 of the first light emission control transistor T7 , and an eighth gate layer pattern 48 of the second light emission control transistor T8 ;

[0079] Among them, the sixth active layer pattern and the sixth gate layer pattern 46 overlap in the vertical projection on the substrate 10, and the overlapping portion on the sixth active layer pattern is the channel of the reset transistor T6; the seventh active layer pattern and the seventh gate layer pattern 47 overlap in the vertical projection on the substrate 10, and the overlapping portion on the seventh active layer is the channel of the first light-emitting control transistor T7; the eighth active layer pattern and the eighth gate layer pattern 48 overlap in the vertical projection on the substrate 10, and the overlapping portion on the eighth active layer pattern is the channel of the second light-emitting control transistor T8.

[0080] In this embodiment, the seventh gate layer pattern 47 is connected to the eighth gate layer pattern 48 , which is equivalent to the light-emitting control signal line En, and can realize the transmission of the light-emitting control signal.

[0081] As shown in Figures 9 to 11, the first end or the second end of the third active layer pattern of the initialization transistor T3 can be designed to be stepped to extend the length of the third active layer pattern to increase the resistance of the source or drain of the initialization transistor T3 to reduce the impact of the leakage of the initialization transistor T3 on the potential of the n1 node.

[0082] As shown in FIG12 and FIG13, the array substrate further includes a second metal layer 50, which is located on a side of the first metal layer 40 away from the substrate 10; the second metal layer 50 includes a second plate pattern of the storage capacitor Cs, an initialization voltage signal line Vint, and a reset voltage signal line Vres;

[0083] The first plate pattern overlaps with the first gate layer pattern 41, and the overlapping portion of the vertical projection of the first gate layer pattern 41 and the second plate pattern on the substrate 10 forms a storage capacitor Cs; that is, the first gate layer pattern 41 is equivalent to the first plate of the storage capacitor Cs, and the second plate pattern is equivalent to the second plate of the storage capacitor Cs.

[0084] As shown in Figures 2, 9, and 11, the semiconductor layer 30 further includes a ninth active layer pattern 39 and a tenth active layer pattern 310 arranged along the first direction. As shown in Figures 12 and 13, the initialization voltage signal line Vint overlaps with the ninth active layer pattern 39, and the initialization signal line Vint is electrically connected to the ninth active layer pattern 39 through a contact hole. The reset voltage signal line Vres overlaps with the tenth active layer pattern 310, and the reset voltage signal line Vres is electrically connected to the tenth active layer pattern 310 through a contact hole. The lateral semiconductor layer 30 and the lateral second metal layer 50 are used to transmit the initialization voltage signal and the reset voltage signal. The resistance of the second metal layer 50 is lower than that of the semiconductor layer 30, which can better transmit signals. The relatively large resistance of the semiconductor layer 30 can relatively eliminate the electrostatic charge generated during the process.

[0085] It should be noted that the schematic planar layout diagrams of the pixel drive circuit in the drawings in the specification of this application only illustrate the functional layers included in the array substrate. The functional layers include semiconductor layers and multiple metal layers. In practice, two adjacent functional layers need to be separated by an insulating layer. Therefore, an insulating film is provided between adjacent functional layers. As shown in Figures 17 to 19, a first insulating layer 71 is provided between the semiconductor layer 30 and the first metal layer 40, and a second insulating layer 72 is provided between the second metal layer 50 and the first metal layer 40. By etching contact holes in the first insulating layer 71, the initialization signal line Vint is electrically connected to the ninth active layer pattern 39, and the reset voltage signal line Vres is electrically connected to the tenth active layer pattern 310.

[0086] Continuing to refer to Figures 12 and 13, the area of ​​the second electrode pattern is not limited to overlapping only with the first gate layer pattern 41. As shown in the square dashed box in Figure 12, the second electrode pattern also covers a portion of the fifth active layer pattern of the compensation transistor T5. This can increase the size of the storage capacitor Cs, improving the voltage regulation effect of this portion of the compensation transistor T5. Furthermore, it can attract more power from other pulse signal routings or nodes within the circuit to the second metal layer 50, thereby shielding the first end of the compensation transistor T5 and reducing disturbances from other signals. It also provides a light-shielding effect, minimizing the risk of light entering the semiconductor layer and generating photogenerated carriers, which could lead to potential changes in the compensation transistor T5.

[0087] Please refer to the oval dotted boxes in FIG. 12 and FIG. 13 . Here, this portion of the second metal layer 50 needs to be narrowed to reduce the overlapping area with the upper film layer, thereby reducing the parasitic capacitance of the horizontal scanning signal.

[0088] As shown in Figures 14, 15, and 17 to 19, the pixel driving circuit further includes a third metal layer 60 disposed along a first direction (lateral direction), and the third metal layer 60 is located on a side of the second metal layer 50 away from the substrate 10, with a third insulating layer 73 disposed between the second metal layer 50 and the third metal layer 60. The third metal layer 60 includes a first scan signal line Sn-1, a second scan signal line Sn, a third scan signal line Sn+1, a source-drain electrode 60 (T4) of a data write transistor T4, a source-drain electrode 60 (T5) of a compensation transistor T5, a source-drain electrode 60 (T7) of a first emission control transistor T7, a first positive power supply voltage signal line 60 (ELVDD), and a source-drain electrode 60 (T8) of a second emission control transistor T8.

[0089] The first scan signal line Sn-1 overlaps with the third gate layer pattern 43 of the initialization transistor T3 and is electrically connected to the third gate layer pattern 43 via a contact hole. The second scan signal line Sn overlaps with the fourth gate layer pattern 44 of the write transistor T4 and the fifth gate layer pattern 45 of the compensation transistor T5 and is electrically connected to the fourth and fifth gate layer patterns 44 and 45 via a contact hole. The third scan signal line Sn+1 overlaps with the sixth gate layer pattern 46 of the reset transistor T6 and is electrically connected to the sixth gate layer pattern 46 via a contact hole. The contact hole provided between the scan signal line and the first metal layer 40 must penetrate all film layers between the scan signal line and the first metal layer 40.

[0090] The source-drain electrode 60 (T4) of the data write transistor T4 overlaps with the fourth active layer pattern of the data write transistor T4 and is electrically connected to one end of the fourth active layer pattern of the data write transistor T4 through a contact hole. The source-drain electrode 60 (T5) of the compensation transistor T5 overlaps with the fifth active layer pattern of the compensation transistor T5 and is electrically connected to the first gate layer pattern 41 through a contact hole. The source-drain electrode 60 (T7) of the first emission control transistor T7 overlaps with the seventh active layer pattern and is electrically connected to one end of the seventh active layer pattern through a contact hole. The source-drain electrode 60 (T7) of the second emission control transistor T8 overlaps with the eighth active layer pattern and is electrically connected to one end of the eighth active layer pattern through a contact hole. Contact holes are provided between the source and drain electrodes of each transistor and each active layer pattern, and all film layers between the source and drain electrodes of each transistor and each active layer pattern need to be etched through.

[0091] As shown in FIG. 12 , a through hole 51 is further provided on the second electrode pattern 50 (Cs). The through hole 51 is used to leak out of the first gate layer pattern 41 and electrically connect to the source-drain electrode 60 ( T5 ) of the compensation transistor T5 .

[0092] As shown in Figures 16 to 19, the pixel driving circuit further includes a fourth metal layer 80, a fourth insulating layer 74, and a fifth insulating layer 75 arranged along the second direction. The fourth metal layer 80 is arranged on the side of the third metal layer 60 away from the substrate 10, and the fifth insulating layer 75 is arranged on the side of the fourth metal layer 80 away from the substrate 10. The second direction here is the vertical direction as viewed along the paper, that is, the vertical direction. The fourth metal layer 80 includes a data line Data, a second positive power supply voltage signal line 80 (ELVDD), and an anode signal transmission layer.

[0093] Transmitting the first power supply voltage signal in both the horizontal and vertical directions can improve the uniformity of the panel during the initialization process; the vertical signal line can increase the area covered by the semiconductor layer 30, reduce the impact of light incidence on the carrier concentration of the semiconductor layer in its area, and reduce the drain potential fluctuation caused by the photogenerated carrier effect.

[0094] As shown in Figures 16, 18, and 19, a first type of contact hole is provided on the fourth insulating layer 74 to electrically connect the source-drain electrode 60 (T4) of the data line Data write transistor T4. A second type of contact hole is provided on the fourth insulating layer to electrically connect the anode signal transmission layer to the source-drain electrode 60 (T8) of the second light-emitting control transistor T8. In subsequent steps, an anode layer is provided on the fifth insulating layer 75. The anode layer is electrically connected to the anode signal transmission layer, thereby electrically connecting the anode layer to the second terminal of the second light-emitting control transistor T8 and the second terminal of the reset transistor T6, thereby achieving electrical connection between the pixel driving circuit and the light-emitting layer. The pixel driving circuit can then transmit a signal to the anode of the light-emitting element OLED, driving the light-emitting element OLED to emit light.

[0095] The array substrate, display panel, and display device provided by the present invention have the following advantages:

[0096] The array substrate includes multiple pixel driving circuits, each including a first transistor and a driving transistor. The array substrate comprises: a substrate; a semiconductor layer located on one side of the substrate, the semiconductor layer including a first active layer pattern for the first transistor and a second active layer pattern for the driving transistor; the first active layer pattern and the second active layer pattern being mirror-image symmetrical; and a first metal layer located on a side of the semiconductor layer away from the substrate, the first metal layer including a first gate layer pattern, at least a portion of the first gate layer pattern overlapping with the first active layer pattern and the second active layer pattern. In the present invention, the first transistor T1 and the driving transistor T2 share the first gate layer pattern as a gate, simplifying the process of manufacturing the pixel driving circuit.

[0097] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that, It includes a plurality of pixel driving circuits, and each pixel driving circuit includes a first transistor and a driving transistor; the array substrate includes: a substrate; a semiconductor layer located on one side of the substrate, and the semiconductor layer includes a first active layer pattern of the first transistor and a second active layer pattern of the driving transistor; the first active layer pattern and the second active layer pattern are mirror-symmetrical; a first metal layer located on the side of the semiconductor layer away from the substrate, and the first metal layer includes a first gate layer pattern, and at least a part of the first gate layer pattern overlaps with the first active layer pattern and the second active layer pattern.

2. The array substrate according to claim 1, wherein The overlapping part of the first gate layer pattern and the first active layer pattern is the first channel of the first transistor, and the overlapping part of the first gate layer pattern and the second active layer pattern is the second channel of the driving transistor, and the first channel and the second channel are bent.

3. The array substrate according to claim 2, wherein The first transistor and the driving transistor share a part of the channel.

4. The array substrate according to claim 3, wherein The pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor; The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor; The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor; wherein, the third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern; the fifth gate layer pattern overlaps with the fifth active layer pattern.

5. The array substrate according to claim 4, wherein The pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor; The semiconductor layer further includes a sixth active layer pattern of the reset transistor, the first light-emitting control transistor's seventh active layer pattern, and the second light-emitting control transistor's eighth active layer pattern; The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor; wherein, the sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

6. The array substrate according to claim 5, characterized in that, The pixel driving circuit further includes a storage capacitor; The array substrate further includes a second metal layer located on the side of the first metal layer away from the substrate; the second metal layer includes a second electrode pattern of the storage capacitor, an initialization voltage signal line, and a reset voltage signal line; The second electrode pattern overlaps with the first gate layer pattern, and the overlapping part of the first gate layer pattern and the vertical projection of the second electrode pattern on the substrate forms the storage capacitor; The semiconductor layer further includes a ninth active layer pattern and a tenth active layer pattern arranged along a first direction, and the initialization voltage signal line overlaps with the ninth active layer pattern; The reset voltage signal line overlaps with the tenth active layer pattern.

7. The array substrate according to claim 6, wherein, It further includes a third metal layer disposed along the first direction, on a side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line; The first scan signal line overlaps with the third gate layer pattern of the initialization transistor; The second scan signal line overlaps with the fourth gate layer pattern of the writing transistor and the fifth gate layer pattern of the compensation transistor; The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

8. The array substrate according to claim 7, wherein, The third metal layer further includes a first positive power supply voltage signal line, and a first electrode plate of the storage capacitor overlaps with the first positive power supply voltage signal line.

9. The array substrate according to claim 8, wherein It further includes a fourth metal layer disposed along the second direction, on a side of the third metal layer away from the substrate.

10. The array substrate according to claim 9, wherein, The fourth metal layer includes a data line and a second positive power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data writing transistor; the second positive power supply voltage signal line overlaps with the first positive power supply voltage signal line.

11. A display panel, characterized in that, It includes the array substrate according to any one of claims 1 to 10.

12. A display device, characterized in that, It includes the array substrate according to any one of claims 1 to 10.

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