Array substrate, display panel and display device

Abstract

Provided in the present invention are an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel driving circuits. Each pixel driving circuit comprises a first transistor and a driving transistor. The array substrate comprises: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer comprising a first active layer pattern; and a first metal layer disposed on the side of the semiconductor layer away from the substrate, the first metal layer comprising a first gate layer pattern, wherein the first gate layer pattern overlaps the first active layer pattern, an overlapping portion is a first channel on the first active layer pattern, and the first transistor and the driving transistor share the first channel and the first gate layer pattern. The layout of the pixel driving circuits of the array substrate provided by the present invention is space-saving and suitable for use in a display panel with a high-density pixel arrangement.

Description

Array substrate, display panel and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) has many advantages, including being fully solid-state, self-luminous, having a wide viewing angle, a wide color gamut, a fast response speed, high luminous efficiency, high brightness, high contrast, being ultra-thin, ultra-light, low power consumption, having a wide operating temperature range, being able to produce large-size and flexible panels, and having a simple manufacturing process. It can realize truly flexible displays and has broad development prospects. In recent years, it has received increasing attention and recognition in the market.

[0003] Organic light-emitting display devices use pixel driver circuits to illuminate the pixels and display the corresponding images. Figure 1 shows an equivalent schematic diagram of a pixel driver circuit. In the prior art, the pixel driver circuits configured on a display panel as shown in Figure 1 have a complex layout structure and require a large layout space, which prevents further improvement in the pixel density of the display panel.

[0004] Summary of the Invention

[0005] In view of the problems in the prior art, an object of the present invention is to provide an array substrate, a display panel and a display device, which save the layout space of the pixel driving circuit and are suitable for display panels with high pixel density.

[0006] An embodiment of the present invention provides an array substrate, including a plurality of pixel driving circuits, wherein the pixel driving circuits include a first transistor and a driving transistor; the array substrate includes:

[0007] substrate;

[0008] a semiconductor layer located on one side of the substrate, wherein the semiconductor layer includes a first active layer pattern;

[0009] a first metal layer located on a side of the semiconductor layer away from the substrate, the first metal layer comprising a first gate layer pattern, the first gate layer pattern overlapping the first active layer pattern; the overlapping portion forming a first channel on the first active layer pattern;

[0010] The first transistor and the driving transistor share the first channel and the first gate layer pattern.

[0011] In some embodiments, the pattern of the first channel pipe is in the shape of a cross.

[0012] In some embodiments, the first gate layer pattern includes a first pattern and a second pattern connected along a first direction, and an area of ​​the first pattern is smaller than an area of ​​the second pattern;

[0013] The second pattern overlaps with a middle portion of the first active layer pattern, and the first pattern overlaps with a first end or a second end of the first active layer pattern.

[0014] In some embodiments, the pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor;

[0015] The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor;

[0016] The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor;

[0017] The third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern, and the fifth gate layer pattern overlaps with the fifth active layer pattern.

[0018] In some embodiments, the pixel driving circuit further includes a reset transistor, a first light emission control transistor, and a second light emission control transistor;

[0019] The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light emission control transistor, and an eighth active layer pattern of the second light emission control transistor;

[0020] The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light emission control transistor, and an eighth gate layer pattern of the second light emission control transistor;

[0021] The sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

[0022] In some embodiments, the pixel driving circuit further includes a storage capacitor;

[0023] The array substrate also includes a second metal layer located on a side of the first metal layer away from the substrate; the second metal layer overlaps with the first gate layer pattern, and the overlapping part of the vertical projection of the first gate layer pattern and the second metal layer on the substrate forms the storage capacitor.

[0024] In some embodiments, the overlapped area of ​​the second metal layer and the first gate layer pattern is 120 μm 2 ~200μm 2 .

[0025] In some embodiments, the device further includes a third metal layer arranged along the first direction and located on a side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line;

[0026] The first scanning signal line overlaps with the third gate layer pattern of the initialization transistor;

[0027] The second scanning signal line overlaps with the fourth gate layer pattern of the write transistor and the fifth gate layer pattern of the compensation transistor;

[0028] The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

[0029] In some embodiments, the third metal layer further includes an initialization voltage signal, a reset voltage signal line, and a first power supply voltage signal line; the third active layer pattern of the initialization transistor overlaps with the initialization voltage signal line;

[0030] The second metal layer overlaps with the first power supply voltage signal line;

[0031] The sixth active layer pattern of the reset transistor overlaps with the reset voltage signal line.

[0032] In some embodiments, the method further includes a fourth metal layer disposed along the second direction and located on a side of the third metal layer away from the substrate.

[0033] In some embodiments, the fourth metal layer includes a data line and the first power supply voltage signal line; the data line overlaps with the fourth active layer pattern for data writing; and the first power supply voltage signal line overlaps with the third metal layer.

[0034] An embodiment of the present invention further provides a display panel, comprising the array substrate described above.

[0035] An embodiment of the present invention further provides a display device, comprising the display substrate described above.

[0036] The array substrate, display panel, and display device provided by the present invention have the following advantages:

[0037] The pixel driving circuit on the array substrate provided by the present invention has a small layout space and can be used in a high pixel density panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0039] FIG1 is an equivalent schematic diagram of a pixel driving circuit;

[0040] 2 is a schematic diagram showing a layout of a semiconductor layer and a first metal layer provided on an array substrate according to an embodiment of the present invention;

[0041] 3 is a schematic diagram showing a layout of a semiconductor layer and a first metal layer provided on an array substrate according to another embodiment of the present invention;

[0042] 4 is a schematic diagram of the layout of an array substrate provided with a second metal layer according to an embodiment of the present invention;

[0043] 5 is a layout diagram of an array substrate provided with a second metal layer according to another embodiment of the present invention;

[0044] FIG6 is a partial enlarged view of an array substrate provided with a second metal layer according to another embodiment of the present invention;

[0045] 7 is a schematic diagram of the layout of an array substrate after contact holes are provided according to an embodiment of the present invention;

[0046] 8 is a schematic diagram of the layout of an array substrate provided with a third metal layer according to an embodiment of the present invention;

[0047] FIG9 is a schematic cross-sectional view taken along section line AA′ in FIG8 ;

[0048] FIG10 is a schematic cross-sectional view taken along line BB′ in FIG8 ;

[0049] 11 is a schematic diagram of the layout of an array substrate provided with a fourth metal layer according to an embodiment of the present invention;

[0050] FIG12 is a schematic cross-sectional view taken along the section line CC' in FIG11;

[0051] FIG13 is a schematic cross-sectional view taken along line DD' in FIG11;

[0052] FIG14 is a schematic cross-sectional view taken along line EE' in FIG11;

[0053] 15 is a schematic diagram of the layout of an array substrate provided with a fourth metal layer according to another embodiment of the present invention;

[0054] FIG16 is a schematic layout diagram of an array substrate provided by another embodiment of the present invention after a fourth metal layer is provided.

[0055] Reference Signs: 10 substrate 73 third insulating layer 20 buffer layer 74 fourth insulating layer 30 semiconductor layer 75 fifth insulating layer 31 first active layer pattern 80 fourth metal layer 40 first metal layer T1 first transistor 41 first gate layer pattern T2 driving transistor 41a first pattern T3 initialization transistor 41b second pattern T4 data writing transistor 43 third gate layer pattern T5 compensation transistor 44 fourth gate layer pattern T6 reset transistor 45 fifth gate layer pattern T7 first emission control transistor 46 sixth gate layer pattern T8 second emission control transistor 47 seventh gate layer pattern Sn-1 first scan signal line 48 eighth gate layer pattern Sn second scan signal line 50 second metal layer Sn+1 third scan signal line 51 through hole Vres reference voltage signal line 60 third metal layer Data data line 71 first insulating layer ELVDD first power supply voltage signal line 72 second insulating layer Vint initialization voltage signal line En emission control signal line DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, identical reference numerals denote identical or similar structures, and thus repetitive descriptions thereof will be omitted. The use of "or" and "either" in this specification may mean "and" or "or."

[0057] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied through different specific embodiments. The details in the present application can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present application. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0058] To address the problems in the prior art, an embodiment of the present invention provides an array substrate. Figure 1 shows an equivalent schematic diagram of a pixel driving circuit in an array substrate provided by an embodiment of the present invention. This application provides a layout design based on the equivalent schematic diagram of the pixel driving circuit shown in Figure 1. As shown in Figure 1, the pixel driving circuit includes a first transistor T1, a driving transistor T2, an initialization transistor T3, a data writing transistor T4, a compensation transistor T5, a reset transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8.

[0059] The first transistor T1 and the driving transistor T2 are turned on and off in response to the potential of the second node n2; the control terminals of the first transistor T1 and the driving transistor T2 are electrically connected to the second node n2.

[0060] The initialization transistor T3 transmits an initialization voltage to the second node n2 in response to the first scan signal. A first terminal of the initialization transistor T3 is electrically connected to the initialization voltage signal line Vint, a second terminal of the initialization transistor T3 is electrically connected to the second node n2, and a control terminal of the initialization transistor T3 is electrically connected to the first scan signal line Sn-1.

[0061] The data write transistor T4 and the compensation transistor T5 respond to the second scan signal to transmit the data voltage and the threshold voltage Vth of the first transistor T1 to the second node n2 and store them in the storage capacitor Cs. The control terminal of the data write transistor T4 is electrically connected to the second scan signal line Sn, the first terminal of the data write transistor T4 is electrically connected to the data line Data, and the second terminal of the data write transistor T4 is electrically connected to the first terminal of the first transistor T1. The control terminal of the compensation transistor T5 is electrically connected to the second scan signal line Sn, the first terminal of the compensation transistor T5 is electrically connected to the second terminal of the first transistor T1, and the second terminal of the compensation transistor T5 is electrically connected to the second node n2. Because the first transistor T1 and the drive transistor T2 have exactly the same size, the threshold voltage of the drive transistor T2 is the same as the threshold voltage of the first transistor T1. The first plate of the storage capacitor Cs is electrically connected to the second node n2, and the second plate of the storage capacitor Cs is electrically connected to the first power supply voltage signal line ELVDD.

[0062] Reset transistor T6 responds to the third scan signal to write a reference voltage to the first terminal of the light-emitting element OLED to reset the potential of the first terminal of the light-emitting element OLED. The control terminal of reset transistor T6 is electrically connected to the third scan signal line Sn+1, the first terminal of reset transistor T6 is electrically connected to the reset voltage signal line Vres, and the second terminal of reset transistor T6 is electrically connected to the anode of the light-emitting element. Here, the anode of the light-emitting element OLED is the anode of the light-emitting element.

[0063] The first emission control transistor T7 and the second emission control transistor T8 respond to the emission control signal to drive the light-emitting element OLED to emit light. The control terminal of the first emission control transistor T7 is electrically connected to the emission control signal line En, the first terminal of the first emission control transistor T7 is electrically connected to the first power supply voltage signal line ELVDD, and the second terminal of the first emission control transistor T7 is electrically connected to the first terminal of the driving transistor T2. The control terminal of the second emission control transistor T8 is electrically connected to the emission control signal line En, the first terminal of the second emission control transistor T8 is electrically connected to the second terminal of the driving transistor T2, and the second terminal of the second emission control transistor T8 is electrically connected to the anode of the light-emitting element OLED.

[0064] It should be noted that in the circuits provided in the embodiments of the present application, nodes do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram. The control terminal of a transistor refers to the gate of the transistor, the first terminal of a transistor refers to one of the source or drain of the transistor, and the second terminal of the transistor refers to the other of the source or drain. Transistors include P-type transistors and N-type transistors. In this embodiment, a P-type transistor is used as an example for explanation.

[0065] The array substrate provided in the embodiment of the present invention includes multiple pixel driving circuits, but only the layout of one pixel driving circuit is taken as an example to describe the present invention in detail. The layouts of the remaining pixel driving circuits can be any of the ones described in the following embodiments.

[0066] Figures 2 to 16 show the layout design of each layer of the pixel driving circuit in Figure 1 and schematic cross-sectional structures of some positions. In conjunction with Figures 2 to 16, it can be seen that the array substrate provided by the embodiment of the present invention includes a substrate 10, and the pixel driving circuit is located on one side of the substrate 10; the pixel driving circuit includes a first transistor T1 and a driving transistor T2; the array substrate includes a semiconductor layer 30, which is located on one side of the substrate 10, and the semiconductor layer 30 includes a first active layer pattern 31; a first metal layer 40, which is located on a side of the semiconductor layer 30 away from the substrate 10, and the first metal layer 40 includes a first gate layer pattern 41, and the first gate layer pattern 41 and the first active layer pattern 31 overlap in a vertical projection of the substrate 10, and the overlapping portion in the first active layer pattern 31 is a first channel; the first transistor T1 and the driving transistor T2 share the first channel and the first gate layer pattern 41.

[0067] By making the first transistor T1 and the driving transistor T2 share a channel and a gate, the layout space of the pixel driving circuit is saved, which is conducive to use in a display panel with a high pixel density.

[0068] It should be noted that the first metal layer 40 here forms the gate of the transistor in the pixel driving circuit, and the semiconductor layers located on both sides of the channel form the source or drain of the transistor in the pixel driving circuit.

[0069] As shown in Figures 9, 10, 12 and 14, a buffer layer 20 is provided between the substrate 10 and the semiconductor layer 30 to ensure good contact between the substrate 10 and the semiconductor layer 30.

[0070] In this embodiment, the first channels of the first transistor T1 and the driving transistor T2 have a zigzag pattern, meaning that the channels of the first transistor T1 and the driving transistor T2 are zigzag. Since the brightness of the light-emitting element in the pixel is related to the drive current generated by the driving transistor, which is controlled by the data signal transmitted by the data line, increasing the channel length of the driving transistor T2 can expand the data voltage range of the data signal and improve the ability of the driving transistor T2 to control the light-emitting element, thereby improving the display quality of the display panel. In some high-PPI products, when the pixel layout space is narrow and insufficient for a sufficiently long channel, the aforementioned zigzag channel can be used to increase the channel length and meet the channel length requirement. Referring to the white lines in Figures 1 and 2, the first channel is designed as a zigzag, further lengthening the charging and light-emitting paths. As shown in Figures 1 and 2, the path from the data write transistor T4, the first transistor T1, the compensation transistor T5 to the second node n2 is the charging path. The path from the first light-emitting control transistor T7, the driving transistor T2, and the second light-emitting control transistor T8 is the light-emitting path.

[0071] Continuing with Figure 2 , the first gate layer pattern 41 includes a first pattern 41a and a second pattern 42b connected along a first direction. The area of ​​the first pattern 41a is smaller than that of the second pattern 41b. The orthographic projection of the first gate layer pattern 41 on the substrate 10 is in the shape of a flag. In some embodiments, the first gate layer pattern 41 includes only the second pattern 41b. However, in this embodiment, the first pattern 41a is added to extend the area of ​​the first gate layer pattern 41. This increases the area of ​​the subsequently provided storage capacitor Cs, reduces the amount of change in the gate potential of the driving transistor T2 due to leakage, and improves voltage regulation.

[0072] As shown in Figures 2 and 3, the second pattern 41b overlaps with the middle part of the first active layer pattern 31, and the first pattern 41a overlaps with the first end or the second end of the first active layer pattern 31, that is, the first gate layer pattern 41 is arranged to the left or right of the first active layer pattern 31. At this time, the first transistor T1 and the driving transistor T2 can also be regarded as a device with four terminals. For example, as shown in Figure 2, the four-terminal device includes a first terminal n1, a second terminal n2 (i.e., a second node), a third terminal n3 and a fourth terminal n4. The first terminal n1 and the fourth terminal n4 can be regarded as the source of the four-terminal device, the second terminal n2 can be regarded as the gate of the four-terminal device, and the third terminal n3 can be regarded as the drain of the four-terminal device. When in use, it can be regarded as using the gate, source and one of the drains of the four-terminal device, and the other drain is suspended to realize the conduction function of the thin film transistor.

[0073] As shown in FIG3 , in another embodiment, the first pattern 41 a overlaps with the second end of the first active layer pattern 31. In this case, the first transistor T1 and the driving transistor T2 can also be regarded as a device with four terminals, including a first terminal n1, a second terminal n2, a third terminal n3, and a fourth terminal n4. The first terminal n1 and the fourth terminal n4 can be regarded as drains, the second terminal n2 can be regarded as a gate, and the third terminal n3 can be regarded as a source.

[0074] 2 and 3 , the pixel driving circuit further includes an initialization transistor T3, a data writing transistor T4, and a compensation transistor T5; the semiconductor layer 30 further includes a third active layer pattern of the initialization transistor T3, a fourth active layer pattern of the data writing transistor T4, and a fifth active layer pattern of the compensation transistor T5;

[0075] The first metal layer 40 also includes a third gate layer pattern 43 of the initialization transistor T3, a fourth gate layer pattern 44 of the data writing transistor T4, and a fifth gate layer pattern 45 of the compensation transistor T5. The third gate layer pattern 43 overlaps with the third active layer pattern in a vertical projection on the substrate 10, and the overlapping portion is the channel of the initialization transistor T3; the fourth gate layer pattern 44 overlaps with the fourth active layer pattern in a vertical projection on the substrate 10, and the overlapping portion is the channel of the data writing transistor T4; the fifth active layer pattern overlaps with the fifth gate layer pattern 45 in a vertical projection on the substrate 10, and the overlapping portion is the channel of the compensation transistor T5.

[0076] The third gate layer pattern 43 of the initialization transistor T3 and the third active layer pattern have two unconnected overlapping portions. The design of the third gate layer pattern 43 and the third active layer pattern of the initialization transistor T3 is equivalent to designing the initialization transistor T3 as a dual-gate transistor, that is, the initialization transistor T3 includes a first sub-transistor T3a and a second sub-transistor T3b.

[0077] The fifth gate layer pattern 45 of the compensation transistor T5 and the fifth active layer pattern have two unconnected overlapping portions. The design of the fifth gate layer pattern 45 and the fifth active layer pattern of the compensation transistor T5 is equivalent to designing the compensation transistor T5 as a dual-gate transistor, that is, the compensation transistor T5 includes a third sub-transistor T5a and a fourth sub-transistor T5b.

[0078] Furthermore, the pixel driving circuit further includes a reset transistor T6, a first light emission control transistor T7, and a second light emission control transistor T8; the semiconductor layer 30 further includes a sixth active layer pattern of the reset transistor T6, a seventh active layer pattern of the first light emission control transistor T7, and an eighth active layer pattern of the second light emission control transistor T8;

[0079] The first metal layer 40 further includes a sixth gate layer pattern 46 of the reset transistor T6 , a seventh gate layer pattern 47 of the first light emission control transistor T7 , and an eighth gate layer pattern 48 of the second light emission control transistor T8 ;

[0080] Among them, the sixth active layer pattern and the sixth gate layer pattern 46 overlap in the vertical projection on the substrate 10, and the overlapping part is the channel of the reset transistor T6; the seventh active layer pattern and the seventh gate layer pattern 47 overlap in the vertical projection on the substrate 10, and the overlapping part is the channel of the first light-emitting control transistor T7; the eighth active layer pattern and the eighth gate layer pattern 48 overlap in the vertical projection on the substrate 10, and the overlapping part is the channel of the second light-emitting control transistor T8.

[0081] In this embodiment, the seventh gate layer pattern 47 is connected to the eighth gate layer pattern 48 , which is equivalent to the light-emitting control signal line En, and can realize the transmission of the light-emitting control signal.

[0082] 2 , a step structure (shown in an elliptical dotted box) is designed on the semiconductor layer 30 connected to the fifth active layer pattern of the compensation transistor T5, the first active layer pattern of the first transistor T1 and the driving transistor T2, and the eighth active layer pattern of the second light-emitting control transistor T8. This can reduce the parasitic capacitance of this section of the semiconductor and ease the difficulty of charging; it can also reduce the area of ​​the semiconductor layer that can be exposed to light, reduce the impact of the photogenerated carrier effect on the drain node of the compensation / or driving transistor, and weaken the current change caused by potential fluctuations.

[0083] As shown in Figures 9 and 10, a first insulating layer 71 is provided between the semiconductor layer 30 and the first metal layer 40. The first insulating layer 71 may be made of silicon oxide (SiO2). The first insulating layer 71 is not shown in the layout design.

[0084] As shown in Figures 4 and 10, in one embodiment, the array substrate further includes a second metal layer 50 located on a side of the first metal layer 40 away from the substrate 10; the second metal layer 50 overlaps with the vertical projection of the first gate layer pattern 41 on the substrate 10. The overlapping portion of the second metal layer 50 and the vertical projection of the first gate layer pattern 41 on the substrate 10 forms a storage capacitor Cs, that is, the first gate layer pattern 41 is the first plate of the storage capacitor Cs, and the second metal layer 50 is the second plate of the storage capacitor Cs. In some embodiments, the overlapping area of ​​the second metal layer 50 and the first gate layer pattern 41 is 120μm 2 ~200μm 2 .

[0085] Continuing with Figure 4 , the area of ​​the second metal layer 50 is not limited to overlapping only with the first gate layer pattern 41. As shown in the dashed box in Figure 4 , the second metal layer 50 also overlaps with the vertical projections of the third active layer pattern of the initialization transistor T3, the fifth active layer pattern of the compensation transistor T5, the fourth active layer pattern of the data write transistor T4, the seventh active layer pattern of the first emission control transistor T7, and the eighth active layer pattern of the second emission control transistor T8 on the substrate 10. The second metal layer 50 shields the semiconductor layer, shielding it from voltage changes at other nodes and pulse signal voltage transitions, which can affect the potential of the shielded semiconductor layer through capacitive coupling. Furthermore, it blocks light, preventing incident light from causing changes in the carrier concentration of the semiconductor layer, which could affect the potential of that section of the semiconductor layer.

[0086] As shown in FIG5 , in another embodiment, the second metal layer 50 also shields part of the semiconductor layer of other transistors, as shown in the dotted box in FIG5 . The difference between FIG5 and the second metal layer 50 in FIG4 is that the area of ​​the second metal layer 50 is increased, covering a larger area of ​​the semiconductor layer. Compared with the second metal layer 50 shown in FIG4 , the area of ​​the second metal layer 50 in FIG5 is further increased, that is, the shielding area is increased, which can better reduce the impact of the pulse signal voltage transition and other node potential coupling on the lower plate of the capacitor (i.e., the first gate layer pattern 41), and reduce the gate voltage fluctuation and current fluctuation of the pixel driving circuit during the compensation stage and the light-emitting stage.

[0087] Part of the second metal layer 50 will shield the semiconductor layer of the driving transistor T2, thereby shielding the source of the driving transistor T2 and reducing the impact of other node voltage changes and pulse signal transitions on the source potential of the driving transistor T2 and the compensation transistor T5. According to the MOSFET current formula, the transistor current I∝(Vgs-Vth) 2 According to the formula, shielding the source of the transistor is beneficial to the stability of the compensation current of the compensation transistor T5 and the stability of the light-emitting current of the driving transistor T2.

[0088] As shown in Figure 6, in another embodiment, the area of ​​the second metal layer 50 overlapping with the semiconductor layer 30 is relatively reduced compared to the design in Figure 5, and the reduction in the area of ​​the second metal layer 50 reduces the parasitic capacitance generated by the second metal layer 50 to other signals, especially the parasitic capacitance of the scan line and the data line, thereby reducing the delay of Tr (rise time) and Tf (fall time) during signal transmission and improving the display uniformity of the panel.

[0089] As shown in Figures 4, 5, 6 and 10, a through hole 51 is provided on the first plate of the storage capacitor Cs, and the through hole 51 is opposite to the first gate layer pattern 41. The length of the through hole 51 is recorded as m, and the width is recorded as n, which satisfies: m ≥ 1.5 μm, n ≥ 1.5 μm, so as to weaken the potential fluctuation caused by the capacitive coupling effect on the second plate of the storage capacitor Cs, that is, the gate of the driving transistor T2.

[0090] As shown in Figure 10, a second insulating layer 72 is provided between the first metal layer 40 and the second metal layer 50. The overlapping portion of the projections of the first metal layer 40 and the second metal layer 50 on the substrate 10 (shown in the dashed box in the figure) forms a storage capacitor Cs. The dielectric constant of the second insulating layer 72 is greater than that of the first insulating layer 71. Furthermore, referring to Figure 10, a third insulating layer 73 is provided on the side of the second metal layer 50 away from the substrate 10. The second insulating layer 72 and the third insulating layer 73 are also not shown in the layout design.

[0091] As shown in FIG7 , the pixel driving circuit further includes a plurality of contact holes (shown in dashed boxes in the figure) disposed on each insulating layer. The contact holes are disposed on each insulating layer to expose the semiconductor layer or each metal layer. Subsequently, the semiconductor layer and each metal layer are electrically connected to the signal lines to provide electrical signals to the semiconductor layer and the metal layer. It should be noted that the planar layout diagram only illustrates the functional layers included in the array substrate. The functional layers include the semiconductor layer, the first metal layer, the second metal layer, etc. In practice, adjacent functional layers need to be separated by an insulating layer. Therefore, an insulating film is provided between adjacent functional layers.

[0092] As shown in Figures 8 to 10, the pixel driving circuit further includes a third metal layer 60 arranged along a first direction, and the third metal layer 60 is located on the side of the second metal layer 50 away from the substrate 10. In this embodiment, the first direction is the left-right direction as viewed from the paper, i.e., the lateral direction. The resistivity of the third metal layer 60 is less than that of the first metal layer 40 and the second metal layer 50. Using the third metal layer 60 to transmit the lateral scanning signal can reduce the impedance of the scanning signal and reduce the delay in voltage rise and fall caused by RC loading (capacitive resistance load) during circuit transmission.

[0093] As shown in Figure 8, the third metal layer 60 includes a first scan signal line Sn-1, a second scan signal line Sn, a third scan signal line Sn+1, a source-drain electrode of a data write transistor T4, a source-drain electrode of a compensation transistor T5, a source-drain electrode of a first light-emitting control transistor T7, a source-drain electrode of a second light-emitting control transistor T8, a first power supply voltage signal line ELVDD, an initialization voltage signal line Vint, and a reset voltage signal line Vres. Among them, the first scan signal line Sn-1 overlaps with the third gate layer pattern 43 of the initialization transistor T3, and the first scan signal line Sn-1 is electrically connected to the third gate layer pattern 43 through a contact hole; the second scan signal line Sn overlaps with the fourth gate layer pattern 44 of the write transistor T4 and the fifth gate layer pattern 45 of the compensation transistor T5, and the second scan signal line Sn is electrically connected to the fourth gate layer pattern 44 and the fifth gate layer pattern 45 through a contact hole; the third scan signal line Sn+1 overlaps with the sixth gate layer pattern 46 of the reset transistor T6, and the third scan signal line Sn+1 is electrically connected to the sixth gate layer pattern 46 through a contact hole; the third active layer pattern of the initialization transistor T3 overlaps with the initialization voltage signal line Vint, and the initialization voltage signal line Vint It is electrically connected to the third active layer pattern through a contact hole; the second metal layer 50 overlaps with the first power supply voltage signal line ELVDD, and the first power supply voltage signal is electrically connected to the second metal layer 50 and one end of the seventh active layer pattern of the first light-emitting control transistor T7 through the contact hole; the source and drain electrodes of the data writing transistor T4 overlap with the fourth active layer pattern of the data writing transistor T4; the source and drain electrodes of the compensation transistor T5 overlap with the fifth active layer pattern of the compensation transistor T5, and the source and drain electrodes of the compensation transistor T5 are electrically connected to the first gate layer pattern 41; the source and drain electrodes of the first light-emitting control transistor T7 overlap with the active layer pattern of the first light-emitting control transistor T7, and the source and drain electrodes of the first light-emitting control transistor T7 are electrically connected to one end of the active layer of the first light-emitting control transistor T7.

[0094] In other embodiments, the initialization voltage signal line Vint and the reset voltage signal line Vres can be a semiconductor layer. When the initialization voltage signal line Vint and the reset voltage signal line Vres are semiconductor layers, as shown in Figures 2 and 3, they can be provided in the same layer as the semiconductor layer 30. When the initialization voltage signal line Vint and the reset voltage signal line Vres are semiconductor layers, the resistance of the semiconductor layer is large and the anti-ESD effect is good. During the process preparation, static electricity is easily transmitted along the metal or semiconductor layer, and the greater the resistance, the easier it is to eliminate the influence of static electricity, and the longer the propagation path, the more easily the static electricity charge is dispersed, preventing charge accumulation and breakdown.

[0095] The first power voltage signal line ELVDD is laterally connected in parallel with the second metal layer 50 to transmit the first power voltage signal, which helps to reduce the voltage drop (IR Drop) during signal transmission and improve the current uniformity of the panel.

[0096] Preferably, the thickness of the third insulating layer 73 is greater than the sum of the thicknesses of the first insulating layer 71 and the second insulating layer 72. The increased thickness of the third insulating layer 73 reduces parasitic capacitance on the signal line and reduces the risk of electrostatic damage. This is because the signal line connects multiple transistors in series, forming a complete circuit excluding the light-emitting element, and has many layers stacked underneath. This prevents severe electrostatic damage during the manufacturing process due to insufficient thickness of the third insulating layer 73.

[0097] In another embodiment, the third insulating layer 73 may be a double-layer insulating layer, comprising a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer and the second insulating layer 72 are made of the same material to prevent the second insulating layer 72 from being subjected to lattice adaptation stress and thermal adaptation stress, which could affect the stability of the storage capacitor Cs. The material of the first sub-insulating layer has a relatively low dielectric constant, which can relatively reduce the parasitic capacitance between the third metal layer 60, the second metal layer 50, and the semiconductor layer 30.

[0098] As shown in Figures 11 to 16, the pixel driving circuit further includes a fourth metal layer 80 and a fourth insulating layer 74. The fourth metal layer 80 is disposed along the second direction on the side of the substrate 10 away from the third insulating layer 73, and the fourth insulating layer 74 is disposed on the side of the fourth metal layer 80 away from the substrate 1. The second direction herein refers to the vertical direction as viewed along the paper, i.e., the longitudinal direction. As shown in Figure 11, the fourth metal layer 80 includes a data line Data and a first power supply voltage signal line ELVDD (in the longitudinal direction). Figure 12 shows a schematic cross-sectional view taken along line CC' in Figure 11. As shown in Figure 12, in some embodiments, the contact holes defined in the fourth insulating layer 74 are larger than the contact holes defined in the third insulating layer 73. The fourth insulating layer 74 can be an organic layer. Contact holes in organic layers can be formed through exposure and development. Larger contact holes in organic layers ensure complete openings. If the contact holes in the third insulating layer 73 are inorganic layers, the third insulating layer 73 can be formed through a process that can be realized. The contact holes in inorganic layers can be smaller, thus saving space.

[0099] Please continue to refer to Figure 11. The second metal layer 50 overlaps with the fourth active layer pattern on the data write transistor T4 (see the dotted box). Here, the second metal layer 50 can shield the semiconductor layer on the data write transistor T4, and can attract more electricity on the data line Data and the second scan signal line Sn to the signal line of the fourth metal layer 80 that transmits the first power supply voltage signal (vertical), thereby enhancing the shielding effect on the data line Data and the second scan signal line Sn, and weakening the influence of the two pulse signals on the potential of other nodes in the circuit.

[0100] Figure 13 shows a schematic cross-sectional view taken along line DD' in Figure 11 . As shown in Figure 13 , a fifth insulating layer 75 is provided on a side away from the fourth metal layer 80. In some embodiments, the fifth insulating layer 75 may be an organic layer that can provide a planarization effect. A contact hole is provided in the fourth insulating layer 74, exposing the first power supply voltage signal line ELVDD (vertically) below the contact hole. This allows the first power supply voltage signal line ELVDD (horizontally) provided on the fourth insulating layer 74 to contact the source and drain electrodes of the first emission control transistor T7 through the contact hole, thereby electrically connecting the source and drain electrodes of the first emission control transistor T7 to the first power supply voltage signal line ELVDD.

[0101] The setting of the vertical signal transmission line can transmit the first power supply voltage signal in both the horizontal and vertical directions, thereby improving the uniformity of the panel during the initialization process; the vertical signal line covers part or all of the left semiconductor, thereby reducing the impact of light incidence on the carrier concentration of the semiconductor layer in its area, and reducing the drain potential fluctuation caused by the photogenerated carrier effect.

[0102] As shown in Figures 11 and 14, the fourth metal layer 80 also includes an anode signal transmission layer, which is electrically connected to the source and drain electrodes of the second emission control transistor T8 through contact holes. It should be noted that the contact holes provided in the anode signal transmission layer and the contact holes for the source and drain electrodes of the second emission control transistor T8 are staggered in the thickness direction of the substrate 10.

[0103] As shown in FIG15 , in another embodiment, the fourth metal layer 80 further includes an initialization voltage signal line Vint. The initialization voltage signal line Vint in the fourth metal layer 80 is arranged vertically and connected to the horizontally arranged initialization voltage signal line Vint via contact holes formed in the fourth insulating layer 74. The initialization voltage signal line Vint is designed to have a horizontal and vertical mesh-like interlaced structure, thereby improving the uniformity of the panel during the anode reset process. In other embodiments, the reset voltage signal line Vres may also be designed to have a horizontal and vertical mesh-like interlaced structure.

[0104] As shown in Figure 16, the fourth metal layer 80 also includes a second power supply voltage signal line ELVSS, which transmits a second power supply voltage signal. The second power supply voltage signal line ELVSS is not connected to any underlying signal lines and is used to reduce the IR drop (voltage drop) of the ELVSS signal, thereby improving the current uniformity of the panel. In other embodiments, the fourth metal layer 80 can also be other signal lines that are not electrically connected to the underlying signal lines. Those skilled in the art can make specific settings based on actual needs.

[0105] A complete pixel includes any one of the pixel circuits shown in FIG. 11 , FIG. 15 and FIG. 16 or a combination thereof.

[0106] An embodiment of the present invention further provides a display panel including the array substrate described above, which can achieve all the technical effects of the array substrate described above and will not be described in detail here.

[0107] An embodiment of the present invention further provides a display device including the array substrate described above, which can achieve all the technical effects of the array substrate described above and is not further described here. The display device can be a mobile phone, computer, camera, watch, camcorder, projector, billboard, automobile display, etc.

[0108] The display panel and display device provided by the present invention have the following advantages:

[0109] The array substrate includes multiple pixel driving circuits, each including a first transistor and a driving transistor. The array substrate comprises a substrate, a semiconductor layer, and a first metal layer. The semiconductor layer is located on one side of the substrate and includes a first active layer pattern. The first metal layer is located on a side of the semiconductor layer away from the substrate and includes a first gate layer pattern, which overlaps with the first active layer pattern. The overlapping portion in the first active layer pattern is a first channel. The first transistor and the driving transistor share the first channel and the first gate layer pattern. The pixel driving circuit layout of the array substrate provided by the present invention saves space and is suitable for display panels with high-density pixel arrangements.

[0110] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that, It includes a plurality of pixel driving circuits, and the pixel driving circuit includes a first transistor and a driving transistor; The array substrate includes: A substrate; A semiconductor layer located on one side of the substrate, and the semiconductor layer includes a first active layer pattern; A first metal layer located on the side of the semiconductor layer away from the substrate, and the first metal layer includes a first gate layer pattern, and the first gate layer pattern overlaps with the first active layer pattern; the overlapping portion is a first channel on the first active layer pattern; The first transistor and the driving transistor share the first channel and the first gate layer pattern.

2. The array substrate according to claim 1, wherein The pattern of the first channel is in a shape like the Chinese character 'ji'.

3. The array substrate according to claim 2, wherein The first gate layer pattern includes a first pattern and a second pattern connected in a first direction, and the area of the first pattern is smaller than the area of the second pattern; Wherein, the second pattern overlaps with the middle part of the first active layer pattern, and the first pattern overlaps with the first end or the second end of the first active layer pattern.

4. The array substrate according to claim 3, wherein The pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor; The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor; The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor; Wherein, the third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern; the fifth gate layer pattern overlaps with the fifth active layer pattern.

5. The array substrate according to claim 4, wherein The pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor; The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor; The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor; Wherein, the sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

6. The array substrate according to claim 5, wherein The pixel driving circuit further includes a storage capacitor; The array substrate further includes a second metal layer located on the side of the first metal layer away from the substrate; the second metal layer overlaps with the first gate layer pattern, and the overlapping portion of the first gate layer pattern and the vertical projection of the second metal layer on the substrate forms the storage capacitor.

7. The array substrate according to claim 6, wherein The overlapping area of the second metal layer and the first gate layer pattern is 120 μm 2 ~200 μm 2 .

8. The array substrate according to claim 7, wherein It further includes a third metal layer arranged in the first direction and located on the side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line; The first scan signal line overlaps with the third gate layer pattern of the initialization transistor; The second scan signal line overlaps with the fourth gate layer pattern of the write transistor and the fifth gate layer pattern of the compensation transistor; The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

9. The array substrate according to claim 8, wherein, The third metal layer further includes an initialization voltage signal line, a reset voltage signal line, and a first power supply voltage signal line; The third active layer pattern of the initialization transistor overlaps with the initialization voltage signal line; The second metal layer overlaps with the first power supply voltage signal line; The sixth active layer pattern of the reset transistor overlaps with the reset voltage signal line.

10. The array substrate according to claim 9, wherein, It further includes a fourth metal layer disposed along the second direction, on a side of the third metal layer away from the substrate.

11. The array substrate according to claim 10, wherein The fourth metal layer includes a data line and the first power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data write transistor; the first power supply voltage signal line overlaps with the third metal layer.

12. A display panel, characterized in that, An array substrate according to any one of claims 1 to 11 is included.

13. A display device, characterized in that, An array substrate according to any one of claims 1 to 11 is included.

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