Display substrate and display device

Abstract

A display substrate and a display device, which relate to the technical field of display. The display substrate comprises a base substrate, and a display region and a non-display region that are disposed on one side of the base substrate. The display region comprises: scanning lines extending in a row direction, and data lines extending in a column direction, wherein the scanning lines are located in a first metal layer, and the data lines are located in a second metal layer. The non-display region comprises: scanning fan-out lines, which are connected to the scanning lines and comprise first scanning fan-out lines and second scanning fan-out lines, wherein the first scanning fan-out lines are located in the first metal layer, and the second scanning fan-out lines are located in the second metal layer; and data fan-out lines, which are connected to the data lines and comprise first data fan-out lines and second data fan-out lines, wherein the first data fan-out lines are located in the second metal layer, the second data fan-out lines are located in a third metal layer, and orthographic projections of the first data fan-out lines and the second scanning fan-out lines on the base substrate do not overlap.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the development of display technology, the demand for customized display screens is increasing. Whether it is consumer products or automotive screens, there is a market demand for special-shaped display areas or overall special shapes.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising:

[0005] A base substrate, and a display area and a non-display area arranged on one side of the base substrate;

[0006] The display area includes: scan lines extending along the row direction, and data lines extending along the column direction, the scan lines are located in the first metal layer, and the data lines are located in the second metal layer;

[0007] The non-display area includes:

[0008] a scan fan-out line connected to the scan line, comprising a first scan fan-out line and a second scan fan-out line, wherein the first scan fan-out line is located in the first metal layer, and the second scan fan-out line is located in the second metal layer;

[0009] A data fan-out line is connected to the data line, including a first data fan-out line and a second data fan-out line, the first data fan-out line is located in the second metal layer, the second data fan-out line is located in the third metal layer, and the first data fan-out line and the second scan fan-out line have no overlapping orthographic projections on the substrate.

[0010] In some embodiments, the non-display area further includes:

[0011] A first fan-out area includes the first data fan-out line and the second data fan-out line; and

[0012] The second fan-out area includes the first scanning fan-out line and the second scanning fan-out line, and is located on the same side of the display area as the first fan-out area. The second fan-out area is located on a side of the first fan-out area away from the display area.

[0013] In some embodiments, the display area includes a plurality of sub-pixels, each sub-pixel includes a common electrode, the common electrode is located in the first conductive layer, and the common electrodes of the plurality of sub-pixels are interconnected;

[0014] The second metal layer further includes a first common voltage line located between the first fan-out area and the second fan-out area and connected to the common electrode.

[0015] In some embodiments, the first fan-out area and the second fan-out area are arranged along a row direction, and the first metal layer further includes:

[0016] The scan lead extends along the row direction in the non-display area, passes through the first fan-out area and the first common voltage line in the row direction, and is connected between the scan line and the first scan fan-out line or the second scan fan-out line.

[0017] In some embodiments, the non-display area further includes:

[0018] The first electrostatic discharge unit is disposed between the first common voltage line and the second fan-out area, and is connected to the scan lead and the first common voltage line respectively, for transferring electrostatic charge on the scan lead to the first common voltage line.

[0019] In some embodiments, the first transparent conductive layer further includes: a first connection pattern, located in the non-display area and connected to the common electrode;

[0020] The sub-pixels further include pixel electrodes, which are located in the second transparent conductive layer. The pixel electrodes of different sub-pixels are spaced apart from each other. The second transparent conductive layer further includes:

[0021] The common transfer pattern is located in the non-display area, is separated from the pixel electrode, is connected to the first common voltage line through a first via hole, and is connected to the first connection pattern through a second via hole.

[0022] In some embodiments, the second metal layer further comprises:

[0023] a second common voltage line extending along a column direction and located between two adjacent data lines; and

[0024] The second connection pattern is located in the non-display area, connected to the second common voltage line, and further connected to the common transfer pattern through a third via hole.

[0025] In some embodiments, the second via hole is located on a side of the third via hole close to the display area, and the first connection pattern is located away from a boundary of the display area and on a side of the third via hole close to the display area.

[0026] In some embodiments, the number of the second via holes is greater than or equal to the number of the third via holes.

[0027] In some embodiments, the first connection pattern includes:

[0028] A first sub-pattern and a second sub-pattern are separated from each other and arranged along the row direction, a size of the first sub-pattern along the column direction is smaller than a size of the second sub-pattern along the column direction, and the number of second vias connecting the first sub-pattern is smaller than the number of second vias connecting the second sub-pattern.

[0029] In some embodiments, the second metal layer further includes: a third connection pattern, located in the non-display area and connected to an end of the data line close to the second data fan-out line;

[0030] The third metal layer further includes: a fourth connection pattern, located in the non-display area and connected to an end of the second data fan-out line close to the data line;

[0031] The second transparent conductive layer further includes:

[0032] The data transfer pattern is connected to the third connection pattern through a fourth via hole, and is connected to the fourth connection pattern through a fifth via hole, the fourth via hole is located on a side of the fifth via hole close to the display area, and the fourth connection pattern is located close to the boundary of the display area on a side of the fourth via hole away from the display area.

[0033] In some embodiments, the number of the fourth via holes is equal to the number of the fifth via holes.

[0034] In some embodiments, the first metal layer further comprises:

[0035] a scan lead, located in the non-display area and connected between the scan line and the second scan fan-out line; and

[0036] a fifth connection pattern, located in the non-display area and connected to an end of the scan lead close to the second scan fan-out line;

[0037] The second metal layer further includes: a sixth connection pattern, located in the non-display area and connected to an end of the second scan fan-out line close to the fifth connection pattern;

[0038] The second transparent conductive layer further includes a scan switching pattern, which is connected to the fifth connection pattern and the sixth connection pattern through via holes.

[0039] In some embodiments, the non-display area further includes:

[0040] a binding area, comprising a plurality of scanning terminals, wherein the scanning terminals are connected to the scanning lines; and

[0041] a compensation capacitor, located on a side of the display area away from the binding area, comprising a first electrode plate and a second electrode plate arranged opposite to each other, the first electrode plate being located on the second metal layer, and the second electrode plate being located on the first transparent conductive layer;

[0042] The second metal layer further includes:

[0043] a third common voltage line, located between the compensation capacitor and the display area, and connected to the second electrode plate; and

[0044] a seventh connection pattern connected to the first electrode plate;

[0045] The second transparent conductive layer further includes a capacitor transfer pattern, which is respectively connected to the seventh connection pattern and the scan fan-out line through via holes.

[0046] In some embodiments, in an orthographic projection on the base substrate, the first electrode plate extends in a bow shape, and a gap exists between the seventh connection pattern and the scan fan-out line that are arranged opposite to each other.

[0047] In some embodiments, the non-display area further includes:

[0048] a third fan-out area, including the first data fan-out line and the second data fan-out line, and located on a different side of the display area from the first fan-out area;

[0049] The first metal layer also includes: a fourth common voltage line, which is connected to the first common voltage line and is located on the same side of the display area as the third fan-out area, and in the orthographic projection on the base substrate, the fourth common voltage line overlaps with the first data fan-out line and the second data fan-out line located in the third fan-out area.

[0050] In some embodiments, the display area includes a plurality of sub-pixels arranged along row and column directions;

[0051] The data fan-out line includes: a first extension segment, a second extension segment, and a third extension segment connected in sequence, the first extension segment and the third extension segment extend along the column direction, the first extension segment is connected between the data line and the second extension segment, the extension direction of the second extension segment is different from the row direction and the column direction, and the line width of the first extension segment is greater than or equal to the line width of the second extension segment, and the line width of the third extension segment is greater than or equal to the line width of the first extension segment.

[0052] In some embodiments, in an orthographic projection on the substrate, two adjacent first extension segments are arranged in different layers and have a first gap, two adjacent second extension segments are arranged in different layers and overlap, are flush with each other, or have a second gap, and two adjacent third extension segments are arranged in different layers and have a third gap; and

[0053] The first gap is substantially equal to at least one time of an arrangement period of the sub-pixels along a row direction. The first gap is greater than or equal to the third gap, and the third gap is greater than or equal to the second gap.

[0054] In some embodiments, the second metal layer further comprises:

[0055] A first data terminal is located in the non-display area and is connected to an end of the first data fan-out line away from the display area;

[0056] The third metal layer further includes:

[0057] The second data terminal is located in the non-display area and is connected to an end of the second data fan-out line away from the display area.

[0058] In some embodiments, the display area includes a plurality of sub-pixels, each sub-pixel includes a common electrode and a pixel electrode, the common electrode is located in the first conductive layer, and the pixel electrode is located in the second transparent conductive layer, the common electrodes of the plurality of sub-pixels are interconnected, and the pixel electrodes of different sub-pixels are separated from each other;

[0059] The first metal layer, the second metal layer, the third metal layer, the first transparent conductive layer and the second transparent conductive layer are stacked in sequence, and the first metal layer is arranged close to the base substrate; or

[0060] The first metal layer, the second metal layer, the first transparent conductive layer, the third metal layer and the second transparent conductive layer are stacked in sequence, and the first metal layer is arranged close to the base substrate.

[0061] In some embodiments, the first metal layer, the second metal layer, and the third metal layer are made of the same material.

[0062] In some embodiments, in an orthographic projection on the substrate, the first scan fan-out lines and the second scan fan-out lines are alternately arranged in sequence, and the first data fan-out lines and the second data fan-out lines are alternately arranged in sequence.

[0063] In some embodiments, in the orthographic projection on the base substrate, the figure tangent to the edge of the display area is a trapezoid or an inverted trapezoid.

[0064] The present disclosure provides a display substrate, comprising:

[0065] A base substrate, and a display area and a non-display area arranged on one side of the base substrate;

[0066] The display area includes: scan lines extending along the row direction, and data lines extending along the column direction, the scan lines are located in the first metal layer, and the data lines are located in the second metal layer;

[0067] The non-display area includes:

[0068] a scan fan-out line connected to the scan line, comprising a first scan fan-out line and a second scan fan-out line, wherein the first scan fan-out line is located in the first metal layer, and the second scan fan-out line is located in the third metal layer;

[0069] A data fan-out line is connected to the data line, including a first data fan-out line and a second data fan-out line, the first data fan-out line is located in the second metal layer, the second data fan-out line is located in the first metal layer, and the second data fan-out line and the first scan fan-out line have no overlapping orthographic projections on the substrate.

[0070] The present disclosure provides a display device, comprising:

[0071] The display substrate according to any one of the embodiments; and

[0072] The driving circuit is respectively connected to the scan fan-out lines and the data fan-out lines in the display substrate, and is used for driving the display substrate to perform display.

[0073] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0074] BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0076] FIG1 exemplarily shows a schematic planar structural diagram of a first display substrate;

[0077] FIG2 exemplarily shows a circuit layout diagram of a first area in a non-display area;

[0078] FIG3 exemplarily shows a partial enlarged view of the dotted boxes B2 and B3;

[0079] FIG4 exemplarily shows a schematic cross-sectional structure diagram of a display substrate along lines AA′ and BB′;

[0080] FIG5 exemplarily shows a schematic planar structural diagram of a second display substrate;

[0081] FIG6 exemplarily shows a schematic diagram of the structure of region C and the vicinity of region C of the first display substrate;

[0082] FIG7 exemplarily shows a schematic diagram of the structure of region C and the vicinity of region C of a second display substrate;

[0083] FIG8 exemplarily shows a schematic cross-sectional structure diagram of a sub-pixel in a display area;

[0084] FIG9 exemplarily shows a circuit equivalent diagram of a first electrostatic discharge unit;

[0085] FIG10 exemplarily shows a circuit layout diagram of the second area in the non-display area;

[0086] FIG11 exemplarily shows a cross-sectional view of a connection structure between a common transfer pattern and a first common voltage line;

[0087] FIG12 exemplarily shows a schematic cross-sectional structural diagram of a first adapter unit;

[0088] FIG13 exemplarily shows a schematic cross-sectional structure diagram of a third adapter unit;

[0089] FIG14 exemplarily shows a circuit layout diagram of a third area in the non-display area;

[0090] FIG15 exemplarily shows a schematic cross-sectional structural diagram of a second adapter unit;

[0091] FIG16 exemplarily shows a schematic cross-sectional structural diagram of a fourth adapter unit;

[0092] FIG17 exemplarily shows a circuit layout diagram of a compensation capacitor;

[0093] FIG18 exemplarily shows a schematic cross-sectional structure diagram of a display substrate along lines HH′, II′, and JJ′;

[0094] FIG19 exemplarily shows a circuit layout diagram of a second electrostatic discharge unit;

[0095] FIG20 exemplarily shows a circuit equivalent diagram of a second electrostatic discharge unit;

[0096] FIG21 exemplarily shows a circuit layout diagram of the third fan-out area in the non-display area;

[0097] FIG22 exemplarily shows a circuit layout diagram of data fan-out lines in a non-display area;

[0098] FIG23 exemplarily shows a schematic structural diagram of a first data terminal and a second data terminal;

[0099] FIG24 exemplarily shows a schematic planar structural diagram of a third display substrate;

[0100] FIG. 25 exemplarily shows another cross-sectional structural diagram of the display substrate along AA′ and BB′.

[0101] Detailed description

[0102] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0103] The present disclosure provides a display substrate 01, as shown in FIG1 . The display substrate 01 includes a base substrate 11 (not shown in FIG1 ), and a display area AA and a non-display area NA disposed on one side of the base substrate 11. The display area AA includes scan lines SC extending along a row direction f1 and data lines DT extending along a column direction f2. The scan lines SC are located in a first metal layer M1, and the data lines DT are located in a second metal layer M2.

[0104] FIG2 shows a circuit layout diagram at the dotted line frame B1 in FIG1. ​​FIG3 B2 shows a partial enlarged view of the dotted line frame B2 in FIG2, and FIG3 B3 shows a partial enlarged view of the dotted line frame B3 in FIG2.

[0105] As shown in Figures 2 and 3, the non-display area NA includes: a scan fan-out line 11, which is connected to the scan line SC, including a first scan fan-out line 111 and a second scan fan-out line 112, the first scan fan-out line 111 is located in the first metal layer M1, and the second scan fan-out line 112 is located in the second metal layer M2; and a data fan-out line 12, which is connected to the data line DT, including a first data fan-out line 121 and a second data fan-out line 122, the first data fan-out line 121 is located in the second metal layer M2, and the second data fan-out line 122 is located in the third metal layer M3, and the orthographic projections of the first data fan-out line 121 and the second scan fan-out line 112 on the base substrate 11 have no overlap.

[0106] 4 shows a schematic cross-sectional structure diagram along the lines AA' and BB' in FIG3. As shown in FIG4, the first metal layer M1, the second metal layer M2 and the third metal layer M3 are three stacked film layers.

[0107] The display substrate 01 provided by the present disclosure is shown in Figure 4. The scanning fan-out line 11 is double-layered in the first metal layer M1 and the second metal layer M2, and the data fan-out line 12 is double-layered in the second metal layer M2 and the third metal layer M3. This not only realizes a narrow frame, but also avoids a short circuit between the scanning fan-out line 11 and the data fan-out line 12, so that the data fan-out line 12 and the scanning fan-out line 11 can be located on the same side of the display area AA, which is conducive to the realization of an irregular display substrate 01 design.

[0108] Exemplarily, as shown in FIG. 1 , the orthographic projections of the scan lines SC and the data lines DT on the base substrate 11 intersect with each other and define a plurality of sub-pixels PX, and the plurality of sub-pixels PX are located in the display area AA.

[0109] In some embodiments, as shown in FIG. 4 , in an orthographic projection on the base substrate 11 , the first scanning fan-out lines 111 and the second scanning fan-out lines 112 are alternately arranged in sequence.

[0110] In some embodiments, as shown in FIG. 4 , in an orthographic projection on the base substrate 11 , the first data fan-out lines 121 and the second data fan-out lines 122 are alternately arranged in sequence.

[0111] In some embodiments, as shown in FIG2 , the non-display area NA further includes: a first fan-out area FAN1, including a first data fan-out line 121 and a second data fan-out line 122; and a second fan-out area FAN2, including a first scan fan-out line 111 and a second scan fan-out line 112, which are located on the same side of the display area AA as the first fan-out area FAN1, and the second fan-out area FAN2 is located on a side of the first fan-out area FAN1 away from the display area AA.

[0112] For example, as shown in FIG1 or FIG5 , the scan fan-out line 11 is located in area B of the non-display area NA, part of the data fan-out line 12 is located in area A of the non-display area NA, and area C is the overlapping area of ​​area A and area B, that is, the scan fan-out line 11 and the data fan-out line 12 are both arranged in area C, so the first fan-out area FAN1 and the second fan-out area FAN2 are arranged in area C.

[0113] For example, FIG6 shows a schematic diagram of the structure of region C and its surroundings in FIG1 . As shown in the upper diagram of FIG6 , region C is located to the left of display area AA. Correspondingly, as shown in the lower diagram of FIG6 , both the first fan-out region FAN1 and the second fan-out region FAN2 are located to the left of display area AA. To the left of display area AA, the second fan-out region FAN2, the first fan-out region FAN1, and the display area AA are arranged sequentially along row direction f1.

[0114] For example, FIG7 shows a schematic diagram of the structure of region C and its surroundings in FIG5 . As shown in the upper figure of FIG7 , region C is located on the lower left side of display area AA. Correspondingly, as shown in the lower figure of FIG7 , both the first fan-out area FAN1 and the second fan-out area FAN2 are located on the lower left side of display area AA, with the first fan-out area FAN1 located between display area AA and the second fan-out area FAN2.

[0115] Exemplarily, as shown in FIG8 , the sub-pixel PX includes a common electrode 81 . The common electrode 81 is located on the first transparent conductive layer T1 . The common electrodes 81 of a plurality of sub-pixels PX are interconnected.

[0116] Exemplarily, as shown in FIG8 , the sub-pixel PX further includes a pixel electrode 82 . The pixel electrode 82 is located in the second transparent conductive layer T2 , and the pixel electrodes 82 of different sub-pixels PX are spaced apart from each other.

[0117] In some embodiments, as shown in FIG. 2 , the second metal layer M2 further includes a first common voltage line COM1 located between the first fan-out area FAN1 and the second fan-out area FAN2 and electrically connected to the common electrode 81 in the sub-pixel PX.

[0118] 2 , the extension direction f3 of the first common voltage line COM1 between the first fan-out area FAN1 and the second fan-out area FAN2 is substantially parallel to the extension direction f4 of the data fan-out lines 12 and the scan fan-out lines 11 on either side of the first common voltage line COM1. The extension direction f3 of the first common voltage line COM1 is different from the row direction f1 and the column direction f2.

[0119] In some embodiments, as shown in Figure 2, the first fan-out area FAN1 and the second fan-out area FAN2 are arranged along the row direction f1, and the first metal layer M1 further includes: a scan lead 13, which extends at least partially along the row direction f1 in the non-display area NA, passes through the first fan-out area FAN1 and the first common voltage line COM1 in the row direction f1, and is connected between the scan line SC and the first scan fan-out line 111 or the second scan fan-out line 112.

[0120] Since the scan lead 13 passes through the first fan-out area FAN1, and the first fan-out area FAN1 includes the first data fan-out line 121 located in the second metal layer M2 and the second data fan-out line 122 located in the third metal layer M3, by setting the scan lead 13 in the first metal layer M1, a short circuit can be avoided between the crossed scan lead 13 and the first data fan-out line 121, or between the scan lead 13 and the second data fan-out line 122.

[0121] By disposing the first common voltage line COM1 on the second metal layer M2 and the scan lead 13 on the first metal layer M1 , a short circuit between the first common voltage line COM1 and the scan lead 13 that are intersecting with each other can be avoided.

[0122] In some embodiments, as shown in Figure B2 in Figure 3, the non-display area NA also includes: a first electrostatic discharge unit ES1, which is arranged between the first common voltage line COM1 and the second fan-out area FAN2, and is electrically connected to the scan lead 13 and the first common voltage line COM1, respectively, for transferring the electrostatic charge on the scan lead 13 to the first common voltage line COM1.

[0123] As shown in FIG3B2, the arrangement direction of the plurality of first electrostatic discharge units ES1 is substantially parallel to the extension direction f3 of the first common voltage line COM1. The plurality of first electrostatic discharge units ES1 are connected to the same first common voltage line COM1, and different first electrostatic discharge units ES1 are connected to different scan leads 13.

[0124] For example, as shown in FIG. 3B2 , each first electrostatic discharge unit ES1 is located on one side of a scan lead 13 connected to the first electrostatic discharge unit ES1. The first electrostatic discharge unit ES1 is connected to the first common voltage line COM1 via a common lead 14. The common lead 14 is located between the first electrostatic discharge unit ES1 and the first common voltage line COM1 and extends along the row direction f1. The common lead 14 is, for example, provided on the same layer as the first common voltage line COM1, both located on the second metal layer M2.

[0125] Referring to Figure 9, an equivalent circuit diagram of the first electrostatic discharge unit ES1 is shown. The first electrostatic discharge unit ES1 includes four transistors. The connection relationship of the four transistors is shown in Figure 9. When there is too much electrostatic charge on the scanning lead 13, the four transistors are turned on, thereby transmitting the electrostatic charge on the scanning lead 13 to the first common voltage line COM1.

[0126] Exemplarily, as shown in FIG6 , an outer common voltage line COM is further provided on a side of the second fan-out area FAN2 away from the first fan-out area FAN1 . The outer common voltage line COM is, for example, located in the first metal layer M1 .

[0127] To achieve connection between the first common voltage line COM1 and the common electrode 81, as shown in FIG10 , in some embodiments, the first transparent conductive layer T1 further includes a first connection pattern 91 located in the non-display area NA and connected to the common electrode 81. As shown in FIG10 , the second transparent conductive layer T2 further includes a common transfer pattern 92 located in the non-display area NA and spaced apart from the pixel electrode 82.

[0128] As shown in Figures 3 and 11 , the common transfer pattern 92 is connected to the first common voltage line COM1 through a first via H1 . Figure 11 is a schematic cross-sectional view taken along CC′ in Figure 3 .

[0129] As shown in Figures 10, 12 and 13, the common transfer pattern 92 is connected to the first connection pattern 91 through the second via H2. Figure 12 is a schematic cross-sectional view taken along DD' in Figure 10, and Figure 13 is a schematic cross-sectional view taken along EE' in Figure 10.

[0130] Among them, the first connection pattern 91 and the common electrode 81 are arranged on the same layer in the first transparent conductive layer T1 and are connected to each other, and the first common voltage line COM1 is located in the second metal layer M2. In this embodiment, a bridge connection between the first common voltage line COM1 and the first connection pattern 91 is achieved through a common transfer pattern 92 located in the second transparent conductive layer T2, thereby achieving a connection between the first common voltage line COM1 and the common electrode 81, and the common transfer pattern 92 is arranged on the same layer as the pixel electrode 82, which can reduce the mask process, simplify the process and reduce costs.

[0131] In some embodiments, as shown in FIG10 , the second metal layer M2 further includes: a second common voltage line COM2 extending along the column direction f2 and located between two adjacent data lines DT; and a second connection pattern 93 located in the non-display area NA and connected to the second common voltage line COM2. As shown in FIG12 and FIG13 , the second connection pattern 93 is further connected to the common transfer pattern 92 via a third via H3.

[0132] The second connection pattern 93 and the second common voltage line COM2 are disposed on the same layer in the second metal layer M2 and are interconnected. In this embodiment, the common transfer pattern 92 located in the second transparent conductive layer T2 is further connected to the second connection pattern 93 located in the second metal layer M2 through a third via H3, thereby achieving a bridge connection between the first common voltage line COM1 and the second connection pattern 93, and further achieving a connection between the first common voltage line COM1 and the second common voltage line COM2.

[0133] In some embodiments, as shown in FIG10 , the second via hole H2 is located on a side of the third via hole H3 close to the display area AA, and the first connection pattern 91 is located away from the boundary of the display area AA and close to the display area AA of the third via hole H3. In this way, the third via hole H3 can be avoided without drilling a hole in the first transparent conductive layer T1.

[0134] Exemplarily, as shown in FIG10 , the second via holes H2 are all located between the third via holes H3 in the display area AA.

[0135] Exemplarily, the orthographic projection of the common transfer pattern 92 on the base substrate 11 covers the orthographic projection of the second connection pattern 93 on the base substrate 11, and the orthographic projection of the second connection pattern 93 on the base substrate 11 covers the orthographic projection of the first connection pattern 91 on the base substrate 11, and the second connection pattern 93 is arranged in a one-to-one correspondence with the first connection pattern 91.

[0136] In some embodiments, as shown in FIG. 10 , the number of the second via holes H2 is greater than or equal to the number of the third via holes H3 .

[0137] For example, in the first adapter unit Z1 shown in FIG10 , the number of the second via holes H2 is equal to the number of the third via holes H3 , and both numbers are, for example, 2.

[0138] For example, in the third adapter unit Z3 shown in FIG10 , the number of second vias H2 is greater than the number of third vias H3. For example, the number of second vias H2 is 4, and the number of third vias H3 is 2. Since the second vias H2 connect the first transparent conductive layer T1 and the second transparent conductive layer T2, increasing the number of second vias H2 can effectively reduce the connection resistance and improve the connection reliability between the first transparent conductive layer T1 and the second transparent conductive layer T2. In some embodiments, as shown in FIG10 , the first connection pattern 91 includes: a first sub-pattern 911 and a second sub-pattern 912 that are spaced apart from each other and arranged along the row direction f1. The size of the first sub-pattern 911 along the column direction f2 is smaller than the size of the second sub-pattern 912 along the column direction f2, and the number of second vias H2 connecting the first sub-pattern 911 is smaller than the number of second vias H2 connecting the second sub-pattern 912.

[0139] Exemplarily, as shown in Figure 10, the first sub-pattern 911 is connected to the common transfer pattern 92 through two second vias H2, the second sub-pattern 912 is connected to the common transfer pattern 92 through four second vias H2, and the size of the first sub-pattern 911 along the column direction f2 is approximately half the size of the second sub-pattern 912 along the column direction f2.

[0140] For example, as shown in Figure 10, the first transfer unit Z1 includes a first sub-pattern 911, a second connection pattern 93, a portion of the common transfer pattern 92 connected to the first sub-pattern 911 and the second connection pattern 93, a second via H2, and a third via H3; the third transfer unit Z3 includes a second sub-pattern 912, a second connection pattern 93, a portion of the common transfer pattern 92 connected to the second sub-pattern 912 and the second connection pattern 93, a second via H2, and a third via H3.

[0141] Exemplarily, the first switching unit Z1 is disposed in an area with limited space in the column direction f2, such as an area near a corner of the display substrate 01, and the third switching unit Z3 is disposed in other areas with sufficient space in the column direction f2.

[0142] Exemplarily, as shown in FIG. 3 B2 , a plurality of first via holes H1 are arranged in an array along the row direction f1 and the column direction f2 .

[0143] For example, as shown in Figure 10, in the first adapter unit Z1, the plurality of second vias H2 are arranged along the row direction f1, and the plurality of third vias H3 are arranged along the row direction f1. As shown in Figure 10, in the third adapter unit Z3, the plurality of second vias H2 are arranged along the row direction f1 and the column direction f2, and the plurality of third vias H3 are arranged along the row direction f1.

[0144] Exemplarily, as shown in FIG10 , the first transparent conductive layer T1 further includes: a protruding pattern 02 located in the non-display area NA and connected to the common electrode 81 , that is, in the row direction f1 , the first connection pattern 91 and the protruding pattern 02 are alternately arranged one by one, which can simplify the design.

[0145] In some embodiments, as shown in FIG14 , the second metal layer M2 further includes: a third connection pattern 141, located in the non-display area NA, connected to the end of the data line DT near the second data fan-out line 122. The third metal layer M3 further includes: a fourth connection pattern 142, located in the non-display area NA, connected to the end of the second data fan-out line 122 near the data line DT. As shown in FIG15 , the second transparent conductive layer T2 further includes: a data transfer pattern 143, connected to the third connection pattern 141 through a fourth via H4, and connected to the fourth connection pattern 142 through a fifth via H5. The fourth via H4 is located on the side of the fifth via H5 near the display area AA, and the fourth connection pattern 142 is located near the boundary of the display area AA on the side of the fourth via H4 away from the display area AA. In this way, the fourth via H4 can be avoided without drilling a hole in the fourth transfer pattern. FIG15 is a schematic diagram of the cross-sectional structure along FF' in FIG14 .

[0146] As shown in FIG. 14 , the second transfer unit Z2 includes a third connection pattern 141 , a fourth connection pattern 142 , a data transfer pattern 143 , a fourth via hole H4 , and a fifth via hole H5 .

[0147] Among them, the third connection pattern 141 and the data line DT are arranged on the same layer in the second metal layer M2 and are connected to each other, and the fourth connection pattern 142 and the second data fan-out line 122 are arranged on the same layer in the third metal layer M3 and are connected to each other. The data transfer pattern 143 arranged on the second transparent conductive layer T2 is used to realize the bridge connection between the third connection pattern 141 and the fourth connection pattern 142, thereby realizing the connection between the data line DT and the second data fan-out line 122, and the data transfer pattern 143 is arranged on the same layer as the pixel electrode 82, which can reduce the mask process, simplify the process and reduce the cost.

[0148] Exemplarily, the orthographic projection of the data transfer pattern 143 on the base substrate 11 covers the orthographic projection of the third connection pattern 141 on the base substrate 11 , and the orthographic projection of the third connection pattern 141 on the base substrate 11 covers the orthographic projection of the fourth connection pattern 142 on the base substrate 11 .

[0149] 14 , the width of the third connection pattern 141 along the row direction f1 is greater than the width of the data line DT along the row direction f1 , and the width of the fourth connection pattern 142 along the row direction f1 is greater than the width of the second data fan-out line 122 along the row direction f1 .

[0150] Exemplarily, as shown in FIG. 14 , the plurality of fourth via holes H4 and the plurality of fifth via holes H5 are arranged along the row direction f1 .

[0151] Exemplarily, as shown in FIG. 14 , the number of the fourth via holes H4 is equal to the number of the fifth via holes H5 , and both numbers are 2 in FIG. 14 .

[0152] As shown in FIG14 , the first data fan-out line 121 and the data line DT are provided in the same layer and are connected to each other, and the second data fan-out line 122 is connected to the data line DT via a second switching unit Z2 .

[0153] In some embodiments, as shown in Figure B2 in Figure 3, the first metal layer M1 further includes: a scan lead 13, located in the non-display area NA, connected between the scan line SC and the second scan fan-out line 112; and a fifth connection pattern 31, located in the non-display area NA, connected to an end of the scan lead 13 close to the second scan fan-out line 112. The second metal layer M2 further includes: a sixth connection pattern 32, located in the non-display area NA, connected to an end of the second scan fan-out line 112 close to the fifth connection pattern 31. As shown in Figures 3 and 16, the second transparent conductive layer T2 further includes: a scan transfer pattern 33, connected to the fifth connection pattern 31 and the sixth connection pattern 32 through vias, respectively. Figure 16 is a schematic diagram of the cross-sectional structure along GG' in Figure 3.

[0154] As shown in FIG. 3 B2 , the fourth switching unit Z4 includes a fifth connection pattern 31 , a sixth connection pattern 32 and a scan switching pattern 33 .

[0155] Among them, the scan line SC, the scan lead 13 and the fifth connection pattern 31 are arranged on the same layer in the first metal layer M1 and are connected in sequence, the sixth connection pattern 32 and the second scan fan-out line 112 are arranged on the same layer in the second metal layer M2 and are connected to each other, and the bridge connection between the fifth connection pattern 31 and the sixth connection pattern 32 is realized by the scan transfer pattern 33 arranged in the second transparent conductive layer T2, thereby realizing the connection between the scan line SC or the scan lead 13 and the second scan fan-out line 112, and the scan transfer pattern 33 is arranged on the same layer as the pixel electrode 82, which can reduce the mask plate process, simplify the process and reduce the cost.

[0156] As shown in FIG. 3 B2 , the first scanning fan-out line 111 and the scanning lead 13 are provided on the same layer and are connected to each other, and the second scanning fan-out line 112 and the scanning lead 13 are connected via a fourth switching unit Z4 .

[0157] Exemplarily, as shown in FIG3 , the fourth switching unit Z4 is located between the first electrostatic discharge unit ES1 and the second fan-out area FAN2 .

[0158] Exemplarily, as shown in FIG10 , at least one of the first adapter unit Z1, the second adapter unit Z2, and the third adapter unit Z3 is disposed at the end of the sub-pixel PX arranged in a stepped manner, and the scanning lead 13 that overlaps with these adapter units in the row direction f1 is wound to the side of these adapter units away from the display area AA, and then extends from the display area AA to the non-display area NA along the row direction f1.

[0159] For example, as shown in FIG10 , the scan lead 13 includes a first lead segment 131 and a second lead segment 132. The first lead segment 131 is connected between the scan line SC and the second lead segment 132. The first lead segment 131 extends along the column direction f2, and the second lead segment 132 extends along the row direction f1. In the column direction f2, the second lead segment 132 is offset from the connected scan line SC by approximately the size of one sub-pixel PX.

[0160] In some embodiments, as shown in FIG1 , the non-display area NA further includes a binding area BD including a plurality of scan terminals (not shown in FIG1 , located in the GIC area), which are connected to the scan lines SC.

[0161] As shown in FIG17 , the non-display area NA further includes: a compensation capacitor C, which is located on the side of the display area AA away from the binding area BD, and includes a first electrode plate E1 and a second electrode plate E2 arranged opposite to each other, wherein the first electrode plate E1 is located on the second metal layer M2, and the second electrode plate E2 is located on the first transparent conductive layer T1.

[0162] As shown in Figure 17, the second metal layer M2 further includes a third common voltage line COM3, located between the compensation capacitor C and the display area AA and connected to the second electrode plate E2; and a seventh connection pattern 172, connected to the first electrode plate E1. The second transparent conductive layer T2 also includes a capacitor transfer pattern 173, which is connected to the seventh connection pattern 172 and the scan fan-out line 11 through vias.

[0163] FIG18 shows a schematic cross-sectional structure diagram along lines HH', II', and JJ' in FIG17. As shown in FIG18, a capacitor transfer pattern 173 located in the second transparent conductive layer T2 is used to bridge the seventh connection pattern 172 and the scan fan-out line 11, thereby achieving a connection between the first electrode plate E1 and the scan fan-out line 11. Furthermore, the capacitor transfer pattern 173 is provided on the same layer as the pixel electrode 82, which reduces mask steps, simplifies the process, and reduces costs.

[0164] In this embodiment, by providing a compensation capacitor C on a side away from the scan terminal, capacitance differences caused by differences in the number of pixels in different rows can be compensated, thereby improving display uniformity.

[0165] 17 , the first transparent conductive layer T1 further includes an eighth connection pattern 174 , one end of which is connected to the second electrode plate E2 , and the other end of which is connected to the third common voltage line COM3 through a via hole, thereby achieving connection between the second electrode plate E2 and the third common voltage line COM3 .

[0166] When the first transparent conductive layer T1 is located between the second metal layer M2 and the second transparent conductive layer T2, since the thickness of the insulating layer located between the first transparent conductive layer T1 and the second metal layer M2 is relatively small, the capacitance of the compensation capacitor C can be increased by disposing the first electrode plate E1 of the compensation capacitor C on the second metal layer M2 and the second electrode plate E2 of the compensation capacitor C on the first transparent conductive layer T1.

[0167] Exemplarily, as shown in FIG17 , the compensation capacitor C is located at the end of the sub-pixels PX arranged in a stepped manner, the position of the compensation capacitor C in the column direction f2 corresponds to the position of a row of sub-pixels PX in the column direction f2, and the size of the compensation capacitor C in the column direction f2 is approximately equal to the size of a row of sub-pixels PX in the column direction f2.

[0168] In some embodiments, as shown in Figure 17, the multiple compensation capacitors C include a first compensation capacitor C1 and a second compensation capacitor C2, the multiple scanning leads 13 include a first scanning lead 133 and a second scanning lead 134, the first scanning lead 133 is connected to the first compensation capacitor C1, and the second scanning lead 134 is connected to the second compensation capacitor C2, the number of sub-pixels connected to the first scanning lead 133 is greater than the number of sub-pixels connected to the second scanning lead 134, and the capacitance of the first compensation capacitor C1 is less than the capacitance of the second compensation capacitor C2.

[0169] Exemplarily, as shown in FIG17 , the size of the first compensation capacitor C1 in the row direction f1 is smaller than the size of the second compensation capacitor C2 in the row direction f1 .

[0170] In a specific implementation, the capacitance difference can be calculated based on the number of sub-pixels connected to the first scan line SC and the number of sub-pixels connected to the second scan line SC, and then the compensation capacitor C connected to the first scan line SC and the compensation capacitor C connected to the second scan line SC are set according to the capacitance difference.

[0171] As shown in FIG17 , as the number of sub-pixels PX decreases row by row in the direction from the display area AA to the non-display area NA (from bottom to top in FIG17 ), the required compensation capacitor C becomes larger and larger. By providing the compensation capacitor C, the capacitance difference between two adjacent rows of sub-pixels PX can be reduced. For example, the capacitance difference between two adjacent rows of sub-pixels PX can be controlled within 7%.

[0172] In some embodiments, as shown in FIG17 , in an orthographic projection on the base substrate 11, the first electrode plate E1 extends in a bow shape, and a gap d exists between the seventh connection pattern 172 and the scan fan-out line 11. Providing the gap d prevents an antenna effect caused by an excessively long first electrode plate E1.

[0173] Exemplarily, as shown in FIG17 , a first electrostatic discharge unit ES1 is further provided between the compensation capacitor C and a row of sub-pixels PX. The first electrostatic discharge unit ES1 is connected to the third common voltage line COM3 and the scan lead 13 respectively.

[0174] In some embodiments, as shown in FIG. 19 , the non-display area NA further includes: a second electrostatic discharge unit ESD2 , which is disposed between the third common voltage line COM3 and the display area AA and is connected to the data line DT and the third common voltage line COM3 , respectively, for transferring the electrostatic charge on the data line DT to the third common voltage line COM3 .

[0175] As shown in FIG. 19 , a plurality of second electrostatic discharging units ESD2 are connected to the same third common voltage line COM3 , and different second electrostatic discharging units ESD2 are connected to different data lines DT.

[0176] For example, as shown in FIG. 19 , the second electrostatic discharge unit ESD2 is connected to the third common voltage line COM3 via a bridge pattern 191 located on the second transparent conductive layer T2 .

[0177] Referring to Figure 20, an equivalent circuit diagram of the second electrostatic release unit ESD2 is shown. The second electrostatic release unit ESD2 includes two transistors. The connection relationship between the two transistors is shown in Figure 20. When there is too much electrostatic charge on the scanning lead 13, the two transistors are turned on, thereby transmitting the electrostatic charge on the data line DT to the third common voltage line COM3.

[0178] In some embodiments, as shown in FIG21 , the non-display area NA further includes a third fan-out area FAN3, including a first data fan-out line 121 and a second data fan-out line 122, located on a different side of the display area AA from the first fan-out area FAN1. The first metal layer M1 further includes a fourth common voltage line COM4, ​​connected to the first common voltage line COM1, located on the same side of the display area AA as the third fan-out area FAN3. In an orthographic projection onto the base substrate 11, the fourth common voltage line COM4 overlaps with both the first data fan-out line 121 and the second data fan-out line 122 located in the third fan-out area FAN3.

[0179] Since the fourth common voltage line COM4 overlaps the third fan-out area FAN3 , disposing the fourth common voltage line COM4 in the first metal layer M1 can prevent a short circuit between the fourth common voltage line COM4 and the data fan-out line 12 that cross each other.

[0180] Exemplarily, the fourth common voltage line COM4 is connected to the first common voltage line COM1 via a bridge pattern located in the second transparent conductive layer T2 .

[0181] Exemplarily, as shown in FIG. 1 or FIG. 6 , the third fan-out area FAN3 is disposed between the bonding area BD and the display area AA.

[0182] In some embodiments, as shown in FIG. 1 , the display area AA includes a plurality of sub-pixels PX arranged along a row direction f1 and a column direction f2 .

[0183] In some embodiments, as shown in FIG22 , the data fan-out line 12 includes a first extension segment 221, a second extension segment 222, and a third extension segment 223, which are sequentially connected. The first extension segment 221 and the third extension segment 223 extend along the column direction f2. The first extension segment 221 is connected between the data line DT and the second extension segment 222. The extension direction of the second extension segment 222 is different from both the row direction f1 and the column direction f2. The line width of the first extension segment 221 is greater than or equal to the line width of the second extension segment 222, and the line width of the third extension segment 223 is greater than or equal to the line width of the first extension segment 221. By increasing the line width of the third extension segment 223, the resistance of the data fan-out line 12 is reduced.

[0184] In some embodiments, as shown in FIG22 , in an orthographic projection on the base substrate 11, two adjacent first extension segments 221 are disposed in different layers and have a first gap d1, two adjacent second extension segments 222 are disposed in different layers and overlap, align, or have a second gap, and two adjacent third extension segments 223 are disposed in different layers and have a third gap d3. Furthermore, the first gap d1 is approximately equal to at least one times the arrangement period of the sub-pixels PX along the row direction f1, the first gap d1 is greater than or equal to the third gap d3, and the third gap d3 is greater than or equal to the second gap.

[0185] In FIG. 22 , the first gap d1 is substantially equal to twice the arrangement period of the sub-pixels PX along the row direction f1 .

[0186] In some embodiments, as shown in FIG23 , the second metal layer M2 further includes a first data terminal 231 located in the non-display area NA and connected to an end of the first data fan-out line 121 away from the display area AA. The third metal layer M3 further includes a second data terminal 232 located in the non-display area NA and connected to an end of the second data fan-out line 122 away from the display area AA.

[0187] For example, as shown in FIG23 , the orthographic projection of the second transparent conductive layer T2 on the base substrate 11 covers the orthographic projections of the first data terminal 231 and the second data terminal 232 on the base substrate 11, thereby protecting the first data terminal 231 and the second data terminal 232. In addition, the second transparent conductive layer T2 is connected to the first data terminal 231 and the second data terminal 232 through vias.

[0188] The first data fan-out line 121 is connected between the first data terminal 231 and the data line DT, and the second data fan-out line 122 is connected between the second data terminal 232 and the data line DT. The first data terminal 231 and the second data terminal 232 are both located in the bonding area BD. The bonding area BD may also include a scan terminal. The scan fan-out line 11 is connected between the scan line SC and the scan terminal.

[0189] In some embodiments, as shown in FIG8 , the display area AA includes a plurality of sub-pixels PX, and the sub-pixels PX include a common electrode 81 and a pixel electrode 82. The common electrode 81 is located in the first transparent conductive layer T1, and the pixel electrode 82 is located in the second transparent conductive layer T2. The common electrodes 81 of the plurality of sub-pixels PX are interconnected, and the pixel electrodes 82 of different sub-pixels PX are separated from each other.

[0190] Exemplarily, the first metal layer M1 , the second metal layer M2 , the third metal layer M3 , the first transparent conductive layer T1 and the second transparent conductive layer T2 are stacked in sequence, and the first metal layer M1 is disposed close to the base substrate 11 .

[0191] The display substrate 01 provided in this example can be prepared according to the following process: first metal layer M1 → gate insulating layer → active layer → second metal layer M2 → first passivation layer → third metal layer M3 → first transparent conductive layer T1 → second passivation layer → second transparent conductive layer T2.

[0192] In order to prevent the etching solution of the first transparent conductive layer T1 from corroding the material of the third metal layer M3, illustratively, the first metal layer M1, the second metal layer M2, the first transparent conductive layer T1, the third metal layer M3 and the second transparent conductive layer T2 are stacked in sequence, and the first metal layer M1 is arranged close to the base substrate 11.

[0193] The display substrate 01 provided in this example can be prepared according to the following process: first metal layer M1 → gate insulating layer → active layer → second metal layer M2 → first passivation layer → first transparent conductive layer T1 → third metal layer M3 → second passivation layer → second transparent conductive layer T2.

[0194] In some embodiments, the first metal layer M1 and the second metal layer M2 are made of the same material. Thus, the scan fan-out lines 11 disposed on different layers can be designed to have the same line width, thereby reducing resistance differences between the scan fan-out lines 11 disposed on different layers and preventing horizontal streaks. If the first metal layer M1 and the second metal layer M2 are made of different materials, the line widths of the scan fan-out lines 11 disposed on different layers need to be compensated to reduce resistance differences between the scan fan-out lines 11 disposed on different layers and prevent horizontal streaks.

[0195] In some embodiments, the second metal layer M2 and the third metal layer M3 are made of the same material. Thus, the data fan-out lines 12 disposed in different layers can be designed to have the same line width, thereby reducing resistance differences between the data fan-out lines 12 disposed in different layers and preventing horizontal streaks. If the second metal layer M2 and the third metal layer M3 are made of different materials, the line widths of the data fan-out lines 12 disposed in different layers need to be compensated to reduce resistance differences between the data fan-out lines 12 disposed in different layers and prevent horizontal streaks.

[0196] In some embodiments, in the orthographic projection on the base substrate 11 , the pattern AAW tangent to the edge of the display area AA is a trapezoid or an inverted trapezoid.

[0197] For example, as shown in FIG1 , in the orthographic projection on the base substrate 11 , the figure AAW tangent to the edge of the display area AA is an inverted trapezoid (such as the dotted box in FIG1 ). In FIG1 , the four corners of the display area AA are designed as arcs, and the figure tangent to the edge of the display substrate 01 is also an inverted trapezoid.

[0198] For example, as shown in FIG5 , in the orthographic projection on the base substrate 11, the figure AAW tangent to the edge of the display area AA is a trapezoid (such as the dotted box in FIG5 ). In FIG5 , the four corners of the display area AA are designed as arcs, and the figure tangent to the edge of the display substrate 01 is also a trapezoid.

[0199] Exemplarily, as shown in FIG24 , in the orthographic projection on the base substrate 11 , the figure AAW circumscribed to the edge of the display area AA is a trapezoid (such as the dotted box in FIG24 ), and in FIG24 , the lower left corner and the lower right corner of the display area AA are right angles.

[0200] Exemplarily, the scan fan-out lines 11 connecting the odd-numbered scan lines SC and the scan fan-out lines 11 connecting the even-numbered scan lines SC are located on opposite sides of the display area AA. The scan fan-out lines 11 located on the same side of the display area AA include alternating first scan fan-out lines 111 and second scan fan-out lines 112. For example, the scan fan-out lines 11 connecting the odd-numbered scan lines SC are located on the left side of the display area AA, and the scan fan-out lines 11 connecting the even-numbered scan lines SC are located on the right side of the display area AA. The scan fan-out lines 11 located on the left side include alternating first scan fan-out lines 111 and second scan fan-out lines 112, and the scan fan-out lines 11 located on the right side include alternating first scan fan-out lines 111 and second scan fan-out lines 112.

[0201] The present disclosure provides a display substrate 01, as shown in FIG1 . The display substrate 01 includes a base substrate 11 (not shown in FIG1 ), and a display area AA and a non-display area NA disposed on one side of the base substrate 11. The display area AA includes scan lines SC extending along a row direction f1 and data lines DT extending along a column direction f2. The scan lines SC are located in a first metal layer M1, and the data lines DT are located in a second metal layer M2.

[0202] FIG2 shows a circuit layout diagram at the dotted line frame B1 in FIG1. ​​FIG3 B2 shows a partial enlarged view of the dotted line frame B2 in FIG2, and FIG3 B3 shows a partial enlarged view of the dotted line frame B3 in FIG2.

[0203] As shown in Figures 2 and 3, the non-display area NA includes: a scan fan-out line 11, which is connected to the scan line SC, including a first scan fan-out line 111 and a second scan fan-out line 112, the first scan fan-out line 111 is located in the first metal layer M1, and the second scan fan-out line 112 is located in the third metal layer M3; and a data fan-out line 12, which is connected to the data line DT, including a first data fan-out line 121 and a second data fan-out line 122, the first data fan-out line 121 is located in the second metal layer M2, the second data fan-out line 122 is located in the first metal layer M1, and the second data fan-out line 122 and the first scan fan-out line 111 have no overlapping orthographic projections on the base substrate 11.

[0204] Referring to Figure 25 , there is shown another cross-sectional structural diagram along the lines AA′ and BB′ in Figure 3 . As shown in Figure 25 , the first metal layer M1 , the second metal layer M2 and the third metal layer M3 are three stacked film layers.

[0205] In the display substrate 01 provided by the present disclosure, the scanning fan-out line 11 is double-layered in the first metal layer M1 and the third metal layer M3, and the data fan-out line 12 is double-layered in the first metal layer M1 and the second metal layer M2. This not only realizes a narrow frame, but also avoids a short circuit between the scanning fan-out line 11 and the data fan-out line 12, so that the data fan-out line 12 and the scanning fan-out line 11 can be located on the same side of the display area AA, which is conducive to the realization of an irregular display substrate 01 design.

[0206] The present disclosure provides a display device, comprising: a display substrate provided in any embodiment; and a driving circuit, respectively connected to a scan fan-out line and a data fan-out line in the display substrate, for driving the display substrate to perform display.

[0207] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate.

[0208] The display device provided herein may be any product or component with a display function, such as a display panel, display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted display device, smartwatch, fitness wristband, personal digital assistant, etc. The display panel may be, for example, a liquid crystal display panel.

[0209] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0210] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0211] As used herein, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0212] References herein to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0213] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0214] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0215] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0216] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0217] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0218] The use of "for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0219] The use of "based on" or "according to" in this document is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0220] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0221] As used herein, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute equality and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0222] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0223] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0224] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate, comprising: a substrate, and a display area and a non-display area disposed on one side of the substrate; the display area includes: scan lines extending in the row direction, and data lines extending in the column direction, the scan lines are located in a first metal layer, and the data lines are located in a second metal layer; the non-display area includes: scan fan-out lines, connected to the scan lines, including a first scan fan-out line and a second scan fan-out line, the first scan fan-out line is located in the first metal layer, and the second scan fan-out line is located in the second metal layer; data fan-out lines, connected to the data lines, including a first data fan-out line and a second data fan-out line, the first data fan-out line is located in the second metal layer, the second data fan-out line is located in a third metal layer, and the first data fan-out line and the second scan fan-out line do not overlap in the orthographic projection on the substrate.

2. The display substrate according to claim 1, wherein The non-display area further includes: a first fan-out area, including the first data fan-out line and the second data fan-out line; and a second fan-out area, including the first scan fan-out line and the second scan fan-out line, located on the same side of the display area as the first fan-out area, and the second fan-out area is located on the side of the first fan-out area away from the display area.

3. The display substrate according to claim 2, wherein, The display area includes a plurality of sub-pixels, the sub-pixels include a common electrode, the common electrode is located in a first conductive layer, and the common electrodes of the plurality of sub-pixels are interconnected; the second metal layer further includes: a first common voltage line, located between the first fan-out area and the second fan-out area, and connected to the common electrode.

4. The display substrate according to claim 3, wherein, The first fan-out area and the second fan-out area are arranged in the row direction, and the first metal layer further includes: scan leads, extending in the row direction in the non-display area, penetrating the first fan-out area and the first common voltage line in the row direction, and connected between the scan line and the first scan fan-out line or the second scan fan-out line.

5. The display substrate according to claim 4, wherein, The non-display area further includes: a first electrostatic discharge unit, disposed between the first common voltage line and the second fan-out area, connected to the scan lead and the first common voltage line respectively, for transmitting the electrostatic charge on the scan lead to the first common voltage line.

6. The display substrate according to claim 3, wherein, The first transparent conductive layer further includes: a first connection pattern, located in the non-display area, and connected to the common electrode; the sub-pixel further includes a pixel electrode, the pixel electrode is located in a second transparent conductive layer, and the pixel electrodes of different sub-pixels are separated from each other, and the second transparent conductive layer further includes: a common transfer pattern, located in the non-display area, separated from the pixel electrode, connected to the first common voltage line through a first via, and connected to the first connection pattern through a second via.

7. The display substrate according to claim 6, wherein, The second metal layer further includes: a second common voltage line, extending in the column direction, located between two adjacent data lines; and a second connection pattern, located in the non-display area, connected to the second common voltage line, and further connected to the common transfer pattern through a third via.

8. The display substrate according to claim 7, wherein The second vias are located on a side of the third vias close to the display area, and a boundary of the first connection pattern away from the display area is located on a side of the third vias close to the display area.

9. The display substrate according to claim 7, wherein, The number of the second vias is greater than or equal to the number of the third vias.

10. The display substrate according to claim 6, wherein, The first connection pattern includes: a first sub-pattern and a second sub-pattern which are separated from each other and arranged in a row direction, a size of the first sub-pattern in a column direction is smaller than a size of the second sub-pattern in the column direction, and the number of the second vias connecting the first sub-pattern is smaller than the number of the second vias connecting the second sub-pattern.

11. The display substrate according to claim 6, wherein, The second metal layer further includes: a third connection pattern, located in the non-display area and connected to one end of the data line close to the second data fan-out line; The third metal layer further includes: a fourth connection pattern, located in the non-display area and connected to one end of the second data fan-out line close to the data line; The second transparent conductive layer further includes: a data transfer pattern, connected to the third connection pattern through a fourth via and connected to the fourth connection pattern through a fifth via, the fourth via is located on a side of the fifth via close to the display area, and a boundary of the fourth connection pattern close to the display area is located on a side of the fourth via away from the display area.

12. The display substrate according to claim 11, wherein, The number of the fourth vias is equal to the number of the fifth vias.

13. The display substrate according to claim 6, wherein The first metal layer further includes: a scan lead, located in the non-display area and connected between the scan line and the second scan fan-out line; and a fifth connection pattern, located in the non-display area and connected to one end of the scan lead close to the second scan fan-out line; The second metal layer further includes: a sixth connection pattern, located in the non-display area and connected to one end of the second scan fan-out line close to the fifth connection pattern; The second transparent conductive layer further includes: a scan transfer pattern, respectively connected to the fifth connection pattern and the sixth connection pattern through vias.

14. The display substrate according to claim 6, wherein, The non-display area further includes: a bonding area, including a plurality of scan terminals, and the scan terminals are connected to the scan line; and a compensation capacitor, located on a side of the display area away from the bonding area, including a first electrode plate and a second electrode plate arranged oppositely, the first electrode plate is located in the second metal layer, and the second electrode plate is located in the first transparent conductive layer; The second metal layer further includes: a third common voltage line, located between the compensation capacitor and the display area and connected to the second electrode plate; and a seventh connection pattern, connected to the first electrode plate; The second transparent conductive layer further includes: a capacitor transfer pattern, respectively connected to the seventh connection pattern and the scan fan-out line through vias.

15. The display substrate according to claim 14, wherein, In a front projection on the substrate, the first electrode plate extends in a bow shape, and there is a gap between the relatively arranged seventh connection pattern and the scan fan-out line.

16. The display substrate according to claim 3, wherein, The non-display area further includes: a third fan-out area, including the first data fan-out line and the second data fan-out line, and is located on a different side of the display area from the first fan-out area; The first metal layer further includes: a fourth common voltage line, connected to the first common voltage line, located on the same side of the display area as the third fan-out area, and in a front projection on the substrate, the fourth common voltage line overlaps both the first data fan-out line and the second data fan-out line located in the third fan-out area.

17. The display substrate according to claim 1, wherein, The display area includes a plurality of sub-pixels arranged in a row direction and a column direction; The data fan-out line includes: a first extension section, a second extension section, and a third extension section connected in sequence. The first extension section and the third extension section extend in the column direction. The first extension section is connected between the data line and the second extension section. The extension direction of the second extension section is different from both the row direction and the column direction, and the line width of the first extension section is greater than or equal to the line width of the second extension section, and the line width of the third extension section is greater than or equal to the line width of the first extension section.

18. The display substrate according to claim 17, wherein, In a front projection on the substrate, two adjacent first extension sections are arranged in different layers and have a first gap. Two adjacent second extension sections are arranged in different layers and overlap, are flush with each other, or have a second gap. Two adjacent third extension sections are arranged in different layers and have a third gap; and The first gap is approximately equal to at least one time the arrangement period of the sub-pixels in the row direction. The first gap is greater than or equal to the third gap, and the third gap is greater than or equal to the second gap.

19. The display substrate according to claim 1, wherein The second metal layer further includes: A first data terminal, located in the non-display area, connected to one end of the first data fan-out line away from the display area; The third metal layer further includes: A second data terminal, located in the non-display area, connected to one end of the second data fan-out line away from the display area.

20. The display substrate according to claim 1, wherein, The display area includes a plurality of sub-pixels. The sub-pixels include a common electrode and a pixel electrode. The common electrode is located in a first conductive layer, and the pixel electrode is located in a second transparent conductive layer. The common electrodes of the plurality of sub-pixels are interconnected, and the pixel electrodes of different sub-pixels are separated from each other; The first metal layer, the second metal layer, the third metal layer, the first transparent conductive layer, and the second transparent conductive layer are stacked in sequence, and the first metal layer is disposed close to the substrate; or The first metal layer, the second metal layer, the first transparent conductive layer, the third metal layer, and the second transparent conductive layer are stacked in sequence, and the first metal layer is disposed close to the substrate.

21. The display substrate according to claim 1, wherein, The first metal layer, the second metal layer, and the third metal layer are made of the same material.

22. The display substrate according to claim 1, wherein, In a front projection on the substrate, the first scan fan-out line and the second scan fan-out line are alternately arranged in sequence, and the first data fan-out line and the second data fan-out line are alternately arranged in sequence.

23. The display substrate according to claim 1, wherein In a front projection on the substrate, the figure tangent to the edge of the display area is a trapezoid or an inverted trapezoid.

24. A display substrate, including: A substrate, and a display area and a non-display area provided on one side of the substrate; The display area includes: scan lines extending in the row direction and data lines extending in the column direction, the scan lines being located in the first metal layer and the data lines being located in the second metal layer; The non-display area includes: Scan fan-out lines, connected to the scan lines, including a first scan fan-out line and a second scan fan-out line, the first scan fan-out line being located in the first metal layer and the second scan fan-out line being located in the third metal layer; Data fan-out lines, connected to the data lines, including a first data fan-out line and a second data fan-out line, the first data fan-out line being located in the second metal layer and the second data fan-out line being located in the first metal layer, and the orthographic projections of the second data fan-out line and the first scan fan-out line on the substrate have no overlap.

25. A display device, comprising: The display substrate according to any one of claims 1 to 24; And A driving circuit, respectively connected to the scan fan-out lines and the data fan-out lines in the display substrate, for driving the display substrate to display.

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