Display substrate and display apparatus

Abstract

A display substrate and a display apparatus, relating to the technical field of display. The display substrate comprises a display region and a gate driving circuit located on at least one side of the display region. The display region comprises a plurality of scan lines extending along a row direction and a plurality of sub-pixels arranged in an array along the row direction and a column direction, at least one scan line being provided between every two adjacent rows of sub-pixels. The gate driving circuit located on the same side of the display region comprises a plurality of shift registers which are cascaded with each other, the shift registers being connected to the scan lines, and at least two shift registers connected to different scan lines being located in the same row.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] As costs decrease and appearance requirements improve, more and more display substrates use gate on array (GOA) row drivers.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising a display area, and a gate driving circuit located on at least one side of the display area;

[0005] The display area includes a plurality of scan lines extending along the row direction, and a plurality of sub-pixels arranged in an array along the row direction and the column direction, and at least one scan line is provided between two adjacent rows of sub-pixels;

[0006] The gate driving circuits located on the same side of the display area include a plurality of shift registers cascaded with each other. The shift registers are connected to the scan lines, and at least two shift registers connected to different scan lines are located in the same row.

[0007] In some embodiments, the plurality of shift registers include a first shift register and a second shift register arranged in the same row, and the first shift register and the second shift register are respectively connected to different scan lines;

[0008] The first shift register and the second shift register are translationally symmetric along the row direction, or the first shift register and the second shift register are mirror-symmetric about a first axis, and the first axis extends along the column direction.

[0009] In some embodiments, the plurality of shift registers include a first register column and a second register column arranged along a row direction, and the first register column and the second register column both include a plurality of shift registers arranged along a column direction;

[0010] The shift registers in the first register column are connected to the first signal line group, and the shift registers in the second register column are connected to the second signal line group. The first signal line group and the second signal line group each include at least one signal line, and the signal lines in the first signal line group and the signal lines in the second signal line group are not shared.

[0011] In some embodiments, in the row direction, the first register column and the second register column are translationally symmetrical, the first signal line group and the second signal line group are translationally symmetrical, and the translation distance of the first register column relative to the second register column is approximately equal to the translation distance of the first signal line group relative to the second signal line group.

[0012] In some embodiments, the plurality of shift registers include a third register column and a fourth register column arranged in a row direction and adjacent to each other, and the third register column and the fourth register column each include a plurality of shift registers arranged in a column direction;

[0013] The shift registers in the third register column are connected to a third signal line group, and the shift registers in the fourth register column are connected to a fourth signal line group. The third signal line group and the fourth signal line group both include a first signal line and share the first signal line.

[0014] In some implementations, the first signal line is located between the third register column and the fourth register column.

[0015] In some embodiments, the first signal line includes at least one of the following: a clock signal line, a gate-on signal line, and a first gate-off signal line, wherein the gate-on signal line is used to provide a gate-on voltage, and the gate-on voltage is used to turn on the thin film transistor of the sub-pixel, and the first gate-off signal line is used to provide a gate-off voltage, and the gate-off voltage is used to turn off the thin film transistor of the sub-pixel.

[0016] In some embodiments, the third register column and the fourth register column are mirror-symmetrical about a second axis, and the second axis extends along a column direction.

[0017] In some embodiments, the third signal line group further includes: a second signal line located on a side of the third register column away from the fourth register column, and / or located between the third register column and the first signal line;

[0018] The fourth signal line group further includes: a third signal line located on a side of the fourth register column away from the third register column, and / or located between the fourth register column and the first signal line.

[0019] In some embodiments, the second signal line and the third signal line are mirror-symmetrical about a third axis, and the third axis extends along a column direction.

[0020] In some embodiments, the second signal line and the third signal line each independently include at least one of the following: a gate-on signal line, a first gate-off signal line, a frame start signal line, a first noise reduction voltage signal line, a second noise reduction voltage signal line, an initialization signal line, a second gate-off signal line, and a low gate-off signal line;

[0021] Among them, the gate-on signal line is used to provide a gate-on voltage, and the gate-on voltage is used to turn on the thin film transistor of the sub-pixel; the first gate-off signal line and the second gate-off signal line are both used to provide a gate-off voltage, and the gate-off voltage is used to turn off the thin film transistor of the sub-pixel; the low gate-off signal line is used to provide a low gate-off voltage, and the low gate-off voltage is less than the gate-off voltage.

[0022] In some embodiments, the plurality of shift registers include a third shift register and a fourth shift register, the output end of the third shift register is connected to the input end of the fourth shift register, and the third shift register and the fourth shift register are located in the same column.

[0023] In some embodiments, the plurality of shift registers are arranged in a zigzag pattern or a bow pattern in a cascade sequence.

[0024] In some embodiments, the number of shift registers connected to different scan lines and located in the same row is 2, and the shift registers of odd stages are located in the same column, and the shift registers of even stages are located in the same column.

[0025] In some embodiments, the gate driving circuit is further connected to a plurality of clock signal lines, and the plurality of clock signal lines are used to transmit M clock signals with different timings;

[0026] The number of shift registers connected to different scan lines and located in the same row is N, M is greater than N, and M is divisible by N, and both M and N are positive integers.

[0027] In some embodiments, the number of shift registers connected to different scan lines and located in the same row is greater than or equal to 2 and less than or equal to 4.

[0028] In some embodiments, the number of shift registers connected to different scan lines and located in the same row is N, and in the column direction, the arrangement period of the shift registers is substantially equal to N times the arrangement period of the sub-pixels.

[0029] In some embodiments, in the column direction, a scan line and a row of sub-pixels are alternately arranged in sequence, and the distance between two adjacent scan lines is substantially equal to the arrangement period of the sub-pixels along the column direction.

[0030] In some embodiments, the plurality of shift registers include a first shift register and a second shift register arranged in the same row, the first shift register is located on a side of the second shift register away from the display area, at least one clock signal line extending along a column direction is further provided between the first shift register and the second shift register, and the first shift register and the second shift register are respectively connected to different scan lines;

[0031] The first shift register is connected to the scan line via a remote lead, the remote lead includes a first line segment and a second line segment, the first shift register, the first line segment, the second line segment and the scan line are connected in sequence, and the first line segment and the clock signal line are arranged in different layers and intersect with each other;

[0032] The two adjacent remote leads are a first remote lead and a second remote lead, and the distance between the first line segment of the first remote lead and the first line segment of the second remote lead is smaller than the distance between the second line segment of the first remote lead and the second line segment of the second remote lead.

[0033] In some embodiments, the second shift register is connected to the scan line via a short-range lead, and two adjacent short-range leads are a first short-range lead and a second short-range lead;

[0034] The second line segment of the first remote lead, the first short-range lead, the second line segment of the second remote lead, and the second short-range lead all extend along the row direction and are arranged sequentially along the column direction. The spacing between the second line segment of the first remote lead and the first short-range lead, and the spacing between the second line segment of the second remote lead and the second short-range lead are both smaller than the spacing between the first short-range lead and the second line segment of the second remote lead.

[0035] In some embodiments, the short-range lead is connected to a reverse extension line, the reverse extension line is located on a side of the short-range lead away from the display area, and the reverse extension line and the short-range lead are arranged in different layers, and the short-range lead and the long-range lead are arranged in the same layer;

[0036] In the orthographic projection on the plane where the display substrate is located, the second line segment of the first remote lead overlaps with the reverse extension line connecting the first proximal lead, and the second line segment of the second remote lead overlaps with the reverse extension line connecting the second proximal lead.

[0037] In some embodiments, the second shift register is connected to the scan line via a short-range lead, and two adjacent short-range leads are a first short-range lead and a second short-range lead;

[0038] The second line segment of the first remote lead, the first proximal lead, the second proximal lead and the second line segment of the second remote lead all extend along the row direction and are arranged sequentially along the column direction. The spacing between the second line segment of the first remote lead and the first proximal lead, as well as the spacing between the second proximal lead and the second line segment of the second remote lead, are both smaller than the spacing between the first proximal lead and the second proximal lead.

[0039] In some embodiments, the shift register is connected to a clock signal line, which is further connected to multiple clock patterns. The multiple clock patterns are separated from each other along the column direction, and the clock signal line and the clock pattern are arranged in different layers and connected through a first via.

[0040] In some embodiments, the clock signal line includes a first sub-clock signal line and a second sub-clock signal line adjacent to each other, and the first sub-clock signal line and the second sub-clock signal line are connected via a connecting portion;

[0041] The clock pattern includes: a first sub-pattern corresponding to the position of the first sub-clock signal line, a second sub-pattern corresponding to the position of the second sub-clock signal line, and a third sub-pattern corresponding to the position of the connecting portion, the first sub-pattern and the second sub-pattern extend along the column direction, and the third sub-pattern is connected between the first sub-pattern and the second sub-pattern.

[0042] In some embodiments, the display area further includes: a plurality of data lines extending along a column direction;

[0043] The multiple sub-pixels are divided into multiple pixel units, and the pixel unit includes multiple sub-pixels arranged in a column direction. The multiple sub-pixels located in the same pixel unit are connected to the same data line and are respectively connected to different scan lines. The size of the sub-pixel along the row direction is larger than the size of the sub-pixel along the column direction.

[0044] In some embodiments, the display substrate includes two gate driving circuits, and the two gate driving circuits are located on opposite sides of the display area.

[0045] The present disclosure provides a display device, comprising:

[0046] The display substrate according to any one of the embodiments; and

[0047] The source driving circuit is connected to the display substrate and is used to drive the display substrate to perform display.

[0048] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0049] BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0051] FIG1 exemplarily shows a schematic planar structural diagram of a display substrate in the related art;

[0052] FIG2 exemplarily shows a schematic structural diagram of a first display substrate provided by the present disclosure;

[0053] FIG3 exemplarily shows a schematic structural diagram of a second display substrate provided by the present disclosure;

[0054] FIG4 a exemplarily shows a circuit layout diagram of a first gate drive circuit;

[0055] FIG4 b exemplarily shows a circuit layout diagram of a column of shift registers in the first gate driving circuit;

[0056] FIG4 c exemplarily shows a circuit layout diagram of another column of shift registers in the first gate driving circuit;

[0057] FIG4 d exemplarily shows a lead layout diagram of a first gate drive circuit;

[0058] FIG5 a exemplarily shows a circuit layout diagram of a second gate drive circuit;

[0059] FIG5 b exemplarily shows a circuit layout diagram of a column of shift registers in the second gate driving circuit;

[0060] FIG5 c exemplarily shows a circuit layout diagram of another column of shift registers in the second gate driving circuit;

[0061] FIG5 d exemplarily shows a first signal line layout diagram of a second gate driving circuit;

[0062] FIG5e exemplarily shows a lead layout diagram of a second gate drive circuit;

[0063] FIG6 a exemplarily shows a circuit layout diagram of a third gate driving circuit;

[0064] FIG6 b exemplarily shows a first signal line layout diagram of a third gate driving circuit;

[0065] FIG6 c exemplarily shows a clock signal line layout diagram;

[0066] FIG7 exemplarily shows a schematic diagram of a connection structure of a gate drive circuit;

[0067] FIG8 exemplarily shows a schematic diagram of an arrangement structure of multiple shift registers in a gate drive circuit;

[0068] FIG9 exemplarily shows a schematic diagram of an arrangement structure of multiple shift registers in another gate drive circuit;

[0069] FIG10 exemplarily shows a schematic diagram of the connection structure between a clock pattern and a clock signal line.

[0070] Detailed description

[0071] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0072] 1 shows a schematic structural diagram of a display substrate in the related art. 2 and 3 show schematic structural diagrams of a display substrate provided by the present disclosure.

[0073] As shown in Figures 1 to 3, the display substrate includes a display area AA and a gate drive circuit GOA located on at least one side of the display area AA. The display area AA includes multiple scan lines SC extending along the row direction f1 and multiple sub-pixels PX arranged in an array along the row direction f1 and the column direction f2. The gate drive circuit GOA located on the same side of the display area AA includes multiple cascaded shift registers GOA units. The shift registers GOA units are connected to the scan lines SC, with different scan lines SC connected to different shift registers GOA units.

[0074] In the related art shown in FIG1 , multiple shift register GOA units connected to different scan lines SC are arranged along the column direction f2 , only one shift register GOA unit is provided in each row, and the height of the shift register GOA unit in the column direction f2 is approximately the height of a row of sub-pixels PX.

[0075] As shown in FIG2 or FIG3, at least two shift register GOA units connected to different scan lines SC are located in the same row, that is, a plurality of shift register GOA units connected to different scan lines SC are arranged in an array along the row direction f1 and the column direction f2, and at least two shift register GOA units connected to different scan lines SC are arranged in the same row.

[0076] The display substrate provided by the present disclosure arranges multiple shift register GOA units connected to different scan lines SC in the same row, such as two, three, four or more shift register GOA units in one row. In this way, the shift register GOA units can occupy the height of two, three, four or more rows of sub-pixels PX in the column direction f2, thereby increasing the height space of the shift register GOA units in the column direction f2, which is conducive to realizing a display substrate with a small arrangement period of sub-pixels PX.

[0077] Illustratively, the multiple shift register GOA units located on the same side of the display area AA and cascaded with each other include a first-stage shift register GOA unit 1st connected to the first row of sub-pixels PX, a second-stage shift register GOA unit 2nd connected to the second row of sub-pixels PX, a third-stage shift register GOA unit 3rd connected to the third row of sub-pixels PX3, etc. For each shift register GOA unit, the number of stages of the shift register GOA unit is the number of rows of sub-pixels PX connected to the shift register GOA unit.

[0078] Exemplarily, as shown in FIG2 , in the gate driving circuit GOA, two shift registers GOA units connected to different scan lines SC are arranged in parallel in one row, so that the shift register GOA unit can occupy the height of two rows of sub-pixels PX in the column direction f2.

[0079] For example, as shown in FIG3 , in the gate driving circuit GOA, four shift registers GOA units connected to different scan lines SC are arranged in parallel in one row, so that the shift register GOA unit can occupy the height of four rows of sub-pixels PX in the column direction f2.

[0080] For example, for a display substrate with a pixel unit P size of 126.6μm*126.6μm, the height of a row of sub-pixels PX is 42.2μm. In the display substrate shown in FIG1 , since the shift register GOA unit occupies the height of a row of sub-pixels PX in the column direction f2, the height of the shift register GOA unit in the column direction f2 is approximately 42.2μm. Since the height of a thin-film transistor in the column direction f2 is approximately 39μm, the 42.2μm height space is only large enough to accommodate one thin-film transistor, leaving no excess space for the associated signal lines.

[0081] In the display substrate shown in FIG. 2 , since the shift register GOA unit can occupy the height of two rows of sub-pixels PX in the column direction f2, the height of the shift register GOA unit in the column direction f2 is approximately 84.4 μm, which increases the height space of the shift register GOA unit in the column direction f2, facilitating the arrangement of thin film transistors and related signal lines.

[0082] In the display substrate shown in FIG3 , since the shift register GOA unit occupies the height of four rows of sub-pixels PX in the column direction f2, the height of the shift register GOA unit in the column direction f2 is approximately 168.8 μm, which increases the height space of the shift register GOA unit in the column direction f2, facilitating the arrangement of thin film transistors and related signal lines.

[0083] In the present disclosure, the gate driving circuit GOA is used to sequentially provide scanning signals to the scanning lines SC. The scanning signals are, for example, pulse signals.

[0084] In some embodiments, as shown in Figure 2 or Figure 3, at least one scan line SC is provided between two adjacent rows of sub-pixels PX. For example, in Figure 2 and Figure 3, one scan line SC is provided between two adjacent rows of sub-pixels PX.

[0085] In a specific implementation, in order to avoid crosstalk between adjacent sub-pixels PX, a gap is set between two adjacent rows of sub-pixels PX. By setting at least one scan line SC between two adjacent rows of sub-pixels PX, the gap space can be fully utilized, which is conducive to improving the aperture ratio.

[0086] In some embodiments, as shown in Figure 2 or Figure 3, at least one row of sub-pixels PX is disposed between two adjacent scan lines SC. For example, in Figure 2 and Figure 3, at least one row of sub-pixels PX is disposed between two adjacent scan lines SC.

[0087] For example, as shown in FIG2 or FIG3, a scan line SC and a row of sub-pixels PX are arranged alternately in sequence. This helps improve the display uniformity of the display substrate and avoids horizontal stripes caused by the alternating arrangement of multiple scan lines SC and multiple rows of sub-pixels PX.

[0088] In some embodiments, as shown in FIG. 2 or FIG. 3 , in the column direction f2 , the distance between two adjacent scan lines SC is substantially equal to the arrangement period of the sub-pixels PX along the column direction f2 .

[0089] In some embodiments, as shown in FIG. 4a , FIG. 5a or FIG. 6a , the plurality of shift registers GOA unit include a first shift register GOA unit1 and a second shift register GOA unit2 arranged in the same row, and the first shift register GOA unit1 and the second shift register GOA unit2 are respectively connected to different scan lines SC.

[0090] The first shift register GOA unit 1 and the second shift register GOA unit 2 may be any two shift registers GOA units located in the same row. For example, the first shift register GOA unit 1 is a first-stage shift register GOA unit 1st, and the second shift register GOA unit 2 is a second-stage shift register GOA unit 2nd, as shown in FIG4a, FIG5a, or FIG6a.

[0091] For another example, as shown in FIG4a, FIG5a, or FIG6a, the first shift register GOA unit1 is the third-stage shift register GOA unit 3rd, and the second shift register GOA unit2 is the fourth-stage shift register GOA unit 4th. For another example, the first shift register GOA unit1 is the fifth-stage shift register GOA unit 5th, and the second shift register GOA unit2 is the sixth-stage shift register GOA unit 6th. For another example, the first shift register GOA unit1 is the seventh-stage shift register GOA unit 7th, and the second shift register GOA unit2 is the eighth-stage shift register GOA unit 8th.

[0092] 4a , the first shift register GOA unit1 and the second shift register GOA unit2 are symmetrically shifted along the row direction f1 , that is, the first shift register GOA unit1 can at least partially overlap with the second shift register GOA unit2 after being shifted a certain distance along the row direction f1 .

[0093] For example, as shown in FIG5a or FIG6a, the first shift register GOA unit1 and the second shift register GOA unit2 are mirror-symmetric about a first axis, and the first axis extends along the column direction f2. That is, after the first shift register GOA unit1 is rotated 180° about the first axis, it can at least partially overlap with the second shift register GOA unit2.

[0094] In some embodiments, as shown in FIG4 a , the plurality of shift register GOA units include a first register column 41 and a second register column 42 arranged along a row direction f1. The first register column 41 and the second register column 42 each include a plurality of shift register GOA units arranged along a column direction f2. The shift register GOA units in the first register column 41 and the shift register GOA units in the second register column 42 are connected to different scan lines SC, respectively.

[0095] As shown in Figure 4a, the shift register GOA unit in the first register column 41 is connected to the first signal line group 43, and the shift register GOA unit in the second register column 42 is connected to the second signal line group 44. The first signal line group 43 and the second signal line group 44 each include at least one signal line, and the signal lines in the first signal line group 43 and the signal lines in the second signal line group 44 are not shared.

[0096] That is, as shown in FIG. 4 a , the signal lines in the second signal line group 44 are not connected to the shift register GOA unit in the first register column 41 , and the signal lines in the first signal line group 43 are not connected to the shift register GOA unit in the second register column 42 .

[0097] In some embodiments, as shown in FIG4 a , in the row direction f1, the first register column 41 and the second register column 42 are translationally symmetrical, the first signal line group 43 and the second signal line group 44 are translationally symmetrical, and the translation distance of the first register column 41 relative to the second register column 42 is approximately equal to the translation distance of the first signal line group 43 relative to the second signal line group 44.

[0098] Exemplarily, a translation distance of the first register column 41 relative to the second shift register GOA unit 2 is a first distance, and a translation distance of the first signal line group 43 relative to the second signal line group 44 is also the first distance.

[0099] Exemplarily, the first signal line group 43 and the second signal line group 44 each independently include at least one of the following signal lines: a clock signal line CLK, a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL.

[0100] Exemplarily, the gate-on signal line VGH is used to provide a gate-on voltage, which is used to turn on the thin film transistor of the sub-pixel PX. The first gate-off signal line VGL1 and the second gate-off signal line VGL2 are both used to provide a gate-off voltage, which is used to turn off the thin film transistor of the sub-pixel PX. The low gate-off signal line LVGL is used to provide a low gate-off voltage, which is lower than the gate-off voltage. The first gate-off signal line VGL1 and the second gate-off signal line VGL2 can be connected to the same signal input terminal.

[0101] In some embodiments, as shown in FIG. 4 a , the signal lines in the first signal line group 43 may be located on a side of the first register column 41 away from the second register column 42 and / or on a side close to the second register column 42 .

[0102] As shown in FIG4 b , the first signal line group 43 includes a plurality of clock signal lines CLK, a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL. The first signal line group 43 is divided into a first group 43 - 1 and a second group 43 - 2. The first group 43 - 1 includes the frame start signal line STV, the first noise reduction voltage signal line VDDE, the second noise reduction voltage signal line VDDO, the initialization signal line INIT, the second gate-off signal line VGL2, and the low gate-off signal line LVGL, arranged sequentially along the row direction f1. The group is located on the side of the first register bank 41 away from the second register bank 42. The second group 43 - 2 includes a gate-on signal line VGH, a first gate-off signal line VGL1 and a plurality of clock signal lines CLK sequentially arranged along the row direction f1 , and is located on a side of the first register column 41 close to the second register column 42 .

[0103] In some embodiments, as shown in FIG. 4 a , the signal lines in the second signal line group 44 may be located on a side of the second register column 42 away from the first register column 41 and / or on a side close to the first register column 41 .

[0104] As shown in FIG4 c , the second signal line group 44 includes a plurality of clock signal lines CLK, a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL. The second signal line group 44 is divided into a third group 44 - 1 and a fourth group 44 - 2. The third group 44 - 1 includes the frame start signal line STV, the first noise reduction voltage signal line VDDE, the second noise reduction voltage signal line VDDO, the initialization signal line INIT, the second gate-off signal line VGL2, and the low gate-off signal line LVGL, arranged sequentially along the row direction f1. The third group 44 - 1 is located on the side of the second register bank 42 that is closer to the first register bank 41. The fourth group 44 - 2 includes a gate-on signal line VGH, a first gate-off signal line VGL1 , and a plurality of clock signal lines CLK sequentially arranged along the row direction f1 , and is located on a side of the second register column 42 away from the first register column 41 .

[0105] In a specific implementation, the first register column 41 and the second register column 42 may also be mirror-symmetrical, and the first signal line group 43 and the second signal line group 44 may also be mirror-symmetrical, which is not limited in the present disclosure.

[0106] In the display substrate shown in Figure 4a, since the positions of the clock signal line CLK in the first signal line group 43 and the clock signal line CLK in the second signal line group 44 are different, the surrounding environment of the clock signal line CLK (such as the situation where the clock signal line CLK is covered with a sealing glue and a light-shielding layer) is quite different, resulting in a large load difference between the clock signal line CLK in the first signal line group 43 and the clock signal line CLK in the second signal line group 44.

[0107] To address the large load difference, in some embodiments, as shown in FIG5a or FIG6a, the plurality of shift register GOA units include a third register column 51 and a fourth register column 52 arranged adjacent to each other along the row direction f1. The third register column 51 and the fourth register column 52 each include a plurality of shift register GOA units arranged along the column direction f2. The shift register GOA units in the third register column 51 and the shift register GOA units in the fourth register column 52 are connected to different scan lines SC, respectively.

[0108] As shown in Figure 5a or Figure 6a, the shift register GOA unit in the third register column 51 is connected to the third signal line group 53, and the shift register GOA unit in the fourth register column 52 is connected to the fourth signal line group 54. The third signal line group 53 and the fourth signal line group 54 both include a first signal line 55 and share the first signal line 55.

[0109] As shown in Figure 5a or Figure 6a, the first signal line 55 is connected not only to the shift register GOA unit in the third register column 51, but also to the shift register GOA unit in the fourth register column 52. By sharing the first signal line 55, the wiring space occupied by the signal line can be reduced, which is conducive to reducing the frame.

[0110] In some embodiments, as shown in FIG. 5 a or FIG. 6 a , the first signal line 55 is located between the third register column 51 and the fourth register column 52 .

[0111] Since the first signal line 55 is connected to the shift register GOA units in both the third register bank 51 and the fourth register bank 52 , the wiring length and difficulty can be simplified by arranging the first signal line 55 between the third register bank 51 and the fourth register bank 52 .

[0112] In some embodiments, the first signal line 55 includes at least one of the following: a clock signal line CLK, a gate-on signal line VGH, and a first gate-off signal line VGL1.

[0113] For example, as shown in FIG5 a , the first signal line 55 includes a plurality of clock signal lines CLK, and the plurality of clock signal lines CLK are located between the third register column 51 and the fourth register column 52. In FIG5 a , the gate-on signal line VGH and the first gate-off signal line VGL1 connected to the third register column 51 are located between the third register column 51 and the first signal line 55; and the gate-on signal line VGH and the first gate-off signal line VGL1 connected to the fourth register column 52 are located between the fourth register column 52 and the first signal line 55.

[0114] For example, as shown in FIG6 a , the first signal lines 55 include a plurality of clock signal lines CLK, a gate-on signal line VGH, and a first gate-off signal line VGL1. These first signal lines 55 are located between the third register column 51 and the fourth register column 52. The gate-on signal line VGH and the first gate-off signal line VGL1 can be located on one side or both sides of the plurality of clock signal lines CLK. In FIG6 a , the gate-on signal line VGH and the first gate-off signal line VGL1 are located on the side of the plurality of clock signal lines CLK closer to the third register column 51. Of course, the gate-on signal line VGH and the first gate-off signal line VGL1 can also be located on the side of the plurality of clock signal lines CLK closer to the fourth register column 52, but this disclosure is not limited thereto.

[0115] Exemplarily, as shown in FIG6 a , the shift register GOA unit in the third register column 51 and the shift register GOA unit in the fourth register column 52 are connected to the same gate-on signal line VGH and the same first gate-off signal line VGL1 .

[0116] When the first signal line 55 includes a clock signal line CLK, the surrounding environments of the clock signal line CLK connected to the third register column 51 and the clock signal line CLK connected to the fourth register column 52 are consistent, thereby reducing the load difference between the clock signal line CLK connected to the third register column 51 and the clock signal line CLK connected to the fourth register column 52, thereby improving the display effect.

[0117] Furthermore, when the first signal line 55 includes the clock signal line CLK, the gate-on signal line VGH, and the first gate-off signal line VGL1, the space occupied by the signal line can be further reduced, and the frame can be further reduced.

[0118] In some embodiments, as shown in FIG5a and FIG6a , the third register bank 51 and the fourth register bank 52 are mirror-symmetric about a second axis, where the second axis extends along the bank direction f2. That is, the third register bank 51 can at least partially overlap with the fourth register bank 52 after being rotated 180° about the second axis.

[0119] In some embodiments, as shown in FIG5a or FIG6a , the third signal line group 53 further includes a second signal line 56 located on a side of the third register column 51 facing away from the fourth register column 52 and / or located between the third register column 51 and the first signal line 55. The second signal line 56 is not connected to the shift register GOA unit in the fourth register column 52.

[0120] In some embodiments, as shown in FIG5a or FIG6a, the fourth signal line group 54 further includes a third signal line 57 located on a side of the fourth register column 52 facing away from the third register column 51, and / or located between the fourth register column 52 and the first signal line 55. The third signal line 57 is not connected to the shift register GOA unit in the third register column 51.

[0121] Exemplarily, the second signal line 56 and the third signal line 57 each independently include at least one of the following: a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2 and a low gate-off signal line LVGL.

[0122] Exemplarily, the second signal lines 56 include a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL. As shown in FIG5a or FIG5b , the second signal lines 56 are divided into a first sub-line 56-1 and a second sub-line 56-2. The first sub-line 56-1 includes the frame start signal line STV, the first noise reduction voltage signal line VDDE, the second noise reduction voltage signal line VDDO, the initialization signal line INIT, the second gate-off signal line VGL2, and the low gate-off signal line LVGL, arranged sequentially along the row direction f1. The first sub-line 56-1 is located on the side of the third register column 51 facing away from the fourth register column 52. The second sub-line 56-2 includes the gate-on signal line VGH and the first gate-off signal line VGL1, arranged sequentially along the row direction f1, and is located between the third register column 51 and the first signal line 55.

[0123] Exemplarily, the third signal lines 57 include a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL. As shown in FIG5 a or FIG5 c , the third signal lines 57 are divided into a third sub-line 57 - 1 and a fourth sub-line 57 - 2. The third sub-line 57 - 1 includes the frame start signal line STV, the first noise reduction voltage signal line VDDE, the second noise reduction voltage signal line VDDO, the initialization signal line INIT, the second gate-off signal line VGL2, and the low gate-off signal line LVGL, arranged in sequence in the direction opposite to the row direction f1. The third sub-line 57 - 1 is located on the side of the fourth register column 52 facing away from the third register column 51. The fourth sub-line 57 - 2 includes a gate-on signal line VGH and a first gate-off signal line VGL1 sequentially arranged in the opposite direction of the row direction f1 , and is located between the fourth register column 52 and the first signal line 55 .

[0124] For example, as shown in FIG6a , the second signal lines 56 include a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL, which are sequentially arranged along the row direction f1. These second signal lines 56 are all located on a side of the third register column 51 away from the fourth register column 52. The third signal lines 57 include a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL, which are sequentially arranged along the opposite direction of the row direction f1. These third signal lines 57 are all located on a side of the fourth register column 52 away from the third register column 51.

[0125] 5a or 6a, the second signal line 56 and the third signal line 57 are mirror-symmetric about a third axis, and the third axis extends along the column direction f2. That is, the second signal line 56 can at least partially overlap with the third signal line 57 after rotating 180° about the third axis.

[0126] By arranging the second signal line 56 and the third signal line 57 to be mirror-symmetrical, the design and wiring difficulty can be simplified.

[0127] Exemplarily, when the third register column 51 and the fourth register column 52 are mirror-symmetrical about the second axis, and the second signal line 56 and the third signal line 57 are mirror-symmetrical about the third axis, the third axis substantially coincides with the second axis.

[0128] It should be noted that the third register column 51 and the fourth register column 52 may also be symmetrically shifted along the row direction f1 , and the second signal line 56 and the third signal line 57 may also be symmetrically shifted along the row direction f1 , which is not limited in the present disclosure.

[0129] To reduce the resistance of the clock signal line CLK, in a first example, as shown in FIG5d , the clock signal line CLK includes a first sub-clock signal line CLK1 and a second sub-clock signal line CLK2 that are adjacent to and connected to each other. A gap is provided between the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2. The first sub-clock signal line CLK1 and the second sub-clock signal line CLK2 are connected by a plurality of connectors 58 , which are spaced apart from each other along the column direction f2 . The line widths of the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2 are, for example, the same as the line widths of other signal lines, such as the gate-on signal line VGH and the first gate-off signal line VGL1 . By connecting the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2 in parallel, the resistance of the clock signal line CLK can be effectively reduced.

[0130] To reduce the resistance of the clock signal line CLK, in a second example, as shown in FIG5d , the clock signal line CLK is connected to a plurality of clock patterns 59 . The plurality of clock patterns 59 are spaced apart from each other along the column direction f2 . The clock signal line CLK and the clock patterns 59 are disposed on different layers and connected via a first via H1 (as shown in FIG10 ). By connecting the clock signal line CLK and the clock patterns 59 in parallel, the resistance of the clock signal line CLK can be effectively reduced. The clock signal line CLK is, for example, disposed on the same layer as the scan line SC, and the clock patterns 59 are, for example, disposed on the same layer as the data line DT.

[0131] As shown in Figure 5d, when the clock signal line CLK includes an adjacent first sub-clock signal line CLK1 and a second sub-clock signal line CLK2, and the first sub-clock signal line CLK1 is connected to the second sub-clock signal line CLK2 through multiple connecting parts 58, the clock pattern 59 includes: a first sub-pattern 591 corresponding to the position of the first sub-clock signal line CLK1, a second sub-pattern 592 corresponding to the position of the second sub-clock signal line CLK2, and a third sub-pattern 593 corresponding to the position of the connecting part 58. The first sub-pattern 591 and the second sub-pattern 592 extend along the column direction f2, and the third sub-pattern 593 connects the midpoint of the first sub-pattern 591 and the midpoint of the second sub-pattern 592. The first sub-pattern 591, the second sub-pattern 592, and the third sub-pattern 593 connected to each other constitute an H-type clock pattern 59.

[0132] To reduce the resistance of the clock signal line CLK, in a third example, as shown in FIG6c , the line width of the clock signal line CLK is greater than the line widths of other signal lines, such as the gate-on signal line VGH and the first gate-off signal line VGL1. For example, the line width of the clock signal line CLK is twice the line width of other signal lines, such as the gate-on signal line VGH or the first gate-off signal line VGL1. By widening the clock signal line CLK, the resistance of the clock signal line CLK can be effectively reduced.

[0133] In some embodiments, as shown in FIG7 , the plurality of shift registers GOA unit include a third shift register GOA unit 3 and a fourth shift register GOA unit 4, wherein an output terminal Opt of the third shift register GOA unit 3 is connected to an input terminal Ipt of the fourth shift register GOA unit 4, and the third shift register GOA unit 3 and the fourth shift register GOA unit 4 are located in the same column. The output terminal Opt of the third shift register GOA unit 3 is also connected to a scan line SC.

[0134] Exemplarily, the output end Opt of the first-stage shift register GOA unit 1st is connected to the input end Ipt of the fifth-stage shift register GOA unit 5th. In this case, the third shift register GOA unit3 is the first-stage shift register GOA unit 1st, the fourth shift register GOA unit4 is the fifth-stage shift register GOA unit 5th, and the first-stage shift register GOA unit 1st and the fifth-stage shift register GOA unit 5th are located in the same column.

[0135] Exemplarily, the output end Opt of the second-stage shift register GOA unit 2nd is connected to the input end Ipt of the sixth-stage shift register GOA unit 6th. In this case, the third shift register GOA unit3 is the second-stage shift register GOA unit 2nd, the fourth shift register GOA unit4 is the sixth-stage shift register GOA unit 6th, and the second-stage shift register GOA unit 2nd and the sixth-stage shift register GOA unit 6th are located in the same column.

[0136] In some embodiments, a plurality of shift register GOA units are arranged in a zigzag or a bow shape according to a cascade sequence.

[0137] For example, as shown in FIG8 , the first-stage shift register GOA unit 1st, the second-stage shift register GOA unit 2nd, the third-stage shift register GOA unit 3, etc. are arranged in a Z-shape in a cascade order from the lowest level to the highest level. For example, in FIG8 , two shift registers GOA units are arranged in each row according to a preset direction f3 (i.e., the direction in which the gate drive circuit GOA points to the display area AA, such as the row direction f1). Along the preset direction f3, the first row is arranged with the first-stage shift register GOA unit 1st and the second-stage shift register GOA unit 2nd, the second row is arranged with the third-stage shift register GOA unit 3rd and the fourth-stage shift register GOA unit 4th, the third row is arranged with the fifth-stage shift register GOA unit 5th and the sixth-stage shift register GOA unit 6th, and the fourth row is arranged with the seventh-stage shift register GOA unit 7th and the eighth-stage shift register GOA unit 8th.

[0138] For example, as shown in FIG9 , the first-stage shift register GOA unit 1st, the second-stage shift register GOA unit 2nd, the third-stage shift register GOA unit 3, etc. can also be arranged in a bow shape in a cascade order from the lowest level to the highest level. For example, in FIG9 , each row is arranged with two shift registers GOA unit according to a preset direction f3. Along the preset direction f3, the first row is arranged with the first-stage shift register GOA unit 1st and the second-stage shift register GOA unit 2nd, the second row is arranged with the fourth-stage shift register GOA unit 4th and the third-stage shift register GOA unit 3rd, the third row is arranged with the fifth-stage shift register GOA unit 5th and the sixth-stage shift register GOA unit 6th, and the fourth row is arranged with the eighth-stage shift register GOA unit 8th and the seventh-stage shift register GOA unit 7th.

[0139] In some embodiments, as shown in FIG8 , the number of shift register GOA units connected to different scan lines SC and located in the same row is 2, and odd-numbered shift register GOA units are located in the same column, and even-numbered shift register GOA units are located in the same column.

[0140] For example, in Figure 8, the odd-numbered shift register GOA units, such as the first-stage shift register GOA unit 1st, the third-stage shift register GOA unit 3rd, the fifth-stage shift register GOA unit 5th, and the seventh-stage shift register GOA unit 7th, are located in the same column; the even-numbered shift register GOA units, such as the second-stage shift register GOA unit 2nd, the fourth-stage shift register GOA unit 4th, the sixth-stage shift register GOA unit 6th, and the eighth-stage shift register GOA unit 8th, are located in the same column.

[0141] In some embodiments, the gate driving circuit GOA is further connected to a plurality of clock signal lines CLK, and the plurality of clock signal lines CLK are used to transmit M clock signals with different timings.

[0142] Exemplarily, the number of shift register GOA units connected to different scan lines SC and located in the same row is N, M is greater than N, and M is divisible by N, M and N are both positive integers, and N is a positive integer greater than or equal to 2.

[0143] For example, for a 4CLK product, M=4, N=2, that is, two shift register GOA units connected to different scan lines SC can be set in one row.

[0144] For 8CLK products, M=8, N=2 or 4, that is, one row can be provided with two (as shown in FIG. 4 a , FIG. 5 a and FIG. 6 a ) or four shift register GOA units connected to different scan lines SC.

[0145] For 10CLK products, M=10, N=2 or 5, that is, two or five shift register GOA units connected to different scan lines SC can be set in one row.

[0146] For 12CLK products, M=12, N=2, 3, 4 or 6, that is, a row can be provided with two, three, four or six shift register GOA units connected to different scan lines SC.

[0147] For 16CLK products, M=16, N=2, 4 or 8, that is, one row can be provided with two, four or eight shift register GOA units connected to different scan lines SC.

[0148] In some embodiments, the number of shift register GOA units connected to different scan lines SC and located in the same row is greater than or equal to 2 and less than or equal to 4. This can increase the height space of the shift register GOA unit in the column direction f2 and prevent the gate driver circuit GOA from occupying too much space in the row direction f1.

[0149] In some embodiments, the number of shift register GOA units connected to different scan lines SC and located in the same row is N. In the column direction f2, the arrangement period of the shift register GOA units is approximately equal to N times the arrangement period of the sub-pixels PX.

[0150] For example, as shown in FIG2 , two shift register GOA units connected to different scan lines SC are arranged in one row, ie, N=2. In the column direction f2 , the arrangement period of the shift register GOA units is approximately equal to twice the arrangement period of the sub-pixels PX.

[0151] For example, three shift register GOA units connected to different scan lines SC are provided in one row, ie, N=3. In the column direction f2, the arrangement period of the shift register GOA units is approximately equal to three times the arrangement period of the sub-pixels PX.

[0152] For example, as shown in FIG3 , four shift register GOA units connected to different scan lines SC are arranged in one row, ie, N=4. In the column direction f2 , the arrangement period of the shift register GOA units is approximately equal to 4 times the arrangement period of the sub-pixels PX.

[0153] In some embodiments, as shown in Figure 4a, Figure 5a or Figure 6a, the multiple shift registers GOA unit include a first shift register GOA unit1 and a second shift register GOA unit2 arranged in the same row, the first shift register GOA unit1 is located on a side of the second shift register GOA unit2 away from the display area AA, and at least one clock signal line CLK extending along the column direction f2 is further provided between the first shift register GOA unit1 and the second shift register GOA unit2, and the first shift register GOA unit1 and the second shift register GOA unit2 are respectively connected to different scan lines SC.

[0154] As shown in Figure 5d, the first shift register GOA unit1 is connected to the scan line SC through a remote lead 61. The remote lead 61 includes a first line segment 61L and a second line segment 61R. The first shift register GOA unit1, the first line segment 61L, the second line segment 61R and the scan line SC are connected in sequence. The first line segment 61L and the clock signal line CLK are arranged on different layers and cross each other.

[0155] As shown in Figure 5d, the two adjacent remote leads 61 are the first remote lead 611 and the second remote lead 612, and the distance g1 between the first line segment 61L of the first remote lead 611 and the first line segment 61L of the second remote lead 612 is smaller than the distance g2 between the second line segment 61R of the first remote lead 611 and the second line segment 61R of the second remote lead 612.

[0156] In this embodiment, by gathering the first line segments 61L, more wiring space can be reserved (as shown in the black solid line frame position in Figure 5d). These wiring spaces can be used to set the clock pattern 59 (as shown in Figure 5d). The clock pattern 59 is set on the same layer as the remote lead 61 and is connected to the clock signal line CLK through the first via H1 to reduce the resistance of the clock signal line CLK.

[0157] The first remote lead 611 and the second remote lead 612 are connected between different first shift registers GOA unit1 and the scan line SC.

[0158] For example, in the column direction f2 , a plurality of shift register GOA units may be provided between the second line segment 61R of the first remote lead 611 and the second line segment 61R of the second remote lead 612 .

[0159] As shown in FIG5c , in the column direction f2, two shift register GOA units are arranged between the second line segment 61R of the first remote lead 611 and the second line segment 61R of the second remote lead 612. In this case, the spacing g2 between the second line segment 61R of the first remote lead 611 and the second line segment 61R of the second remote lead 612 is approximately the height of the two shift register GOA units in the column direction f2.

[0160] In some embodiments, as shown in FIG4d or 5e, the second shift register GOA unit 2 is connected to the scan line SC via a short-range lead 62, where two adjacent short-range leads 62 are a first short-range lead 621 and a second short-range lead 622. The first short-range lead 621 and the second short-range lead 622 are connected between different second shift registers GOA unit 2 and the scan line SC.

[0161] As shown in Figure 5e, the second line segment 61R of the first remote lead 611, the first proximal lead 621, the second line segment 61R of the second remote lead 612, and the second proximal lead 622 all extend along the row direction f1 and are arranged in sequence along the column direction f2. The spacing g3 between the second line segment 61R of the first remote lead 611 and the first proximal lead 621, and the spacing g4 between the second line segment 61R of the second remote lead 612 and the second proximal lead 622 are both smaller than the spacing g5 between the first proximal lead 621 and the second line segment 61R of the second remote lead 612.

[0162] As shown in Figure 5e, proximal lead 62 is connected to reverse extension line 64, which is located on the side of proximal lead 62 away from display area AA. Reverse extension line 64 and proximal lead 62 are arranged on different layers, while proximal lead 62 and remote lead 61 are arranged on the same layer. In an orthographic projection onto the plane of the display substrate, the second line segment 61R of first remote lead 611 overlaps with reverse extension line 64 connecting first proximal lead 621, while the second line segment 61R of second remote lead 612 overlaps with reverse extension line 64 connecting second proximal lead 622.

[0163] For example, as shown in FIG5d , the shift register GOA unit is connected to the clock signal line CLK via a clock lead 63. Multiple clock leads 63 (four as shown in FIG5d ) are located between a first remote lead 611 and a second remote lead 612. The clock leads 63 are, for example, provided on the same layer as the remote leads 61, but on a different layer from the clock signal line CLK and connected via vias.

[0164] 5 d , the first line segment 61L of the first remote lead 611 , the first line segment 61L of the second remote lead 612 , and the plurality of clock leads 63 between the first remote lead 611 and the second remote lead 612 are arranged at equal intervals in the column direction f2 .

[0165] To further save wiring space, as shown in FIG5 d , among the multiple clock leads 63 located between the first remote lead 611 and the second remote lead 612 , a first clock lead 631 connected to the third register column 51 on the left and a second clock lead 632 connected to the fourth register column 52 on the right are arranged along the row direction f1. In FIG5 d , the first clock lead 631 and the second clock lead 632 are arranged opposite to each other.

[0166] As shown in Figure 4d, the second line segment 61R of the first remote lead 611, the first proximal lead 621, the second proximal lead 622 and the second line segment 61R of the second remote lead 612 all extend along the row direction f1 and are arranged in sequence along the column direction f2. The spacing g6 between the second line segment 61R of the first remote lead 611 and the first proximal lead 621, and the spacing g7 between the second proximal lead 622 and the second line segment 61R of the second remote lead 612 are both smaller than the spacing g8 between the first proximal lead 621 and the second proximal lead 622.

[0167] In some embodiments, as shown in FIG4d or FIG5e , the shift register GOA unit is connected to the scan line SC via a lead 45. The plurality of leads 45 include a first lead, a second lead, and a third lead that are sequentially adjacent along a column direction. The distance between the first lead and the second lead is greater or less than the distance between the second lead and the third lead. That is, the distance between the first lead and the second lead is not equal to the distance between the second lead and the third lead.

[0168] The first lead, the second lead and the third lead may be any three adjacent leads 45 .

[0169] For example, the leads 45 may include long-range leads 61 and short-range leads 62. The leads 45 may be provided on the same layer as the data lines DT, and the signal lines (such as the clock signal lines CLK) extending along the column direction f2 may be provided on the same layer as the scan lines SC.

[0170] For example, as shown in FIG4d or FIG5e, when the first lead, the second lead, and the third lead are lead Y1, lead Y2, and lead Y3, respectively, the distance between the first lead and the second lead is smaller than the distance between the second lead and the third lead. When the first lead, the second lead, and the third lead are lead Y6, lead Y7, and lead Y8, respectively, the distance between the first lead and the second lead is larger than the distance between the second lead and the third lead.

[0171] In some embodiments, as shown in FIG4 d or FIG5 e , the plurality of leads 45 are divided into a plurality of lead groups 46 , each of which includes two adjacent leads 45 . The plurality of lead groups 46 include a first lead group, a second lead group, and a third lead group that are sequentially adjacent along a column direction. The distance between the first lead group and the second lead group is greater than or less than the distance between the second lead group and the third lead group. That is, the distance between the first lead group and the second lead group is not equal to the distance between the second lead group and the third lead group.

[0172] As shown in FIG4d or FIG5e , two adjacent leads 45 form a lead group 46. Multiple lead groups 46 are arranged along the column direction f2. Each lead 45 belongs to only one lead group 46, and different lead groups 46 include different leads 45. For example, lead Y1 and lead Y2 form lead group Z1, lead Y3 and lead Y4 form lead group Z2, lead Y5 and lead Y6 form lead group Z3, and lead Y7 and lead Y8 form lead group Z4.

[0173] 4d or 5e, for each lead group 46, the distance between two leads 45 is the second distance d2. The second distances d2 of different lead groups 46 are substantially the same.

[0174] The first lead group, the second lead group and the third lead group may be any three adjacent lead groups 46 .

[0175] Exemplarily, as shown in Figure 4d or Figure 5e, when the first lead group, the second lead group and the third lead group are lead group Z1, lead group Z2 and lead group Z3 respectively, the distance between the first lead group and the second lead group is greater than the distance between the second lead group and the third lead group; when the first lead group, the second lead group and the third lead group are lead group Z2, lead group Z3 and lead group Z4 respectively, the distance between the first lead group and the second lead group is less than the distance between the second lead group and the third lead group.

[0176] Furthermore, when the distance between the first lead group and the second lead group is greater than the distance between the second lead group and the third lead group, the distance between the first lead group and the second lead group is greater than the second distance d2, and the distance between the second lead group and the third lead group is less than or equal to the second distance d2. When the distance between the first lead group and the second lead group is less than the distance between the second lead group and the third lead group, the distance between the first lead group and the second lead group is less than or equal to the second distance d2, and the distance between the second lead group and the third lead group is greater than the second distance d2.

[0177] Illustratively, as shown in FIG4d , Y1 , Y4 , Y5 , and Y8 are long-range leads 61 , and Y2 , Y3 , Y6 , and Y7 are short-range leads; as shown in FIG5e , Y1 , Y3 , Y5 , and Y8 are long-range leads 61 , and Y2 , Y4 , Y6 , and Y7 are short-range leads.

[0178] In some embodiments, as shown in Figure 4d or Figure 5e, multiple lead groups 46 are divided into multiple lead units 47 arranged periodically along the column direction f2, and the lead unit 47 includes two sub-units 471 arranged along the column direction f2. Different sub-units 471 include the same number of lead groups 46, and the two sub-units 471 are axially symmetrically arranged.

[0179] 4d or 5e, each subunit 471 includes two lead groups 46. One subunit 471 includes lead group Z1 and lead group Z2, and the other subunit 471 includes lead group Z3 and lead group Z4. The two subunits 471 are axially symmetrical, and the symmetry axis extends along the row direction f1.

[0180] In some embodiments, as shown in FIG. 4 d or FIG. 5 e , the subunit 471 includes a plurality of lead sets 46 . The plurality of lead sets 46 in the same subunit 471 are axially symmetrically arranged, and the axis of symmetry extends, for example, along the row direction f1 .

[0181] 4d or 5e , lead groups Z1 and Z2 within the same subunit 471 are axially symmetrically arranged, with the axis of symmetry extending along the row direction f1. Lead groups Z3 and Z4 within the same subunit 471 are axially symmetrically arranged, with the axis of symmetry extending along the row direction f1.

[0182] For example, as shown in FIG4b or FIG5b, the shift register GOA unit includes a plurality of transistors, and at least one transistor in two shift register GOA units arranged along the column direction f2 is mirror-symmetrical, and the axis of symmetry extends along the row direction f1. For example, as shown in FIG4a, the transistors in the first-stage shift register GOA unit 1st are mirror-symmetrical with the transistors in the third-stage shift register GOA unit 3rd.

[0183] In a specific implementation, the display substrate may include one or more gate driving circuits GOA. For example, as shown in FIG2 or FIG3 , the display substrate includes two gate driving circuits GOA, and the two gate driving circuits GOA are located on opposite sides of the display area AA.

[0184] As shown in FIG2 or FIG3 , multiple shift register GOA units within the same gate drive circuit GOA are located on the same side of the display area AA. Different gate drive circuits GOA are located on different sides of the display area AA. In FIG2 and FIG3 , one gate drive circuit GOA is located on the left side of the display area AA, and the other gate drive circuit GOA is located on the right side of the display area AA.

[0185] In some embodiments, as shown in Figure 2 or Figure 3, the display area AA further includes: a plurality of data lines DT extending along the column direction f2, the plurality of sub-pixels PX are divided into a plurality of pixel units P, the pixel unit P includes a plurality of sub-pixels PX arranged in the column direction f2, the plurality of sub-pixels PX located in the same pixel unit P are connected to the same data line DT and are respectively connected to different scan lines SC, and the size of the sub-pixel PX along the row direction f1 is larger than the size of the sub-pixel PX along the column direction f2.

[0186] By arranging multiple sub-pixels PX in the same pixel unit P to be connected to the same data line DT and to different scan lines SC, the number of data lines DT can be reduced, thereby reducing the number of source driver chips required, thereby reducing costs. The source driver chip is used to provide data signals to the data lines DT.

[0187] For example, as shown in FIG2 or FIG3, the pixel unit P includes three sub-pixels PX, and the three sub-pixels PX are connected to the same data line DT and are respectively connected to different scan lines SC. In this way, triple rate driving (TRD) can be achieved, and the number of source driver chips can be reduced by 2 / 3, thereby reducing costs.

[0188] Exemplarily, as shown in FIG. 2 or FIG. 3 , the three sub-pixels PX located in the same pixel unit P are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively.

[0189] In a three-speed drive display substrate, the number of scan lines SC is tripled compared to a single-speed drive display substrate. Consequently, the number of shift register GOA units in the gate drive circuit GOA also increases accordingly. If a single shift register GOA unit were still provided per row, the height space available for each shift register GOA unit in the column direction f2 would be reduced, making it impossible to route wires. The display substrate provided by the present disclosure, by arranging multiple shift register GOA units in the same row, increases the height space available for each shift register GOA unit in the column direction f2, facilitating the layout of thin-film transistors and associated signal lines, and facilitating the implementation of three-speed drive.

[0190] The present disclosure provides a display device, comprising: a display substrate as provided in any embodiment; and a source driving circuit connected to the display substrate and configured to drive the display substrate to perform display.

[0191] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate or display substrate.

[0192] Exemplarily, the source driver circuit is a source driver chip.

[0193] Exemplarily, the source driver circuit is connected to the data line DT. When multiple sub-pixels PX located in the same pixel unit P are connected to the same data line DT and are respectively connected to different scan lines SC, the source driver circuit can provide data signals to the same data line DT in a time-division manner to drive the multiple sub-pixels PX connected to the same data line DT to display in sequence.

[0194] The display device provided herein may be any product or component with a display function, such as a display panel, display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted display device, smartwatch, fitness wristband, personal digital assistant, etc. The display panel may be, for example, a liquid crystal display panel.

[0195] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0196] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0197] As used herein, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0198] References herein to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0199] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0200] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0201] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0202] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0203] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0204] The use of "for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0205] The use of "based on" or "according to" in this document is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0206] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0207] As used herein, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute equality and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0208] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0209] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0210] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate includes a display area and a gate driving circuit located on at least one side of the display area; Among them, The display area includes a plurality of scan lines extending in a row direction and a plurality of sub-pixels arranged in an array in the row direction and the column direction, and at least one scan line is provided between adjacent two rows of sub-pixels; The gate driving circuit located on the same side of the display area includes a plurality of cascaded shift registers, the shift registers are connected to the scan lines, and at least two shift registers connected to different scan lines are located in the same row.

2. The display substrate according to claim 1, wherein, The plurality of shift registers include a first shift register and a second shift register arranged in the same row, and the first shift register and the second shift register are respectively connected to different scan lines; The first shift register and the second shift register are translationally symmetric in the row direction, or the first shift register and the second shift register are mirror symmetric about a first axis, and the first axis extends in the column direction.

3. The display substrate according to claim 1 or 2, wherein The plurality of shift registers include a first register column and a second register column arranged in the row direction, and both the first register column and the second register column include a plurality of shift registers arranged in the column direction; The shift registers in the first register column are connected to a first signal line group, the shift registers in the second register column are connected to a second signal line group, both the first signal line group and the second signal line group include at least one signal line, and the signal lines in the first signal line group and the signal lines in the second signal line group do not share.

4. The display substrate according to claim 3, wherein, In the row direction, the first register column and the second register column are translationally symmetric, the first signal line group and the second signal line group are translationally symmetric, and the translation distance of the first register column relative to the second register column is approximately equal to the translation distance of the first signal line group relative to the second signal line group.

5. The display substrate according to claim 1 or 2, wherein, The plurality of shift registers include a third register column and a fourth register column arranged adjacent to each other in the row direction, and both the third register column and the fourth register column include a plurality of shift registers arranged in the column direction; The shift registers in the third register column are connected to a third signal line group, the shift registers in the fourth register column are connected to a fourth signal line group, both the third signal line group and the fourth signal line group include a first signal line, and the first signal line is shared.

6. The display substrate according to claim 5, wherein, The first signal line is located between the third register column and the fourth register column.

7. The display substrate according to claim 5 or 6, wherein, The first signal line includes at least one of the following: a clock signal line, a gate turn-on signal line, and a first gate turn-off signal line, where the gate turn-on signal line is used to provide a gate turn-on voltage, the gate turn-on voltage is used to turn on the thin film transistor of the sub-pixel, and the first gate turn-off signal line is used to provide a gate turn-off voltage, and the gate turn-off voltage is used to turn off the thin film transistor of the sub-pixel.

8. The display substrate according to claim 6, wherein, The third register column and the fourth register column are mirror symmetric about a second axis, and the second axis extends in the column direction.

9. The display substrate according to claim 6 or 8, wherein The third signal line group further includes: a second signal line, located on a side of the third register column away from the fourth register column, and / or, located between the third register column and the first signal line; The fourth signal line group further includes: a third signal line, located on a side of the fourth register column away from the third register column, and / or, located between the fourth register column and the first signal line.

10. The display substrate according to claim 9, wherein, The second signal line and the third signal line are mirror-symmetrical about a third axis, and the third axis extends in the column direction.

11. The display substrate according to claim 9 or 10, wherein Each of the second signal line and the third signal line independently includes at least one of the following: a gate turn-on signal line, a first gate turn-off signal line, a frame start signal line, a first noise reduction voltage signal line, a second noise reduction voltage signal line, an initialization signal line, a second gate turn-off signal line, and a low gate turn-off signal line; Wherein, the gate turn-on signal line is used to provide a gate turn-on voltage for turning on the thin film transistor of the sub-pixel, the first gate turn-off signal line and the second gate turn-off signal line are both used to provide a gate turn-off voltage for turning off the thin film transistor of the sub-pixel, the low gate turn-off signal line is used to provide a low gate turn-off voltage, and the low gate turn-off voltage is less than the gate turn-off voltage.

12. The display substrate according to any one of claims 1 to 11, wherein, The plurality of shift registers includes a third shift register and a fourth shift register, an output end of the third shift register is connected to an input end of the fourth shift register, and the third shift register and the fourth shift register are located in the same column.

13. The display substrate according to any one of claims 1 to 12, wherein, The plurality of shift registers are arranged in a Z-shaped layout or a bow-shaped layout in a cascading order.

14. The display substrate according to any one of claims 1 to 13, wherein The number of shift registers connecting different scan lines and located in the same row is 2, and the odd-level shift registers are located in the same column, and the even-level shift registers are located in the same column.

15. The display substrate according to any one of claims 1 to 14, wherein, The gate driving circuit is further connected to a plurality of clock signal lines for transmitting M clock signals with different timings; The number of shift registers connecting different scan lines and located in the same row is N, M is greater than N, and M is divisible by N, and both M and N are positive integers.

16. The display substrate according to any one of claims 1 to 15, wherein, The number of shift registers connecting different scan lines and located in the same row is greater than or equal to 2 and less than or equal to 4.

17. The display substrate according to any one of claims 1 to 16, wherein, The number of shift registers connecting different scan lines and located in the same row is N, and in the column direction, the layout period of the shift registers is approximately equal to N times the layout period of the sub-pixels.

18. The display substrate according to any one of claims 1 to 17, wherein, In the column direction, a scan line and a row of sub-pixels are alternately arranged in sequence, and the distance between two adjacent scan lines is approximately equal to the layout period of the sub-pixels in the column direction.

19. The display substrate according to any one of claims 1 to 18, wherein, The plurality of shift registers includes a first shift register and a second shift register arranged in the same row, the first shift register is located on a side of the second shift register away from the display area, and at least one clock signal line extending in the column direction is further provided between the first shift register and the second shift register, and the first shift register and the second shift register are respectively connected to different scan lines; The first shift register is connected to the scanning line through a remote lead, the remote lead includes a first line segment and a second line segment, the first shift register, the first line segment, the second line segment, and the scanning line are connected in sequence, and the first line segment and the clock signal line are arranged on different layers and intersect with each other; Two adjacent remote leads are a first remote lead and a second remote lead, and the distance between the first line segment of the first remote lead and the first line segment of the second remote lead is less than the distance between the second line segment of the first remote lead and the second line segment of the second remote lead. The second shift register is connected to the scanning line through a short-range lead, and two adjacent short-range leads are a first short-range lead and a second short-range lead; 20. The display substrate according to claim 19, wherein The second line segment of the first remote lead, the first short-range lead, the second line segment of the second remote lead, and the second short-range lead all extend in the row direction and are arranged in sequence in the column direction. The distance between the second line segment of the first remote lead and the first short-range lead, and the distance between the second line segment of the second remote lead and the second short-range lead are both less than the distance between the first short-range lead and the second line segment of the second remote lead. The short-range lead is connected to a reverse extension line. The reverse extension line is located on the side of the short-range lead away from the display area, and the reverse extension line and the short-range lead are arranged on different layers. The short-range lead and the remote lead are arranged on the same layer; 21. The display substrate according to claim 20, wherein, In the orthographic projection on the plane where the display substrate is located, the second line segment of the first remote lead overlaps with the reverse extension line connecting the first short-range lead, and the second line segment of the second remote lead overlaps with the reverse extension line connecting the second short-range lead. The second shift register is connected to the scanning line through a short-range lead, and two adjacent short-range leads are a first short-range lead and a second short-range lead; 22. The display substrate according to claim 19, wherein The second line segment of the first remote lead, the first short-range lead, the second short-range lead, and the second line segment of the second remote lead all extend in the row direction and are arranged in sequence in the column direction. The distance between the second line segment of the first remote lead and the first short-range lead, and the distance between the second short-range lead and the second line segment of the second remote lead are both less than the distance between the first short-range lead and the second short-range lead. The shift register is connected to the clock signal line. The clock signal line is also connected to a plurality of clock patterns. The plurality of clock patterns are arranged separately from each other in the column direction. The clock signal line and the clock patterns are arranged on different layers and are connected through a first via.

23. The display substrate according to any one of claims 1 to 22, wherein, The clock signal line includes adjacent first sub-clock signal line and second sub-clock signal line, and the first sub-clock signal line and the second sub-clock signal line are connected through a connecting portion; 24. The display substrate according to claim 23, wherein, ​ The clock pattern includes: a first sub-pattern corresponding to the position of the first sub-clock signal line, a second sub-pattern corresponding to the position of the second sub-clock signal line, and a third sub-pattern corresponding to the position of the connection portion. The first sub-pattern and the second sub-pattern extend in the column direction, and the third sub-pattern is connected between the first sub-pattern and the second sub-pattern.

25. The display substrate according to any one of claims 1 to 24, wherein, The display area further includes: a plurality of data lines extending in the column direction; The plurality of sub-pixels are divided into a plurality of pixel units. Each pixel unit includes a plurality of sub-pixels arranged in the column direction. The plurality of sub-pixels in the same pixel unit are connected to the same data line and are respectively connected to different scan lines. The size of the sub-pixel in the row direction is greater than the size of the sub-pixel in the column direction.

26. The display substrate according to any one of claims 1 to 25, wherein, The display substrate includes two of the gate driving circuits, and the two gate driving circuits are located on opposite sides of the display area.

27. A display device, comprising: The display substrate according to any one of claims 1 to 26; and a source driving circuit, connected to the display substrate for driving the display substrate to display.

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