Specially-shaped display panel and display device

Abstract

Provided in the embodiments of the present disclosure are a specially-shaped display panel and a display device. The specially-shaped display panel comprises a display area and a peripheral area arranged around the display area, wherein there is a specially-shaped boundary between the display area and the peripheral area. A color film substrate comprises: a first substrate, which has a virtual display area arranged around the display area and corresponding to the peripheral area, wherein the virtual display area comprises a plurality of virtual pixels arranged around edge display pixels, and the virtual pixels comprise a plurality of virtual sub-pixels having different light emission colors; a black matrix layer, which is located on the side of the first substrate that faces an array substrate, wherein the black matrix layer covers the display area and the virtual display area, and the black matrix layer is provided with an opening corresponding to each display sub-pixel located in the display area; and a plurality of filter structures, which are located on the side of the black matrix layer that is away from the first substrate, wherein the filter structures fill the openings in the display area, and, in the virtual display area, the filter structures correspond to the virtual sub-pixels in terms of position and are arranged on the side of the black matrix layer that is away from the first substrate.

Description

Special-shaped display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a special-shaped display panel and a display device. Background Art

[0002] With the development of science and technology, the uses of display devices are becoming more and more extensive, which makes people's requirements for display panels in display devices more and more diverse. In order to meet people's diverse demands for the appearance of display panels, special-shaped display panels come into being.

[0003] Special-shaped display panels break through the limitations of the single rectangular structure of display panels, making display panels more versatile, such as in automotive displays. The display area of ​​special-shaped display panels is non-rectangular, such as circular or elliptical.

[0004] Summary of the Invention

[0005] The present disclosure provides a special-shaped display panel and a display device, and the specific solutions are as follows:

[0006] An embodiment of the present disclosure provides a special-shaped display panel, comprising a display area and a peripheral area surrounding the display area, wherein a special-shaped border is defined between the display area and the peripheral area; the display area comprises a plurality of display pixels arranged in an array along row and column directions, wherein the display pixels comprise a plurality of display sub-pixels emitting different colors; the plurality of display pixels include edge display pixels covered by the special-shaped border and regular display pixels not covered by the special-shaped border;

[0007] The special-shaped display panel includes an array substrate and a color filter substrate that are arranged opposite to each other and spaced apart. The color filter substrate includes:

[0008] a first substrate, the first substrate having a virtual display area arranged around the display area corresponding to the peripheral area, the virtual display area including a plurality of virtual pixels arranged around the edge display pixels, the virtual pixels including a plurality of virtual sub-pixels with different luminous colors;

[0009] a black matrix layer, located on a side of the first substrate facing the array substrate, the black matrix layer covering the display area and the virtual display area, and the black matrix layer having an opening corresponding to each display sub-pixel located in the display area;

[0010] Multiple filter structures are located on the side of the black matrix layer away from the first substrate, the filter structures are filled in the openings in the display area, and the filter structures are arranged at positions corresponding to the virtual sub-pixels in the virtual display area on the side of the black matrix layer away from the first substrate.

[0011] In a possible implementation, in the above-mentioned special-shaped display panel provided by the embodiment of the present disclosure, at least one virtual pixel is provided on one side in the row direction and / or one side in the column direction of each edge display pixel.

[0012] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the array substrate includes a second substrate and a pixel electrode layer arranged on the side of the second substrate facing the color film substrate, the pixel electrode layer includes a display pixel electrode arranged corresponding to each of the display sub-pixels and a virtual pixel electrode arranged corresponding to some of the virtual sub-pixels, and the virtual pixel electrode is arranged on one side of the edge of at least one row of the display pixel electrodes.

[0013] In a possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the array substrate includes, corresponding to the peripheral area, a driver chip binding area, and a fan-out area located between the driver chip binding area and the display area and surrounding at least a portion of the display area; the fan-out area includes a plurality of fan-out traces; wherein,

[0014] An orthographic projection of the filter structure corresponding to at least part of the virtual sub-pixels on the second substrate and an orthographic projection of at least part of the fan-out traces on the second substrate have an overlapping area;

[0015] An orthographic projection of the virtual pixel electrode on the second substrate does not overlap with an orthographic projection of the fan-out trace on the second substrate.

[0016] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the array substrate includes, corresponding to the display area, a plurality of scan lines extending along the row direction and arranged along the column direction, and a plurality of data lines extending along the column direction and arranged along the row direction; wherein the plurality of scan lines and the plurality of data lines are insulated and intersected to define the plurality of display pixels, and the driver chip binding area is located on one side of the extension direction of the plurality of data lines;

[0017] The array substrate further includes a first gate driving circuit and a second gate driving circuit located on both sides of the plurality of scan lines in an extending direction corresponding to the peripheral area, wherein the first gate driving circuit is electrically connected to one end of each of the scan lines, and the second gate driving circuit is electrically connected to the other end of each of the scan lines;

[0018] Among them, the first gate driving circuit is located on a side of a part of the fan-out area away from the display area, and the second gate driving circuit is located on a side of another part of the fan-out area away from the display area, and the first gate driving circuit and the second gate driving circuit are both arranged in a conformal manner around the display area.

[0019] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the first gate driving circuit and the second gate driving circuit each include a plurality of shift register units arranged in cascade, each of the shift register units including a charging transistor arranged near an edge of the peripheral area; wherein,

[0020] There are at least two adjacent shift register units, wherein the width of the charging transistor of one shift register unit is greater than the width of the charging transistor of the other shift register unit, the height of the charging transistor of the one shift register unit is less than the height of the charging transistor of the other shift register unit, and the channel width-to-length ratios of the charging transistors of the two adjacent shift register units are the same.

[0021] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the array substrate corresponding to the peripheral area further includes: a first common electrode ring arranged between the first gate driving circuit, the second gate driving circuit and the display area, and a second common electrode ring arranged on the side of the first gate driving circuit and the second gate driving circuit away from the display area; the first common electrode ring and the second common electrode ring are electrically connected.

[0022] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the array substrate includes a spacing area corresponding to the peripheral area, which is located on the other side of the extension direction of the multiple data lines and between the first gate driving circuit and the second gate driving circuit, and the first common electrode ring and the second common electrode ring are electrically connected in the spacing area.

[0023] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the first common electrode ring and the data line are provided in the same layer;

[0024] The second common electrode ring is arranged in the same layer as the data line or the scan line;

[0025] Alternatively, the second common electrode ring includes a first sub-common electrode ring and a second sub-common electrode ring which are stacked and electrically connected to each other, the first sub-common electrode ring is arranged in the same layer as the data line, and the second sub-common electrode ring is arranged in the same layer as the scan line.

[0026] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the fan-out trace includes an inclined segment arranged around the display area and a vertical segment arranged along an extension direction of the data line, and the vertical segment is located between the display area and the driver chip binding area;

[0027] The inclined segment includes a first sub-inclined segment and a second sub-inclined segment, one end of the first sub-inclined segment is electrically connected to one end of the vertical segment, the other end of the vertical segment is electrically connected to the driver chip in the driver chip binding area, the other end of the first sub-inclined segment is connected to one end of the second sub-inclined segment through a corresponding via structure and a transparent conductive portion, and the other end of the second sub-inclined segment is electrically connected to one end of the data line.

[0028] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the array substrate includes a common electrode corresponding to the display area, and the common electrode is electrically connected to the first common electrode ring through a via hole in the peripheral area;

[0029] The gate line is located between the second substrate and the data line, the common electrode is located on a side of the data line facing away from the second substrate, the transparent conductive portion and the common electrode are provided in the same layer, the second sub-inclined segment and the data line are provided in the same layer, and the first sub-inclined segment and the vertical segment, which are electrically connected to each other, are provided in the same film layer;

[0030] A portion of the first sub-inclined segments is arranged in the same layer as the scan lines, another portion of the first sub-inclined segments is arranged in the same layer as the data lines, and the first sub-inclined segments arranged in the same layer as the scan lines and the first sub-inclined segments arranged in the same layer as the data lines are alternately arranged along the row direction.

[0031] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the array substrate further includes: a gate insulating layer located between the gate line and the data line, and a passivation layer located between the data line and the common electrode;

[0032] The other end of the first sub-inclined segment disposed in the same layer as the scan line is electrically connected to a transition portion via a via hole penetrating the gate insulating layer, the transition portion is electrically connected to one end of the corresponding transparent conductive portion via a via hole penetrating the passivation layer, and the other end of the transparent conductive portion is electrically connected to one end of the corresponding second sub-inclined segment via a via hole penetrating the passivation layer; wherein the transition portion is disposed in the same layer as the data line;

[0033] Alternatively, the other end of the first sub-inclined segment arranged in the same layer as the scan line is electrically connected to one end of the corresponding transparent conductive portion through a via hole penetrating the gate insulation layer and the passivation layer, and the other end of the transparent conductive portion is electrically connected to one end of the corresponding second sub-inclined segment through a via hole penetrating the passivation layer.

[0034] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the other end of the first sub-inclined segment arranged in the same layer as the data line is electrically connected to one end of the corresponding transparent conductive portion through a via hole penetrating the passivation layer, and the other end of the transparent conductive portion is electrically connected to one end of the corresponding second sub-inclined segment through a via hole penetrating the passivation layer.

[0035] In a possible implementation, in the above-mentioned special-shaped display panel provided by the embodiment of the present disclosure, the via structure corresponding to the first sub-inclined segment arranged in the same layer as the scan line and the via structure corresponding to the first sub-inclined segment arranged in the same layer as the data line are located in different rows.

[0036] In a possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the multiple via structures between each of the first sub-inclined segments and each of the second sub-inclined segments along the direction from the edge of the driving chip to the center of the driving chip are divided into multiple via areas, and along the direction from the edge of the driving chip to the center of the driving chip, two adjacent via areas form a step structure.

[0037] In a possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, a plurality of virtual routing lines are arranged between the first sub-inclined segments to which two adjacent via structures in two adjacent via areas are electrically connected, and the extension direction of the virtual routing lines is the same as the extension direction of the first sub-inclined segments, and the virtual routing lines include a plurality of sub-virtual routing lines that are disconnected.

[0038] In a possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the width of the inclined segment is smaller than the width of the vertical segment, and the width of the gap between adjacent inclined segments is smaller than the width of the gap between adjacent vertical segments.

[0039] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, a protective layer is provided on a side of the vertical segment facing away from the second substrate, and the protective layer is provided on the same layer as the common electrode.

[0040] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the width of the vertical segment along the row direction is less than or equal to the width of the protective layer along the row direction.

[0041] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, the array substrate further includes an anti-static circuit corresponding to the peripheral area, which is arranged between the first common electrode ring and the display area and surrounds a portion of the display area, and the anti-static circuit is arranged opposite to the driver chip binding area.

[0042] The anti-static circuit is electrically connected to the other end of the data line, and is used to release static electricity accumulated on the data line through a static electricity release end.

[0043] In a possible implementation, in the above-mentioned special-shaped display panel provided by an embodiment of the present disclosure, the driver chip binding area further includes ET test residual traces on both sides along the row direction, and the driver chip binding area further includes an ET test circuit; wherein, the ET test residual traces include cut residual traces and leads, the cut ends of the cut residual traces are wrapped with an insulating layer, one end of the cut residual traces away from the cut end is electrically connected to one end of the lead, and the other end of the lead is electrically connected to the ET test circuit; wherein,

[0044] The pixel electrode layer is located between the data line and the second substrate. The ET test residual trace is provided in the same layer as the pixel electrode layer. The cut end of the ET test residual trace is wrapped with an insulating layer.

[0045] In one possible implementation, in the above-mentioned special-shaped display panel provided in an embodiment of the present disclosure, a portion of the edge display pixels located in the display area is blocked by the black matrix layer, and in each row of the display pixels, the area of ​​each edge display pixel in each row of the display pixels blocked by the black matrix layer gradually decreases from a direction where the overlapping area between the display area and the edge display pixels is small to a direction where the overlapping area is large.

[0046] In a possible implementation, in the above-mentioned special-shaped display panel provided by the embodiment of the present disclosure, the areas of the sub-pixels in the same edge display pixel blocked by the black matrix layer are the same.

[0047] In a possible implementation, in the above-mentioned irregular display panel provided by an embodiment of the present disclosure, a region of each sub-pixel blocked by the black matrix layer is close to the irregular boundary.

[0048] In a possible implementation, in the above-mentioned special-shaped display panel provided in the embodiment of the present disclosure, the shape of the special-shaped display panel includes a circle or an ellipse.

[0049] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned special-shaped display panels provided by the embodiment of the present disclosure.

[0050] In a possible implementation, in the above-mentioned display device provided in the embodiment of the present disclosure, the display device is a vehicle-mounted display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1 is a schematic plan view of a special-shaped display panel provided by an embodiment of the present disclosure;

[0052] FIG2 is an enlarged structural diagram of the dotted box E in FIG1 ;

[0053] FIG3 is a plan view of a row of sub-pixels corresponding to the display area AA and the peripheral area BB in the color filter substrate;

[0054] FIG4 is a schematic cross-sectional view along the DD′ direction in FIG3 ;

[0055] FIG5 is a plan view schematically showing a color filter substrate and an array substrate;

[0056] FIG6 is another schematic plan view of a special-shaped display panel;

[0057] FIG7 is an enlarged schematic diagram of the fan-out area;

[0058] FIG8 is a schematic diagram of the specific structure of the first gate drive circuit GOA1 in FIG6;

[0059] FIG9 is an enlarged schematic diagram of the dotted box M1 and the dotted box M2 in FIG8 ;

[0060] FIG10 is an enlarged schematic diagram of the first common electrode ring COM1 and the second common electrode ring COM2;

[0061] FIG11 is a schematic diagram of the enlarged structure within the dotted box Q in FIG6 ;

[0062] FIG12 is a schematic diagram of the enlarged structure within the dotted frame R in FIG6 ;

[0063] FIG13 is a schematic diagram of the enlarged structure within the dotted box K in FIG6 ;

[0064] FIG14 is a schematic diagram of the enlarged structure within the dotted frame Z in FIG13;

[0065] FIG15 is a schematic diagram of the enlarged structure within the dotted box J in FIG13 ;

[0066] FIG16 is a schematic cross-sectional view taken along the CC' direction in FIG15;

[0067] FIG17 is another cross-sectional schematic diagram along the CC' direction in FIG15;

[0068] FIG18 is another cross-sectional schematic diagram along the EE' direction in FIG15;

[0069] FIG19 is a partial enlarged schematic diagram of FIG15;

[0070] FIG20 is a schematic cross-sectional view taken along the AA′ direction in FIG14 ;

[0071] FIG21 is a schematic cross-sectional view along the BB′ direction in FIG14 ;

[0072] FIG22 is a schematic diagram of the structure of the vertical section and the protective layer;

[0073] FIG23 is a schematic structural diagram of an anti-static circuit;

[0074] FIG24 is an enlarged plan view of the area within the dotted box N in FIG13 ;

[0075] FIG25 is a schematic cross-sectional view taken along the FF′ direction in FIG24 ;

[0076] FIG26 is a schematic diagram of the structure of the grounding wire;

[0077] FIG. 27 is a schematic diagram showing a structure in which edge display pixels are blocked by a light shielding layer. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0079] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0080] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0081] As automotive displays become increasingly integrated with vehicle bodies, requirements for bezels are becoming increasingly stringent. Demand for custom-shaped and circular automotive displays is increasing, while also placing high demands on reliability. The inventors of this case discovered that existing custom-shaped automotive displays suffer from low display quality, reliability, and yield rates due to poor pattern uniformity caused by etching and exposure at the edges of the custom-shaped display area.

[0082] To address the issues of low display quality, reliability, and yield rate in existing automotive-mounted special-shaped display screens, an embodiment of the present disclosure provides a special-shaped display panel. As shown in FIG1 , FIG1 is a planar schematic diagram of the special-shaped display panel. The special-shaped display panel includes a display area AA and a peripheral area BB disposed around the display area AA, with a special-shaped boundary L between the display area AA and the peripheral area BB. As shown in FIG2 , FIG2 is an enlarged structural schematic diagram of the dotted box E in FIG1 . The display area AA includes a plurality of display pixels P arranged in an array along a row direction X and a column direction Y. The display pixels P include a plurality of display sub-pixels sp having different luminous colors. The plurality of display pixels P include edge display pixels PA covered by the special-shaped boundary L and regular display pixels PB not covered by the special-shaped boundary L.

[0083] The special-shaped display panel includes an array substrate and a color filter substrate that are arranged oppositely and spaced apart, as shown in Figures 3 and 4. Figure 3 is a plan view of a row of sub-pixels in the color filter substrate corresponding to the display area AA and the peripheral area BB, and Figure 4 is a cross-sectional view along the DD' direction in Figure 3. The color filter substrate includes:

[0084] A first substrate 1, the first substrate 1 corresponding to the peripheral area BB having a virtual display area PD arranged around the display area AA, the virtual display area PD including a plurality of virtual pixels PN arranged around the edge display pixel PA, the virtual pixel PN including a plurality of virtual sub-pixels np with different luminous colors;

[0085] A black matrix layer 2 is located on the side of the first substrate 1 facing the array substrate. The black matrix layer 2 covers the display area AA and the virtual display area PD. The black matrix layer 2 is provided with an opening corresponding to each display sub-pixel sp located in the display area AA.

[0086] Multiple filter structures 3 are located on the side of the black matrix layer 2 away from the first substrate 1. The filter structure 3 is filled in the opening in the display area AA. The filter structure 3 is set at the position of the virtual sub-pixel np in the virtual display area PD on the side of the black matrix layer 2 away from the first substrate 1.

[0087] The above-mentioned special-shaped display panel provided by the embodiment of the present disclosure can effectively improve the etching uniformity of the position of the special-shaped display area by setting virtual pixels around the display area in the peripheral area, that is, the virtual pixels are located outside the special-shaped boundary, and effectively solve the problems of low display quality, reliability and yield rate of existing vehicle-mounted special-shaped display screens.

[0088] It should be noted that the irregular boundary in the embodiment of the present disclosure refers to the boundary between the display area AA and the peripheral area BB.

[0089] It should be noted that the edge display pixels covered by the irregular-shaped boundary, wherein covering means that the orthographic projections of the display pixels and the irregular-shaped boundary on the first substrate overlap.

[0090] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG2 , a display pixel P may include three sub-pixels sp having different luminous colors, for example, R (red), G (green), and B (blue). Of course, a display pixel P in the embodiments of the present disclosure is not limited to the above-mentioned case of including three sub-pixels. For example, a display pixel P may also include four sub-pixels, for example, R (red), G (green), B (blue), and white (W).

[0091] In some embodiments, the shape of the special-shaped display panel provided by the embodiments of the present disclosure may include, but is not limited to, a circle or an ellipse having a special-shaped display area. The embodiments of the present disclosure take a circular shape of the special-shaped display panel as an example, as shown in FIG1 , where the shape of the special-shaped boundary L is a circle. In order to ensure that the edge display pixels PA covered by the special-shaped boundary L have etching uniformity with conventional display pixels PB, it is necessary to ensure that pixels are provided on the top, bottom, left, and right sides of each edge display pixel PA. This ensures etching uniformity of the edge display pixels PA. Because some edge display pixels PA have a peripheral area BB on their row direction X side, some edge display pixels PA have a peripheral area BB on their column direction Y side, and some edge display pixels PA have both a peripheral area BB on their row direction X side and their column direction Y side, the present disclosure provides at least one virtual pixel PN on the row direction X side of some edge display pixels PA, provides at least one virtual pixel PN on the column direction Y side of some edge display pixels PA, and provides at least one virtual pixel PN on both the row direction X and column direction Y sides of some edge display pixels PA.

[0092] In some embodiments, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in FIG5 , FIG5 is a plan view schematic diagram of a color filter substrate and an array substrate. The array substrate includes a second substrate and a pixel electrode layer disposed on the side of the second substrate facing the color filter substrate. The pixel electrode layer includes a display pixel electrode 41 disposed corresponding to each display sub-pixel sp and a dummy pixel electrode 42 disposed corresponding to some dummy sub-pixels np, and the dummy pixel electrode 42 is disposed on one side of the edge of at least one row of display pixel electrodes 41. Thus, when the pixel electrode layer is manufactured using an etching process, by disposing the dummy pixel electrode 42 on one side of the edge of at least one row of display pixel electrodes 41, the etching uniformity of the pixel electrode layer can be improved, thereby improving the display quality, reliability, and product quality of the vehicle-mounted special-shaped display screen.

[0093] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 5 to 7, Figure 6 is another planar schematic diagram of the special-shaped display panel, Figure 5 is an enlarged structural schematic diagram within the dotted box F in Figure 6, and Figure 7 is an enlarged schematic diagram of the fan-out area. The array substrate corresponds to the peripheral area BB and includes: a driver chip binding area (represented by IC), and a fan-out area BP located between the driver chip binding area IC and the display area AA and arranged around at least a portion of the display area AA. The fan-out area BP is arranged in a conformal manner around the display area AA; the fan-out area BP includes a plurality of fan-out traces 5; wherein,

[0094] The orthographic projections of the filter structures 3 corresponding to at least some of the virtual sub-pixels np on the second substrate overlap with the orthographic projections of at least some of the fan-out traces 5 on the second substrate. This is because the color filter substrate does not have traces disposed within the peripheral area BB corresponding to the color filter substrate. Therefore, there is no spatial restriction on the color filter substrate corresponding to the peripheral area BB. That is, a large number of virtual pixels PN can be disposed in the peripheral area BB corresponding to the color filter substrate to ensure that each edge display pixel PA is surrounded by pixels, thereby achieving uniform etching of the edge display pixels PA.

[0095] The orthographic projection of the virtual pixel electrode 42 on the second substrate does not overlap with the orthographic projection of the fan-out trace 5 on the second substrate. This is because the array substrate needs to be provided with a fan-out trace 5 corresponding to the peripheral area BB, and the fan-out trace 5 is generally made of the material of the pixel electrode layer. In order to avoid a short circuit between the virtual pixel electrode 42 and the fan-out trace 5, only a small area (the area close to the display area AA) of the array substrate corresponding to the peripheral area BB is used to set the virtual pixel electrode 42 to ensure that the orthographic projection of the virtual pixel electrode 42 on the second substrate does not overlap with the orthographic projection of the fan-out trace 5 on the second substrate.

[0096] It should be noted that, as shown in Figures 4 and 5, the structural design of the virtual pixels PN and display pixels P corresponding to the color filter substrate is the same. For example, each display pixel P corresponding to the color filter substrate includes R (red), G (green), and B (blue) display sub-pixels sp, and each display sub-pixel sp is correspondingly provided with a filter structure 3. The virtual pixel PN also includes R (red), G (green), and B (blue) virtual sub-pixels np, and each virtual sub-pixel np is also correspondingly provided with a filter structure 3. However, the difference between the display pixel P and the virtual pixel PN is that the filter structure 3 corresponding to each display sub-pixel sp is provided in the opening of the black matrix layer 2, while the filter structure 3 corresponding to the virtual sub-pixel np is blocked by the black matrix layer 2.

[0097] It should be noted that, as shown in FIG5 , since the color filter substrate is not provided with wiring corresponding to the peripheral area BB, its peripheral area BB is not spatially restricted. Therefore, a larger number of filter structures 3 can be provided in the peripheral area BB corresponding to the color filter substrate, while the array substrate needs to be provided with fan-out wiring 5 corresponding to the peripheral area BB. Therefore, the array substrate has only a very small space corresponding to the peripheral area B to provide the virtual pixel electrode 42. Therefore, the virtual pixel electrode 42 provided on the array substrate corresponding to the peripheral area BB is only provided corresponding to the portion of the filter structure 3 provided on the color filter substrate corresponding to the peripheral area BB. That is, there is a portion of the filter structure 3 on the color filter substrate, and no virtual pixel electrode 42 is provided on the array substrate directly below it.

[0098] It should be noted that, as shown in Figure 5, the pixel structure design of the array substrate corresponding to the positions of the display pixel electrode 41 and the virtual pixel electrode 42 is the same. For example, the display pixel electrode 41 and the virtual pixel electrode 42 are both electrically connected to the corresponding pixel driving circuit, and the pixel driving circuit corresponding to the display pixel electrode 41 and the pixel driving circuit corresponding to the virtual pixel electrode 42 are respectively electrically connected to the corresponding gate line and data line, that is, the display pixel electrode 41 and the virtual pixel electrode 42 can respectively input data signals thereto through the data line; but the difference between the positions of the display pixel electrode 41 and the virtual pixel electrode 42 is that the virtual pixel electrode 42 is blocked by the black matrix layer 2 on the color filter substrate, while the display pixel electrode 41 is set corresponding to the opening of the black matrix layer 2 on the color filter substrate.

[0099] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG5 and FIG6 , the array substrate includes, corresponding to the display area AA: a plurality of scan lines G extending along the row direction X and arranged along the column direction Y, and a plurality of data lines S extending along the column direction Y and arranged along the row direction X; wherein the plurality of scan lines G and the plurality of data lines S are insulated and cross-linked to define a plurality of display pixels P, and the driver chip binding area IC is located on one side of the extending direction of the plurality of data lines S;

[0100] The array substrate further includes a first gate drive circuit GOA1 and a second gate drive circuit GOA2 located on both sides of the extending direction of the plurality of scan lines G, corresponding to the peripheral area BB. The first gate drive circuit GOA1 is electrically connected to one end of each scan line G, and the second gate drive circuit GOA2 is electrically connected to the other end of each scan line G.

[0101] The first gate drive circuit GOA1 is located on a side of a portion of the fan-out area BP away from the display area AA, and the second gate drive circuit GOA2 is located on a side of another portion of the fan-out area BP away from the display area AA. Both the first gate drive circuit GOA1 and the second gate drive circuit GOA2 are conformally arranged around the display area AA. This conformal arrangement of the gate drive circuits around the display area AA allows the peripheral area BB to be nearly circular, meeting current customer design requirements for in-vehicle displays.

[0102] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiment of the present disclosure, as shown in Figures 6 and 8, Figure 8 is a specific structural diagram of the first gate drive circuit GOA1 in Figure 6, and the first gate drive circuit GOA1 and the second gate drive circuit GOA2 both include a plurality of shift register units 100 arranged in cascade, and each shift register unit 100 includes a charging transistor T arranged near the edge of the peripheral area BB; since the shape of the special-shaped display panel provided by the embodiment of the present disclosure is circular, the border of the circular screen is generally small, GOA1 and GOA2 need to be placed along the periphery of the fan-out area BP while ensuring that each shift register unit 100 is cascaded correctly. At the same time, since it is a vehicle-mounted special-shaped screen, the transistor characteristics in the shift register unit 100 require better uniformity, and the transistor cannot be designed to be rotated. At the same time, it is necessary to ensure that the outer edge area of ​​GOA1 and GOA2 wrapped by the frame sealant is greater than 200μm.

[0103] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 6 to 9, the left figure in Figure 9 is an enlarged schematic diagram within the dotted box M1 in Figure 8, and the right figure in Figure 9 is an enlarged schematic diagram within the dotted box M2 in Figure 8. Since GOA1 and GOA2 are placed along the periphery of the fan-out area BP, when the GOA starting end shift register unit 100 or the end shift register unit 100 or any shift register unit 100 in the peripheral area BB of the special-shaped display panel cannot meet the cascade requirements due to the size limitation of the peripheral area BB, the size of the shift register unit 100 along the row direction and the column direction can be changed, but the channel width-to-length ratio, direction and The angle remains unchanged. For example, in each gate drive circuit, there are at least two adjacent shift register units 100 (e.g., the first and second shift register units 100 from top to bottom in FIG8 ), wherein the width W1 of the charging transistor T of one shift register unit 100 (e.g., the first) along the row direction X is greater than the width W2 of the charging transistor T of the other shift register unit 100 (e.g., the second) along the row direction X, the height H1 of the charging transistor T of one shift register unit 100 (the first) along the column direction X is less than the height H2 of the charging transistor T of the other shift register unit 100 (the second) along the column direction X, and the channel width-to-length ratio of the charging transistors T of the two adjacent shift register units 100 is the same. In this way, while the gate drive circuit makes the outer frame of the special-shaped display panel closer to a circle and meets customer design requirements for special-shaped display panels, the reliability of the in-vehicle special-shaped display screen can be guaranteed.

[0104] In some embodiments, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figure 6, the specific structure of the shift register unit 100 in the first gate drive circuit GOA1 and the second gate drive circuit GOA2 is the same, and the first gate drive circuit GOA1 and the second gate drive circuit GOA2 are generally symmetrically arranged about the central area of ​​the special-shaped display panel. The specific working principles of the first gate drive circuit GOA1 and the second gate drive circuit GOA2 are the same as those in the related art, and the present disclosure does not explain this.

[0105] In some embodiments, in the above-described special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 6 and 10 (Figure 10 is an enlarged schematic diagram of the first common electrode ring COM1 and the second common electrode ring COM2), the array substrate further includes, corresponding to the peripheral area BB: a first common electrode ring COM1 disposed between the first gate drive circuit GOA1, the second gate drive circuit GOA2, and the display area AA; and a second common electrode ring COM2 disposed on a side of the first gate drive circuit GOA1 and the second gate drive circuit GOA2 away from the display area AA; the first common electrode ring COM1 and the second common electrode ring COM2 are electrically connected. The present disclosure employs a parallel design of the first and second common electrode rings COM1 and COM2, which can reduce the common electrode resistance and ensure a consistent film thickness in the peripheral area BB.

[0106] In some embodiments, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 6 and 10, the array substrate corresponds to the peripheral area BB and includes a spacing area BD located on the other side of the extension direction of the multiple data lines (column direction Y) and located between the first gate drive circuit GOA1 and the second gate drive circuit GOA2, and the first common electrode ring COM1 and the second common electrode ring COM2 are electrically connected in the spacing area BD, and the spacing area BD facilitates the electrical connection of the first common electrode ring COM1 and the second common electrode ring COM2.

[0107] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, the first common electrode ring and the second common electrode ring may be provided in the same layer as the data line, so that the first common electrode ring and the second common electrode ring are directly connected in the spacing area BD.

[0108] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, the first common electrode ring can be set in the same layer as the data line, and the second common electrode ring can be set in the same layer as the scan line, so that the first common electrode ring and the second common electrode ring need to be connected through a via in the spacing area BD.

[0109] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, the first common electrode ring can be arranged in the same layer as the data line, and the second common electrode ring can include a first sub-common electrode ring and a second sub-common electrode ring that are stacked and electrically connected to each other, the first sub-common electrode ring is arranged in the same layer as the data line, and the second sub-common electrode ring is arranged in the same layer as the scan line, so that the first sub-common electrode ring and the second sub-common electrode ring are connected through a via, and the first common electrode ring and the first sub-common electrode ring are directly connected in the spacing area BD.

[0110] It should be noted that the above merely lists several possible film layer positions of the first common electrode ring and the second common electrode ring, and is certainly not limited thereto.

[0111] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 11 and 12, Figure 11 is an enlarged schematic diagram of the structure within the dotted box Q in Figure 6, and Figure 12 is an enlarged schematic diagram of the structure within the dotted box R in Figure 6, the array substrate includes a common electrode 6 corresponding to the display area AA. The common electrode 6 is electrically connected to the first common electrode ring COM1 in the peripheral area BB through a via V. When the special-shaped display panel is in operation, the driver chip applies a common signal to the common electrode 6 through the first common electrode ring COM1.

[0112] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG13 and FIG14 , FIG13 is an enlarged schematic diagram of the structure within the dotted box K in FIG6 , and FIG14 is an enlarged schematic diagram of the structure within the dotted box Z in FIG13 , the fan-out trace 5 includes an inclined segment 51 arranged around the display area AA and a vertical segment 52 arranged along the extending direction S of the data line (column direction Y), and the vertical segment 52 is located between the display area AA and the driver chip binding area IC;

[0113] As shown in FIG15 , FIG15 is an enlarged schematic diagram of the structure within the dashed box J in FIG13 . The inclined segment 51 includes a first sub-inclined segment 511 and a second sub-inclined segment 512. One end of the first sub-inclined segment 511 is electrically connected to one end of the vertical segment 52, and the other end of the vertical segment 52 is electrically connected to the driver chip in the driver chip binding area IC. The other end of the first sub-inclined segment 511 is electrically connected to one end of the second sub-inclined segment 512 through a corresponding via structure H and a transparent conductive portion 7. The other end of the second sub-inclined segment 512 is electrically connected to one end S1 of the data line S. The fan-out trace 5 in the disclosed embodiment utilizes a skip-via design. This allows for static discharge through the vias for ESD protection, while also reducing the resistance of the fan-out trace 5 by electrically connecting the transparent conductive portion 7 to the metal trace through the vias.

[0114] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 15 to 18, Figure 16 is a cross-sectional schematic diagram along the CC' direction in Figure 15, Figure 17 is another cross-sectional schematic diagram along the CC' direction in Figure 15, and Figure 18 is a cross-sectional schematic diagram along the EE' direction in Figure 15, the gate line G is located between the second substrate 8 (the second substrate of the array substrate) and the data line S, the common electrode 6 is located on the side of the data line S away from the second substrate 8, the transparent conductive portion 7 is provided in the same layer as the common electrode 6, the second sub-inclined segment 512 is provided in the same layer as the data line S, and the first sub-inclined segment 511 and the vertical segment 52 that are electrically connected to each other are located in the same film layer;

[0115] A portion of the first sub-slanted segments 511 (indicated by 511') is arranged on the same layer as the scan line G, while another portion of the first sub-slanted segments 511 (indicated by 511") is arranged on the same layer as the data line S. The first sub-slanted segments 511' arranged on the same layer as the scan line G and the first sub-slanted segments 511" arranged on the same layer as the data line S are alternately arranged along the row direction X. By routing the first sub-slanted segments 511 in layers in the fan-out area BP, the wiring space in the fan-out area BP can be reduced, thereby facilitating a narrow bezel design.

[0116] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG15 and FIG16 , the array substrate further includes: a gate insulating layer GI located between the gate line G and the data line S, and a passivation layer PVX located between the data line S and the common electrode 6;

[0117] The other end of the first inclined sub-segment 511', provided on the same layer as the scan line G, is electrically connected to the transition portion 9 via a via penetrating the gate insulating layer GI. The transition portion 9 is electrically connected to one end of the corresponding transparent conductive portion 7 via a via penetrating the passivation layer PVX. The other end of the transparent conductive portion 7 is electrically connected to one end of the corresponding second inclined sub-segment 512 via a via penetrating the passivation layer PVX. The transition portion 9 is provided on the same layer as the data line S. In this way, the first inclined sub-segment 511' is electrically connected to the second inclined sub-segment 512 via the via, the transition portion 9, the via, the transparent conductive portion 7, and the via, achieving ESD protection and reducing fan-out traces 5.

[0118] In some embodiments, in the above-described special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 15 and 17 , the other end of the first sub-slanted segment 511′, disposed in the same layer as the scan line G, is electrically connected to one end of the corresponding transparent conductive portion 7 via a via hole penetrating the gate insulating layer GI and the passivation layer PVX. The other end of the transparent conductive portion 7 is electrically connected to one end of the corresponding second sub-slanted segment 512 via a via hole penetrating the passivation layer PVX. In this way, the first sub-slanted segment 511′ can be electrically connected to the second sub-slanted segment 512 via the via hole, the transparent conductive portion 7, and the via hole, achieving an ESD protection design and reducing the fan-out trace 5.

[0119] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 15 and 18, the other end of the first sub-inclined segment 511" arranged in the same layer as the data line S is electrically connected to one end of the corresponding transparent conductive portion 7 through a via hole penetrating the passivation layer PVX, and the other end of the transparent conductive portion 7 is electrically connected to one end of the corresponding second sub-inclined segment 512 through a via hole penetrating the passivation layer PVX. In this way, the first sub-inclined segment 511" can be electrically connected to the second sub-inclined segment 512 through the via hole, the transparent conductive portion 7 and the via hole, thereby achieving an anti-ESD design and reducing the purpose of the fan-out wiring 5.

[0120] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 15 and 19, Figure 19 is a partially enlarged schematic diagram of Figure 15, the via structure H corresponding to the first sub-inclined segment 511' provided on the same layer as the scan line S and the via structure H corresponding to the first sub-inclined segment 511" provided on the same layer as the data line S are located in different rows. This is conducive to the layout of the fan-out trace 5 and realizes a narrow frame design.

[0121] In some embodiments, to improve the electrostatic discharge capability, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 15, 16, and 19, the number of via holes penetrating the gate insulating layer GI between the first sub-inclined segment 511' and the transition portion 9, which are provided in the same layer as the scan line G, can be multiple. The embodiment of the present disclosure takes two as an example, and the two via holes can be arranged along the row direction. When the number of via holes penetrating the gate insulating layer GI is four or more, the multiple via holes can be distributed in an array. The number of via holes penetrating the passivation layer PVX between the transition portion 9 and the transparent conductive portion 7 can be multiple. The embodiment of the present disclosure takes two as an example, and the two via holes can be arranged along the row direction. When the number of via holes penetrating the passivation layer PVX is four or more, the multiple via holes can be distributed in an array. The number of via holes penetrating the passivation layer PVX between the transparent conductive portion 7 and the second sub-inclined segment 512 can be multiple. The embodiment of the present disclosure takes two as an example, and the two via holes can be arranged along the row direction. When the number of via holes penetrating the passivation layer PVX is four or more, the multiple via holes can be distributed in an array.

[0122] In some embodiments, in order to improve the electrostatic discharge capability, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 15, 17 and 19, the number of vias penetrating the gate insulating layer GI and the passivation layer PVX between the first sub-inclined segment 511' and the transparent conductive portion 7 arranged on the same layer as the scan line G can be multiple. The embodiment of the present disclosure takes two as an example, and the two vias can be arranged along the row direction. When the number of vias penetrating the gate insulating layer GI and the passivation layer PVX is four or more, the multiple vias can be distributed in an array; the number of vias penetrating the passivation layer PVX between the transparent conductive portion 7 and the second sub-inclined segment 512 can be multiple. The embodiment of the present disclosure takes two as an example, and the two vias can be arranged along the row direction. When the number of vias penetrating the passivation layer PVX is four or more, the multiple vias can be distributed in an array.

[0123] In some embodiments, in order to improve the electrostatic discharge capability, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 15, 18 and 19, the number of vias penetrating the passivation layer PVX between the first sub-inclined segment 511' and the transparent conductive portion 7 set with the data line S layer can be multiple. The embodiment of the present disclosure takes two as an example, and the two vias can be arranged along the row direction. When the number of vias penetrating the passivation layer PVX is four or more, the multiple vias can be distributed in an array; the number of vias penetrating the passivation layer PVX between the transparent conductive portion 7 and the second sub-inclined segment 512 can be multiple. The embodiment of the present disclosure takes two as an example, and the two vias can be arranged along the row direction. When the number of vias penetrating the passivation layer PVX is four or more, the multiple vias can be distributed in an array.

[0124] In some embodiments, in the above-described special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG15 , the multiple via structures H between each first sub-slanted segment 511 and each second sub-slanted segment 512 along the direction from the edge of the driver chip to the center of the driver chip (i.e., the row direction X) are divided into multiple via areas (the three dashed boxes represent three via areas, but are of course not limited to three). Furthermore, along the direction from the edge of the driver chip to the center of the driver chip, two adjacent via areas form a stepped structure. This staggered via design facilitates a narrow bezel design.

[0125] In some embodiments, in the above-described special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG15 , a plurality of dummy routing lines 500 are disposed between the first sub-sloped segments 511 electrically connected to two adjacent via structures H in two adjacent via regions. The dummy routing lines 500 extend in the same direction as the first sub-sloped segments 511, and the dummy routing lines 500 include multiple sub-dummy routing lines that are disconnected. Specifically, a portion of the dummy routing lines 500 is disposed on the same layer as the scan lines G, while another portion of the dummy routing lines 500 is disposed on the same layer as the data lines S. The dummy routing lines 500 disposed on the same layer as the scan lines G and the dummy routing lines 500 disposed on the same layer as the data lines S are alternately disposed along the row direction X.

[0126] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 20 and 21, Figure 20 is a schematic cross-sectional view along the AA' direction in Figure 14, and Figure 21 is a schematic cross-sectional view along the BB' direction in Figure 14. The width of the inclined segment 51 is smaller than the width of the vertical segment 52, and the width of the gap between adjacent inclined segments 51 is smaller than the width of the gap between adjacent vertical segments 52. This is because the width of the lower frame in the peripheral area BB is wider than the width of the left and right frames, so the lower frame has more space for the layout of the vertical segment 52. Therefore, the width of the vertical segment 52 can be increased to reduce resistance, and the width of the gap between adjacent vertical segments 52 can be designed to be wider to prevent short circuits between adjacent traces.

[0127] In some embodiments, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 20 and 21, the width of the inclined segment 51 can be about 2.9 μm, the width of the vertical segment 52 can be 6 μm, the gap width between adjacent inclined segments 51 can be 4.35 μm, and the gap width between adjacent vertical segments 52 can be 5 μm. Of course, it is not limited to this and is designed according to the specific space of the peripheral area B.

[0128] In some embodiments, in the above-described special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 21 and 22, a protective layer 20 is provided on the side of the vertical segment 52 facing away from the second substrate. The protective layer 20 is provided on the same layer as the common electrode 6. Since the common electrode 6 is generally made of ITO, the protective layer 20 made of ITO can prevent the vertical segment 52 of the metal material below from being corroded by water and oxygen, etc. In this way, the pattern of the protective layer 20 and the common electrode 6 can be formed in a single patterning process, simply by changing the original pattern when forming the common electrode 6. There is no need to add a separate process for preparing the protective layer 20, which can simplify the preparation process, save production costs, and improve production efficiency.

[0129] In some embodiments, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figure 22, the width of the vertical segment 52 along the row direction X can be less than or equal to the width of the protective layer 20 along the row direction X, which can further effectively prevent the vertical segment 52 of the metal material from being corroded by water and oxygen.

[0130] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG6 , FIG12 , and FIG23 , FIG23 is an enlarged schematic diagram of the anti-static circuit in FIG6 , the array substrate further includes an anti-static circuit 200 corresponding to the peripheral area BB, which is arranged between the first common electrode ring COM1 and the display area AA and surrounds a portion of the display area AA. The anti-static circuit 200 is arranged opposite to the driver chip binding area IC, that is, the anti-static circuit 200 is arranged on the side of the other end S2 of the data line S.

[0131] The anti-static circuit 200 is electrically connected to the other end S2 of the data line S. The anti-static circuit 200 is used to release static electricity accumulated on the data line S through the static discharge terminal. Specifically, the structure of the anti-static circuit 200 is shown in Figure 12. The anti-static circuit 200 includes multiple sub-circuits connected in series. The sub-circuits are composed of a number of transistors. Each sub-circuit is electrically connected to the other end S2 of the data line S. The specific structure of the anti-static circuit 200 can be the same as that in the related art and will not be described in detail in this disclosure.

[0132] It should be noted that the present disclosure can improve the anti-static effect by simultaneously releasing static electricity from the data line S by using the via structure H connected to one end S1 of the data line and the anti-static circuit 200 connected to the other end S2 of the data line S as shown in Figure 15.

[0133] It should be noted that the one end S1 of the data line S refers to the end close to the driver chip binding area IC, and the other end S2 of the data line S refers to the end opposite to the one end S1 of the data line S.

[0134] It should be noted that the peripheral area BB can be approximately divided into an upper frame, a lower frame, a left frame and a right frame, the driver chip binding area IC is located in the lower frame, and the anti-static circuit 200 is located in the upper frame.

[0135] In some embodiments, in the above-mentioned special-shaped display panel provided by the embodiments of the present disclosure, as shown in Figures 13, 24 and 25, Figure 24 is an enlarged plan view within the dotted box N in Figure 13, and Figure 25 is a cross-sectional view along the FF' direction in Figure 24. The driver chip binding area IC also includes ET test residual traces 300 on both sides along the row direction, and the driver chip binding area IC also includes an ET test circuit; wherein, the ET test residual trace 300 includes a cutting residual trace 301 and a lead 302, the cutting end of the cutting residual trace 301 is wrapped with an insulating layer 400, and the end of the cutting residual trace 301 away from the cutting end is electrically connected to one end of the lead 302, and the other end of the lead 302 is electrically connected to the ET test circuit; wherein,

[0136] The pixel electrode layer is located between the data line S and the second substrate, and the ET test residual trace 300 can be set in the same layer as the pixel electrode layer. Specifically, due to the limited size of the frame, it is impossible to design an ET test PAD in the special-shaped display panel. The present disclosure designs the ET test PAD on both sides of the driver chip binding area IC, which can be cut into a rectangular display panel for ET testing first, and then cut into a special-shaped display panel of standard size after the test is completed; and the present disclosure wraps the cut end of the cut residual trace 301 with an insulating layer 400, that is, after the ET test PAD is removed, it is necessary to apply the insulating layer 400 to the cut end to prevent the cut residual trace 301 from being exposed at the cut end. This is because when the product is in a high temperature and high humidity environment, the cut end may attract water vapor into the panel, causing circuit board corrosion, product abnormality, and thus reliability issues.

[0137] In some embodiments, the ET test circuit provided by the embodiments of the present disclosure may be the same as that in the related art.

[0138] In some embodiments, in order to shield the interference of external signals on the internal circuit of the display panel, in the above-mentioned special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 6 and 26, the peripheral area BB also includes a ground wire GND arranged on the side of the second common electrode ring COM2 away from the display area AA and surrounding the display area AA, and the side of the driver chip binding area IC away from the display area AA includes a flexible circuit board (FPC), and the ground wire GND can be electrically connected to the ground terminal on the flexible circuit board FPC through silver glue.

[0139] Due to the shape limitations of the special-shaped display panel, a jagged effect is easily displayed at the edge of the display area. To reduce this jagged effect, in the special-shaped display panel provided in the embodiments of the present disclosure, as shown in Figures 2-5 and 27, portions of the edge display pixels PA located in the display area AA are shielded by the black matrix layer 2 to form a special-shaped boundary L. Within each row of display pixels P, the area of ​​each edge display pixel PA shielded by the black matrix layer 2 gradually decreases from the direction aa where the overlap area between the display area AA and the edge display pixels PA is small to the direction aa where the overlap area is large. This reduces the transmittance of the sub-pixels sp in the edge display pixels PA closer to the special-shaped boundary L, thereby reducing the jaggies. At the same time, the further away from the edge display pixel PA is from the irregular boundary L, the higher the transmittance of the sub-pixel sp is, so that the brightness of the sub-pixel sp can be gradually increased along the aa direction, and a uniform brightness transition can be achieved, thereby reducing the brightness difference between adjacent edge display pixels PA, and making the brightness of multiple edge display pixels PA arranged in sequence in the same row smoothly transition, thereby further weakening the visual effect of the jagged feeling in the area where the irregular boundary L is located during the display process, and improving the display effect of the irregular display panel.

[0140] In some embodiments, in the above-described special-shaped display panel provided by the embodiments of the present disclosure, as shown in FIG13 , FIG24 , and FIG25 , each sub-pixel sp in the same edge display pixel PA has the same area blocked by the black matrix layer 2. This ensures that each sub-pixel sp in the same edge display pixel PA has the same light transmittance, thereby preventing the problem of a single color in the same edge display pixel PA being too bright.

[0141] In some embodiments, in the above-described irregular display panel provided by the embodiments of the present disclosure, as shown in Figures 13, 24, and 25, the area of ​​each sub-pixel sp blocked by the black matrix layer 2 is close to the irregular boundary. This allows for uniform brightness from the edge of the display area AA to the center, resulting in a smooth brightness transition from the edge of the display area AA to the center, further reducing the jagged effect at the irregular boundary L.

[0142] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising any of the aforementioned special-shaped display panels provided in the embodiments of the present disclosure. This display device may be, for example, an in-vehicle display screen or a watch. The implementation of this display device can refer to the aforementioned special-shaped display panel embodiments, and any repetitive details will not be repeated.

[0143] In some embodiments, in the above-mentioned display device provided in the embodiments of the present disclosure, the display device of the present disclosure may be a liquid crystal display device.

[0144] In some embodiments, among the above-mentioned display devices provided in the embodiments of the present disclosure, the display device of the present disclosure may be a vehicle-mounted display device.

[0145] The embodiments of the present disclosure provide a special-shaped display panel and a display device. By setting virtual pixels around the display area in the peripheral area, that is, the virtual pixels are located outside the special-shaped boundary, the etching uniformity of the position of the special-shaped display area can be effectively improved, and the problems of low display quality, reliability and yield rate of existing vehicle-mounted special-shaped display screens can be effectively solved.

[0146] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0147] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An irregular display panel, wherein, It includes a display area and a peripheral area disposed around the display area, with an irregular boundary between the display area and the peripheral area; the display area includes a plurality of display pixels arranged in an array along the row direction and the column direction, and the display pixels include a plurality of display sub-pixels with different emission colors; among the plurality of display pixels, there are edge display pixels covered by the irregular boundary and regular display pixels not covered by the irregular boundary; The irregular display panel includes an array substrate and a color filter substrate that are opposite and spaced apart, and the color filter substrate includes: A first substrate, which has a virtual display area disposed around the display area corresponding to the peripheral area. The virtual display area includes a plurality of virtual pixels disposed around the edge display pixels, and the virtual pixels include a plurality of virtual sub-pixels with different emission colors; A black matrix layer, located on the side of the first substrate facing the array substrate. The black matrix layer covers the display area and the virtual display area, and the black matrix layer is provided with openings corresponding to each of the display sub-pixels located in the display area; A plurality of filter structures, located on the side of the black matrix layer away from the first substrate. The filter structures are filled in the openings in the display area, and the filter structures are disposed on the side of the black matrix layer away from the first substrate at positions corresponding to the virtual sub-pixels in the virtual display area.

2. The shaped display panel according to claim 1, wherein, At least one of the virtual pixels is disposed on one side in the row direction and / or one side in the column direction of each of the edge display pixels.

3. The shaped display panel according to claim 1 or 2, wherein, The array substrate includes a second substrate and a pixel electrode layer disposed on the side of the second substrate facing the color filter substrate. The pixel electrode layer includes display pixel electrodes corresponding to each of the display sub-pixels and virtual pixel electrodes corresponding to some of the virtual sub-pixels, and the virtual pixel electrodes are disposed on one side of the edge of at least one row of the display pixel electrodes.

4. The shaped display panel according to claim 3, wherein, The array substrate corresponding to the peripheral area includes: a driver chip bonding area, and a fan-out area located between the driver chip bonding area and the display area and disposed around at least part of the display area; the fan-out area includes a plurality of fan-out traces; wherein, The orthographic projection of the filter structure corresponding to at least part of the virtual sub-pixels on the second substrate and the orthographic projection of at least part of the fan-out traces on the second substrate have an overlapping area; The orthographic projection of the virtual pixel electrode on the second substrate and the orthographic projection of the fan-out traces on the second substrate do not overlap.

5. The shaped display panel according to claim 4, wherein, The array substrate corresponding to the display area includes: a plurality of scan lines extending along the row direction and arranged along the column direction, and a plurality of data lines extending along the column direction and arranged along the row direction; wherein, the plurality of scan lines and the plurality of data lines are insulated and crossed to define the plurality of display pixels, and the driver chip bonding area is located on one side in the extending direction of the plurality of data lines; The array substrate further includes a first gate driving circuit and a second gate driving circuit located on both sides of the extending direction of the plurality of scanning lines corresponding to the peripheral region. The first gate driving circuit is electrically connected to one end of each of the scanning lines, and the second gate driving circuit is electrically connected to the other end of each of the scanning lines; Wherein, the first gate driving circuit is located on one side of a part of the fan-out region away from the display region, the second gate driving circuit is located on one side of another part of the fan-out region away from the display region, and both the first gate driving circuit and the second gate driving circuit are arranged conformally around the display region.

6. The special-shaped display panel according to claim 5, wherein, Both the first gate driving circuit and the second gate driving circuit include a plurality of cascaded shift register units. Each shift register unit includes a charging transistor disposed near the edge of the peripheral region; wherein, At least in two adjacent shift register units, the width of the charging transistor of one shift register unit is greater than that of the charging transistor of the other shift register unit, the height of the charging transistor of the one shift register unit is less than that of the charging transistor of the other shift register unit, and the channel width-to-length ratios of the charging transistors of the two adjacent shift register units are the same.

7. The special-shaped display panel according to claim 5 or 6, wherein, The array substrate further includes, corresponding to the peripheral region: a first common electrode ring disposed between the first gate driving circuit, the second gate driving circuit and the display region, and a second common electrode ring disposed on the side of the first gate driving circuit and the second gate driving circuit away from the display region; the first common electrode ring and the second common electrode ring are electrically connected.

8. The special-shaped display panel according to claim 7, wherein, The array substrate includes, corresponding to the peripheral region, a spacer region located on the other side of the extending direction of the plurality of data lines and between the first gate driving circuit and the second gate driving circuit. The first common electrode ring and the second common electrode ring are electrically connected in the spacer region.

9. The shaped display panel according to claim 8, wherein, The first common electrode ring is disposed on the same layer as the data lines; The second common electrode ring is disposed on the same layer as the data lines or the scanning lines; Or, the second common electrode ring includes a first sub-common electrode ring and a second sub-common electrode ring which are stacked and electrically connected to each other. The first sub-common electrode ring is disposed on the same layer as the data lines, and the second sub-common electrode ring is disposed on the same layer as the scanning lines.

10. The shaped display panel according to claim 9, wherein, The fan-out routing includes an inclined segment disposed around the display region and a vertical segment disposed along the extending direction of the data lines. The vertical segment is located between the display region and the driving chip bonding region; The inclined segment includes a first sub-inclined segment and a second sub-inclined segment. One end of the first sub-inclined segment is electrically connected to one end of the vertical segment, the other end of the vertical segment is electrically connected to the driving chip in the driving chip bonding region, the other end of the first sub-inclined segment is connected to one end of the second sub-inclined segment through a corresponding via structure and a transparent conductive portion, and the other end of the second sub-inclined segment is electrically connected to one end of the data line.

11. The special-shaped display panel according to claim 10, wherein, The array substrate includes a common electrode corresponding to the display area, and the common electrode is electrically connected to the first common electrode ring through a via hole in the peripheral area; The gate line is located between the second substrate and the data line, and the common electrode is located between the On a side of the data line away from the second substrate, the transparent conductive portion is disposed in the same layer as the common electrode, the second sub-inclined segment is disposed in the same layer as the data line, and the first sub-inclined segment and the vertical segment electrically connected to each other are located in the same film layer; A portion of the first sub-slanted segments are arranged in the same layer as the scan lines, another portion of the first sub-slanted segments are arranged in the same layer as the data lines, and the first sub-slanted segments arranged in the same layer as the scan lines and the first sub-slanted segments arranged in the same layer as the data lines are alternately arranged along the row direction.

12. The shaped display panel according to claim 11, wherein, The array substrate further comprises: a gate insulating layer located between the gate line and the data line, and a passivation layer located between the data line and the common electrode; The other end of the first sub-inclined segment disposed in the same layer as the scan line is electrically connected to the transition portion through a via hole penetrating the gate insulating layer, the transition portion is electrically connected to one end of the corresponding transparent conductive portion through a via hole penetrating the passivation layer, and the other end of the transparent conductive portion is electrically connected to one end of the corresponding second sub-inclined segment through a via hole penetrating the passivation layer; wherein the transition portion is disposed in the same layer as the data line; Alternatively, the other end of the first sub-inclined segment arranged in the same layer as the scanning line is electrically connected to one end of the corresponding transparent conductive portion through a via hole penetrating the gate insulating layer and the passivation layer, and the other end of the transparent conductive portion is electrically connected to one end of the corresponding second sub-inclined segment through a via hole penetrating the passivation layer.

13. The shaped display panel according to claim 12, wherein, The other end of the first sub-inclined segment arranged in the same layer as the data line is electrically connected to one end of the corresponding transparent conductive portion through a via hole penetrating the passivation layer, and the other end of the transparent conductive portion is electrically connected to one end of the corresponding second sub-inclined segment through a via hole penetrating the passivation layer.

14. The shaped display panel according to claim 13, wherein, The via structure corresponding to the first sub-inclined segment arranged in the same layer as the scan line and the via structure corresponding to the first sub-inclined segment arranged in the same layer as the data line are located in different rows.

15. The shaped display panel according to claim 14, wherein, The multiple via structures between each of the first sub-inclined sections and each of the second sub-inclined sections along the direction from the edge of the driving chip to the center of the driving chip are divided into multiple via areas, and in the direction from the edge of the driving chip to the center of the driving chip, two adjacent via areas form a step structure.

16. The special-shaped display panel according to claim 15, wherein, A plurality of virtual routing lines are arranged between the first sub-inclined sections electrically connected to two adjacent via structures of two adjacent via areas, the extension direction of the virtual routing lines is the same as the extension direction of the first sub-inclined sections, and the virtual routing lines include a plurality of sub-virtual routing lines that are disconnected.

17. The shaped display panel according to any one of claims 10-16, wherein, The width of the inclined segment is smaller than the width of the vertical segment, and the width of the gap between adjacent inclined segments is smaller than the width of the gap between adjacent vertical segments.

18. The shaped display panel according to claim 17, wherein, A protective layer is disposed on a side of the vertical section facing away from the second substrate, and the protective layer is disposed on the same layer as the common electrode.

19. The shaped display panel according to claim 18, wherein, The width of the vertical segment along the row direction is less than or equal to the width of the protective layer along the row direction.

20. The special-shaped display panel according to any one of claims 7-19, wherein, The array substrate further includes an anti-static circuit corresponding to the peripheral region, which is disposed between the first common electrode ring and the display region and surrounds a part of the display region, and the anti-static circuit is disposed opposite to the driving chip bonding region; The anti-static circuit is electrically connected to the other end of the data line, and the anti-static circuit is used to release the accumulated static electricity on the data line through the static electricity release terminal.

21. The shaped display panel according to any one of claims 5-20, wherein, ET test residual traces are further included on both sides of the driving chip bonding region along the row direction, and the driving chip bonding region further includes an ET test circuit; wherein, the ET test residual traces include cutting residual traces and leads, the cutting end of the cutting residual traces is wrapped with an insulating layer, one end of the cutting residual traces far from the cutting end is electrically connected to one end of the lead, and the other end of the lead is electrically connected to the ET test circuit; wherein, The pixel electrode layer is located between the data line and the second substrate, the ET test residual traces are disposed on the same layer as the pixel electrode layer, and the cutting end of the ET test residual traces is wrapped with an insulating layer.

22. The special-shaped display panel according to any one of claims 1-21, wherein, A part of the edge display pixels located in the display region is blocked by the black matrix layer. In each row of the display pixels, the direction is from the direction with a small overlapping area between the display region and the edge display pixels to the direction with a large overlapping area, and the area of each of the edge display pixels blocked by the black matrix layer in each row of the display pixels gradually decreases.

23. The shaped display panel according to claim 22, wherein, The areas of the sub-pixels in the same edge display pixel blocked by the black matrix layer are the same.

24. The shaped display panel according to claim 23, wherein, The region of each sub-pixel blocked by the black matrix layer is close to the special-shaped boundary.

25. The shaped display panel according to any one of claims 1-24, wherein, The shape of the special-shaped display panel includes a circle or an ellipse.

26. A display device, wherein, It includes the special-shaped display panel according to any one of claims 1-25.

27. The display device according to claim 26, wherein, The display device is a vehicle-mounted display device.

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