Gate driving unit and display apparatus

Abstract

The present application provides a gate driving unit and a display apparatus. By electrically connecting a plurality of cascaded gate driving circuits to a frequency division control line transmitting a frequency division control signal, a frequency division control module in each gate driving circuit, on the basis of the frequency division control signal, controls signal transmission between a first power terminal and a first node or a second node, thereby controlling a voltage level state of gate control signals outputted by a first output module and a second output module.

Description

Gate driving unit and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving unit and a display device. Background Art

[0002] A variable refresh rate design can reduce the power consumption of display panels. However, in some scenarios, different display areas of the display panel display different content. If the same refresh rate is used to drive different display areas, then the areas displaying static images and dynamic images will also be driven at the same refresh rate, resulting in a waste of resources. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a gate driving circuit and a display device, which can realize zone-by-zone and frequency-by-frequency driving.

[0004] An embodiment of the present application provides a gate drive unit, comprising a frequency division control line and a plurality of cascaded gate drive circuits, wherein the frequency division control line is configured to transmit a frequency division control signal to the plurality of gate drive circuits. Each gate drive circuit comprises a first control module, a first output module, a second output module, and a frequency division control module. The first control module is electrically connected to a first node of the gate drive circuit of the current stage, and the first control module is configured to control signal transmission between one of a first power supply terminal and a second power supply terminal and the first node based on a corresponding first clock signal, a start signal, and one of the first gate control signals output by the gate drive circuit of the previous stage. The first output module is electrically connected to at least the first node of the gate drive circuit of the current stage, and the first output module is configured to control the electrical connection between a third power supply terminal and a first output terminal of the gate drive circuit of the current stage based on the potential of the first node, and the first output terminal outputs the first gate control signal of the gate drive circuit of the current stage. The second output module is electrically connected to the second node of the gate drive circuit of the current stage and the third node of the gate drive circuit of the current stage, and is configured to output a second gate control signal of the gate drive circuit of the current stage according to the potential of the second node and the potential of the third node. The frequency division control module is electrically connected to the first node of the gate drive circuit of the current stage, and is configured to control signal transmission between the first power supply terminal and the first node or the second node according to the frequency division control signal.

[0005] An embodiment of the present application also provides a display device, comprising any of the above-mentioned gate drive units and a display panel. The display panel includes a plurality of sub-pixels, each of which includes a light-emitting device and a pixel drive circuit for driving the light-emitting device to emit light, the pixel drive circuit including at least a drive transistor, a data transistor, and a compensation transistor; the drive transistor is configured to drive the light-emitting device to emit light according to a corresponding data signal, the input end of the compensation transistor is electrically connected to the output end of the drive transistor, the output end of the compensation transistor is electrically connected to the control end of the drive transistor, the input end of the data transistor is configured to receive the corresponding data signal, and the output end of the data transistor is electrically connected to the input end of the drive transistor. The first gate control signals generated by the plurality of gate drive circuits are output to the control ends of the compensation transistors of the plurality of sub-pixels, and the second gate control signals generated by the plurality of gate drive circuits are output to the control ends of the data transistors of the plurality of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] 1A and 1B are schematic structural diagrams of a gate driving unit provided in an embodiment of the present application;

[0007] 2A to 2D are circuit diagrams of a gate drive circuit provided in an embodiment of the present application;

[0008] 3A to 3D are timing diagrams of a gate drive circuit provided in an embodiment of the present application;

[0009] FIG4 is a schematic structural diagram of a display device provided in an embodiment of the present application;

[0010] FIG5 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0011] 6A to 6C are timing diagrams corresponding to the display device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0012] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0013] The gate drive unit and display device provided in the embodiments of the present application electrically connect multiple cascaded gate drive circuits to a frequency-division control line that transmits a frequency-division control signal. This allows the frequency-division control module within each gate drive circuit to control signal transmission between a first power supply terminal and a first node or a second node according to the frequency-division control signal, thereby controlling the level of the gate control signals output by the first output module and the second output module, so that the gate control signal output by at least one gate drive circuit always maintains an inactive level. When the gate drive unit is used in a display device, the frequency-division control signal is used to control the level of the gate control signals output by the multiple gate drive circuits, thereby achieving frequency-division and partition control of the display panel.

[0014] Specifically, Figures 1A and 1B are schematic diagrams of the structure of a gate drive unit provided in an embodiment of the present application. The present application provides a gate drive unit comprising a frequency division control line LFL and a plurality of cascaded gate drive circuits GDC, wherein the plurality of cascaded gate drive circuits GDC are electrically connected to the frequency division control line LFL, and the frequency division control line LFL is configured to transmit a frequency division control signal FD to the plurality of gate drive circuits GDC.

[0015] 1A and 1B , the gate driving unit is electrically connected to a plurality of clock lines. The plurality of clock lines provide the required first clock signal XCK and second clock signal CK to the plurality of gate driving circuits GDC. This allows the plurality of gate driving circuits GDC to share the clock signals transmitted by the plurality of clock lines, thereby reducing the number of clock signals used by the gate driving unit, the number of clock signal lines, and the wiring space occupied by the clock signal lines.

[0016] Optionally, the multiple clock lines include a first clock line CKL1 to a fourth clock line CKL4. The first clock signal XCK corresponding to the 4x+1-stage gate driver circuit GDC (4x+1) is provided by the second clock line CKL2, and the second clock signal CK corresponding to the 4x+1-stage gate driver circuit GDC (4x+1) is provided by the first clock line CKL1; the first clock signal XCK corresponding to the 4x+2-stage gate driver circuit GDC (4x+2) is provided by the third clock line CKL3, and the second clock signal CK corresponding to the 4x+2-stage gate driver circuit GDC (4x+2) is provided by the second clock line CKL2. The first clock signal XCK corresponding to the 4x+3-stage gate driver circuit GDC(4x+3) is provided by the fourth clock line CKL4, and the second clock signal CK corresponding to the 4x+3-stage gate driver circuit GDC(4x+3) is provided by the third clock line CKL3. The first clock signal XCK corresponding to the 4x+4-stage gate driver circuit GDC(4x+4) is provided by the first clock line CKL1, and the second clock signal CK corresponding to the 4x+4-stage gate driver circuit GDC(4x+4) is provided by the fourth clock line CKL4. Where x≥0.

[0017] Figures 2A to 2D are circuit diagrams of gate drive circuits provided in embodiments of the present application, using the n-th gate drive circuit GDC(n) as an example for illustration. Nout(n) represents the first output terminal of the n-th gate drive circuit GDC(n), Pout(n) represents the second output terminal of the n-th gate drive circuit GDC(n), and P(n) represents the third node of the n-th gate drive circuit GDC(n).

[0018] Each gate driving circuit GDC includes a first control module 10 , a second control module 20 , a first output module 30 , a second output module 40 and a frequency division control module 50 .

[0019] The first control module 10 is electrically connected to the first node K1 of the current-stage gate drive circuit GDC. The first control module 10 is configured to control signal transmission between the first node K1 and one of the first power supply terminal PVGL and the second power supply terminal PVGH according to the corresponding first clock signal XCK and the start signal STV.

[0020] Optionally, the first-stage gate driving circuit GDC among the multiple gate driving circuits GDC uses the start signal stv as the start signal STV, so that the first-stage gate driving circuit GDC(1) controls the signal transmission between one of the first power supply terminal PVGL and the second power supply terminal PVGH and the first node K1 of the first-stage gate driving circuit GDC(1) according to the corresponding first clock signal XCK and the start signal stv.

[0021] Optionally, an n-th-stage gate driver circuit GDC(n) among the plurality of gate driver circuits GDC uses the nA-th-stage first gate control signal Nscan(nA) output by the nA-th-stage gate driver circuit GDC(nA) as a start signal STV, so that the n-th-stage gate driver circuit GDC(n) controls signal transmission between one of the first power supply terminal PVGL and the second power supply terminal PVGH and the first node K1 of the n-th-stage gate driver circuit GDC(n) based on the corresponding first clock signal XCK and the nA-th-stage first gate control signal Nscan(nA) output by the nA-th-stage gate driver circuit GDC(nA). Where n>1, A≥1.

[0022] Optionally, in order to reduce the load corresponding to the first output terminal Nout of the gate drive circuit GDC, the n-th level gate drive circuit GDC(n) among the multiple gate drive circuits GDC controls the signal transmission between one of the first power supply terminal PVGL and the second power supply terminal PVGH and the first node K1 of the n-th level gate drive circuit GDC(n) according to the corresponding first clock signal XCK and the potential of the third node P of the nA-th level gate drive circuit GDC(nA).

[0023] Optionally, please continue to refer to FIG. 2A to FIG. 2D , the first control module 10 includes a first transistor T1 , a second transistor T2 and a third transistor T3 .

[0024] The first control terminal and the second control terminal of the first transistor T1 are configured to receive a start signal STV, and the input terminal of the first transistor T1 is electrically connected to the first power terminal PVGL.

[0025] The control end of the second transistor T2 is electrically connected to the first control end of the first transistor T1 , the input end of the second transistor T2 is electrically connected to the second power supply end PVGH, and the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1 .

[0026] The control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the output end of the third transistor T3 is electrically connected to the first node K1 .

[0027] Optionally, the first control module 10 is also electrically connected to the third node P of the gate drive circuit GDC at this level, and the first control module 10 is configured to control the electrical connection between the second power terminal PVGH or the third power terminal NVGL and the first node K1 according to the potential of the third node P.

[0028] Optionally, please continue to refer to FIG. 2A to FIG. 2D , the first control module 10 includes a fourth transistor T4 , a fifth transistor T5 , and a sixth transistor T6 .

[0029] The first control terminal and the second control terminal of the fourth transistor T4 are configured to receive a corresponding first clock signal XCK, and the output terminal of the fourth transistor T4 is electrically connected to the first node K1. The control terminal of the fifth transistor T5 and the first control terminal and the second control terminal of the sixth transistor T6 are electrically connected to the third node P. The input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH, the output terminal of the fifth transistor T5 is electrically connected to the input terminal of the fourth transistor T4, the input terminal of the sixth transistor T6 is electrically connected to the third power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node K1.

[0030] 2A to 2D , the second control module 20 is electrically connected to the first node K1 of the current-stage gate driver circuit GDC and the third node P of the current-stage gate driver circuit GDC. The second control module 20 is configured to control signal transmission between the first power supply terminal PVGL or the second power supply terminal PVGH and the third node P based on the potential of the first node K1.

[0031] Optionally, please continue to refer to FIG. 2A to FIG. 2D , the gate driving unit further includes a seventh transistor T7 and an eighth transistor T8 .

[0032] The first control terminal and the second control terminal of the seventh transistor T7 are electrically connected to the first node K1, the input terminal of the seventh transistor T7 is electrically connected to the first power supply terminal PVGL, the output terminal of the seventh transistor T7 is electrically connected to the third node P, the control terminal of the eighth transistor T8 is electrically connected to the first node K1, the input terminal of the eighth transistor T8 is electrically connected to the second power supply terminal PVGH, and the output terminal of the eighth transistor T8 is electrically connected to the third node P.

[0033] Please continue to refer to Figures 2A to 2D. The first output module 30 is electrically connected to at least the first node K1 of the gate drive circuit GDC of this stage. The first output module 30 is configured to control the electrical connection between the third power supply terminal NVGL and the first output terminal Nout of the gate drive circuit GDC of this stage according to the potential of the first node K1. The first output terminal Nout outputs the first gate control signal Nscan of the gate drive circuit GDC of this stage.

[0034] The second output module 40 is electrically connected to the second node K2 of the gate drive circuit GDC of this level and the third node P of the gate drive circuit GDC of this level. The second output module 40 is configured to output the second gate control signal Pscan of the gate drive circuit GDC of this level according to the potential of the second node K2 and the potential of the third node P.

[0035] The frequency division control module 50 is electrically connected to the first node K1 of the current-stage gate driving circuit GDC. The frequency division control module 50 is configured to control signal transmission between the first power supply terminal PVGL and the first node K1 or the second node K2 according to the frequency division control signal LF.

[0036] By setting up a frequency division control module 50, each gate driving circuit GDC can control the level state of the first gate control signal Nscan and the second gate control signal Pscan according to the frequency division control signal LF, so that when the gate driving unit is used in a display device, the levels of the first gate control signal Nscan and the second gate control signal Pscan output by the corresponding gate driving circuit GDC are controlled to remain in an invalid level state, thereby enabling the display panel to achieve frequency division and partition control.

[0037] Since each gate drive circuit GDC can output the first gate control signal Nscan and the second gate control signal Pscan at the same time, the same frequency-divided control signal LF can be used to control the level states of the first gate control signal Nscan and the second gate control signal Pscan, or two frequency-divided control signals LF can be used to respectively control the level states of the first gate control signal Nscan and the second gate control signal Pscan.

[0038] Accordingly, as shown in FIG1A , multiple gate drive circuits GDC are electrically connected to the same frequency-division control line LFL, so that the frequency-division control signal LF transmitted through the frequency-division control line LFL controls the level states of the first gate control signal Nscan and the second gate control signal Pscan output by the multiple gate drive circuits GDC. As shown in FIG1B , the frequency-division control line LFL includes a first frequency-division control line LFL1 and a second frequency-division control line LFL2. The multiple gate drive circuits GDC are electrically connected to the first frequency-division control line LFL1 and the second frequency-division control line LFL2, so that the first frequency-division control signal NLF transmitted through the first frequency-division control line LFL1 and the second frequency-division control signal PLF transmitted through the second frequency-division control line LFL2 controls the level states of the first gate control signal Nscan and the second gate control signal Pscan output by the multiple gate drive circuits GDC.

[0039] The following describes the circuit structure of the gate drive circuit GDC, taking multiple gate drive circuits GDC controlled by the same frequency division control line LFL as an example. Referring again to Figures 2A-2C , the frequency division control module 50 is electrically connected to the first control module 10. The frequency division control module 50 controls signal transmission between the first power terminal PVGL and the first node K1 based on the frequency division control signal LF.

[0040] Optionally, the frequency division control module 50 is electrically connected to the first transistor T1 or the third transistor T3 to achieve electrical connection with the first control module 10 .

[0041] Optionally, referring to FIG. 2A , the frequency division control module 50 includes a frequency division transistor Tf. The control terminal of the frequency division transistor Tf is configured to receive a frequency division control signal LF. The input terminal of the frequency division transistor Tf is electrically connected to the output terminal of the third transistor T3. The output terminal of the frequency division transistor Tf is electrically connected to the first node K1. The frequency division transistor Tf is configured to control signal transmission between the first node K1 and the output terminal of the third transistor T3 according to the frequency division control signal LF, so as to disconnect signal transmission between the first node K1 and the first power supply terminal PVGL when the frequency division transistor Tf is turned off. When the frequency division transistor Tf is turned on, the first node K1 is electrically connected to the output terminal of the third transistor T3, thereby enabling signal transmission between the first power supply terminal PVGL and the first node K1, thereby controlling signal transmission between the first node K1 and the first power supply terminal PVGL.

[0042] Optionally, referring to FIG. 2B , the frequency division control module 50 includes a frequency division transistor Tf. A control terminal of the frequency division transistor Tf is configured to receive a frequency division control signal LF. An input terminal of the frequency division transistor Tf is configured to receive a corresponding first clock signal XCK. An output terminal of the frequency division transistor Tf is electrically connected to a control terminal of a third transistor T3. The frequency division transistor Tf is configured to control the conduction of the third transistor T3 based on the frequency division control signal LF, thereby controlling signal transmission between the first node K1 and the first power supply terminal PVGL.

[0043] Optionally, referring to FIG. 2C , the frequency division control module 50 includes a frequency division transistor Tf. A control terminal of the frequency division transistor Tf is configured to receive a frequency division control signal LF. An input terminal of the frequency division transistor Tf is configured to receive a start signal stv or a first gate control signal Nscan output by a pre-stage gate drive circuit GDC. An output terminal of the frequency division transistor Tf is electrically connected to a first control terminal of the first transistor T1. The frequency division transistor Tf is configured to control the conduction of the first transistor T1 and the second transistor T2 based on the frequency division control signal LF, thereby controlling signal transmission between the first node K1 and the first power supply terminal PVGL.

[0044] 2A to 2C , the first output module 30 is configured to control signal transmission between the third power terminal NVGL or the fourth power terminal NVGH and the first output terminal Nout according to the potential of the first node K1 .

[0045] Optionally, the first output module 30 includes a first output transistor To1 and a second output transistor To2 .

[0046] The first control end, the second control end and the control end of the first output transistor To1 and the second output transistor To2 are electrically connected to the first node K1, the input end of the first output transistor To1 is electrically connected to the third power supply end NVGL, the input end of the second output transistor To2 is electrically connected to the fourth power supply end NVGH, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected to the first output end Nout of the gate drive circuit GDC of this level.

[0047] Optionally, the second output module 40 includes a third output transistor To3 , a fourth output transistor To4 , and a storage capacitor C0 .

[0048] The control end of the third output transistor To3 is electrically connected to the second node K2, the input end of the third output transistor To3 is configured to receive the corresponding second clock signal CK, the control end of the fourth output transistor To4 is electrically connected to the third node P of the current-stage gate drive circuit GDC, the input end of the fourth output transistor To4 is electrically connected to the second power supply end PVGH, and the output end of the fourth output transistor To4 and the output end of the third output transistor To3 are electrically connected to the second output end Pout of the current-stage gate drive circuit GDC.

[0049] A first end of the storage capacitor C0 is electrically connected to the control end of the third output transistor To3 , and a second end of the storage capacitor C0 is electrically connected to the second output end Pout of the current-stage gate driving circuit GDC.

[0050] Optionally, each gate drive circuit GDC further includes an output control module 60 , which is electrically connected to the first node K1 and the second node K2 , and is configured to control signal transmission between the first node K1 and the second node K2 according to an output control signal ST.

[0051] Optionally, please continue to refer to FIG. 2A and FIG. 2C , the output control module 60 includes a first switch transistor Ts1 , a second switch transistor Ts2 , and a third capacitor Cs.

[0052] The input end of the first switch transistor Ts1 is electrically connected to the first node K1 , the input end of the second switch transistor Ts2 is electrically connected to the output end of the first switch transistor Ts1 , and the output end of the second switch transistor Ts2 is electrically connected to the second node K2 .

[0053] A first end of the third capacitor Cs is electrically connected to the control end of the first switch transistor Ts1 , and a second end of the third capacitor Cs is electrically connected to the output end of the first switch transistor Ts1 .

[0054] The control end of the first switch transistor Ts1 is configured to receive a first output control signal ST1, and the control end of the second switch transistor Ts2 is configured to receive a second output control signal ST2. The output control signal ST includes the first output control signal ST1 and the second output control signal ST2.

[0055] Optionally, the control terminal of the first switching transistor Ts1 of the n-th stage gate driver circuit GDC(n) is configured to receive the nB-th stage first gate control signal Nscan(nB) output by the nB-th stage gate driver circuit GDC(nB) as the first output control signal ST1, and the control terminal of the second switching transistor Ts2 of the n-th stage gate driver circuit GDC(n) is configured to receive the nC-th stage first gate control signal Nscan(nC) output by the nC-th stage gate driver circuit GDC(nC) as the second output control signal ST2. Wherein, B>0, C>0.

[0056] Optionally, to reduce the load of the gate drive circuit GDC, the control terminal of the first switching transistor Ts1 of the n-th-stage gate drive circuit GDC(n) is electrically connected to the third node P(nB) of the nB-th-stage gate drive circuit GDC(nB), so that the first switching transistor Ts1 of the n-th-stage gate drive circuit GDC(n) is turned on or off according to the potential of the third node P of the nB-th-stage gate drive circuit GDC(nB) (i.e., corresponding to the first output control signal ST1). The control terminal of the second switching transistor Ts2 of the n-th-stage gate drive circuit GDC(n) is electrically connected to the third node P(nC) of the nC-th-stage gate drive circuit GDC(nC), so that the second switching transistor Ts2 of the n-th-stage gate drive circuit GDC(n) is turned on or off according to the potential of the third node P of the nC-th-stage gate drive circuit GDC(nC) (i.e., corresponding to the second output control signal ST2).

[0057] Optionally, in some embodiments, A=1, B=10, and C=2, so that the pulse width of the valid pulse of the first gate control signal Nscan is greater than the pulse width of the valid pulse of the second gate control signal Pscan.

[0058] Correspondingly, the control end of the second transistor T2 of the first-stage gate driving circuit GDC(1) is configured to receive the start signal stv, and the control end of the second transistor T2 of each stage of the gate driving circuit GDC located after the first-stage gate driving circuit GDC(1) is configured to receive the first gate control signal Nscan output by the previous stage of the gate driving circuit GDC (for example, the control end of the second transistor T2 of the n-stage gate driving circuit GDC(n) is configured to receive the first gate control signal Nscan(n-1) output by the n-1-stage gate driving circuit GDC(n-1)). The first output control signal ST1 received by the control end of the first switching transistor Ts1 of the first-stage gate driving circuit GDC(1) to the tenth-stage gate driving circuit GDC(10) corresponds to the low-level signal VGL, and the control end of the first switching transistor Ts1 of each stage of the gate driving circuit after the tenth-stage gate driving circuit GDC(10) is configured to receive the first gate control signal Nscan output by the first ten stages of the gate driving circuit (for example, the control end of the first switching transistor Ts1 of the n-stage gate driving circuit GDC(n) is configured to receive the n-10th stage first gate control signal Nscan(n-10) output by the n-10th stage gate driving circuit GDC(n-10)). The second output control signal ST2 received by the control end of the second switching transistor Ts2 of the first-stage gate driving circuit GDC(1) to the second-stage gate driving circuit GDC(2) corresponds to the low-level signal VGL, and the control end of the second switching transistor Ts2 of each stage of the gate driving circuit after the second-stage gate driving circuit GDC(2) is configured to receive the first gate control signal Nscan output by the first two stages of the gate driving circuit (the control end of the second switching transistor Ts2 of the n-stage gate driving circuit GDC(n) is configured to receive the n-2-stage first gate control signal Nscan(n-2) output by the n-2-stage gate driving circuit GDC(n-2)), as shown in FIG1A .

[0059] The following describes the circuit structure of the gate drive circuit GDC, using an example in which multiple gate drive circuits GDC use a two-frequency division control signal LF to control the level states of the first gate control signal Nscan and the second gate control signal Pscan, respectively. Referring to FIG. 2D , the frequency division control module 50 is designed to correspond to the first output module 30 and the second output module 40. The frequency division control module 50 controls signal transmission between the first power supply terminal PVGL and the second node K2 based on the frequency division control signal LF.

[0060] 2D , the second node K2 includes a first sub-node K21 and a second sub-node K22 , the frequency division control signal LF includes a first frequency division control signal NLF and a second frequency division control signal PLF, and the frequency division control module 50 includes a first frequency division control module 501 and a second frequency division control module 502 .

[0061] The first frequency division control module 501 is electrically connected to the first node K1 and the first sub-node K21 , and is configured to control signal transmission between the first power terminal PVGL and the first sub-node K21 according to a first frequency division control signal NLF.

[0062] The second frequency division control module 502 is electrically connected to the first node K1 and the second sub-node K22 , and is configured to control signal transmission between the first power terminal PVGL and the second sub-node K22 according to a second frequency division control signal PLF.

[0063] The first output module 30 is electrically connected to the first sub-node K21 and is configured to output a first gate control signal Nscan for the current-stage gate driver circuit GDC based on the potential of the first node K1 and the potential of the first sub-node K21. The second output module 40 is electrically connected to the second sub-node K22 and is configured to output a second gate control signal Pscan for the current-stage gate driver circuit GDC based on the potential of the second sub-node K22 and the potential of the third node P.

[0064] A first frequency-division control module 501 is provided to control signal transmission between the first node K1 and the first subnode K21, thereby controlling the level of the first gate control signal Nscan. A second frequency-division control module 502 is provided to control signal transmission between the first node K1 and the second subnode K22, thereby controlling the level of the second gate control signal Pscan. The first frequency-division control module 501 and the second frequency-division control module 502 cooperate with each other to control the levels of the first gate control signal Nscan and the second gate control signal Pscan.

[0065] Optionally, please continue to refer to FIG. 2D , the first frequency-dividing control module 501 includes a first frequency-dividing transistor Tf1 , a second frequency-dividing transistor Tf2 , and a first capacitor C1 .

[0066] The control terminal of the first frequency-dividing transistor Tf1 is electrically connected to the third node P of the current-stage gate driving circuit GDC, and the input terminal of the first frequency-dividing transistor Tf1 is configured to receive a first frequency-dividing control signal NLF.

[0067] The control terminal of the second frequency dividing transistor Tf2 is electrically connected to the output terminal of the first frequency dividing transistor Tf1 , the input terminal of the second frequency dividing transistor Tf2 is electrically connected to the first node K1 , and the output terminal of the second frequency dividing transistor Tf2 is electrically connected to the first sub-node K21 .

[0068] A first end of the first capacitor C1 is electrically connected to the control end of the second frequency-dividing transistor Tf2 , and a second end of the first capacitor C1 is electrically connected to the first sub-node K21 .

[0069] Optionally, please continue to refer to FIG. 2D , the second frequency-dividing control module 502 includes a third frequency-dividing transistor Tf3 , a fourth frequency-dividing transistor Tf4 , and a second capacitor C2 .

[0070] The control terminal of the third frequency-dividing transistor Tf3 is electrically connected to the third node P of the current-stage gate driving circuit GDC, and the input terminal of the third frequency-dividing transistor Tf3 is configured to receive the second frequency-dividing control signal PLF.

[0071] The control terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the output terminal of the third frequency-dividing transistor Tf3 , the input terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the first node K1 , and the output terminal of the fourth frequency-dividing transistor Tf4 is electrically connected to the second sub-node K22 .

[0072] A first end of the second capacitor C2 is electrically connected to the control end of the fourth frequency-dividing transistor Tf4 , and a second end of the second capacitor C2 is electrically connected to the second sub-node K22 .

[0073] By making the control end of the first frequency-dividing transistor Tf1 and the control end of the third frequency-dividing transistor Tf3 be controlled by the third node P of the current-stage gate driving circuit GDC, when the level state of the first frequency-dividing control signal NLF and the second frequency-dividing control signal PLF of the gate driving unit changes, the gate control signal output by the corresponding multi-stage gate driving circuit GDC can still meet the design expectations, thereby reducing the probability of abnormality in the multi-stage first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit.

[0074] Because the first frequency-division control module 501 is designed corresponding to the first output module 30 and the second frequency-division control module 502 is designed corresponding to the second output module 40, when the multi-stage gate drive circuit GDC is controlled by the first frequency-division control signal NLF and the second frequency-division control signal PLF, the connection relationship between the first output module 30 and the second output module 40 is different from the connection relationship between the first output module 30 and the second output module 40 when the multi-stage gate drive circuit GDC is controlled by a frequency-division control signal LF.

[0075] Accordingly, please continue to refer to FIG. 2D , the first output module 30 includes a first output transistor To1 and a second output transistor To2 .

[0076] The first control terminal and the second control terminal of the first output transistor To1 are electrically connected to the first node K1 , and the input terminal of the first output transistor To1 is electrically connected to the third power terminal NVGL.

[0077] The control end of the second output transistor To2 is electrically connected to the first sub-node K21, the input end of the second output transistor To2 is electrically connected to the fourth power supply end NVGH, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected to the first output end Nout of the current-level gate drive circuit GDC.

[0078] Continuing to refer to FIG. 2D , the second output module 40 includes a third output transistor To3 , a fourth output transistor To4 , and a storage capacitor C0 .

[0079] The control terminal of the third output transistor To3 is electrically connected to the second sub-node K22 , and the input terminal of the third output transistor To3 is configured to receive the corresponding second clock signal CK.

[0080] The control end of the fourth output transistor To4 is electrically connected to the third node P, the input end of the fourth output transistor To4 is electrically connected to the second power supply end PVGH, and the output end of the fourth output transistor To4 and the output end of the third output transistor To3 are electrically connected to the second output end Pout of the current-stage gate drive circuit GDC.

[0081] A first end of the storage capacitor C0 is electrically connected to the control end of the third output transistor To3 , and a second end of the storage capacitor C0 is electrically connected to the second output end Pout of the current-stage gate driving circuit GDC.

[0082] That is, when the multi-stage gate drive circuit GDC is controlled by the first frequency-division control signal NLF and the second frequency-division control signal PLF, the control end of the second output transistor To2 is electrically connected to the first sub-node K21, and the control end of the third output transistor To3 is electrically connected to the second sub-node K22, so that the conduction and cutoff of the second output transistor To2 are controlled by the potential of the first sub-node K21, and the conduction and cutoff of the third output transistor To3 are controlled by the potential of the second sub-node K22.

[0083] Optionally, in some embodiments, at least one gate drive circuit GDC further includes a third control module 801, which is electrically connected to the third node P of the gate drive circuit GDC at this stage and the first sub-node K21 of the gate drive circuit GDC at this stage. The third control module 801 is configured to control signal transmission between the second power supply terminal PVGH and the first sub-node K21 according to the corresponding first clock signal XCK and the potential of the third node P.

[0084] Optionally, please continue to refer to FIG. 2D , the third control module 801 includes a ninth transistor T9 and a tenth transistor T10 .

[0085] The first control terminal and the second control terminal of the ninth transistor T9 are configured to receive the corresponding first clock signal XCK, and the output terminal of the ninth transistor T9 is electrically connected to the first sub-node K21.

[0086] The control end of the tenth transistor T10 is electrically connected to the third node P of the current-stage gate driving circuit GDC, the input end of the tenth transistor T10 is electrically connected to the second power supply end PVGH, and the output end of the tenth transistor T10 is electrically connected to the input end of the ninth transistor T9.

[0087] Optionally, in some embodiments, at least one gate drive circuit GDC further includes a switch module 90, which is electrically connected between the second frequency division control module 502 and the second sub-node K22, and the switch module 90 is configured to control the electrical connection between the second frequency division control module 502 and the second sub-node K22 according to the corresponding switch control signal SC.

[0088] Optionally, please continue to refer to Figure 2D, the switch module 90 includes an eleventh transistor T11, the control end of the eleventh transistor T11 is configured to receive a switch control signal SC, the input end of the eleventh transistor T11 is electrically connected to the output end of the third frequency-dividing transistor Tf3, and the output end of the eleventh transistor T11 is electrically connected to the second sub-node K22.

[0089] Optionally, the control end of the eleventh transistor T11 of the n-th-stage gate driving circuit GDC(n) is configured to receive the nC-th-stage first gate control signal Nscan(nC) output by the nC-th-stage gate driving circuit GDC(nC), so as to use the nC-th-stage first gate control signal Nscan(nC) output by the nC-th-stage gate driving circuit GDC(nC) as the switching control signal SC received by the control end of the eleventh transistor T11 of the n-th-stage gate driving circuit GDC(n).

[0090] Optionally, the switch control signal SC received by the control end of the eleventh transistor T11 of the first-stage gate drive circuit GDC(1) to the second-stage gate drive circuit GDC(2) corresponds to the low-level signal VGL, and the control end of the eleventh transistor T11 of each stage of the gate drive circuit located after the second-stage gate drive circuit GDC(2) is configured to receive the first gate control signal Nscan output by the first two stages of the gate drive circuit (for example, the control end of the eleventh transistor T11 of the n-stage gate drive circuit GDC(n) is configured to receive the n-2-stage first gate control signal Nscan(n-2) output by the n-2-stage gate drive circuit GDC(n-2)), as shown in FIG1B .

[0091] Optionally, the control terminal of the eleventh transistor T11 is electrically connected to the third node P of the preceding gate driver circuit GDC, so that the potential of the third node P of the preceding gate driver circuit GDC serves as a switch control signal SC to control the operating state of the eleventh transistor T11 and reduce the load on the first output terminal Nout of the gate driver circuit GDC. For example, the control terminal of the eleventh transistor T11 of the n-th gate driver circuit GDC(n) is electrically connected to the third node P of the nC-th gate driver circuit GDC(nC), so that the potential of the third node P of the nC-th gate driver circuit GDC(nC) serves as the switch control signal SC received by the control terminal of the eleventh transistor T11 of the n-th gate driver circuit GDC(n).

[0092] Optionally, in some embodiments, at least one gate driving circuit GDC further includes a fourth control module 802 .

[0093] The fourth control module 802 is electrically connected to the third node P of the current-stage gate driver circuit GDC and the second sub-node K22 of the current-stage gate driver circuit GDC. The fourth control module 802 is configured to control signal transmission between the second power supply terminal PVGH and the second sub-node K22 based on the corresponding first clock signal XCK and the potential of the third node P.

[0094] Optionally, referring to FIG. 2D , the fourth control module 802 includes a twelfth transistor T12 and a thirteenth transistor T13 .

[0095] The first control terminal and the second control terminal of the twelfth transistor T12 are configured to receive the corresponding first clock signal XCK, and the output terminal of the twelfth transistor T12 is electrically connected to the input terminal of the eleventh transistor T11 .

[0096] The control end of the thirteenth transistor T13 is electrically connected to the third node P of the current-stage gate driving circuit GDC, the input end of the thirteenth transistor T13 is electrically connected to the second power supply end PVGH, and the output end of the thirteenth transistor T13 is electrically connected to the input end of the twelfth transistor T12.

[0097] Optionally, referring to FIG. 2A to FIG. 2D , at least one gate driving circuit GDC further includes a reset module 70. The reset module 70 is electrically connected to the first node K1. The reset module 70 is configured to control signal transmission between the second power terminal PVGH and the first node K1 according to a reset control signal Ctl.

[0098] Optionally, the reset module 70 includes a reset transistor Tr, a control terminal of the reset transistor Tr is configured to receive a reset control signal Ctl, an input terminal of the reset transistor Tr is electrically connected to the second power terminal PVGH, and an output terminal of the reset transistor Tr is electrically connected to the first node K1.

[0099] Optionally, when the gate driving unit is applied to a display device, the reset module 70 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0100] Optionally, in some embodiments, the voltage corresponding to the first power terminal PVGL is smaller than the voltage corresponding to the second power terminal PVGH, and the voltage corresponding to the third power terminal NVGL is smaller than the voltage corresponding to the fourth power terminal NVGH.

[0101] Optionally, in some embodiments, at least one of the first transistor T1 , the fourth transistor T4 , the sixth transistor T6 , the seventh transistor T7 , the ninth transistor T9 , the twelfth transistor T12 and the first output transistor To1 may have only one control terminal.

[0102] It is understandable that each transistor included in the gate drive circuit GDC may be one of a P-type transistor and an N-type transistor. The semiconductor of each transistor included in the gate drive circuit GDC may be one of a silicon semiconductor and an oxide semiconductor.

[0103] 3A to 3D are timing diagrams of the gate drive circuit provided in an embodiment of the present application, wherein FIG3A corresponds to the gate drive circuit GDC shown in FIG2A to FIG2C , and FIG3B to FIG3C corresponds to the gate drive circuit GDC shown in FIG2D .

[0104] The following first describes the working principle of the gate drive unit by taking multiple gate drive circuits GDC controlled by the same frequency-divided control signal LF as an example. That is, the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the first switch transistor Ts1, the second switch transistor Ts2, the second output transistor To2 to the fourth output transistor To4, and the frequency-divided transistor Tf are P-type transistors, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the first output transistor To1 are N-type transistors, and the frequency-divided control signal LF has a transition from a low level state to a high level state in the p-th level gate drive circuit GDC to the p+q-th level gate drive circuit GDC(p+q) of the corresponding gate drive unit. The first clock signal XCK corresponding to the p+4x-th level gate drive circuit GDC is provided by the second clock line CKL2, the second clock signal CK corresponding to the p+4x-th level gate drive circuit GDC is provided by the first clock line CKL1, and the first clock signal CK corresponding to the p+(4x+1)-th level gate drive circuit GDC is provided by the first clock line CKL2. The clock signal XCK is provided by the third clock line CKL3, the second clock signal CK corresponding to the p+(4x+1)-th gate driver circuit GDC is provided by the second clock line CKL2, the first clock signal XCK corresponding to the p+(4x+2)-th gate driver circuit GDC is provided by the fourth clock line CKL4, the second clock signal CK corresponding to the p+(4x+2)-th gate driver circuit GDC is provided by the third clock line CKL3, the first clock signal XCK corresponding to the p+(4x+3)-th gate driver circuit GDC is provided by the first clock line CKL1, and the second clock signal CK corresponding to the p+(4x+3)-th gate driver circuit GDC is provided by the fourth clock line CKL4. As an example, the working principle of a gate driver unit including the gate driver circuits GDC shown in Figures 2A to 2C and the multiple gate driver circuits GDC of the gate driver unit are cascaded in the cascade manner shown in Figure 1A is described. Wherein, p≥1, q≥1, and x≥0.

[0105] Please continue to refer to Figures 2A to 2C and Figure 3A. In the first stage t1, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a low level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The p-10th level first gate control signal Nscan(p-10) output by the p-10th level gate drive circuit GDC(p-10) ~ the p-4th level first gate control signal Nscan(p-4) output by the p-4th level gate drive circuit GDC(p-4) are in a high level state, the p-3th level first gate control signal Nscan(p-3) output by the p-3th level gate drive circuit GDC(p-3) ~ the p-1th level first gate control signal Nscan(p-1) output by the p-1th level gate drive circuit GDC(p-1) are in a low level state; the frequency division control signal LF is in a low level state.

[0106] In the p-th stage gate driver circuit GDC(p) and the p+4-th stage gate driver circuit GDC(p+4), the second transistor T2, the third transistor T3, the second switch transistor Ts2, and the frequency divider transistor Tf are turned on, while the fourth transistor T4 and the first switch transistor Ts1 are turned off. The second power supply terminal PVGH is electrically connected to the first node K1, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned on, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout. The first power supply terminal PVGL is electrically connected to the third node P, the fifth transistor T5 is turned on, and the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 are turned off.

[0107] In the p+1th level gate drive circuit GDC(p+1) to the p+3th level gate drive circuit GDC(p+3) and the p+5th level gate drive circuit GDC(p+5) to the p+7th level gate drive circuit GDC(p+7), the second transistor T2 is turned on and the third transistor T3 is turned off. Therefore, the p+1th level first gate control signal Nscan(p+1) to the p+3th level first gate control signal Nscan(p+3) and the p+5th level first gate control signal Nscan(p+5) to the p+7th level first gate control signal Nscan(p+7) maintain a low level state, and the p+1th level second gate control signal Pscan(p+1) to the p+3th level second gate control signal Pscan(p+3) and the p+5th level second gate control signal Pscan(p+5) to the p+7th level second gate control signal Pscan(p+7) maintain a high level state.

[0108] In the p+8th level gate drive circuit GDC(p+8), the second transistor T2, the third transistor T3, the first switching transistor Ts1, the second switching transistor Ts2 and the frequency dividing transistor Tf are turned on, the fifth transistor T5, the seventh transistor T7, the first output transistor To1 and the fourth output transistor To4 are turned on, and the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the second output transistor To2 and the third output transistor To3 are turned off.

[0109] The gate driver circuit GDC, located after the p+8th-stage gate driver circuit GDC(p+8), and for which the first clock signal XCK is provided by the second clock line CKL2 and the second clock signal CK is provided by the first clock line CKL1, performs operations similar to those of the p+8th-stage gate driver circuit GDC(p+8) in the first phase t1. The gate driver circuit GDC, located after the p+8th-stage gate driver circuit GDC(p+8), and for which the first clock signal XCK is not provided by the second clock line CKL2 and the second clock signal CK is not provided by the first clock line CKL1, performs operations similar to those of the p+7th-stage gate driver circuit GDC(p+7) in the first phase t1.

[0110] Please continue to refer to Figures 2A to 2C and Figure 3A. In the second stage t2, the first clock signal CK1 provided by the first clock line CKL1 has a low level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The p-10th level first gate control signal Nscan(p-10) output by the p-10th level gate drive circuit GDC(p-10) ~ the p-9th level first gate control signal Nscan(p-9) output by the p-9th level gate drive circuit GDC(p-9) are in a low level state, the p-8th level first gate control signal Nscan(p-8) output by the p-8th level gate drive circuit GDC(p-8) ~ the p-1st level first gate control signal Nscan(p-1) output by the p-1st level gate drive circuit GDC(p-1) are in a high level state; the frequency division control signal LF is in a low level state.

[0111] In the p-th stage gate drive circuit GDC(p), the first switching transistor Ts1, the first transistor T1, and the frequency dividing transistor Tf are turned on, while the second switching transistor Ts2, the second transistor T2, and the third transistor T3 are turned off. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain turned on, while the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 remain turned off.

[0112] In the p+1th through p+qth gate driver circuits GDC(p+1)-GDC(p+q), the second transistor T2 is turned on because the start signal STV received by the control terminal of the second transistor T2 is in a low-level state corresponding to the second phase t2. In the gate driver circuit GDC located after the p-th gate driver circuit GDC(p), where the first clock signal XCK is provided by the first clock line CKL1 and the second clock signal CK is provided by the fourth clock line CKL4, the third transistor T3 is turned on, and the second power supply terminal PVGH is electrically connected to the first node K1. In the gate driver circuit GDC located after the p-th gate driver circuit GDC(p), where the first clock signal XCK is not provided by the first clock line CKL1 and the second clock signal CK is not provided by the fourth clock line CKL4, the third transistor T3 is turned off. The p+1th level first gate control signal Nscan(p+1) to the p+qth level first gate control signal Nscan(p+q) maintain a low level state, and the p+1th level second gate control signal Pscan(p+1) to the p+qth level second gate control signal Pscan(p+q) maintain a high level state.

[0113] 2A to 2C and 3A , in the third phase t3, the first clock signal CK1 provided by the first clock line CKL1 is in a high-level state, the second clock signal CK2 provided by the second clock line CKL2 is in a low-level state, the third clock signal CK3 provided by the third clock line CKL3 is in a high-level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a high-level state. The p-10th level first gate control signal Nscan(p-10) output by the p-10th level gate drive circuit GDC(p-10) ~ the p-8th level first gate control signal Nscan(p-8) output by the p-8th level gate drive circuit GDC(p-8) are in a low level state, the p-7th level first gate control signal Nscan(p-7) output by the p-7th level gate drive circuit GDC(p-7) ~ the p-1th level first gate control signal Nscan(p-1) output by the p-1th level gate drive circuit GDC(p-1) are in a high level state; the frequency division control signal LF is in a low level state.

[0114] In the p-th stage gate drive circuit GDC(p), the first switching transistor Ts1, the first transistor T1, the third transistor T3, and the frequency-dividing transistor Tf are turned on, while the second switching transistor Ts2, the second transistor T2, and the fourth transistor T4 are turned off. The first power supply terminal PVGL is electrically connected to the first node K1. The sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on. The fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned off. The third output transistor To3 remains off. The first output terminal Nout is electrically connected to the third power supply terminal NVGL, and the second output terminal Pout maintains the output state of the first stage t1.

[0115] The p+1th level gate driving circuit GDC(p+1) performs an action similar to the action performed by the p-th level gate driving circuit GDC(p) in the second stage t2 in the third stage t3, the p+2th level gate driving circuit GDC(p+2) performs an action similar to the action performed by the p+1th level gate driving circuit GDC(p+1) in the second stage t2 in the third stage t3, and so on, to obtain the actions performed by the p+3th level gate driving circuit GDC(p+3) to the p+qth level gate driving circuit GDC(p+q) in the third stage t3.

[0116] Continuing with Figures 2A to 2C and 3A, in the fourth phase t4, the first clock signal CK1 provided by the first clock line CKL1 is in a high state, the second clock signal CK2 provided by the second clock line CKL2 is in a high state, the third clock signal CK3 provided by the third clock line CKL3 is in a low state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a high state. The p-10th-stage first gate control signal Nscan(p-10) output by the p-10th-stage gate driver circuit GDC(p-10) to the p-7th-stage first gate control signal Nscan(p-7) output by the p-7th-stage gate driver circuit GDC(p-7) are in a low state, and the p-6th-stage first gate control signal Nscan(p-6) output by the p-6th-stage gate driver circuit GDC(p-6) is in a high state; and the frequency division control signal LF is in a low state.

[0117] In the p-th stage gate drive circuit GDC(p), the first switch transistor Ts1, the first transistor T1, the frequency dividing transistor Tf, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 remain turned on, the fourth transistor T4 is turned on, the third transistor T3 is turned off, and the second switch transistor Ts2, the second transistor T2, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, the fourth output transistor To4, and the third output transistor To3 remain turned off. The first output terminal Nout is electrically connected to the third power supply terminal NVGL, and the second output terminal Pout maintains the output state of the third stage t3.

[0118] The p+1th level gate driving circuit GDC(p+1) performs an action similar to the action performed by the p-th level gate driving circuit GDC(p) in the third stage t3 in the fourth stage t4, the p+2th level gate driving circuit GDC(p+2) performs an action similar to the action performed by the p+1th level gate driving circuit GDC(p+1) in the third stage t3 in the fourth stage t4, and so on, to obtain the actions performed by the p+3th level gate driving circuit GDC(p+3) to the p+qth level gate driving circuit GDC(p+q) in the fourth stage t4.

[0119] Continuing with Figures 2A to 2C and 3A, in the fifth phase t5, the first clock signal CK1 provided by the first clock line CKL1 is in a high state, the second clock signal CK2 provided by the second clock line CKL2 is in a high state, the third clock signal CK3 provided by the third clock line CKL3 is in a high state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a low state. The p-10th-stage first gate control signal Nscan(p-10) output by the p-10th-stage gate driver circuit GDC(p-10) and the p-2th-stage first gate control signal Nscan(p-2) output by the p-2th-stage gate driver circuit GDC(p-2) are in a low state, the p-1th-stage first gate control signal Nscan(p-1) output by the p-1th-stage gate driver circuit GDC(p-1) is in a high state, and the frequency division control signal LF is in a low state.

[0120] In the p-th stage gate drive circuit GDC(p), the first switching transistor Ts1, the first transistor T1, and the frequency-dividing transistor Tf remain turned on, and the second switching transistor Ts2 is turned on, causing the third output transistor To3 to turn on, and the corresponding first clock signal XCK is transmitted to the second output terminal Pout. The second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain turned off. The fourth transistor T4 is turned on, and the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 remain turned on. The first output terminal Nout is electrically connected to the third power supply terminal NVGL.

[0121] In the p+1-th stage gate driver circuit GDC(p+1) and the p+3-th stage gate driver circuit GDC(p+3) to the p+5-th stage gate driver circuit GDC(p+5), the corresponding first clock signal XCK is in a high-level state, the third transistor T3 is turned off, and the second output transistor To2 remains on. In the p+2-th stage gate driver circuit GDC(p+2), the corresponding first clock signal XCK is in a low-level state, the third transistor T3 is turned on, the second switch transistor Ts2 is turned off, the first power supply terminal PVGL is electrically connected to the first node K1, and the second output transistor To2 remains on. The p+6th-level gate driving circuit GDC(p+6) performs an action similar to the action performed by the p-level gate driving circuit GDC(p) in the third stage t3 in the fifth stage t5, the p+7th-level gate driving circuit GDC(p+7) performs an action similar to the action performed by the p+1th-level gate driving circuit GDC(p+1) in the third stage t3 in the fifth stage t5, and so on, to obtain the actions performed by the p+8th-level gate driving circuit GDC(p+8) to the p+qth-level gate driving circuit GDC(p+q) in the fifth stage t5.

[0122] Continuing with Figures 2A to 2C and 3A, in the sixth phase t6, the first clock signal CK1 provided by the first clock line CKL1 is in a low state, the second clock signal CK2 provided by the second clock line CKL2 is in a high state, the third clock signal CK3 provided by the third clock line CKL3 is in a high state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a high state. The p-10th-stage first gate control signal Nscan(p-10) output by the p-10th-stage gate driver circuit GDC(p-10) and the p-1th-stage first gate control signal Nscan(p-1) output by the p-1th-stage gate driver circuit GDC(p-1) are in a low state, and the frequency division control signal LF is in a low state.

[0123] In the p-th stage gate drive circuit GDC(p), the second transistor T2 is turned on, the first switching transistor Ts1, the second switching transistor Ts2, the frequency dividing transistor Tf, and the third output transistor To3 remain turned on, and the corresponding first clock signal XCK is transmitted to the second output terminal Pout, so that the p-th stage second gate control signal Pscan(p) has a low level state. The third transistor T3, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain turned off. The fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 remain turned on, and the first output terminal Nout is electrically connected to the third power supply terminal NVGL.

[0124] The p+1th level gate driving circuit GDC(p+1) performs an action similar to the action performed by the p-th level gate driving circuit GDC(p) in the fifth level t5 in the sixth stage t6, the p+2th level gate driving circuit GDC(p+2) performs an action similar to the action performed by the p+1th level gate driving circuit GDC(p+1) in the fifth level t5 in the sixth stage t6, and so on, to obtain the actions performed by the p+3th level gate driving circuit GDC(p+3) to the p+qth level gate driving circuit GDC(p+q) in the sixth stage t6.

[0125] Continuing with Figures 2A to 2C and 3A, in the seventh phase t7, the first clock signal CK1 provided by the first clock line CKL1 is in a high state, the second clock signal CK2 provided by the second clock line CKL2 is in a low state, the third clock signal CK3 provided by the third clock line CKL3 is in a high state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a high state. The p-10th-stage first gate control signal Nscan(p-10) output by the p-10th-stage gate driver circuit GDC(p-10) and the p-1th-stage first gate control signal Nscan(p-1) output by the p-1th-stage gate driver circuit GDC(p-1) are in a low state, and the frequency division control signal LF is in a low state.

[0126] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the third transistor T3, the first switch transistor Ts1, the second switch transistor Ts2, and the frequency divider transistor Tf are turned on, the second power supply terminal PVGH is electrically connected to the first node K1, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0127] The p+1th-stage gate driver circuit GDC(p+1) performs an action similar to that performed by the pth-stage gate driver circuit GDC(p) at the sixth stage t6 during the seventh stage t7, and the p+1th-stage second gate control signal Pscan(p+1) is at a low level. The p+2th-stage gate driver circuit GDC(p+2) performs an action similar to that performed by the p+1th-stage gate driver circuit GDC(p+1) at the seventh stage t6 during the seventh stage t7, and so on for the p+3th-stage gate driver circuit GDC(p+3) through the p+qth-stage gate driver circuit GDC(p+q) during the seventh stage t7.

[0128] Continuing with Figures 2A to 2C and 3A, in the eighth phase t8, the first clock signal CK1 provided by the first clock line CKL1 is in a high state, the second clock signal CK2 provided by the second clock line CKL2 is in a high state, the third clock signal CK3 provided by the third clock line CKL3 is in a low state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a high state. The p-10th-stage first gate control signal Nscan(p-10) output by the p-10th-stage gate driver circuit GDC(p-10) and the p-1th-stage first gate control signal Nscan(p-1) output by the p-1th-stage gate driver circuit GDC(p-1) are in a low state, and the frequency division control signal LF is in a high state.

[0129] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the first switching transistor Ts1, the second switching transistor Ts2, the fifth transistor T5, the seventh transistor T7, the first output transistor To1 and the fourth output transistor To4 remain turned on, the third transistor T3 and the frequency dividing transistor Tf are turned off, the fourth transistor T4 is turned on, and the first transistor T1, the sixth transistor T6, the second output transistor To2 and the third output transistor To3 remain turned off.

[0130] In the p+1th-level gate drive circuit GDC(p+1) to the p+qth-level gate drive circuit GDC(p+q), since the frequency dividing transistor Tf is turned off, the potential of the first node K1 maintains the state of the seventh stage t7, causing the second output transistor To2 in the p+1th-level gate drive circuit GDC(p+1) to the p+8th-level gate drive circuit GDC(p+8) to be turned on, so that the first output terminal Nout of the p+1th-level gate drive circuit GDC(p+1) to the p+8th-level gate drive circuit GDC(p+8) is electrically connected to the fourth power supply terminal NVGH. The second switching transistors Ts2 and second output transistors To2 in the p+1th-stage gate driver circuits GDC(p+1) through the p+2th-stage gate driver circuits GDC(p+2) are turned on, and the second output terminals Pout of the p+1th-stage gate driver circuits GDC(p+1) through the p+2th-stage gate driver circuits GDC(p+2) receive the corresponding second clock signal CK. The p+2th-stage second gate control signal Pscan(p+2) is in a low level state. In the p+9th-stage gate driver circuits GDC(p+9) through the p+qth-stage gate driver circuits GDC(p+q), the first output transistors To1 and the fourth output transistors To4 are turned on, so that the first output terminals Nout of the p+9th-stage gate driver circuits GDC(p+9) through the p+qth-stage gate driver circuits GDC(p+q) are electrically connected to the third power supply terminal NVGL, and the second output terminals Pout of the p+9th-stage gate driver circuits GDC(p+9) through the p+qth-stage gate driver circuits GDC(p+q) are electrically connected to the second power supply terminal PVGH. Therefore, the p+9th stage first gate control signal Nscan(p+9) of the p+9th stage gate driving circuit GDC(p+9) has no valid pulse output.

[0131] Continuing with Figures 2A to 2C and 3A, in the ninth phase t9, the first clock signal CK1 provided by the first clock line CKL1 is in a high state, the second clock signal CK2 provided by the second clock line CKL2 is in a high state, the third clock signal CK3 provided by the third clock line CKL3 is in a high state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 is in a low state. The p-10th-stage first gate control signal Nscan(p-10) output by the p-10th-stage gate driver circuit GDC(p-10) and the p-1th-stage first gate control signal Nscan(p-1) output by the p-1th-stage gate driver circuit GDC(p-1) are in a low state, and the frequency division control signal LF is in a high state.

[0132] The p-th gate driver circuit GDC(p) maintains the same state as in the eighth stage t8 during the ninth stage t9. In the p+1-th through p+q-th gate driver circuits GDC(p+1) and GDC(p+q), the frequency divider transistor Tf is turned off, and the potential of the first node K1 remains at the state of the eighth stage t8. This causes the second output transistor To2 and the third output transistor To3 in the p+1-th through p+8-th gate driver circuits GDC(p+1) and GDC(p+8) to turn on, electrically connecting the first output terminal Nout of each of the p+1-th through p+8-th gate driver circuits GDC(p+1) and GDC(p+8) to the fourth power supply terminal NVGH. The second switching transistors Ts2 and second output transistors To2 in the p+1th-stage gate driver circuits GDC(p+1) through GDC(p+2) are turned on, and the second output terminals Pout of the p+1th-stage gate driver circuits GDC(p+1) through GDC(p+2) receive the corresponding second clock signal CK. The second switching transistors Ts2 and second output transistors To2 in the p+3th-stage gate driver circuit GDC(p+3) are turned off, and the p+3th-stage second control signal of the p+3th-stage gate driver circuit GDC(p+3) has no valid pulses. In the p+9th-level gate driver circuit GDC(p+9) through the p+qth-level gate driver circuit GDC(p+q), the first output transistor To1 and the fourth output transistor To4 are turned on, so that the first output terminal Nout of the p+9th-level gate driver circuit GDC(p+9) through the p+qth-level gate driver circuit GDC(p+q) are electrically connected to the third power supply terminal NVGL, and the second output terminal Pout is electrically connected to the second power supply terminal PVGH. Therefore, the p+9th-level first gate control signal Nscan(p+9) output by the p+9th-level gate driver circuit GDC(p+9) through the p+10th-level first gate control signal Nscan(p+10) output by the p+10th-level gate driver circuit GDC(p+10) have no valid pulse outputs.

[0133] Afterwards, the frequency division control signal LF maintains a high level state, and the first clock signal CK1 to the fourth clock signal CK4 switch between a high level state and a low level state. The p+9th level first gate control signal Nscan(p+9) output by the p+9th level gate drive circuit GDC(p+9) to the p+qth level first gate control signal Nscan(p+q) output by the p+qth level gate drive circuit GDC(p+q) have no valid pulse outputs, and the p+9th level second gate control signal Pscan(p+9) output by the p+9th level gate drive circuit GDC(p+9) to the p+qth level second gate control signal Pscan(p+q) output by the p+qth level gate drive circuit GDC(p+q) have no valid pulse outputs.

[0134] In the eighth stage t8 and the ninth stage t9, the electrical connection between the third transistor T3 of the gate drive circuit GDC shown in FIG2A and the first node K1 is disconnected, the control end of the first transistor T1 of the gate drive circuit GDC shown in FIG2B does not receive the corresponding start signal STV, and the control end of the third transistor T3 of the gate drive circuit GDC shown in FIG2C does not receive the corresponding first clock signal XCK.

[0135] Therefore, by controlling the frequency division control signal LF, the level states of the gate control signals output by the plurality of gate driving circuits GDC can be controlled, so as to facilitate frequency division and partitioning of the display panel when the gate driving unit is applied to the display panel.

[0136] The following describes the working principle of the gate driving unit by taking multiple gate driving circuits GDC controlled by the first frequency division control signal NLF and the second frequency division control signal PLF as an example. That is, the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the second output transistor To2 to the fourth output transistor To4 are P-type transistors, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the twelfth transistor T12, and the first output transistor To1 are N-type transistors, the first clock signal XCK corresponding to the p+4x-th gate driving circuit GDC is provided by the second clock line CKL2, the second clock signal CK corresponding to the p+4x-th gate driving circuit GDC is provided by the first clock line CKL1, and the first clock signal XCK corresponding to the p+(4x+1)-th gate driving circuit GDC is provided by the third clock line 1B , wherein p≥1, q≥1, and x≥0 are provided as an example, and the working principle of the gate driving unit including the gate driving circuit GDC shown in FIG2D and the multiple gate driving circuits GDC of the gate driving unit are cascaded in the cascade manner shown in FIG1B . Wherein, p≥1, q≥1, and x≥0 are provided.

[0137] 2D and 3B , the first embodiment will be described by taking the transition of the first frequency-divided control signal NLF from a low level state to a high level state in the p-th to p+q-th gate driving circuits GDC(p) and GDC(p+q) of the corresponding gate driving units as an example.

[0138] In the first phase t1, the first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a low-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a high-level state. The p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) and the p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a low-level state.

[0139] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0140] In the p+1th through p+3th gate drive circuits GDC(p+1) and GDC(p+3), the second transistor T2 is turned on and the third transistor T3 is turned off. Consequently, the p+1th through p+3th first gate control signals Nscan(p+1) and Nscan(p+3) remain low, and the p+1th through p+3th second gate control signals Pscan(p+1) and Pscan(p+3) remain high. The p+4th gate drive circuit GDC(p+4) performs similar operations to the p-th gate drive circuit GDC(p) during the first phase t1.

[0141] The gate driver circuit GDC, located after the p+4th-stage gate driver circuit GDC(p+4), and for which the first clock signal XCK is provided by the second clock line CKL2 and the second clock signal CK is provided by the first clock line CKL1, performs operations similar to those of the p-stage gate driver circuit GDC(p) in the first phase t1. The gate driver circuit GDC, located after the p+4th-stage gate driver circuit GDC(p+4), and for which the first clock signal XCK is not provided by the second clock line CKL2 and the second clock signal CK is not provided by the first clock line CKL1, performs operations similar to those of the p+1st-stage gate driver circuits GDC(p+1) to the p+3th-stage gate driver circuits GDC(p+3) in the first phase t1.

[0142] In the second phase t2, the first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a low-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a high-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a low-level state.

[0143] In the p-th stage gate drive circuit GDC(p), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains high.

[0144] In the p+1-th stage gate drive circuit GDC(p+1), the first transistor T1 is turned on, the third transistor T3 is turned off, the p+1-th stage first gate control signal Nscan(p+1) maintains a low level state, and the p+1-th stage second gate control signal Pscan(p+1) maintains a high level state. In the p+2-th stage gate drive circuit GDC(p+2), the second transistor T2 is turned on, the third transistor T3 is turned off, the p+2-th stage first gate control signal Nscan(p+2) maintains a low level state, and the p+2-th stage second gate control signal Pscan(p+2) maintains a high level state.

[0145] The gate driver circuit GDC, located after the p+2-th stage gate driver circuit GDC(p+2), and to which the first clock signal XCK is correspondingly provided by the second clock line CKL2 and the second clock signal CK is correspondingly provided by the first clock line CKL1, performs, in the second phase t2, actions similar to those performed by the p-th stage gate driver circuit GDC(p) in the first phase t1. The gate driver circuit GDC, located after the p+2-th stage gate driver circuit GDC(p+2), and to which the first clock signal XCK is not correspondingly provided by the second clock line CKL2 and the second clock signal CK is not correspondingly provided by the first clock line CKL1, performs, in the second phase t2, actions similar to those performed by the p+1-th stage gate driver circuits GDC(p+1) to the p+3-th stage gate driver circuits GDC(p+3) in the first phase t1.

[0146] In the third phase t3, the first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a low-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a high-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a low-level state.

[0147] In the p-th stage gate drive circuit GDC(p), the first transistor T1, the sixth transistor T6, the eighth transistor T8, the second output transistor To2, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 remain turned on, the fourth transistor T4, the ninth transistor T9, and the twelfth transistor T12 are turned on, the third transistor T3 is turned off, and the second transistor T2, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 remain turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains high.

[0148] During the third phase t3, the p+1-th gate driver circuit GDC(p+1) performs operations similar to those performed by the p-th gate driver circuit GDC(p) during the second phase t2, electrically connecting the fourth power supply terminal NVGH of the p+1-th gate driver circuit GDC(p+1) to the first output terminal Nout, and maintaining the p+1-th second gate control signal Pscan(p+1) at a high level. During the third phase t3, the p+2-th gate driver circuit GDC(p+2) performs operations similar to those performed by the p+1-th gate driver circuit GDC(p+1) during the second phase t2. Similarly, the operations performed by the p+3-th through p+q-th gate driver circuits GDC(p+3) during the third phase t3 are obtained.

[0149] Fourth stage t4: The first clock signal CK1 is in a low state, the second clock signal CK2 is in a high state, the third clock signal CK3 is in a high state, and the fourth clock signal CK4 is in a high state. The p-1th level first gate control signal Nscan(p-1) output by the p-1th level gate driver circuit GDC(p-1) and the p-2th level first gate control signal Nscan(p-2) output by the p-2th level gate driver circuit GDC(p-2) are in a low state. The first frequency division control signal NLF is in a low state, and the second frequency division control signal PLF is in a low state.

[0150] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan outputted by the second output terminal Pout is in a low level state.

[0151] In the p+1th-stage gate driver circuit GDC(p+1) through the p+2th-stage gate driver circuit GDC(p+2) and the p+4th-stage gate driver circuit GDC(p+4) through the p+5th-stage gate driver circuit GDC(p+5), the third transistor T3 is turned off. Therefore, the potential of the first node K1 and the potential of the third node P in the p+1th-stage gate driver circuit GDC(p+1) through the p+2th-stage gate driver circuit GDC(p+2) and the p+4th-stage gate driver circuit GDC(p+4) through the p+5th-stage gate driver circuit GDC(p+5) remain the same as in the third stage t3. In the p+3th-stage gate driver circuit GDC(p+3), the first transistor T1 and the third transistor T3 are turned on, and the first power supply terminal PVGL is electrically connected to the first node K1. Therefore, the p+1th level first gate control signal Nscan(p+1) to the p+5th level first gate control signal Nscan(p+5) maintain a high level state, and the p+1th level first gate control signal Nscan(p+1) to the p+5th level first gate control signal Nscan(p+5) maintain a high level state.

[0152] The p+6th-stage gate driver circuit GDC(p+6) performs an action similar to the action performed by the p-stage gate driver circuit GDC(p) in the third stage t3 during the fourth stage t4. The p+7th-stage gate driver circuit GDC(p+7) performs an action similar to the action performed by the p+1st-stage gate driver circuit GDC(p+1) in the third stage t3 during the fourth stage t4. Similarly, the actions performed by the p+8th-stage gate driver circuit GDC(p+8) to the p+qth-stage gate driver circuit GDC(p+q) during the fourth stage t4 are obtained.

[0153] Fifth stage t5: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a low-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a low-level state.

[0154] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0155] The p+1th-stage gate driver circuit GDC(p+1) performs an action similar to the action performed by the p-th-stage gate driver circuit GDC(p) in the fourth stage t4 during the fifth stage t5, thereby causing the p+1th-stage second gate control signal Pscan(p+1) to be in a low-level state. The p+2th-stage gate driver circuit GDC(p+2) performs an action similar to the action performed by the p+1th-stage gate driver circuit GDC(p+1) in the fourth stage t4 during the sixth stage t6. Similarly, the actions performed by the p+3th-stage gate driver circuit GDC(p+3) through the p+qth-stage gate driver circuit GDC(p+q) during the fifth stage t5 are obtained.

[0156] Phase 6 t6: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a low-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a low-level state.

[0157] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0158] The p+1th-stage gate driver circuit GDC(p+1) performs an action similar to the action performed by the p-th-stage gate driver circuit GDC(p) in the fifth stage t5 during the sixth stage t6, thereby causing the p+1th-stage first gate control signal Nscan(p+1) to be in a low-level state. The p+2th-stage gate driver circuit GDC(p+2) performs an action similar to the action performed by the p+1th-stage gate driver circuit GDC(p+1) in the fifth stage t5 during the sixth stage t6, thereby causing the p+2th-stage second gate control signal Pscan(p+2) to be in a low-level state. Similarly, the actions performed by the p+3th-stage gate driver circuit GDC(p+3) to the p+qth-stage gate driver circuit GDC(p+q) during the sixth stage t6 are obtained.

[0159] Seventh stage t7: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a low-level state. The p-1th stage first gate control signal Nscan(p-1) output by the p-1th stage gate driver circuit GDC(p-1) and the p-2th stage first gate control signal Nscan(p-2) output by the p-2th stage gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a high-level state, and the second frequency division control signal PLF is in a low-level state.

[0160] The p-th stage gate driver circuit GDC(p) maintains the same state as in the sixth stage t6 during the seventh phase t7. The p+1-th stage gate driver circuit GDC(p+1) performs an operation similar to the operation performed by the p-th stage gate driver circuit GDC(p) during the sixth stage t6 during the seventh phase t7. The p+2-th stage gate driver circuit GDC(p+2) performs an operation similar to the operation performed by the p+1-th stage gate driver circuit GDC(p+1) during the sixth stage t6 during the seventh phase t7. The p+3-th stage gate driver circuit GDC(p+3) performs an operation similar to the operation performed by the p+2-th stage gate driver circuit GDC(p+2) during the sixth stage t6 during the seventh phase t7, thereby causing the p+3-th stage second gate control signal Pscan(p+3) to be in a low-level state. Similarly, the operations performed by the p+4-th stage gate driver circuits GDC(p+4) through the p+9-th stage gate driver circuits GDC(p+9) during the seventh phase t7 are obtained.

[0161] In the p+10th stage gate drive circuit GDC(p+10), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains in a high level state.

[0162] In the p+11th stage gate drive circuit GDC(p+11), the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, and the fourth frequency-dividing transistor Tf4 are turned on, and the second transistor T2, the third transistor T3, the eleventh transistor T11, and the second frequency-dividing transistor Tf2 are turned off. Therefore, the p+11th stage first gate control signal Nscan(p+11) has a low level state, and the p+11th stage second gate control signal Pscan(p+11) has a high level state.

[0163] In the p+12th to p+qth gate drive circuits GDC(p+12), the first, third, and fourth frequency-dividing transistors Tf1, Tf3, and Tf4 are turned on, and the second frequency-dividing transistor Tf2 is turned off.

[0164] Phase 8 t8: The first clock signal CK1 is in a low-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a high-level state, and the second frequency division control signal PLF is in a low-level state.

[0165] The p-th stage gate driver circuit GDC(p) maintains the same state as that in the seventh stage t7 during the eighth stage t8. The p+1-th stage gate driver circuit GDC(p+1) performs an operation similar to that performed by the p-th stage gate driver circuit GDC(p) during the seventh stage t7 during the eighth stage t8. The p+2-th stage gate driver circuit GDC(p+2) performs an operation similar to that performed by the p+1-th stage gate driver circuit GDC(p+1) during the seventh stage t7 during the eighth stage t8. The p+3-th stage gate driver circuit GDC(p+3) performs an operation similar to that performed by the p+2-th stage gate driver circuit GDC(p+2) during the seventh stage t7 during the eighth stage t8. The p+4-th stage gate driver circuit GDC(p+4) performs an operation similar to that performed by the p+3-th stage gate driver circuit GDC(p+3) during the seventh stage t7 during the eighth stage t8, so that the p+4-th stage second gate control signal Pscan(p+4) has a low level. Similarly, the actions performed by the p+5th-stage gate driving circuit GDC(p+5) to the p+9th-stage gate driving circuit GDC(p+9) in the seventh stage t7 are obtained.

[0166] In the p+10th stage gate drive circuit GDC(p+10), the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains in a high level state.

[0167] In the p+11th level gate drive circuit GDC(p+11), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the fourth frequency-dividing transistor Tf4 are turned on, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the third frequency-dividing transistor Tf3, and the first output transistor To1 to the fourth output transistor To4 are turned off, so that the p+11th level first gate control signal Nscan(p+11) maintains a low level state, and the p+11th level second gate control signal Pscan(p+11) maintains a high level state.

[0168] In the p+12th-level gate drive circuit GDC(p+12) to the p+13th-level gate drive circuit GDC(p+13), the second transistor T2 is turned on and the third transistor T3 is turned off. Therefore, the p+12th-level first gate control signal Nscan(p+12) and the p+13th-level second gate control signal Pscan(p+13) maintain the same state as that of the seventh stage t7, and the p+12th-level second gate control signal Pscan(p+12) and the p+13th-level second gate control signal Pscan(p+13) maintain the same state as that of the seventh stage t7.

[0169] The p+14th-stage gate driver circuit GDC(p+14) performs an action similar to the action performed by the p+13th-stage gate driver circuit GDC(p+13) at the seventh stage t7 at the eighth stage t8. The p+15th-stage gate driver circuit GDC(p+15) performs an action similar to the action performed by the p+14th-stage gate driver circuit GDC(p+14) at the seventh stage t7 at the eighth stage t8. Similarly, the actions performed by the p+16th-stage gate driver circuit GDC(p+16) to the p+qth-stage gate driver circuit GDC(p+q) at the eighth stage t8 are obtained.

[0170] Ninth stage t9: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a low-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a high-level state, and the second frequency division control signal PLF is in a low-level state.

[0171] During the ninth phase t9, the p-th through p+3-th stage gate driver circuits GDC(p) maintain the same state as during the eighth phase t8. The p+4-th through p+8-th stage first gate control signals Nscan(p+4) and Nscan(p+8) are low, and the p+4-th through p+8-th stage second gate control signals Pscan(p+4) and Pscan(p+8) are high. The p+9-th stage gate driver circuit GDC(p+9) performs operations similar to those performed by the p+3-th stage gate driver circuit GDC(p+3) during the eighth phase t8. The p+10-th stage gate driver circuit GDC(p+10) performs operations similar to those performed by the p+4-th stage gate driver circuit GDC(p+4) during the eighth phase t8 during the ninth phase t9.

[0172] That is, in the p+9th level gate drive circuit GDC(p+9), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the first output transistor To1 and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2 and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0173] In the p+10 stage gate drive circuit GDC, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p+10 stage second gate control signal Pscan(p+10) output by the second output terminal Pout is in a low level state.

[0174] In the p+11th-stage gate drive circuits GDC(p+11) through GDC(p+12), the second transistor T2 is turned on and the third transistor T3 is turned off. Therefore, the p+11th-stage first gate control signal Nscan(p+11) and the p+12th-stage first gate control signal Nscan(p+12) maintain the same state as in the eighth stage t8, and the p+11th-stage second gate control signal Pscan(p+11) and the p+12th-stage second gate control signal Pscan(p+12) maintain the same state as in the eighth stage t8. In the p+11th-stage gate drive circuit GDC(p+11), the eleventh transistor T11 and the third output transistor To3 are turned on.

[0175] The p+13th-stage gate driver circuit GDC(p+13) performs an action similar to the action performed by the p+11th-stage gate driver circuit GDC(p+11) at the eighth stage t8 at the ninth stage t9. The p+14th-stage gate driver circuit GDC(p+14) performs an action similar to the action performed by the p+12th-stage gate driver circuit GDC(p+12) at the eighth stage t8 at the ninth stage t9. Similarly, the actions performed by the p+15th-stage gate driver circuit GDC(p+15) to the p+qth-stage gate driver circuit GDC(p+q) at the ninth stage t9 are obtained.

[0176] In the tenth stage t10, the first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a low-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a high-level state, and the second frequency division control signal PLF is in a low-level state.

[0177] The p-th level gate driving circuit GDC(p) to the p+9-th level gate driving circuit GDC(p+9) maintain the same state as the ninth stage t9 in the tenth stage t10, and the p+10-th level gate driving circuit GDC(p+10) performs actions similar to those performed by the p+9-th level gate driving circuit GDC(p+9) in the ninth stage t9 in the tenth stage t10.

[0178] That is, in the p+10-level gate drive circuit GDC, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the fourth frequency-dividing transistor Tf4, the first output transistor To1 and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2 and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0179] In the p+11th stage gate drive circuit GDC(p+11), the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the fourth frequency-dividing transistor Tf4, and the third output transistor To3 are turned on, while the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the second frequency-dividing transistor Tf2, the third frequency-dividing transistor Tf3, the first output transistor To1, the second output transistor To2, and the fourth output transistor To4 are turned off. The p+11th stage first gate control signal Nscan(p+11) maintains the state of the ninth stage t9, and the p+11th stage second gate control signal Pscan(p+11) outputted from the second output terminal Pout is in a low level state.

[0180] In the p+12th gate drive circuit GDC to the p+13th gate drive circuit GDC, the third transistor T3 is turned off, the p+12th first gate control signal Nscan(p+12) and the p+13th first gate control signal Nscan(p+13) maintain the same state as in the ninth stage t9, and the p+12th second gate control signal Pscan(p+12) and the p+13th second gate control signal Pscan(p+13) maintain the same state as in the ninth stage t9.

[0181] The p+14th-stage gate driver circuit GDC(p+14) performs an action similar to the action performed by the p+13th-stage gate driver circuit GDC(p+13) at the ninth stage t9 at the tenth stage t10. The p+15th-stage gate driver circuit GDC(p+15) performs an action similar to the action performed by the p+14th-stage gate driver circuit GDC(p+14) at the ninth stage t9 at the tenth stage t10. Similarly, the actions performed by the p+15th-stage gate driver circuit GDC(p+15) to the p+qth-stage gate driver circuit GDC(p+q) at the tenth stage t10 are obtained.

[0182] Phase 11: The first clock signal CK1 is in a low state, the second clock signal CK2 is in a high state, the third clock signal CK3 is in a high state, and the fourth clock signal CK4 is in a high state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low state. The first frequency division control signal NLF is in a high state, and the second frequency division control signal PLF is in a low state.

[0183] The p-th to p+10-th stage gate driving circuits GDC(p) to GDC(p+10) maintain the same state as that of the tenth stage t10 in the eleventh stage t11.

[0184] In the p+11th level gate drive circuit GDC(p+11), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth frequency-dividing transistor Tf4, the first output transistor To1 and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the second output transistor To2 and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0185] Afterwards, if the corresponding start signal STV received by the first transistor T1 and the second transistor T2 of each stage of the gate driving circuit GDC is provided by the first output terminal Nout of the previous stage gate driving circuit GDC, then, in the p+12th stage gate driving circuit GDC(p+12) to the p+qth stage gate driving circuit GDC(p+q), since the corresponding start signal STV received by the first transistor T1 and the second transistor T2 of each stage of the gate driving circuit GDC is low level, the p+12th stage gate driving circuit GDC(p+ The p+12th level first gate control signal Nscan(p+12)~the p+qth level first gate control signal Nscan(p+q) output by the p+12th level gate drive circuit GDC(p+q) maintain a low level state, and the p+12th level second gate control signal Pscan(p+12)~the p+qth level second gate control signal Pscan(p+q) output by the p+12th level gate drive circuit GDC(p+12)~the p+qth level gate drive circuit GDC(p+q) maintain a high level state.

[0186] If the start signal STV received by the first transistor T1 and the second transistor T2 of each stage of the gate driving circuit GDC corresponds to the potential of the third node P of the previous stage gate driving circuit GDC, then, in the p+12th stage gate driving circuit GDC(p+12) to the p+qth stage gate driving circuit GDC(p+q), the p+12th stage first gate control signal Nscan(p+12) to the p+qth stage first gate control signal Nscan(p+q) output by the p+12th stage gate driving circuit GDC(p+12) to the p+qth stage gate driving circuit GDC(p+q) maintain a low level state, and the p+12th stage second gate control signal Pscan(p+12) to the p+qth stage second gate control signal Pscan(p+q) output by the p+12th stage gate driving circuit GDC(p+12) to the p+qth stage gate driving circuit GDC(p+q) have a level state corresponding to the corresponding second clock signal CK in some time periods.

[0187] Therefore, by controlling the first frequency division control signal NLF, the level states of the gate control signals output by the plurality of gate driving circuits GDC can be controlled, so as to facilitate frequency division and partitioning of the display panel when the gate driving unit is applied to the display panel.

[0188] 2D and 3C , the second frequency-divided control signal PLF is described as an example in which the second frequency-divided control signal PLF transitions from a low level state to a high level state in the p-th to p+q-th gate driving circuits GDC(p) and GDC(p+q) of the corresponding gate driving units.

[0189] When the first frequency-dividing control signal NLF is at a low level and the second frequency-dividing control signal PLF is at a low level, the operating principle of the p-th to p+q-th gate driving circuits GDC(p) to GDC(p+q) corresponding to the first to sixth stages t1 to t6 can be understood by referring to the description of the first to sixth stages t6 in FIG. 2D and FIG. Therefore, starting from the seventh stage t7, the transition of the second frequency-dividing control signal PLF from a low level to a high level in the p-th to p+q-th gate driving circuits GDC(p) to GDC(p+q) corresponding to the gate driving unit will be described.

[0190] Seventh stage t7: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a low-level state. The p-1th-level first gate control signal Nscan(p-1) output by the p-1th-level gate drive circuit GDC(p-1) and the p-2th-level first gate control signal Nscan(p-2) output by the p-2th-level gate drive circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a low-level state.

[0191] In the p-th level gate drive circuit GDC(p) to the p+1-th level gate drive circuit GDC(p+1), the third transistor T3, the p-th level first gate control signal Nscan(p) to the p+1-th level first gate control signal Nscan(p+1) have a low level state, and the p-th level second gate control signal Pscan to the p+1-th level second gate control signal Pscan(p+1) have a high level state.

[0192] The p+2-th stage gate driver circuit GDC(p+2) performs an action similar to the action performed by the p+1-th stage gate driver circuit GDC(p+1) at the sixth stage t6 in the seventh phase t7, so that the p+2-th stage first gate control signal Nscan(p+2) is in a low-level state. The p+3-th stage gate driver circuit GDC(p+3) performs an action similar to the action performed by the p+2-th stage gate driver circuit GDC(p+2) at the sixth stage t6 in the seventh phase t7, so that the p+3-th stage second gate control signal Pscan(p+3) is in a low-level state. And so on, the actions performed by the p+4-th stage gate driver circuit GDC(p+4) to the p+q-th stage gate driver circuit GDC(p+q) at the seventh phase t7 are obtained.

[0193] Phase 8 t8: The first clock signal CK1 is in a low-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a high-level state.

[0194] During the eighth phase t8, the p-th through p+2-th gate driver circuits GDC(p) maintain the same state as during the seventh phase t7. During the eighth phase t8, the p+3-th gate driver circuit GDC(p+3) performs operations similar to those performed by the p+2-th gate driver circuit GDC(p+2) during the seventh phase t7, thereby causing the p+3-th first gate control signal Nscan(p+3) to be low. During the eighth phase t8, the p+4-th gate driver circuit GDC(p+4) performs operations similar to those performed by the p+3-th gate driver circuit GDC(p+3) during the seventh phase t7, thereby causing the p+4-th second gate control signal Pscan(p+4) to be low. Similarly, the operations performed by the p+5-th through p+10-th gate driver circuits GDC(p+5) during the eighth phase t8 are obtained.

[0195] In the p+11th stage gate drive circuit GDC(p+11), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains in a high state.

[0196] In the p+12th-stage gate drive circuit GDC(p+12), the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, and the first to third frequency-dividing transistors Tf1 to Tf3 are turned on, while the second transistor T2, the third transistor T3, the eleventh transistor T11, and the fourth frequency-dividing transistor Tf4 are turned off. Therefore, the p+12th-stage first gate control signal Nscan(p+12) is in a low-level state, and the p+12th-stage second gate control signal Pscan(p+12) is in a high-level state.

[0197] In the p+13th to p+qth gate driving circuits GDC(p+13), the first to third frequency dividing transistors Tf1 to Tf3 are turned on, and the fourth frequency dividing transistor Tf4 is turned off.

[0198] Ninth stage t9: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a low-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a high-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a high-level state.

[0199] During the ninth phase t9, the p-th through p+3-th gate driver circuits GDC(p) maintain the same state as during the eighth phase t8. During the ninth phase t9, the p+4-th gate driver circuit GDC(p+4) performs operations similar to those performed by the p+3-th gate driver circuit GDC(p+3) during the eighth phase t8, thereby causing the p+4-th first gate control signal Nscan(p+4) to be low. During the ninth phase t9, the p+5-th gate driver circuit GDC(p+5) performs operations similar to those performed by the p+4-th gate driver circuit GDC(p+4) during the eighth phase t8, thereby causing the p+5-th second gate control signal Pscan(p+5) to be low. Similarly, the operations performed by the p+6-th through p+10-th gate driver circuits GDC(p+6) during the ninth phase t9 are obtained.

[0200] In the p+11th stage gate drive circuit GDC(p+11), the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains in a high level state.

[0201] In the p+12th stage gate drive circuit GDC(p+12), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second frequency-dividing transistor Tf2 are turned on, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth frequency-dividing transistor Tf4, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off, the fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p+12th stage second gate control signal Pscan(p+12) maintains a high level state.

[0202] In the p+13th-level gate drive circuit GDC(p+13) to the p+14th-level gate drive circuit GDC(p+14), the third transistor T3 is turned off, and thus, the p+13th-level first gate control signal Nscan(p+13) and the p+14th-level second gate control signal Pscan(p+14) maintain the same state as in the ninth stage t9, and the p+13th-level second gate control signal Pscan(p+13) and the p+14th-level second gate control signal Pscan(p+14) maintain the same state as in the ninth stage t9.

[0203] The p+15th-stage gate driver circuit GDC(p+15) performs an action similar to the action performed by the p+14th-stage gate driver circuit GDC(p+14) at the eighth stage t8 at the ninth stage t9. The p+16th-stage gate driver circuit GDC(p+16) performs an action similar to the action performed by the p+15th-stage gate driver circuit GDC(p+15) at the eighth stage t8 at the ninth stage t9. Similarly, the actions performed by the p+17th-stage gate driver circuit GDC(p+17) to the p+qth-stage gate driver circuit GDC(p+q) at the ninth stage t9 are obtained.

[0204] Phase 10 t10: The first clock signal CK1 is in a high-level state, the second clock signal CK2 is in a high-level state, the third clock signal CK3 is in a high-level state, and the fourth clock signal CK4 is in a low-level state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low-level state. The first frequency division control signal NLF is in a low-level state, and the second frequency division control signal PLF is in a high-level state.

[0205] The p-th through p+4-th stage gate driver circuits GDC(p) maintain the same state as in the ninth stage t9 during the tenth stage t10. The p+5-th through p+9-th stage first gate control signals Nscan(p+5) and Nscan(p+9) are low, and the p+5-th through p+9-th stage second gate control signals Pscan(p+5) and Pscan(p+9) are high. The p+10-th stage gate driver circuit GDC(p+10) performs an operation similar to that performed by the p+4-th stage gate driver circuit GDC(p+4) during the ninth stage t9, causing the p+10-th stage first gate control signal Nscan(p+10) to be low during the tenth stage t10. The p+11th stage gate driving circuit GDC(p+11) performs an action similar to the action performed by the p+5th stage gate driving circuit GDC(p+5) at the ninth stage t9, so that the p+11th stage second gate control signal Pscan(p+11) has a low level state.

[0206] That is, in the p+11-stage gate drive circuit GDC, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p+11-stage second gate control signal Pscan(p+11) outputted from the second output terminal Pout is in a low level state.

[0207] In the p+12th-stage gate driver circuits GDC(p+12) to GDC(p+13), the third transistor T3 is turned off, the p+12th-stage first gate control signal Nscan(p+12) and the p+13th-stage first gate control signal Nscan(p+13) maintain the same state as in the ninth stage t9, and the p+12th-stage second gate control signal Pscan(p+12) and the p+13th-stage second gate control signal Pscan(p+13) maintain the same state as in the ninth stage t9. In the p+12th-stage gate driver circuit GDC(p+12), the eleventh transistor T11 is turned on.

[0208] The p+14th-stage gate driver circuit GDC(p+14) performs an action similar to the action performed by the p+8th-stage gate driver circuit GDC(p+8) at the ninth stage t9 at the tenth stage t10. The p+15th-stage gate driver circuit GDC(p+15) performs an action similar to the action performed by the p+9th-stage gate driver circuit GDC(p+9) at the ninth stage t9 at the tenth stage t10. Similarly, the actions performed by the p+16th-stage gate driver circuit GDC(p+16) to the p+qth-stage gate driver circuit GDC(p+q) at the tenth stage t10 are obtained.

[0209] Phase 11: The first clock signal CK1 is in a low state, the second clock signal CK2 is in a high state, the third clock signal CK3 is in a high state, and the fourth clock signal CK4 is in a high state. The p-1-th level first gate control signal Nscan(p-1) output by the p-1-th level gate driver circuit GDC(p-1) and the p-2-th level first gate control signal Nscan(p-2) output by the p-2-th level gate driver circuit GDC(p-2) are in a low state. The first frequency division control signal NLF is in a low state, and the second frequency division control signal PLF is in a high state.

[0210] The p-th to p+10-th stage gate driver circuits GDC(p) to GDC(p+10) maintain the same state at the eleventh stage t11 as at the tenth stage t10. The p+11-th stage gate driver circuit GDC(p+11) performs an operation at the eleventh stage t11 similar to the operation performed by the p+10-th stage gate driver circuit GDC(p+10) at the tenth stage t10, so that the p+11-th stage first gate control signal Nscan(p+11) is in a low level state.

[0211] In the p+12th stage gate driver circuit GDC(p+12), the p+11th stage first gate control signal Nscan(p+11) maintains the state at the tenth stage t10. Because the fourth frequency-dividing transistor Tf4 is turned off, the p+11th stage second gate control signal Pscan(p+11) maintains the state at the tenth stage t10.

[0212] Similarly, the operating principles of the p+13th-stage gate driving circuit GDC(p+13) to the p+qth-stage gate driving circuit GDC(p+q) corresponding to the eleventh stage t11 can be obtained.

[0213] By analogy, after the eleventh stage t11, the operating principles of the pth stage gate driving circuit GDC(p) to the p+qth stage gate driving circuit GDC(p+q) can be obtained by referring to the description of the seventh stage t7 to the eleventh stage t11.

[0214] It can be understood that the level change time of the first frequency-division control signal NLF and the level change time of the second frequency-division control signal PLF may be the same as or different from each other.

[0215] It can be understood that the working principle of the first frequency division control signal NLF and the second frequency division control signal PLF when the p-th level gate driving circuit GDC(p) to the p+q-th level gate driving circuit GDC(p+q) of the corresponding gate driving unit all have a jump from a low level state to a high level state can be obtained with reference to the working principles of Figures 2D and 3B to 3C.

[0216] It can be understood that by adjusting the level state change moment of the first frequency-dividing control signal NLF, the multi-stage first gate control signal Nscan can be controlled to have no valid pulse at the beginning of the corresponding different stages. By adjusting the level state change moment of the second frequency-dividing control signal PLF, the multi-stage second gate control signal Pscan can be controlled to have no valid pulse at the beginning of the corresponding different stages.

[0217] It can be understood that by adjusting the position of the level state change moment of the first frequency-division control signal NLF relative to the level state change moment of the second frequency-division control signal PLF, the display panel using the gate driving unit can reduce the frequency of the first gate control signal Nscan and the second gate control signal Pscan at different positions.

[0218] According to the working principles analyzed in Figures 2A to 2C and Figure 3A, the gate drive circuit GDC shown in Figures 2A to 2C is used in conjunction with the frequency-dividing control signal LF to control the level state of the gate control signal. When the level state of the frequency-dividing control signal LF changes, some gate drive circuits GDC will implement a transition (for example, after the sixth stage t6, the p+1-th level first gate control signal Nscan(p+1) to the p+8-th level first gate control signal Nscan(p+8) always maintain a high level state. Correspondingly, the p+1-th level second gate control signal Pscan(p+1) to the p+8-th level second gate control signal Pscan(p+8) correspond to the state of the corresponding second clock signal CK), so that the gate control signals output by the subsequent gate drive circuits GDC (such as the p+9-th level gate drive circuit GDC(p+9) to the p+q-th level gate drive circuit GDC(p+q)) are pulse-free.

[0219] According to the working principles analyzed in Figures 2D and 3B to 3C, the gate drive circuit GDC shown in Figure 2D is used in conjunction with the two-frequency division control signal LF to control the level state of the gate control signal. This can make the multi-level first gate control signal Nscan output by the gate drive unit no longer always be in a high level state, and the multi-level second gate control signal no longer always corresponds to the state of the second clock signal CK. This can improve the problems that occur in the gate drive circuit GDC shown in Figures 2A to 2C (that is, after the sixth stage t6, the p+1th level first gate control signal Nscan(p+1) to the p+8th level first gate control signal Nscan(p+8) always maintain a high level state. Correspondingly, the p+1th level second gate control signal Pscan(p+1) to the p+8th level second gate control signal Pscan(p+8) correspond to the state of the corresponding second clock signal CK).

[0220] Furthermore, when the gate drive circuit GDC shown in Figures 2A to 2C is used in conjunction with the frequency-divided control signal LF to control the level of the gate control signal, after the level of the frequency-divided control signal LF changes, the multi-level first gate control signal Nscan may experience a step problem (as shown at A' in Figure 3D) due to the large capacitance of the first capacitor C1 and insufficient conduction of the first switching transistor Ts1. This step problem persists for a number of rows equal to the number of row cycles in which the first gate control signal Nscan remains high. Using the gate drive circuit GDC shown in Figure 2D can alleviate the step problem in the first gate control signal Nscan.

[0221] When the gate drive circuit GDC shown in Figures 2A to 2C is applied to a display panel to implement low-frequency control, the potential of the third node P is used as the start signal STV of the corresponding level of the gate drive circuit GDC, so that the potential of the third node P can correspond to the level transmission signal to achieve frequency reduction in any area of ​​the display panel.

[0222] Optionally, in some embodiments, when the gate drive circuit GDC shown in Figures 2A to 2C is used in conjunction with the frequency division control signal LF to realize the control of the level state of the gate control signal, when the first gate control signal Nscan and the second gate control signal Pscan output by the corresponding level gate drive circuit GDC controlled by the frequency division control signal LF do not have a valid pulse output (such as after the ninth stage t9 corresponding to Figure 3A), the first clock signal CK1 to the fourth clock signal CK4 can be controlled to be in a high level state, thereby reducing power consumption.

[0223] The present application also provides a display device, comprising any of the above-mentioned gate driving units.

[0224] 4 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device includes a display panel and a gate driving unit.

[0225] The display panel includes a plurality of sub-pixels Spi, a plurality of scan lines, and a plurality of data lines DL. The plurality of scan lines and the plurality of data lines DL are electrically connected between a gate driving unit and the plurality of sub-pixels Spi. The plurality of data lines DL are configured to transmit a plurality of data signals.

[0226] Optionally, the multiple scan lines include multiple first scan lines SL1 and multiple second scan lines SL2, the multiple first scan lines SL1 are electrically connected between the first output terminals Nout of the multiple gate drive circuits GDC and the multiple sub-pixels Spi, the multiple second scan lines SL2 are electrically connected between the second output terminals Pout of the multiple gate drive circuits GDC and the multiple sub-pixels Spi, the multiple first scan lines SL1 are configured to transmit multiple first gate control signals Nscan, and the multiple second scan lines SL2 are configured to transmit multiple second gate control signals Pscan.

[0227] Each sub-pixel Spi includes a light-emitting device Di and a pixel driving circuit for driving the light-emitting device Di to emit light.

[0228] Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0229] FIG5 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application.

[0230] The pixel driving circuit includes at least a driving transistor Tdr, a data transistor Tda, and a compensation transistor Tc.

[0231] The driving transistor Tdr and the light emitting device Di are connected in series between the first voltage terminal VDD and the second voltage terminal VSS. The driving transistor Tdr is configured to generate a driving current according to a data signal Vdata transmitted by the corresponding data line DL to drive the light emitting device Di to emit light.

[0232] The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0233] An input terminal of the data transistor Tda is electrically connected to the corresponding data line DL, and the input terminal of the data transistor Tda is configured to receive a corresponding data signal Vdata. An output terminal of the data transistor Tda is electrically connected to an input terminal of the driving transistor Tdr.

[0234] Among them, the first gate control signal Nscan generated by multiple gate driving circuits GDC is output to the control end of the compensation transistor Tc of multiple sub-pixels Spi through multiple first scanning lines SL1; the second gate control signal Pscan generated by multiple gate driving circuits GDC is output to the control end of the data transistor Tda of multiple sub-pixels Spi through multiple second scanning lines SL2.

[0235] By making the data transistors Tda and compensation transistors Tc of multiple sub-pixels Spi be controlled by the first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit, the conduction status of at least one of the corresponding data transistors Tda and compensation transistors Tc is controlled at the position where the display panel needs to achieve frequency division, thereby controlling whether the content displayed by the corresponding sub-pixel Spi is changed, so that the display panel can achieve partitioned and frequency division display.

[0236] Optionally, the compensation transistor Tc includes an oxide transistor or a silicon transistor.

[0237] Optionally, the compensation transistor Tc is a P-type transistor or an N-type transistor, and the data transistor Tda is a P-type transistor or an N-type transistor.

[0238] Optionally, in the gate driving unit, the voltage corresponding to the second power terminal PVGH is greater than the voltage corresponding to the first power terminal PVGL, the voltage corresponding to the fourth power terminal NVGH is greater than the voltage corresponding to the third power terminal NVGL, the compensation transistor Tc is an N-type transistor, and the data transistor Tda is a P-type transistor.

[0239] Optionally, the plurality of scan lines further include a third scan line SL3. Continuing with FIG. 5 , the pixel driving circuit includes a first reset transistor Ti1. A control terminal of the first reset transistor Ti1 is electrically connected to the corresponding third scan line SL3. An input terminal of the first reset transistor Ti1 is configured to receive a first reset signal Vi1. An output terminal of the first reset transistor Ti1 is electrically connected to the control terminal of the driving transistor Tdr. The first reset transistor Ti1 is configured to transmit the first reset signal Vi1 to the control terminal of the driving transistor Tdr to reset the potential of the control terminal of the driving transistor Tdr.

[0240] Optionally, in some embodiments, the first gate control signal Nscan generated by multiple gate driving circuits GDC is output to the control end of the first reset transistor Ti1 of multiple sub-pixels Spi through multiple first scanning lines SL1, and the second gate control signal Pscan generated by multiple gate driving circuits GDC is output to the control end of the data transistor Tda of multiple sub-pixels Spi through multiple second scanning lines SL2, so as to make the data transistors Tda and the first reset transistor Ti1 of the multiple sub-pixels Spii controlled by the first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit, so as to control whether the content displayed by the corresponding sub-pixel Spii changes at the position where the display panel needs to achieve frequency division, so that the display panel can achieve partitioned frequency division display.

[0241] Optionally, in some embodiments, multiple third scan lines SL3 are electrically connected between the control end of the first reset transistor Ti1 of multiple sub-pixels Spi and the first output end Nout of the gate driving unit, so that the first gate control signal Nscan generated by the multiple gate driving circuits GDC is output to the control end of the compensation transistor Tc of the multiple sub-pixels Spi through the multiple first scan lines SL1; the second gate control signal Pscan generated by the multiple gate driving circuits GDC is output to the control end of the data transistor Tda of the multiple sub-pixels Spi through the multiple second scan lines SL2; the first gate control signal Nscan generated by the multiple gate driving circuits GDC is output to the control end of the first reset transistor Ti1 of the multiple sub-pixels Spi through the multiple third scan lines SL3, so that the data transistor Tda, the first reset transistor Ti1 and the compensation transistor Tc of the multiple sub-pixels Spi are controlled by the first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit, so that the display panel can achieve zoned frequency display.

[0242] Optionally, when both the first reset transistor Ti1 and the compensation transistor Tc are controlled by the first gate control signal Nscan of the gate drive unit, the control end of the first reset transistor Ti1 and the control end of the compensation transistor Tc receive different levels of the first gate control signal Nscan. For example, the control end of the first reset transistor Ti1 of the sub-pixel Spii located in the nth row receives the nDth level first gate control signal Nscan, and the control end of the compensation transistor Tc of the sub-pixel Spii located in the nth row receives the n+Eth level first gate control signal Nscan, where D ≥ 1 and E ≥ 1.

[0243] Optionally, the second gate control signal Pscan received by the control terminal of the data transistor Tda and the first gate control signal Nscan received by the control terminal of the compensation transistor Tc are provided by different gate drive circuits GDC. For example, the control terminal of the data transistor Tda of the sub-pixel Spi in the n-th row receives the n-th level second gate control signal Pscan, and the control terminal of the compensation transistor Tc of the sub-pixel Spi in the n-th row receives the n+E-th level first gate control signal Nscan.

[0244] Optionally, the control end of the first reset transistor Ti1 of the sub-pixel Spii located in the nth row receives the first gate control signal Nscan(n-3) of the n-3th level, the control end of the compensation transistor Tc of the sub-pixel Spii located in the nth row receives the first gate control signal Nscan(n+1) of the n+1th level, and the control end of the data transistor Tda of the sub-pixel Spii located in the nth row receives the second gate control signal Pscan(n) of the nth level.

[0245] 5 , the pixel driving circuit of each sub-pixel Spi further includes a second reset transistor Ti2, an input end of the second reset transistor Ti2 being configured to receive a second reset signal Vi2, an output end of the second reset transistor Ti2 being electrically connected to the anode of the light-emitting device Di, and the second reset transistor Ti2 being configured to transmit the second reset signal Vi2 to the anode of the light-emitting device Di to initialize the anode potential of the light-emitting device Di.

[0246] Optionally, in some embodiments, the control terminal of the second reset transistor Ti2 may be controlled by a second gate control signal Pscan. Optionally, the control terminal of the second reset transistor Ti2 is electrically connected to the control terminal of the data transistor Tda, and is electrically connected to the second output terminal Pout of the corresponding gate drive circuit GDC through the plurality of second scan lines SL2, so that the second reset transistor Ti2 is also controlled by the second gate control signal Pscan.

[0247] Optionally, in some embodiments, the control terminal of the second reset transistor Ti2 may be controlled by the first gate control signal Nscan. Optionally, the second reset transistor Ti2 and the compensation transistor Tc are both N-type transistors or both P-type transistors, and the control terminal of the second reset transistor Ti2 is electrically connected to the control terminal of the compensation transistor Tc, so as to be electrically connected to the first output terminal Nout of the corresponding gate drive circuit GDC through the plurality of third scan lines SL3, thereby causing the second reset transistor Ti2 to also be controlled by the first gate control signal Nscan.

[0248] Optionally, the pixel driving circuit of each sub-pixel Spi further includes a light emitting control transistor, which is electrically connected between the input terminal of the driving transistor Tdr and the first voltage terminal VDD, and / or electrically connected between the output terminal of the driving transistor Tdr and the light emitting device Di.

[0249] Optionally, please continue to refer to FIG. 4 , the display panel includes a plurality of light emitting control lines EML, and the plurality of light emitting control lines EML are configured to transmit a plurality of light emitting control signals EMA.

[0250] Optionally, the light-emitting control transistor includes a first light-emitting control transistor Te1 and a second light-emitting control transistor Te2, the input end and the output end of the first light-emitting control transistor Te1 are electrically connected between the first voltage end VDD and the input end of the driving transistor Tdr, the input end and the output end of the second light-emitting control transistor Te2 are electrically connected between the light-emitting device Di and the output end of the driving transistor Tdr, the control ends of the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are electrically connected to the corresponding light-emitting control line EML, and the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are configured to control the light-emitting period of the light-emitting device Di according to the light-emitting control signal EMA transmitted by the corresponding light-emitting control line EML.

[0251] Optionally, the pixel driving circuit of each sub-pixel Spi further includes a fourth capacitor Cst1 , and the fourth capacitor Cst1 is connected in series between the first voltage terminal VDD and the control terminal of the driving transistor Tdr.

[0252] Optionally, in some embodiments, the pixel driving circuit of each sub-pixel Spi further includes a fifth capacitor Cst2 , and the fifth capacitor Cst2 is connected in series between the control terminal of the driving transistor Tdr and the control terminal of the data transistor Tda.

[0253] Optionally, in some embodiments, the plurality of scan lines further include a fourth scan line SL4. The pixel driving circuit of each sub-pixel Spi further includes a third reset transistor Ti3, wherein a control terminal of the third reset transistor Ti3 is electrically connected to the corresponding fourth scan line SL4, an input terminal of the third reset transistor Ti3 is configured to receive a third reset signal Vi3, and an output terminal of the third reset transistor Ti3 is electrically connected to the input terminal of the driving transistor Tdr; the third reset transistor Ti3 is configured to transmit the third reset signal Vi3 to the input terminal of the driving transistor Tdr to reset the potential of the input terminal of the driving transistor Tdr.

[0254] Optionally, the control end of the second reset transistor Ti2 and the control end of the third reset transistor Ti3 are electrically connected so that the second reset transistor Ti2 and the third reset transistor Ti3 are controlled by the same reset control signal EMB, thereby achieving synchronous resetting of the anode potential of the light-emitting device Di and the input potential of the driving transistor Tdr.

[0255] Optionally, in some embodiments, the display panel further includes a first gate driving unit and a second gate driving unit, the first gate driving unit including a plurality of first gate driving circuits electrically connected to the plurality of sub-pixels Spi via a plurality of emission control lines EML, and the plurality of first gate driving circuits configured to generate a plurality of emission control signals EMA. The plurality of second gate driving units include a plurality of second gate driving circuits electrically connected to the control terminals of the third reset transistors Ti3 of the plurality of sub-pixels Spi via a plurality of fourth scan lines SL4, and the plurality of second gate driving circuits GDC configured to generate a plurality of reset control signals EMB.

[0256] The first gate driving circuit for generating the light emitting control signal EMA and the second gate driving circuit for generating the reset control signal EMB may be designed with reference to common circuit structures in the art and will not be described in detail here.

[0257] Optionally, in some embodiments, the display panel includes a display area and a non-display area located on one side of the display area, wherein the gate driving unit, the first gate driving unit and the second gate driving unit are located in the non-display area.

[0258] 6A to 6C are timing diagrams corresponding to the display device provided in an embodiment of the present application. Please continue to refer to FIG. 4 , FIG. 5 and FIG. 6A to FIG. 6C . When the display panel is displaying, a display cycle may include a write frame WF and at least one hold frame HF.

[0259] In order to update the display panel image within the write frame WF, when the gate driving unit shown in Figures 2A to 2C is used to control the multiple sub-pixels Spi, the frequency division control signal LF has an active level (i.e., a level that controls the frequency division transistor Tf to be conductive). When the gate driving unit shown in Figure 2D is used to control the multiple sub-pixels Spi, both the first frequency division control signal NLF and the second frequency division control signal PLF have an active level.

[0260] In the blanking interval following the write frame WF or in at least one hold frame HF following the write frame WF, to maintain the image displayed on some rows of the display panel identical to the image displayed during the write frame WF, when the gate driving unit shown in Figures 2A to 2C is used to control the plurality of sub-pixels Spi, the frequency-dividing control signal LF transitions from an active level state to an inactive level state (i.e., a level state that controls the frequency-dividing transistor Tf to be turned off). When the gate driving unit shown in Figure 2D is used to control the plurality of sub-pixels Spi, at least one of the first frequency-dividing control signal NLF and the second frequency-dividing control signal PLF transitions from an active level state to an inactive level state, so that some gate control signals generated by the gate control unit do not have valid pulses.

[0261] Optionally, the blanking interval includes a horizontal blanking interval and a vertical blanking interval.

[0262] Optionally, when the display panel adopts the gate driving unit shown in Figures 2A to 2C, the frequency-dividing control signal LF may transition from the active level state to the inactive level state at the same or different times for each hold frame HF. When the display panel adopts the gate driving unit shown in Figure 2D, the first frequency-dividing control signal NLF may transition from the active level state to the inactive level state at the same or different times for each hold frame HF, and the second frequency-dividing control signal PLF may transition from the active level state to the inactive level state at the same or different times for each hold frame HF.

[0263] Since the frequency-division control signal LF, the first frequency-division control signal NLF, and the second frequency-division control signal PLF can control the first gate control signal Nscan and the second gate control signal Pscan generated by the gate drive circuit GDC to have no valid pulses when the frequency-division control signal LF, the first frequency-division control signal NLF, and the second frequency-division control signal PLF are in the corresponding invalid level state, and the frequency-division control signal LF, the first frequency-division control signal NLF, and the second frequency-division control signal PLF can control the first gate control signal Nscan and the second gate control signal Pscan generated by the gate drive circuit GDC to have valid pulses when the frequency-division control signal LF, the first frequency-division control signal NLF, and the second frequency-division control signal PLF are in the corresponding valid level state, thus controlling the display area of ​​the display panel to be divided into multiple sub-display areas with different frequencies by controlling the frequency-division control signal LF, the first frequency-division control signal NLF, and the second frequency-division control signal PLF to jump from the valid level state to the invalid level state at different times within different holding frames HF. This can control the display panel to be divided into multiple sub-display areas with different frequencies, control the display panel to achieve frequency division at any position in the display area, and achieve frequency division control of the display area of ​​the display panel.

[0264] Taking the case where the sub-pixel Spi is located in the nth row, the control end of the first reset transistor Ti1 receives the n-3th level first gate control signal Nscan(n-3), the control end of the compensation transistor Tc receives the n+1th level first gate control signal Nscan(n+1), the control end of the data transistor Tda receives the nth level second gate control signal Pscan(n), the light-emitting control transistor receives the light-emitting control signal EMA, the second reset transistor Ti2 and the third reset transistor Ti3 receive the reset control signal EMB, the compensation transistor Tc and the first reset transistor Ti1 are N-type transistors, and the data transistor Tda, the light-emitting control transistor, the second reset transistor Ti2 and the third reset transistor Ti3 are P-type transistors as an example, the frequency division display working principle of the display panel in one display cycle is explained.

[0265] In the write frame WF, in order to reset and update the control terminal data of the multiple driving transistors Tdr included in the display panel, the frequency division control signal LF, or the first frequency division control signal NLF and the second frequency division control signal PLF have an effective level state, so that the gate driving unit can output multiple levels of first gate control signals Nscan and second gate control signals Pscan with effective pulses in the write frame WF. Therefore, in the write frame WF, each row of sub-pixels SpiPi correspondingly undergoes a first reset phase ta1, a second reset phase ta2, a data writing phase ta3, a third reset phase ta4, and a light-emitting phase ta5, as shown in Figure 6A.

[0266] In the first reset stage ta1, the n-3th level first gate control signal Nscan(n-3) has a high level state, the nth level second gate control signal Pscan(n) has a high level state, the n+1th level first gate control signal Nscan(n+1) has a low level state, the reset control signal EMB has a high level state, the light-emitting control signal EMA has a high level state, the first reset transistor Ti1 is turned on, and the first reset signal Vi1 resets the potential of the control end of the driving transistor Tdr.

[0267] In the second reset stage ta2, the n-3th level first gate control signal Nscan(n-3) has a high level state, the nth level second gate control signal Pscan(n) has a high level state, the n+1th level first gate control signal Nscan(n+1) has a high level state, the reset control signal EMB has a high level state, the light-emitting control signal EMA has a high level state, the first reset transistor Ti1 and the compensation transistor Tc are turned on, so that the potential of the output end and the control end of the driving transistor Tdr can be reset according to the first reset signal.

[0268] In the data writing stage ta3, the first gate control signal Nscan(n-3) of the n-3th level has a low level state, the second gate control signal Pscan(n) of the nth level has a low level state, the first gate control signal Nscan(n+1) of the n+1th level has a high level state, the reset control signal EMB has a high level state, the light-emitting control signal EMA has a high level state, the data transistor Tda and the compensation transistor Tc are turned on, and the control end of the driving transistor Tdr is able to write the information of the data signal.

[0269] In the third reset stage ta4, the n-3th level first gate control signal Nscan(n-3) has a low level state, the nth level second gate control signal Pscan(n) has a high level state, the n+1th level first gate control signal Nscan(n+1) has a low level state, the reset control signal EMB has a low level state, the light emitting control signal EMA has a high level state, the second reset transistor Ti2 and the third transistor T3 are turned on, the anode of the light emitting device Di is reset according to the second reset signal Vi2, and the input end of the driving transistor Tdr is reset according to the third reset signal Vi3.

[0270] In the light-emitting stage ta5, the n-3th level first gate control signal Nscan(n-3) has a low level state, the nth level second gate control signal Pscan(n) has a high level state, the n+1th level first gate control signal Nscan(n+1) has a low level state, the reset control signal EMB has a high level state, the light-emitting control signal EMA has a low level state, the first light-emitting control transistor Te1 and the second light-emitting control transistor Ts1 are turned on according to the light-emitting control signal EMA, so that the driving transistor Tdr generates a driving current to drive the corresponding light-emitting device Di to emit light.

[0271] In the hold frame HF, the sub-pixels Spi in some rows can display the same image as that in the write frame WF. Therefore, the sub-pixels Spi in these rows do not need to go through the first reset phase ta1, the second reset phase ta2, and the data write phase ta3 again.

[0272] As shown in FIG6B , the gate driving unit used in the display panel includes a gate driving circuit GDC that adopts the design of FIG2A to FIG2C . Corresponding to a holding frame HF (such as the first holding frame HF1), the frequency-dividing control signal LF has a jump from a valid level state to an invalid level state in the p-th level gate driving circuit GDC(p) to the p+q-th level gate driving circuit GDC(p+q) of the gate driving unit. Then, combined with the analysis of Figure 3A, it can be seen that the multi-level first gate control signal Nscan and the second gate control signal Pscan output by the multi-level gate driving circuit GDC located before the p-level gate driving circuit GDC(p) and the p-level gate driving circuit GDC(p) both have valid pulses, so that the data transistors Tda and the compensation transistors Tc in the multiple sub-pixels Spii electrically connected to the multi-level gate driving circuit GDC located before the p-level gate driving circuit GDC(p) and the multiple sub-pixels Spii electrically connected to the p-level gate driving circuit GDC(p) can all be turned on in the corresponding time period (such as in the data writing phase ta3 of the corresponding writing frame WF), so that the information of the corresponding data signal is transmitted to the control end of the driving transistor Tdr, thereby controlling the change of the driving current generated by the driving transistor Tdr, and realizing the display update of the multiple sub-pixels Spii electrically connected to the multi-level gate driving circuit GDC located before the p-level gate driving circuit GDC(p) and the multiple sub-pixels Spii electrically connected to the p-level gate driving circuit GDC(p).

[0273] However, the multi-stage first gate control signal Nscan and the second gate control signal Pscan output by the multi-stage gate driving circuit GDC located after the p+9-stage gate driving circuit GDC(p+9) and the p+9-stage gate driving circuit GDC(p+9) do not have valid pulses. Therefore, the data transistors Tda and the compensation transistors Tc in the multiple sub-pixels Spii electrically connected to the multi-stage gate driving circuit GDC located after the p+9-stage gate driving circuit GDC(p+9) and the multiple sub-pixels Spii electrically connected to the p+9-stage gate driving circuit GDC(p+9) will not be turned on in the holding frame HF. In the multiple sub-pixels Spii electrically connected to the multi-level gate driving circuit GDC after the p+9-level gate driving circuit GDC(p+9), and the multiple sub-pixels Spii electrically connected to the p+9-level gate driving circuit GDC(p+9), the control end of the driving transistor Tdr retains the information written in the write frame WF, so that the multiple sub-pixels Spii electrically connected to the multi-level gate driving circuit GDC located after the p+9-level gate driving circuit GDC(p+9), and the multiple sub-pixels Spii electrically connected to the p+9-level gate driving circuit GDC(p+9) still display the same content as the content displayed in the write frame WF in the hold frame HF.

[0274] Due to the change in the level state of the corresponding frequency-division control signal LF, the p+1th level first gate control signal Nscan(p+1) to the p+8th level first gate control signal Nscan(p+8) always maintain a high level state, and the p+1th level second gate control signal Pscan(p+1) to the p+8th level second gate control signal Pscan(p+8) correspond to the corresponding second clock signal CK. At least one of the central processing unit, the graphics processing unit, the timing controller and other devices can be used to control the multiple sub-pixels Spi electrically connected to the p+1th level gate driving circuit GDC to the p+8th level gate driving circuit GDC(p+8) to fixedly display a black screen, so as to improve the easily noticeable display abnormality problem of the multiple sub-pixels Spi electrically connected to the p+1th level gate driving circuit GDC to the p+8th level gate driving circuit GDC(p+8).

[0275] As shown in FIG6C , the gate driving unit used in the display panel includes a gate driving circuit GDC that adopts the design of FIG2D . Corresponding to a holding frame HF (such as the first holding frame HF1), the first frequency division control signal NLF and the second frequency division control signal PLF have a jump from a valid level state to an invalid level state corresponding to the p-th level gate driving circuit GDC(p) to the p+q-th level gate driving circuit GDC(p+q) of the gate driving unit. Then, combined with the analysis of Figures 3B to 3C, it can be seen that the multi-level first gate control signal Nscan and the second gate control signal Pscan output by the multi-level gate driving circuit GDC located before the p+11th gate driving circuit GDC(p+11) all have valid pulses, so that in the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC located before the p+11th gate driving circuit GDC(p+11), the data transistor Tda and the compensation transistor Tc can both be turned on in the corresponding time period (such as in the data writing phase ta3 of the corresponding writing frame WF), so that the information of the corresponding data signal is transmitted to the control end of the driving transistor Tdr, thereby controlling the change of the driving current generated by the driving transistor Tdr, and realizing the display update of the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC located before the p+11th gate driving circuit GDC(p+11).

[0276] However, the multi-stage first gate control signal Nscan output by the multi-stage gate drive circuit GDC located after the p+10th-stage gate drive circuit GDC(p+10) does not have a valid pulse, and the multi-stage second gate control signal Pscan output by the multi-stage gate drive circuit GDC located after the p+11th-stage gate drive circuit GDC(p+11) does not have a valid pulse. Therefore, in the multiple sub-pixels Spi that are electrically connected to the multi-stage gate drive circuit GDC located after the p+10th-stage gate drive circuit GDC(p+10), the data transistors Tda will not be turned on during the hold frame HF; and in the multiple sub-pixels Spi that are electrically connected to the multi-stage gate drive circuit GDC located after the p+11th-stage gate drive circuit GDC(p+11), the compensation transistors Tc will not be turned on during the hold frame HF. The p+10th-level second gate control signal Pscan(p+10) output by the p+10th-level gate driving circuit GDC(p+10) has a valid pulse, but the compensation transistor Tc in the multiple sub-pixels Spii electrically connected to the p+10th-level gate driving circuit GDC(p+10) receives the p+11th-level first gate control signal Nscan(p+11) and is cut off. Therefore, the control end of the driving transistor Tdr in the multiple sub-pixels Spii electrically connected to the p+10th-level gate driving circuit GDC(p+10) does not receive new data information in the maintenance frame HF.

[0277] If the first frequency-division control signal NLF jumps from the active level state to the inactive level state before the second frequency-division control signal PLF, and the first reset transistor Ti1 and the compensation transistor Tc of the sub-pixel Spi are both controlled by the first gate control signal Nscan (for example, the control end of the first reset transistor Ti1 located in the nth row is controlled by the n-3th level first gate control signal Nscan(n-3), and the control end of the compensation transistor Tc located in the nth row is controlled by the n+1th level first gate control signal Nscan(n+1)), then, in the hold frame HF, although the sub-pixels Spi in some rows of the display panel are controlled not to receive new data signals, the first reset transistors Ti1 in a plurality of sub-pixels Spi are turned on under the control of the corresponding first gate control signal Nscan, causing the potentials of the control ends of the drive transistors Tdr of the sub-pixels Spi in some rows to be reset (for example, in the hold frame HF, the pth level first gate control signal Nscan(p) to the p+10th level first gate control signal Nscan(p+10) have valid pulse outputs, and the pth level second gate control signal Nscan(n+1) is turned on). If the control signal Pscan to the second gate control signal Pscan(p+11) of the p+11th level have valid pulse outputs, then the first reset transistors Ti1 in the multiple sub-pixels Spi in the p+10th to p+13th rows will be turned on by correspondingly receiving the first gate control signal Nscan(p+8) of the p+8th level to the first gate control signal Nscan(p+10) of the p+10th level, thereby resetting the control terminal potential of the driving transistors Tdr of the multiple sub-pixels Spi in the p+10th to p+13th rows. The compensation reset transistors in the multiple sub-pixels Spi in the p+10th to p+13th rows are cut off when corresponding to the first gate control signals Nscan(p+11) to Nscan(p+14) of the p+11th to p+14th levels. Therefore, the multiple sub-pixels Spi in the p+10th to p+13th rows reset the potential of the control terminal of the driving transistor Tdr. However, no new data information is stored in the control terminal of the driving transistor Tdr, and no original data signal is retained at the control terminal of the driving transistor Tdr. Therefore, display problems may occur.

[0278] In order to improve the problem that the sub-pixels Spi in some rows of the display panel do not receive new data signals and the potential of the control end of the driving transistor Tdr of the sub-pixels Spi in these rows is reset when maintaining the frame HF, the second frequency division control signal PLF can be controlled to jump from the valid level state to the invalid level state before the first frequency division control signal NLF.

[0279] Therefore, when the display panel adopts the gate driving circuit GDC shown in Figure 2D to achieve zoned and frequency-division display, the relative moments when the first frequency-division control signal NLF and the second frequency-division control signal PLF jump from the valid level state to the invalid level state can be controlled, so that the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC located after the p+11th level gate driving circuit GDC (p+11) can display the same content as the write frame WF display content in the hold frame HF.

[0280] It is understandable that within each hold frame HF, the frequency division control signal LF, the first frequency division control signal NLF, and the second frequency division control signal PLF are not limited to corresponding to the p-th level gate driver circuit GDC(p) to the p+q-th level gate driver circuit GDC(p+q) of the gate driver unit, having a transition from a valid level state to an invalid level state. By controlling the frequency division control signal LF, the first frequency division control signal NLF, and the second frequency division control signal PLF to have a transition from a valid level state to an invalid level state corresponding to different levels of gate driver circuits GDC in different hold frames HF, the display area of ​​the display panel can be divided into multiple sub-display areas with different refresh frequencies, thereby realizing the partitioned frequency division setting of the display panel.

[0281] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate driving unit, wherein, It includes a frequency division control line and a plurality of cascaded gate driving circuits. The frequency division control line is configured to transmit a frequency division control signal to the plurality of gate driving circuits. Each gate driving circuit includes: A first control module, electrically connected to a first node of the current-stage gate driving circuit, and configured to control signal transmission between one of a first power supply terminal and a second power supply terminal and the first node according to a corresponding first clock signal and one of a start signal and a first gate control signal output by the previous-stage gate driving circuit; A first output module, at least electrically connected to the first node of the current-stage gate driving circuit, and configured to control electrical connection between a third power supply terminal and a first output terminal of the current-stage gate driving circuit according to the potential of the first node. The first output terminal outputs the first gate control signal of the current-stage gate driving circuit; A second output module, electrically connected to a second node and a third node of the current-stage gate driving circuit, and configured to output a second gate control signal of the current-stage gate driving circuit according to the potential of the second node and the potential of the third node; and A frequency division control module, electrically connected to the first node of the current-stage gate driving circuit, and configured to control signal transmission between the first power supply terminal and the first node or the second node according to the frequency division control signal.

2. The gate driving unit according to claim 1, wherein The first control module includes: A first transistor, a first control end and a second control end of the first transistor are configured to receive one of the start signal and the first gate control signal output by the previous-stage gate driving circuit, and an input end of the first transistor is electrically connected to the first power supply terminal; A second transistor, a control end of the second transistor is electrically connected to the first control end of the first transistor, an input end of the second transistor is electrically connected to the second power supply terminal, and an output end of the second transistor is electrically connected to an output end of the first transistor; and A third transistor, a control end of the third transistor is configured to receive the corresponding first clock signal, an input end of the third transistor is electrically connected to the output end of the first transistor, and an output end of the third transistor is electrically connected to the first node; Wherein, the frequency division control module is electrically connected to the first transistor or the third transistor.

3. The gate driving unit according to claim 2, wherein The frequency division control module includes: A frequency division transistor, a control end of the frequency division transistor is configured to receive the frequency division control signal, an input end of the frequency division transistor is electrically connected to the output end of the third transistor, and an output end of the frequency division transistor is electrically connected to the first node.

4. The gate driving unit according to claim 2, wherein The frequency division control module includes: A frequency division transistor, a control end of the frequency division transistor is configured to receive the frequency division control signal, an input end of the frequency division transistor is configured to receive the corresponding first clock signal, and an output end of the frequency division transistor is electrically connected to the control end of the third transistor.

5. The gate driving unit according to claim 2, wherein, The frequency division control module includes: A frequency-dividing transistor, wherein a control terminal of the frequency-dividing transistor is configured to receive the frequency-dividing control signal, an input terminal of the frequency-dividing transistor is configured to receive the start signal or the first gate control signal output by the previous-stage gate driving circuit, and an output terminal of the frequency-dividing transistor is electrically connected to a first control terminal of the first transistor.

6. The gate driving unit according to claim 1, wherein the first output module includes a first output transistor and a second output transistor. A first control terminal, a second control terminal of the first output transistor and a control terminal of the second output transistor are electrically connected to the first node. An input terminal of the first output transistor is electrically connected to the third power supply terminal. An input terminal of the second output transistor is electrically connected to the fourth power supply terminal. An output terminal of the second output transistor and an output terminal of the first output transistor are electrically connected to the first output terminal of the gate driving circuit of this stage; the second output module includes a third output transistor, a fourth output transistor and a storage capacitor. A control terminal of the third output transistor is electrically connected to the second node. An input terminal of the third output transistor is configured to receive a corresponding second clock signal. A control terminal of the fourth output transistor is electrically connected to the third node. An input terminal of the fourth output transistor is electrically connected to the second power supply terminal. An output terminal of the fourth output transistor and an output terminal of the third output transistor are electrically connected to the second output terminal of the gate driving circuit of this stage; A first end of the storage capacitor is electrically connected to the control terminal of the third output transistor, and a second end of the storage capacitor is electrically connected to the second output terminal of the gate driving circuit of this stage.

7. The gate driving unit according to claim 1, wherein, The second node includes a first sub-node and a second sub-node, and the frequency-dividing control signal includes a first frequency-dividing control signal and a second frequency-dividing control signal; The frequency-dividing control module includes: a first frequency-dividing control module, electrically connected to the first node and the first sub-node, and configured to control signal transmission between the first power supply terminal and the first sub-node according to the first frequency-dividing control signal; and a second frequency-dividing control module, electrically connected to the first node and the second sub-node, and configured to control signal transmission between the first power supply terminal and the second sub-node according to the second frequency-dividing control signal; wherein, the first output module is electrically connected to the first sub-node, and the first output module is configured to output the first gate control signal of the gate driving circuit of this stage according to the potential of the first node and the potential of the first sub-node; the second output module is electrically connected to the second sub-node, and the second output module is configured to output the second gate control signal of the gate driving circuit of this stage according to the potential of the second sub-node and the potential of the third node.

8. The gate driving unit according to claim 7, wherein The first frequency division control module includes a first frequency division transistor, a second frequency division transistor, and a first capacitor. The control terminal of the first frequency division transistor is electrically connected to the third node of the gate driving circuit at this stage, and the input terminal of the first frequency division transistor is configured to receive the first frequency division control signal; The control terminal of the second frequency division transistor is electrically connected to the output terminal of the first frequency division transistor. The input terminal of the second frequency division transistor is electrically connected to the first node, and the output terminal of the second frequency division transistor is electrically connected to the first sub-node; The first end of the first capacitor is electrically connected to the control terminal of the second frequency division transistor, and the second end of the first capacitor is electrically connected to the first sub-node; The second frequency division control module includes a third frequency division transistor, a fourth frequency division transistor, and a second capacitor. The control terminal of the third frequency division transistor is electrically connected to the third node of the gate driving circuit at this stage, and the input terminal of the third frequency division transistor is configured to receive the second frequency division control signal; The control terminal of the fourth frequency division transistor is electrically connected to the output terminal of the third frequency division transistor. The input terminal of the fourth frequency division transistor is electrically connected to the first node, and the output terminal of the fourth frequency division transistor is electrically connected to the second sub-node; The first end of the second capacitor is electrically connected to the control terminal of the fourth frequency division transistor, and the second end of the second capacitor is electrically connected to the second sub-node.

9. The gate driving unit according to claim 8, wherein, The first output module includes a first output transistor and a second output transistor. The first control terminal and the second control terminal of the first output transistor are electrically connected to the first node. The input terminal of the first output transistor is electrically connected to the third power supply terminal. The control terminal of the second output transistor is electrically connected to the first sub-node. The input terminal of the second output transistor is electrically connected to the fourth power supply terminal. The output terminal of the second output transistor and the output terminal of the first output transistor are electrically connected to the first output terminal of the gate driving circuit at this stage; The second output module includes a third output transistor, a fourth output transistor, and a storage capacitor. The control terminal of the third output transistor is electrically connected to the second sub-node. The input terminal of the third output transistor is configured to receive the corresponding second clock signal. The control terminal of the fourth output transistor is electrically connected to the third node. The input terminal of the fourth output transistor is electrically connected to the second power supply terminal. The output terminal of the fourth output transistor and the output terminal of the third output transistor are electrically connected to the second output terminal of the gate driving circuit at this stage; The first end of the storage capacitor is electrically connected to the control terminal of the third output transistor, and the second end of the storage capacitor is electrically connected to the second output terminal of the gate driving circuit at this stage.

10. The gate driving unit according to claim 1, wherein, The first control module further includes a fourth transistor, a fifth transistor, and a sixth transistor. The first control terminal and the second control terminal of the fourth transistor are configured to receive the corresponding first clock signal. The output terminal of the fourth transistor is electrically connected to the first node. The control terminal of the fifth transistor, the first control terminal and the second control terminal of the sixth transistor are electrically connected to the third node. The input terminal of the fifth transistor is electrically connected to the second power supply terminal. The output terminal of the fifth transistor is electrically connected to the input terminal of the fourth transistor. The input terminal of the sixth transistor is electrically connected to the third power supply terminal. The output terminal of the sixth transistor is electrically connected to the first node; The gate driving unit further includes a seventh transistor and an eighth transistor. The first control terminal and the second control terminal of the seventh transistor are electrically connected to the first node. The input terminal of the seventh transistor is electrically connected to the first power supply terminal. The output terminal of the seventh transistor is electrically connected to the third node. The control terminal of the eighth transistor is electrically connected to the first node. The input terminal of the eighth transistor is electrically connected to the second power supply terminal. The output terminal of the eighth transistor is electrically connected to the third node.

11. The gate driving unit according to claim 6, wherein, The gate driving circuit further includes: A first switching transistor, the input terminal of the first switching transistor is electrically connected to the first node; A second switching transistor, the input terminal of the second switching transistor is electrically connected to the output terminal of the first switching transistor, and the output terminal of the second switching transistor is electrically connected to the second node; and A third capacitor, the first end of the third capacitor is electrically connected to the control terminal of the first switching transistor, and the second end of the third capacitor is electrically connected to the output terminal of the first switching transistor; Wherein, the control terminal of the first switching transistor of the nth stage of the gate driving circuit is configured to receive the first gate control signal output by the (n - 10)th stage of the gate driving circuit, and the control terminal of the second switching transistor of the nth stage of the gate driving circuit is configured to receive the first gate control signal output by the (n - 2)th stage of the gate driving circuit.

12. The gate driving unit according to claim 9, wherein, The gate driving circuit further includes: A ninth transistor, the first control terminal and the second control terminal of the ninth transistor are configured to receive the corresponding first clock signal, and the output terminal of the ninth transistor is electrically connected to the first sub-node; A tenth transistor, the control terminal of the tenth transistor is electrically connected to the third node of this stage of the gate driving circuit, the input terminal of the tenth transistor is electrically connected to the second power supply terminal, and the output terminal of the tenth transistor is electrically connected to the input terminal of the ninth transistor; An eleventh transistor, the control terminal of the eleventh transistor is electrically connected to the third node of the previous stage of the gate driving circuit, the input terminal of the eleventh transistor is electrically connected to the output terminal of the third frequency-dividing transistor, and the output terminal of the eleventh transistor is electrically connected to the second sub-node; A twelfth transistor, wherein a first control terminal and a second control terminal of the twelfth transistor are configured to receive the corresponding first clock signal, and an output terminal of the twelfth transistor is electrically connected to an input terminal of the eleventh transistor; A thirteenth transistor, wherein a control terminal of the thirteenth transistor is electrically connected to the third node of the gate driving circuit of this stage, an input terminal of the thirteenth transistor is electrically connected to the second power supply terminal, and an output terminal of the thirteenth transistor is electrically connected to the input terminal of the twelfth transistor.

13. A display device, wherein, Comprising: The gate driving unit according to claim 1; A display panel, including a plurality of sub-pixels, each of the sub-pixels including a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, the pixel driving circuit at least including a driving transistor, a data transistor, and a compensation transistor; the driving transistor is configured to drive the light-emitting device to emit light according to a corresponding data signal, an input terminal of the compensation transistor is electrically connected to an output terminal of the driving transistor, an output terminal of the compensation transistor is electrically connected to a control terminal of the driving transistor, an input terminal of the data transistor is configured to receive the corresponding data signal, and an output terminal of the data transistor is electrically connected to an input terminal of the driving transistor; Wherein, the first gate control signals generated by the plurality of gate driving circuits are output to control terminals of the compensation transistors of the plurality of sub-pixels, and the second gate control signals generated by the plurality of gate driving circuits are output to control terminals of the data transistors of the plurality of sub-pixels.

14. The display device according to claim 13, wherein, The second gate control signal received by the control terminal of the data transistor and the first gate control signal received by the control terminal of the compensation transistor are provided by different stages of the gate driving circuit.

15. The display device according to claim 14, wherein, The control terminal of the data transistor of the sub-pixel located in the nth row receives the nth-stage second gate control signal output by the nth-stage gate driving circuit; the control terminal of the compensation transistor of the sub-pixel located in the nth row receives the (n + 1)th-stage first gate control signal output by the (n + 1)th-stage gate driving circuit.

16. The display device according to claim 13, wherein, The pixel driving circuit includes a first reset transistor, an input terminal of the first reset transistor is configured to receive a first reset signal, and an output terminal of the first reset transistor is electrically connected to a control terminal of the driving transistor; Wherein, the first gate control signals generated by the plurality of gate driving circuits are output to control terminals of the first reset transistors of the plurality of sub-pixels; and the first gate control signal received by the control terminal of the first reset transistor and the first gate control signal received by the control terminal of the compensation transistor are provided by different stages of the gate driving circuit.

17. The display device according to claim 16, wherein, The control terminal of the first transistor of the sub-pixel located in the nth row receives the (n - 3)th-stage first gate control signal output by the (n - 3)th-stage gate driving circuit; the control terminal of the compensation transistor of the sub-pixel located in the nth row receives the (n + 1)th-stage first gate control signal output by the (n + 1)th-stage gate driving circuit.

18. The display device according to claim 13, wherein, Each of the pixel driving circuits further includes: A second reset transistor, the control terminal of the second reset transistor is configured to receive a reset control signal, the input terminal of the second reset transistor is configured to receive a second reset signal, and the output terminal of the second reset transistor is electrically connected to the anode of the light emitting device; A first light emitting control transistor, the control terminal of the first light emitting control transistor is configured to receive a light emitting control signal, and the input terminal and the output terminal of the first light emitting control transistor are electrically connected between a first voltage terminal and the input terminal of the driving transistor; A second light emitting control transistor, the control terminal of the second light emitting control transistor is configured to receive the light emitting control signal, and the input terminal and the output terminal of the second light emitting control transistor are electrically connected between the light emitting device and the output terminal of the driving transistor; and A fourth capacitor, connected in series between the first voltage terminal and the control terminal of the driving transistor.

19. The display device according to claim 18, wherein, Further included are: A first gate driving unit, including a plurality of first gate driving circuits, the plurality of first gate driving circuits are electrically connected to the control terminals of the first light emitting control transistors and the control terminals of the second light emitting control transistors of the plurality of sub-pixels, and the plurality of first gate driving circuits are configured to generate a plurality of the light emitting control signals; and A second gate driving unit, including a plurality of second gate driving circuits, the plurality of second gate driving circuits are electrically connected to the control terminals of the second reset transistors of the plurality of sub-pixels, and the plurality of second gate driving circuits are configured to generate a plurality of the reset control signals.

20. The display device according to claim 18, wherein Each of the pixel driving circuits further includes: A third reset transistor, the control terminal of the third reset transistor is configured to receive the reset control signal, the input terminal of the third reset transistor is configured to receive a third reset signal, and the output terminal of the third reset transistor is electrically connected to the input terminal of the driving transistor; and A fifth capacitor, connected in series between the control terminal of the driving transistor and the control terminal of the data transistor.

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