Address translation circuit and memory

Abstract

Provided in the embodiments of the present disclosure is an address translation circuit. The address translation circuit comprises: a frequency division circuit, which is used for receiving a first address increment signal having a first frequency, and processing and outputting a second address increment signal having a second frequency and a jump signal having the second frequency, wherein the jump signal is used for indicating that a first address jumps between N banks; an address counter, which is used for receiving the second address increment signal and outputting an address counting signal; and a row address increment circuit, which is coupled to the address counter and the frequency division circuit, and is used for outputting a first row address increment signal when the address counting signal indicates that the column address counting is ended and the jump signal indicates the last bank group. By means of the circuit in the embodiments of the present disclosure, address jumping can be realized when different bank groups are used in parallel.

Description

Address conversion circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311872867.1 and application name “Address Conversion Circuit”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and are related to, but not limited to, an address conversion circuit and a memory. Background Art

[0003] During the use of the memory, data read and write errors often occur due to process deviations of the memory cells or circuits. These errors cannot be completely avoided, but they can be compensated by some detection and error correction methods to ensure the normal use of the memory. Therefore, some detection and error correction related circuits are provided in the memory, such as ECS (Error Check and Scrub, error detection and erasure), ECC (Error Checking and Correction, error detection and correction) and other circuits, so as to realize the detection and error correction of the data read and write units in the memory. In order to reduce the space occupied by the detection and error correction related circuits, the above-mentioned circuits can usually synchronously test multiple memory banks (BK, Bank) or memory bank groups (BG, Bank Group). However, in this case, the error-related addresses detected are often difficult to match with the actual addresses, resulting in problems such as incomplete detection data.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, an address conversion circuit is provided, which is applied to a memory, wherein the memory includes N memory bank groups, and the address conversion circuit includes:

[0006] a frequency dividing circuit, configured to receive a first address increment signal having a first frequency, process and output a second address increment signal having a second frequency and a jump signal having the second frequency; wherein the first address increment signal is used to indicate that the memory is in an address increment in a first configuration, the second address increment signal is used to indicate that the memory is in an address increment in a second configuration, and the jump signal is used to indicate that the address jumps between the N memory bank groups; the first frequency is N times the second frequency, where N is a positive integer greater than 1;

[0007] An address counter, configured to receive a second address increment signal and output an address counting signal;

[0008] The row address increasing circuit is coupled to the address counter and the frequency dividing circuit, and is used to output the first row address increasing signal when the address counting signal indicates that the column address counting is finished and the jump signal indicates the last memory bank group.

[0009] In some embodiments, the frequency division circuit includes:

[0010] A first trigger, wherein the clock input terminal is used to receive the first address increase signal, and the output terminal is connected to the data input terminal and outputs the jump signal;

[0011] The first processing unit has a first input terminal coupled to the output terminal of the first trigger, a second input terminal receiving the first address increase signal, and an output terminal outputting the second address increase signal.

[0012] In some embodiments, the frequency division circuit further includes: a first AND gate; the first input terminal of the first AND gate receives a second configuration signal, the second input terminal receives an initial reset signal, the output terminal outputs a reset signal, and the reset terminal of the first trigger receives the reset signal.

[0013] In some embodiments, the address counter comprises:

[0014] M counting units, wherein the output end of each counting unit is used to output the count value of one address; wherein M is an integer greater than 2;

[0015] M-1 second AND gates, each of which has a first input connected to an output of a counting unit and a second input connected to an output of a previous counting unit or an output of a previous second AND gate;

[0016] M-1 XOR gates, the first input end of each XOR gate is connected to the output end of one of the counting units or the output end of the second AND gate, and the second input end is connected to the output end of the counting unit of the next stage.

[0017] In some embodiments, the counting unit includes: a second trigger;

[0018] Wherein, the output terminal of the first second trigger is connected to the data input terminal of the first second trigger;

[0019] The first input end of the first XOR gate is connected to the output end of the first second flip-flop, and the second input end is connected to the output end of the second second flip-flop;

[0020] The first input terminal of the i-th XOR gate is connected to the output terminal of the i-1-th second AND gate, and the second input terminal is connected to the output terminal of the i+1-th trigger; wherein i is an integer greater than 1 and less than M.

[0021] In some embodiments, the first input terminal of the first second AND gate is connected to the output terminal of the second second flip-flop, and the second input terminal is connected to the output terminal of the first second flip-flop;

[0022] The first input terminal of the jth second AND gate is connected to the output terminal of the j+1th second trigger, and the second input terminal is connected to the output terminal of the j-1th second AND gate; wherein j is an integer greater than 1 and less than M.

[0023] In some embodiments, the address counter further comprises: a third AND gate;

[0024] The first input end of the third AND gate is coupled to the frequency dividing circuit for receiving the jump signal; the second input end is connected to the output end of the M-2th second AND gate; the output end of the third AND gate is used to output a stop signal, which indicates the end of address counting.

[0025] In some embodiments, the address counter further comprises:

[0026] A first signal selector, whose first input end is connected to the output end of the Mth second trigger of the address counter, whose second input end is connected to the output end of the frequency division circuit, is used to receive the jump signal, whose control end is used to receive the mode selection signal, and whose output end is connected to the first input end of the third AND gate; the mode selection signal is used to indicate that the memory is in the first configuration or the second configuration.

[0027] In some embodiments, the row address increment circuit includes:

[0028] A fourth AND gate, whose first input end is connected to the address counter and is used to receive the second row address increase signal, whose second input end is connected to the output end of the frequency dividing circuit and is used to receive the jump signal, and whose output end outputs the first row address increase signal; wherein, the second row address increase signal is used to indicate the end of column address counting.

[0029] In some embodiments, the row address increasing circuit further includes:

[0030] A second signal selector, whose first input end is connected to the address counter and is used to receive the second row address increase signal, and whose second input end is connected to the output end of the fourth AND gate, and whose signal selection end is used to receive a mode selection signal; wherein, when the mode selection signal indicates that the memory is in the first configuration, the second signal selector outputs the second row address increase signal; when the mode selection signal indicates that the memory is in the second configuration, the second signal selector outputs the first row address increase signal.

[0031] In some embodiments, the address conversion circuit further includes:

[0032] a third signal selector, having a first input terminal for receiving the first address increment signal, a second input terminal connected to the output terminal of the frequency divider circuit for receiving the second address increment signal, an output terminal connected to the clock input terminal of the address counter, and a signal selection terminal for receiving a mode selection signal;

[0033] When the mode selection signal indicates that the memory is in the first configuration, the third signal selector outputs the first address increase signal; when the mode selection signal indicates that the memory is in the second configuration, the third signal selector outputs the second address increase signal.

[0034] In some embodiments, the duty cycle of the jump signal is 1 / N.

[0035] In some embodiments, the first configuration is an X8 mode of the memory and the second configuration is an X16 mode of the memory.

[0036] In some embodiments, the first processing unit includes a NOR gate, which receives the first address increase signal and the jump signal and generates the second address increase signal.

[0037] According to a second aspect of an embodiment of the present disclosure, a memory is provided, comprising: N memory body groups and the address conversion circuit described above, wherein the N memory body groups perform ECS operations according to the first row address increase signal and stop signal output by the address conversion circuit.

[0038] The disclosed embodiments provide an address conversion circuit that can be applied in scenarios such as ECS or ECC to implement address counting in different situations. In addition to using an address counter for address counting, this disclosed embodiment also incorporates a frequency division circuit and outputs a jump signal for switching between different memory bank groups during the address counting process. This ensures that the recorded address is consistent with the actual address when two memory bank groups are merged, facilitating operations such as recording erroneous addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of an ECS involved in an embodiment of the present disclosure;

[0040] FIG2 is a read and write timing diagram of the ECS operation involved in the embodiment of the present disclosure;

[0041] FIG3 is a signal waveform diagram of error counting in the ECS operation row mode involved in an embodiment of the present disclosure;

[0042] FIG4 is a signal waveform diagram of a maximum error count mode of an ECS operation involved in an embodiment of the present disclosure;

[0043] FIG5 is a schematic diagram of an address conversion circuit provided in an embodiment of the present disclosure;

[0044] FIG6 is a schematic diagram of signal waveforms of an address conversion circuit provided by an embodiment of the present disclosure;

[0045] FIG7 is a schematic structural diagram of a frequency division circuit in an address conversion circuit provided by an embodiment of the present disclosure;

[0046] FIG8 is a schematic diagram of a partial structure of an address conversion circuit provided by an embodiment of the present disclosure;

[0047] FIG9 is a schematic diagram of a partial structure of another address conversion circuit provided by an embodiment of the present disclosure. [0047.1][Corrected 12.06.2024 according to Rule 91] Figure 10 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in a variety of different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are intended only to describe specific embodiments and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] The memory in the embodiments of the present disclosure includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0051] Taking DRAM as an example, its peripheral circuits include an ECS module. The ECS's function is to generate read and write commands through self-timer. During this process, data is not read out, but internally corrected for errors before being written back. Any error signals are transmitted to the error counter for counting.

[0052] The ECS schematic is shown in Figure 1. The ECS command generation unit 11 generates ECS commands, the ECS ARWP (Active Read Write Precharge) generation unit 12 generates related commands, and the ECS address counter 13 counts addresses. The ARWP commands and address count values ​​are sent to the memory array 15 via the DRAM controller 14. Sense amplifiers 16 in the memory array 15 then read and write memory cells. When an error is detected, an error signal is generated, which is transmitted to the error counter 17 to count the number of errors. Furthermore, error counter 17 includes a per-row error counter 18 for counting errors per row. Error counter 17 is connected to the ECS address counter 13 and receives the row increment signal RowInc and the ECS end signal EcsInc. Each row error counter 18 is reset to zero upon detecting the row increment signal RowInc, and counting for a new row begins. Detecting the ECS end signal EcsInc indicates that all addresses have been scanned, thus ending the ECS operation and stopping counting.

[0053] The read and write timing of the ECS operation is shown in Figure 2. Each time the address is updated, an ECS is performed, thereby scanning each storage unit once. The scan ends when all bits of the address are "1". At this time, the ECS end signal EcsInc is received to stop ECS.

[0054] The waveform for recording errors in ECS row mode is shown in Figure 3. If an error occurs during a column address update, an error signal is generated along with the write command, along with an error record update pulse to record the error count for the current row. When all bits in the column address are "1," the current row is scanned, and a row increment signal is generated. The error count at this point is the total number of errors for the row at the end of the scan.

[0055] The waveform of the ECS maximum error count mode is shown in Figure 4. The maximum error record records the address and error count of the row with the most errors in each previously scanned row. If an error is detected while scanning the current row, an error pulse is generated, updating the error count. When all column addresses are "1," the current row is scanned, and a row increment signal is generated. At this point, the error count is the error count for the current row. After a row is scanned, the error count for the current row is compared with the error count in the maximum error record. If the error count for the current row is greater, an error record update pulse is generated. When the replacement signal is high, the maximum error record is updated based on the rising edge of the error record update pulse.

[0056] It should be noted that when the address counter used by the above-mentioned ECS is the address counter in X8 mode, if the ECS operation is performed in X16 mode, the two BGs will be merged, doubling the length of each row. Therefore, if the actual address needs to be recorded, the number of column address bits needs to be doubled. However, the structure of the address counter is fixed, so address recording in X16 mode is actually impossible. As a result, the address recorded by the ECS in X16 mode does not match the actual address, and thus information such as the maximum error row and the maximum error count cannot be accurately recorded.

[0057] Those skilled in the art will understand that the X16 mode refers to a mode in which all 16 input and output terminals of the memory output data, and these 16 input and output terminals can transmit data in parallel. Accordingly, the input and output terminals include the lower 8-bit LDQ (Low Data Queue) and the upper 8-bit UDQ (Up Data Queue). The X8 mode refers to a mode in which 8 input and output terminals output data, that is, only the lower 8-bit LDQ is used. For example, the DRAM in the X16 mode includes 4 BGs, each BG includes 4 BKs, and the page size is 2KB; the DRAM in the X8 mode includes 8 BGs, each BG includes 4 BKs, and the page size is 1KB. Therefore, the length of the row in the X16 mode (that is, the number of column address bits) is twice that of the X8 mode.

[0058] An embodiment of the present disclosure provides an address conversion circuit, which is applied to a memory. The memory includes N memory bank groups. As shown in FIG5 , the address conversion circuit 100 includes:

[0059] The frequency dividing circuit 110 is configured to receive a first address increment signal Inc1 having a first frequency, process and output a second address increment signal Inc2 having a second frequency and a jump signal X having a second frequency; wherein the first address increment signal Inc1 is configured to indicate an address increment of the memory in the first configuration, the second address increment signal Inc2 is configured to indicate an address increment of the memory in the second configuration, and the jump signal X is configured to indicate an address jump between the N memory bank groups; the first frequency is N times the second frequency, where N is a positive integer greater than 1;

[0060] The address counter 120 is configured to receive the second address increase signal Inc2 and output an address counting signal;

[0061] The row address increasing circuit 130 is coupled to the address counter 120 and the frequency dividing circuit 110 , and is configured to output a first row address increasing signal Row_Inc1 when the address counting signal indicates the end of column address counting and the jump signal X indicates the last memory bank group.

[0062] In the disclosed embodiment, the count value of the address counter 120 is the address value. The address here may include each bit value of the column address CA, row address RA, bank address BK, and bank group address BG. The function of the address counter 120 is to count based on the input second address increment signal Inc2, and each count outputs the next address. For example, the least significant bit of the address counter is the column address, so each count is equivalent to incrementing the column address by 1.

[0063] It is understandable that the address counter 120 includes a multi-bit output terminal for outputting the value of each bit address, and a group of values ​​output by the multi-bit output terminal at a time is a complete address. In addition, if it is necessary to find the row address of the current count, or the column address, etc., it can also be directly obtained through the corresponding several output terminals of the address counter 120. For example, the column address includes 6 bits, the row address includes 16 bits, the memory address includes 2 bits, and the memory group address includes 2 bits (if it is in X8 mode, the memory group address includes 3 bits). If the column address corresponding to a row address is found to be the end, that is, the 6-bit column address is all "1", the next count will enter the next row, so the row address is increased by 1 and the column address is cleared to 0. The address counter 120 can count addresses based on the first address increase signal Inc1 as a clock signal, and the frequency of the address counting is the first frequency. When the address counter 120 counts addresses based on the second address increase signal Inc2 as a clock signal, the frequency of its address counting is the second frequency.

[0064] In the embodiment of the present disclosure, the frequency division circuit 110 is used to generate the second address increase signal Inc2 having the second frequency through frequency division. In addition, the jump signal X is generated through frequency division or frequency multiplication.

[0065] The first frequency may be N times the second frequency, where N is a positive integer greater than 1, and illustratively, N is 2 or 4. In other words, the frequency division circuit 110 generates the second address increment signal Inc2 by frequency division, which causes the address counter to jump more slowly. This is done so that different memory bank groups BG can be switched by the jump signal X within one cycle of the second address increment signal.

[0066] In some embodiments, the duty cycle of the skip signal X is 1 / N.

[0067] The frequency of jump signal X is the same as the second address increment signal Inc2. The duty cycle of jump signal X represents the frequency of switching between different memory bank groups. This duty cycle is 1 / N, where N can be an integer greater than 1. For example, when N is equal to 2, the duty cycle of jump signal X is 0.5, or 50%, and jumps twice within one address counting cycle, achieving switching between two different BGs. When N is equal to 4, the duty cycle of jump signal X is 0.25, or 25%, and jumps four times within one address counting cycle, achieving switching between four different BGs.

[0068] Referring to Figure 6 , each cycle of the first address increment signal Inc1 performs sequential ECS read and write operations. The allocation circuit 110 can divide the first address increment signal Inc1 to obtain a frequency-divided signal IncDiv, and generate a jump signal X and a second address increment signal Inc2 based on the frequency-divided signal IncDiv. The address counter 120 counts each bit of the address, illustratively representing the four bits of the bank group and bank numbers BG<1:0>, BK<1:0>, the 16-bit row address Row<15:0>, and the 6-bit column address Col<5:0> as shown in Figure 6 . The first row address increment signal Row_Inc1 indicates a row address carry when all column addresses are 1 and the jump signal X is 1. The end signal EcsOut indicates the completion of all address counting and the completion of the jump signal X jump.

[0069] For example, as shown in Figure 6, the first frequency is twice the second frequency, and the duty cycle of the jump signal X is 0.5. The jump signal X switches between "0" and "1." For example, when the jump signal X is "0," it indicates the first memory bank group BG1, and when the jump signal X is "1," it indicates the second memory bank group BG2. The ECS circuit can perform ECS read and write operations based on the first address increment signal Inc1, but the address counter counts using the second address increment signal Inc2 as the clock. At a single address, two different BGs are actually switched, and ECS read and write operations are performed on the memory cells with the same address in the two different BGs.

[0070] In addition, the address counter 120 counts the column address in each row in sequence. After the column address counting of one row is completed, the row address is carried based on the row address increase signal and the column address count is cleared, thereby entering the next row for counting.

[0071] Because the number of address bits per row is doubled in the second configuration, the jump signal X performs a jump to a different BG for each column address based on the original column address count. Therefore, the row address increment signal cannot simply indicate a row carry when all column address bits in the address counter 120 are "1." It is also necessary to ensure that the jump signal X also jumps to the last BG when the last column address, i.e., when all bits of the column address are "1," is reached before the row address count for a row is considered complete and the row address increment signal is output. Therefore, in the disclosed embodiment, the row address increment circuit 130 outputs the first row address increment signal Row_Inc1 only when the address count signal indicates the end of the column address count and the jump signal X indicates the last bank group. At this point, this signal can be used to indicate that the current column address count is cleared and the row address is carried.

[0072] The first configuration described above uses the first address increment signal Inc1 to implement a complete address count configuration mode. The second configuration uses the second address increment signal Inc2 in conjunction with the jump signal X to implement a complete address count configuration mode. For example, the first configuration is the memory's X8 mode, and the second configuration is the memory's X16 mode.

[0073] In this way, address counting expansion is achieved without modifying the circuitry associated with address counting; simply by adjusting the address counting frequency and adding a jump signal X. Compared to doubling the number of bits in the two column addresses, the solution of the disclosed embodiment can achieve larger-scale address counting in the second configuration without requiring major circuit modifications, while remaining compatible with the first configuration.

[0074] In some embodiments, as shown in FIG7 , the frequency dividing circuit 110 includes:

[0075] A first flip-flop 111, whose clock input terminal is used to receive the first address increase signal Inc1, and whose output terminal is connected to the data input terminal and outputs the jump signal X;

[0076] The first processing unit 112 has a first input terminal coupled to the output terminal of the first flip-flop 111 , a second input terminal receiving the first address increase signal Inc1 , and an output terminal outputting the second address increase signal Inc2 .

[0077] The first flip-flop 111 performs frequency division processing using the first address increment signal Inc1 as a clock, and outputs a frequency-divided signal IncDiv as shown in FIG6 . The output terminal of the first flip-flop 111 is connected to the data input terminal, or the inverted version of the output terminal is connected to the data input terminal. The frequency-divided signal can be used as the jump signal X. The first processing unit 112 then processes the first address increment signal Inc2 to generate the corresponding second address increment signal Inc2. That is, the second frequency of the second address increment signal Inc2 is also obtained through the frequency division processing performed by the first flip-flop 111.

[0078] Exemplarily, the first processing unit 112 may include a NOR gate, whose input signals are the first address increase signal Inc1 and the jump signal X, so as to generate the waveform of the second address increase signal Inc2 as shown in FIG. 6 .

[0079] Here, to align the waveforms of the jump signal X with the second address increment signal Inc2, the frequency divider circuit 110 may further include a first delay unit Delay1 for delaying the jump signal X, and a second delay unit Delay2 for delaying the second address increment signal Inc2. The first and second delay units may include structures such as a plurality of inverters.

[0080] In some embodiments, as shown in Figure 7, the frequency division circuit 110 also includes: a first AND gate 113; the first input end of the first AND gate 113 receives a configuration signal S2 for indicating the second configuration, the second input end receives an initial reset signal, and the output end outputs a reset signal Reset, and the reset end of the first trigger receives the reset signal Reset.

[0081] Here, the reset terminal of the first flip-flop 111 can be reset only when the reset signal Reset is received when the memory is in the second configuration through the first AND gate 113. That is, the frequency dividing circuit 110 is used in the second configuration and may not be used in the first configuration.

[0082] In some embodiments, as shown in FIG8 , the address counter 120 includes:

[0083] M counting units 121, the output end of each level of the counting unit 121 is used to output a count value Q of one address; wherein M is an integer greater than 2;

[0084] M-1 second AND gates 122, each of which has a first input connected to an output of a counting unit 121 and a second input connected to an output of a previous counting unit 121 or an output of a previous second AND gate 122;

[0085] M-1 XOR gates 123, each XOR gate 123 has a first input connected to an output of the counting unit 121 or an output of the second AND gate 122, and a second input connected to an output of the next-stage counting unit 121.

[0086] Each counting unit 121 outputs a count value Q <x>That is, the x-th address in the above-mentioned address count value. For example, the last count value represents the last column address, the first count value represents the BG address, and so on. Exemplarily, the address counter 120 includes: 6 bits of column address, 16 bits of row address, 2 bits of memory bank address, and 3 bits of memory bank group address, for a total of 27 bits. Then the address counter 120 includes 27 counting units 121, 26 second AND gates 122, and 26 XOR gates 123. It should be noted that the memory bank group address here is 3 bits. The reason why 3 counting units 121 are required is to be compatible with the address counter 120 in the X8 configuration. In the X16 configuration, the memory bank group address only requires 2 bits. (Only 4 bits are used as an example in FIG8 )

[0087] XOR gate 123 connects the counting units 121 at each level to implement carry. AND gate 122 determines whether the counting of the connected levels has completed. Only when the count values ​​of all connected levels are 1 will second AND gate 122 output "1," indicating that the counting of the connected levels has completed.

[0088] It can be understood that if the second AND gate 122 is connected to the output terminals of two counting units 121, its output indicates the completion of counting of these two units; if it is connected to the output terminal of one counting unit 121 and the output terminal of another second AND gate 122, its output indicates the completion of counting of both counting units 121 connected to the two second AND gates 122. It can be seen that if multiple second AND gates 122 are connected in sequence, the output result of the last second AND gate 122 can be used to determine whether counting has been completed for all the counting units 121 connected to them.

[0089] Therefore, the output values ​​of the second AND gates 122 with different connections can be used to determine whether counting has completed for the corresponding address bits. This facilitates determining whether counting has completed for each bit representing the "column address" or the "row address" in the address counter 120. Alternatively, all counting units 121 can be connected sequentially via the second AND gates 122 to determine whether counting has completed for all addresses.

[0090] In some embodiments, as shown in FIG8 , the counting unit 121 includes: a second trigger;

[0091] The output terminal of the first second trigger is connected to the data input terminal of the first second trigger; or, an inverter can be further connected between the output terminal of the first trigger and the data input terminal of the first second trigger.

[0092] In some embodiments, the first input terminal of the first XOR gate 123 is connected to the output terminal of the first second flip-flop, and the second input terminal is connected to the output terminal of the second second flip-flop;

[0093] The first input terminal of the i-th XOR gate 123 is connected to the output terminal of the i-1-th second AND gate 122, and the second input terminal is connected to the output terminal of the i+1-th trigger; wherein i is an integer greater than 1 and less than M.

[0094] That is, except for the first XOR gate 123 , each of the other XOR gates 123 is used to perform XOR calculation on the output result of a counting unit 121 and the result of whether the counting of the previous counting units 121 is completed (ie, the output result of the second AND gate 122 ).

[0095] When the output result of the second AND gate 122 connected to the XOR gate 123 is "1" (the previous stage counting is completed) and the output result of the counting unit 121 connected to the XOR gate 123 is "0", it means that the counting unit 121 needs to add 1 at this time. At this time, the XOR gate 123 outputs "1" to the counting unit 121, causing the next output result to jump to "1".

[0096] When the output result of the second AND gate 122 connected to the XOR gate 123 is "1" (the previous stage counting is completed) and the output result of the counting unit 121 connected to the XOR gate 123 is "1", it means that a carry is required. The counting unit 121 needs to add 1 and jump to "0". At this time, the XOR gate 123 outputs "0" to the counting unit 121, causing the next output result to jump to "0".

[0097] When the output result of the second AND gate 122 connected to the XOR gate 123 is "0" (the previous stage count has not ended) and the output result of the counting unit 121 connected to the XOR gate 123 is "1", the counting unit 121 does not need to be changed next time and needs to wait for the jump of the previous stage. At this time, the XOR result is "1", and the next counting result remains "1".

[0098] When the output result of the second AND gate 122 connected to the XOR gate 123 is "0" (the previous stage count has not ended) and the output result of the counting unit 121 connected to the XOR gate 123 is "0", the counting unit 121 does not need to be changed next time and needs to wait for the jump of the previous stage. At this time, the XOR result is "0", and the next counting result remains "0".

[0099] For the first XOR gate 123, its first input terminal is connected to the output terminal of the first-stage counting unit 121. That is, it only needs to determine whether the count value of the counting unit 121 is "0" or "1" to determine whether the next-stage counting unit 121 maintains the count value or increases by 1. In some embodiments, as shown in Figure 8, the first input terminal of the first second-stage AND gate 122 is connected to the output terminal of the second second flip-flop, and the second input terminal is connected to the output terminal of the first second flip-flop.

[0100] The first input terminal of the jth second AND gate 122 is connected to the output terminal of the j+1th second flip-flop, and the second input terminal is connected to the output terminal of the j-1th second AND gate 122; where j is an integer greater than 1 and less than M.

[0101] The connection method of the second AND gates 122 is similar to that of an XOR gate. Thus, the input of each second AND gate 122 is the result of whether all counting units 121 in the previous stage have completed counting, and the count value of the counting unit 121 connected to it is ANDed. This sequentially records whether the counting of each stage before each counting unit 121 has completed counting. It can be understood that the output result of the second AND gate 122 connected to the last counting unit 121 indicates whether the entire address counter 120 has completed counting.

[0102] In some embodiments, as shown in FIG8 , the address counter further includes a third AND gate 124 , wherein a first input terminal of the third AND gate 124 is coupled to the frequency dividing circuit 110 for receiving the jump signal X; a second input terminal is connected to the output terminal of the M-2 second AND gate 122 ; and an output terminal of the third AND gate is used to output a stop signal EcsOut, wherein the stop signal EcsOut indicates the end of address counting.

[0103] The M-2nd second AND gate 122, the penultimate second AND gate 122, outputs "1" at its first output terminal, indicating that all address counting by the address counter 120 in the X16 configuration has concluded. However, during the final counting cycle, the jump signal X must transition once. That is, while the second AND gate 122 outputs "1," the jump signal X first outputs "0" and then "1." When the jump signal X reaches "1," the final address count for the second memory bank has concluded, effectively completing all address counting.

[0104] Therefore, third AND gate 124 is used to AND the output of the second-to-last AND gate 122 with jump signal X. When its output is "1," it indicates the end of all counting. This signal serves as stop signal EcsOut, indicating the end of address counting. Thus, when applied to ECS, this signal can indicate the end of ECS operations.

[0105] In some embodiments, as shown in FIG8 , the row address increasing circuit 130 includes:

[0106] The fourth AND gate 131 has a first input connected to the address counter 120 for receiving the second row address increment signal Row_Inc2, a second input connected to the output of the frequency divider circuit 110 for receiving the jump signal X, and an output of the first row address increment signal Row_Inc1; wherein the second row address increment signal Row_Inc2 is used to indicate the end of column address counting.

[0107] The second row address increment signal, Row_Inc2, is a carry indication signal output by the address counter 120 when the column address counts are all "1s." In the first configuration, this signal indicates the completion of column counts for the current row. In the second configuration, however, it can only indicate the completion of column address counts by the address counter and cannot indicate the completion of column counts for all BGs.

[0108] Therefore, the embodiment of the present disclosure utilizes the fourth AND gate 131 to AND the second row address increment signal Row_Inc2 with the jump signal X. When both are "1," it indicates that the last column address of the last BG has been counted, and the next row can be carried forward. This outputs the first row address increment signal Row_Inc1, which instructs the counter to switch to the next row for counting in the second configuration.

[0109] In some embodiments, as shown in FIG9 , the address counter 120 further includes:

[0110] The first signal selector 125 has a first input end connected to the output end of the Mth second trigger of the address counter, a second input end connected to the output end of the frequency dividing circuit 110, and is used to receive the jump signal X. The control end of the first signal selector 125 is used to receive the mode selection signal S, and the output end of the first signal selector 125 is connected to the first input end of the third AND gate; the mode selection signal S is used to indicate that the memory is in the first configuration or the second configuration.

[0111] Thus, when the mode selection signal S indicates the second configuration, the circuit shown in FIG9 is consistent with FIG8 , that is, the third AND gate 124 outputs the stop signal only when the address counter 120 completes all counting and the jump signal jumps to the last memory bank group.

[0112] When the mode selection signal S indicates the first configuration, the input signal of one input terminal of the third AND gate 124 is the output signal of the second-to-last second AND gate 122, and the input signal of the other input terminal is the output signal of the last-stage counting unit 121, which indicates that the counting of the address counter is completed.

[0113] In this way, the output signal of the third AND gate 124 is compatible with the first configuration and the second configuration, and both are used to indicate whether to end address counting.

[0114] In some embodiments, as shown in FIG9 , the row address increasing circuit 130 further includes:

[0115] The second signal selector 132 has a first input end connected to the address counter 120 for receiving the second row address increase signal Row_Inc2, a second input end connected to the output end of the fourth AND gate 131, and a signal selection end for receiving the mode selection signal S; wherein, when the mode selection signal S indicates that the memory is in the first configuration, the output end RowOut of the second signal selector 132 outputs the second row address increase signal Row_Inc2; when the mode selection signal S indicates that the memory is in the second configuration, the second signal selector 132 outputs the first row address increase signal Row_Inc1.

[0116] In this way, the second signal selector 132 can be used to switch the row address increase signal used in the first configuration and the second configuration to indicate that the column address counting of the current row is finished and the counting of the next row is started.

[0117] It is understandable that when the memory is in the second configuration, the second row address increase signal Row_Inc2 does not represent the end of counting of a row of any memory bank, but only represents that the count value of each unit in the address counter for implementing column address counting is maximum.

[0118] In this way, the second signal selector 132 can be used to achieve compatibility of the row address increasing circuit 130 with the first configuration and the second configuration.

[0119] In some embodiments, the address conversion circuit 100 further includes:

[0120] a third signal selector 140, having a first input terminal for receiving the first address increment signal Inc1, a second input terminal connected to the output terminal of the frequency dividing circuit 110 and for receiving the second address increment signal Inc2, an output terminal connected to the clock input terminal Clk of the address counter 120, and a signal selection terminal for receiving a mode selection signal S;

[0121] When the mode selection signal S indicates that the memory is in the first configuration, the third signal selector 140 outputs the first address increment signal Inc1; when the mode selection signal S indicates that the memory is in the second configuration, the third signal selector outputs the second address increment signal Inc2.

[0122] Similar to the first and second signal selectors described above, the third signal selector 140 is also used to switch between the first and second memory configurations. When the first configuration is selected, the first address increment signal Inc1 is transmitted to the clock input of the address counter 120 as the clock signal for address counting. Thus, the address counter 120 performs address counting at the first frequency under the first configuration. When the second configuration is selected, the second address increment signal Inc2 is transmitted to the address counter 120 as the clock signal. This switches the counting frequency of the address counter 120 to the second frequency, thereby reducing the jump speed of the address counter 120. This allows for multiple jumps of the jump signal X to be added to each address counting cycle, enabling the sequential counting of the same address across multiple memory bank groups during each address counting cycle.

[0123] In this way, the compatibility of the entire address conversion circuit with the first configuration and the second configuration of the memory is achieved. [0123.1][Corrected 12.06.2024 according to Rule 91] A memory is also provided in an embodiment of the present disclosure, including the address conversion circuit 100 and N memory body groups 200 provided in the above embodiment. The memory will be described in detail below. It should be noted that the description of the above embodiment is also applicable to the embodiment of the memory. To avoid repetition, the contents mentioned in the above embodiment will not be described in detail below. [0123.2][Corrected 12.06.2024 according to Rule 91] The memory includes: the address conversion circuit provided in the above embodiment and N memory bank groups, and the N memory bank groups perform ECS operations according to the first row address increase signal and stop signal output by the address conversion circuit. [0123.3] [Corrected 12.06.2024 in accordance with Rule 91] Referring to FIG. 10 , a schematic diagram illustrating the structure of a memory device according to another embodiment of the present disclosure is shown. As shown in FIG. 10 , the memory device 10 includes N memory bank groups 200 and an address conversion circuit 100. The N memory bank groups 200 perform ECS operations based on the first row address increment signal Row_Inc1 and the stop signal Ecs_out output by the address conversion circuit 100. This ensures that the recorded address is consistent with the actual address when two memory bank groups are merged, thereby facilitating the recording of erroneous addresses and facilitating the execution of ECS operations by the memory device 10.

[0124] It should be understood that "some embodiments", "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0125] It should be noted that, in this document, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0126] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.< / x>

Claims

1. An address conversion circuit (100), characterized in that, Applied to a memory (10), the memory (10) includes N bank groups (200), and the address conversion circuit (100) includes: A frequency division circuit (110) for receiving a first address increment signal (Inc1) having a first frequency, processing and outputting a second address increment signal (Inc2) having a second frequency and a jump signal (X) having the second frequency; wherein, the first address increment signal (Inc1) is used to indicate the address increment of the memory (10) in the first configuration, the second address increment signal (Inc2) is used to indicate the address increment of the memory (10) in the second configuration, the jump signal (X) is used to indicate the jump of the address between the N bank groups (200), the first frequency is N times the second frequency, and N is a positive integer greater than 1; An address counter (120) for receiving the second address increment signal (Inc2) and outputting an address count signal; A row address increment circuit (130) coupled to the address counter (120) and the frequency division circuit (110), for outputting a first row address increment signal (Row_Inc1) when the address count signal indicates the end of column address counting and the jump signal (X) indicates the last bank group (200).

2. The address conversion circuit (100) according to claim 1, characterized in that The frequency division circuit (110) includes: A first flip-flop (111) whose clock input terminal is used to receive the first address increment signal (Inc1), and whose output terminal and data input terminal are connected and output the jump signal (X); A first processing unit (112) whose first input terminal is coupled to the output terminal of the first flip-flop (111), whose second input terminal receives the first address increment signal (Inc1), and whose output terminal outputs the second address increment signal (Inc2).

3. The address conversion circuit (100) according to claim 2, characterized in that, The frequency division circuit (110) further includes: a first AND gate (113); the first input terminal of the first AND gate (113) receives a configuration signal (S2) for indicating the second configuration, the second input terminal receives an initial reset signal, and the output terminal outputs a reset signal (Reset), and the reset terminal of the first flip-flop (111) receives the reset signal (Reset).

4. The address conversion circuit (100) according to claim 1, characterized in that The address counter (120) includes: M counting units (121), and the output terminals of each level of the counting units (121) are respectively used to output the count value (Q) of one bit of the address; wherein, M is an integer greater than 2; M-1 second AND gates (122), the first input terminal of each second AND gate (122) is connected to the output terminal of one counting unit (121), and the second input terminal is connected to the output terminal of the previous-level counting unit (121) or the output terminal of the previous second AND gate (122); M-1 exclusive-OR gates (123), the first input terminal of each exclusive-OR gate (123) is connected to the output terminal of one counting unit (121) or the output terminal of one second AND gate (122), and the second input terminal is connected to the output terminal of the next-level counting unit (121).

5. The address conversion circuit (100) according to claim 4, wherein The counting unit (121) includes: a second flip-flop; Among them, the output terminal of the first second flip-flop is connected to the data input terminal of the first second flip-flop; The first input terminal of the first exclusive-OR gate (123) is connected to the output terminal of the first second flip-flop, and the second input terminal is connected to the output terminal of the second second flip-flop; The first input terminal of the i-th exclusive-OR gate (123) is connected to the output terminal of the (i - 1)-th second AND gate (122), and the second input terminal is connected to the output terminal of the (i + 1)-th second flip-flop; where i is an integer greater than 1 and less than M.

6. The address conversion circuit (100) according to claim 5, wherein The first input terminal of the first second AND gate (122) is connected to the output terminal of the second second flip-flop, and the second input terminal is connected to the output terminal of the first second flip-flop; The first input terminal of the j-th second AND gate (122) is connected to the output terminal of the (j + 1)-th second flip-flop, and the second input terminal is connected to the output terminal of the (j - 1)-th second AND gate (122); where j is an integer greater than 1 and less than M.

7. The address conversion circuit (100) according to claim 5, characterized in that The address counter (120) further includes: a third AND gate (124); The first input terminal of the third AND gate (124) is coupled to the frequency division circuit (110) for receiving the jump signal (X); the second input terminal is connected to the output terminal of the (M - 2)-th second AND gate (122); the output terminal of the third AND gate (124) is used to output a stop signal (EcsOut), and the stop signal (EcsOut) indicates the end of address counting.

8. The address conversion circuit (100) according to claim 7, wherein The address counter (120) further includes: A first signal selector (125), whose first input terminal is connected to the output terminal of the M-th second flip-flop of the address counter (120), whose second input terminal is connected to the output terminal of the frequency division circuit (110) for receiving the jump signal (X), whose control terminal is used to receive a mode selection signal (S), and whose output terminal is connected to the first input terminal of the third AND gate (124); the mode selection signal (S) is used to indicate that the memory (10) is in the first configuration or the second configuration.

9. The address conversion circuit (100) according to claim 1, wherein The row address increment circuit (130) includes: A fourth AND gate (131), whose first input terminal is connected to the address counter (120) for receiving a second row address increment signal (Row_Inc2), whose second input terminal is connected to the output terminal of the frequency division circuit (110) for receiving the jump signal (X), and whose output terminal outputs a first row address increment signal (Row_Inc1); where the second row address increment signal (Row_Inc2) is used to indicate the end of column address counting.

10. The address conversion circuit (100) according to claim 9, characterized in that, The row address increment circuit (130) further includes: A second signal selector (132) having a first input terminal connected to the address counter (120) for receiving the second row address increment signal (Row_Inc2), a second input terminal connected to the output terminal of the fourth AND gate (131), and a signal selection terminal for receiving a mode selection signal (S); wherein, when the mode selection signal (S) indicates that the memory (10) is in the first configuration, the second signal selector (132) outputs the second row address increment signal (Row_Inc2); when the mode selection signal (S) indicates that the memory (10) is in the second configuration, the second signal selector (132) outputs the first row address increment signal (Row_Inc1).

11. The address conversion circuit (100) according to claim 1, characterized in that, Further comprising: A third signal selector (140) having a first input terminal for receiving the first address increment signal (Inc1), a second input terminal connected to the output terminal of the frequency division circuit (110) for receiving the second address increment signal (Inc2), an output terminal connected to the clock input terminal of the address counter (120), and a signal selection terminal for receiving a mode selection signal (S); wherein, when the mode selection signal (S) indicates that the memory (10) is in the first configuration, the third signal selector (140) outputs the first address increment signal (Inc1); when the mode selection signal (S) indicates that the memory (10) is in the second configuration, the third signal selector (140) outputs the second address increment signal (Inc2).

12. The address conversion circuit (100) according to claim 1, wherein The duty cycle of the jump signal (X) is 1 / N.

13. The address conversion circuit (100) according to claim 1, characterized in that, The first configuration is the X8 mode of the memory (10), and the second configuration (10) is the X16 mode of the memory.

14. The address conversion circuit (100) according to claim 2, characterized in that, The first processing unit (112) includes a NOR gate that receives the first address increment signal (Inc1) and the jump signal (X) and generates the second address increment signal (Inc2).

15. A memory (10), characterized in that, Comprising: N memory bank groups (200) and the address conversion circuit (100) according to any one of claims 1-14, and the N memory bank groups (200) perform an ECS operation according to the first row address increment signal (Row_Inc1) and the stop signal (Ecs_out) output by the address conversion circuit (100).

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