Wiring substrate, light-emitting substrate, and display device

Abstract

Disclosed are a wiring substrate, a light-emitting substrate, and a display device. The wiring substrate comprises: a substrate comprising a functional area and a bonding area; a plurality of columns of pad units, at least one of the plurality of columns of pad units comprising a plurality of pad units cascaded in a first direction, at least one pad unit comprising a first pad area comprising a plurality of types of first pads, and the plurality of types of first pads comprising at least one data pad and at least one ground pad; and a plurality of traces electrically connected to the plurality of pad units, the plurality of traces comprising a plurality of data signal lines and a plurality of ground signal lines, the plurality of data signal lines comprising a plurality of first data signal lines each electrically connected to the data pads of a plurality of first pad areas in a column of pad units, and the ground signal lines each being electrically connected to the ground pads of two first pad areas which are located in adjacent columns of pad units and cascaded.

Description

Wiring substrate, light-emitting substrate, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application number PCT / CN2023 / 142936, filed with the State Intellectual Property Office of the People's Republic of China on December 28, 2023, and entitled "Wiring Substrate, Light-Emitting Substrate and Display Device," the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a wiring substrate, a light-emitting substrate, and a display device. Background Art

[0004] Micro light-emitting diodes have a significant increase in usage in the display field due to their smaller size, ultra-high brightness, and long life.

[0005] Summary of the Invention

[0006] An embodiment of the present disclosure provides a wiring substrate, the wiring substrate comprising:

[0007] A substrate comprising a functional area and a binding area located on one side of the functional area in a first direction;

[0008] A plurality of pad unit columns are located on one side of the substrate in the functional area; at least one of the plurality of pad unit columns includes a plurality of pad units cascaded along a first direction; at least one of the plurality of pad units includes: a first pad area; the first pad area includes: a plurality of first pads, the plurality of first pads including at least one data pad and at least one ground pad;

[0009] Multiple routing lines; the multiple routing lines are electrically connected to the multiple pad units; the multiple routing lines include: multiple data signal lines and multiple ground signal lines; the multiple data signal lines include: multiple first data signal lines, the first data signal lines are electrically connected to the data pads of the multiple first pad areas in a column of pad units, and the ground signal lines are electrically connected to the ground pads of two first pad areas located in adjacent pad unit columns and cascaded.

[0010] In some embodiments, the ground pads of the plurality of first pad regions in one pad unit column are adjacent to the ground pads of the plurality of first pad regions in an adjacent pad unit column.

[0011] In some embodiments, the ground pads of the plurality of first pad regions in one pad unit column are mirror-imaged to the ground pads of the plurality of first pad regions in an adjacent pad unit column.

[0012] In some embodiments, the routing further includes: a plurality of address signal lines, and a plurality of second voltage lines;

[0013] The first pad area further includes: an address pad, a relay pad, and at least one power pad;

[0014] The address signal line is electrically connected to the address pad and the relay pad, and the second voltage line is electrically connected to the power pad;

[0015] In two first pad areas adjacent to and respectively located in two cascaded pad unit columns, one address pad is disposed adjacent to a relay pad in another first pad area.

[0016] In some embodiments, the address pads and relay pads of the first pad region in one pad unit column are rotated 180° and mirrored with the address pads and relay pads of the first pad region in an adjacent pad unit column.

[0017] In some embodiments, in two adjacent pad unit columns, the cascading directions of the plurality of pad units are opposite;

[0018] The wiring substrate includes 2N pad unit columns; the arrangement of the multiple first pads in the first pad area in the 2nth pad unit column after rotating 180° is the same as the arrangement of the multiple first pads in the first pad area in the (2n-1)th pad unit column; wherein N is a positive integer and n is a positive integer not greater than N.

[0019] In some embodiments, at least one data pad and at least one ground pad are located in the same column in the first direction;

[0020] At least one data pad and at least one ground pad include a portion located at an edge of the first pad region close to the ground signal line.

[0021] In some embodiments, the ground signal line includes: a trunk extending along a first direction; the trunk is located between two pad unit columns electrically connected to the ground signal line.

[0022] In some embodiments, the first data signal line includes a plurality of first sub-segments; the first sub-segments are electrically connected to data pads of two first pad regions cascaded in the pad unit column;

[0023] The orthographic projection of the first sub-segment on the substrate is located on a side of the orthographic projection of the main body on the substrate facing the orthographic projection of the pad unit column on the substrate.

[0024] In some embodiments, the plurality of data signal lines further include: a plurality of second data signal lines;

[0025] The second data signal line is electrically connected to the data pads of two cascaded first pad areas located in adjacent pad unit columns.

[0026] In some embodiments, the ground signal line includes a trunk portion; and an orthographic projection of the second data signal line on the substrate is located on a side of the orthographic projection of the trunk portion on the substrate away from the binding region.

[0027] In some embodiments, two adjacent and cascaded pad unit columns are electrically connected to the same trunk line.

[0028] In some embodiments, two adjacent and cascaded pad unit columns are electrically connected to different trunk portions, and the branches are electrically connected to the ground pads of two cascaded first pad regions located in adjacent pad unit columns, respectively.

[0029] In some embodiments, the ground signal line includes a trunk; the pad unit further includes: at least one second pad area; the second pad area is electrically connected to the first pad area;

[0030] The first pad also includes: at least one output pad;

[0031] The plurality of traces further include: a plurality of first voltage lines extending along a first direction;

[0032] The first voltage line is electrically connected to the input ends of the plurality of second pad regions in the pad unit column, and the output ends of the second pad regions are electrically connected to the output pads;

[0033] The first voltage line and the trunk portion electrically connected to the same pad unit column are respectively located on both sides of the pad unit column.

[0034] In some embodiments, at least some adjacent pad unit columns are electrically connected to the same first voltage line.

[0035] In some embodiments, the first pad area further includes: an address pad, a relay pad, and at least one power pad;

[0036] The routing also includes: a plurality of address signal lines, and a plurality of second voltage lines;

[0037] The address signal line includes a plurality of second sub-segments;

[0038] One end of the second sub-segment is electrically connected to a relay pad of a first pad area, and the other end of the second sub-segment is electrically connected to an address pad of a first pad area of ​​a next level of the first pad area;

[0039] The second voltage line includes a plurality of third sub-segments; the third sub-segments are electrically connected to the power supply pads of the two cascaded first pad areas;

[0040] In the first direction, the relay pad and the at least one power pad are located in different columns.

[0041] In some embodiments, the first pad area includes a plurality of first pads arranged in an M×2 manner to form a first pad column and a second pad column; M is a positive integer;

[0042] In the second direction, the orthographic projection of the second pad column on the substrate is located between the orthographic projection of the first pad column on the substrate and the orthographic projection of the main body on the substrate;

[0043] At least part of at least one data pad, a relay pad, and at least part of at least one ground pad are located in the second pad column, and at least part of at least one output pad and at least one power pad are located in the first pad column.

[0044] In some embodiments, the trace is disposed on the same layer as the first pad;

[0045] The address pad is located in the second pad column;

[0046] In the second pad column, the arrangement direction of the address pads and the relay pads is the same as the cascade direction of the multiple pad units in the pad unit column;

[0047] In the second pad column, in the first direction, the orthographic projection of the ground pad on the substrate is located between the orthographic projection of the address pad on the substrate and the orthographic projection of the relay pad on the substrate;

[0048] The orthographic projection of the second sub-segment of the two cascaded first pad areas in the column of electrically connected pad units on the substrate is located between the orthographic projection of the first sub-segment on the substrate and the orthographic projection of the main body on the substrate.

[0049] In some embodiments, the at least one data pad includes: a data input pad and a data output pad; in each pad unit column, the data output pad of the first pad region of the i-th level is electrically connected to the data input pad of the first pad region of the (i+1)-th level through the first sub-segment; wherein i is a positive integer;

[0050] In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data output pad of the last first pad region in a pad unit column, and the other end of the second data signal line is electrically connected to the data input pad of the first first pad region in a pad unit column;

[0051] The data input pad and the data output pad are located in the second pad column; the arrangement direction of the data input pad and the data output pad is the same as the cascade direction of the multiple pad units in the pad unit column, and the data input pad and the data output pad are electrically connected;

[0052] The orthographic projection of the address pad on the substrate is located between the orthographic projection of the data input pad and the orthographic projection of the ground pad on the substrate, and the orthographic projection of the relay pad on the substrate is located between the orthographic projection of the data output pad and the orthographic projection of the ground pad on the substrate.

[0053] In some embodiments, the at least one data pad includes: a data input pad and a data output pad; in each pad unit column, the data input pad of the first pad region of the i-th level is electrically connected to the data output pad of the first pad region of the (i+1)-th level through the first sub-segment; wherein i is a positive integer;

[0054] In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data input pad of the last first pad region in a pad unit column, and the other end of the second data signal line is electrically connected to the data output pad of the first first pad region in a pad unit column;

[0055] The data input pad and the data output pad are located in the second pad column; the arrangement direction of the data output pad and the data input pad is the same as the cascade direction of the multiple pad units in the pad unit column, and the data input pad and the data output pad are electrically connected;

[0056] The orthographic projection of the address pad on the substrate is located between the orthographic projection of the data input pad and the orthographic projection of the ground pad on the substrate, and the orthographic projection of the relay pad on the substrate is located between the orthographic projection of the data output pad and the orthographic projection of the ground pad on the substrate.

[0057] In some embodiments, in the second direction, the data output pads of the first pad region and the data input pads of the first pad region rotated 180° are located in the same row;

[0058] The address pads of the first pad area and the relay pads of the first pad area rotated 180 degrees are located in the same row;

[0059] The second data signal line extends along the second direction, and an orthographic projection of the second data signal line on the substrate is located on a side of the orthographic projection of the branch on the substrate away from the binding area;

[0060] The second subsegment electrically connecting two adjacent pad unit columns extends along the second direction. The orthographic projection of the second subsegment electrically connecting two adjacent pad unit columns on the substrate is located between the orthographic projection of the second data signal line on the substrate and the orthographic projection of the branch on the substrate.

[0061] In some embodiments, the at least one power pad includes: a first power pad and a second power pad; the first power pad and the second power pad are both located in a first pad column;

[0062] In the first pad column, the arrangement direction of the first power pad and the second power pad is the same as the cascade direction of the plurality of pad units in the pad unit column;

[0063] In the first direction, the orthographic projection of the output pad on the substrate is located between the orthographic projection of the first power pad on the substrate and the orthographic projection of the second power pad on the substrate;

[0064] One end of the third sub-segment is electrically connected to the second power pad of a first pad area, and the other end of the third sub-segment is electrically connected to the first power pad of a first pad area next to the first pad area.

[0065] In some embodiments, in the second direction, the power pads and the data pads are located in the same row.

[0066] In some embodiments, the first pad region includes a plurality of ground pads, and the plurality of ground pads are all located in the second pad column.

[0067] In some embodiments, the output pads included in the first pad region are all located in a first pad column.

[0068] In some embodiments, at least a portion of the at least one data pad and the address pad are located in a first pad column;

[0069] In the first pad column, the arrangement direction of the data pads, the address pads, the power pads and the output pads is the same as the cascade direction of the multiple pad units in the pad unit column;

[0070] In the second pad column, the arrangement direction of the ground pads, the data pads, and the relay pads is the same as the cascade direction of the plurality of pad units in the pad unit column;

[0071] One end of the first sub-segment is electrically connected to the data pad located in the second pad column, and the other end of the first sub-segment is electrically connected to the data pad located in the first pad column;

[0072] The orthographic projection of the first sub-segment on the substrate is located between the orthographic projection of the second sub-segment on the substrate and the orthographic projection of the main body on the substrate.

[0073] In some embodiments, the trace is disposed on the same layer as the first pad;

[0074] At least a portion of the at least one power pad is located in the second pad column;

[0075] In the second pad column, the arrangement direction of the ground pads, the data pads, the relay pads, and the power pads is the same as the cascade direction of the multiple pad units in the pad unit column;

[0076] One end of the third sub-segment is electrically connected to the power pad located in the second pad column, and the other end of the third sub-segment is electrically connected to the power pad located in the first pad column;

[0077] The orthographic projection of the second subsegment of the two first pad areas cascaded in the electrical connection pad unit column on the substrate is located between the orthographic projection of the first subsegment on the substrate and the orthographic projection of the third subsegment of the two first pad areas cascaded in the electrical connection pad unit column on the substrate.

[0078] In some embodiments, in the plurality of traces electrically connected to the two first pad areas cascaded in the pad unit column, the arrangement direction of the first sub-segment, the second sub-segment, and the third sub-segment in the first direction is the same as the cascade direction of the plurality of pad units in the pad unit column;

[0079] Among the multiple traces electrically connected to the two first pad areas cascaded in the two pad unit columns, the second data signal line, the second sub-segment and the third sub-segment are arranged in sequence in a direction from the binding area to the functional area.

[0080] In some embodiments, the at least one data pad includes: a data input pad and a data output pad; the data input pad is located in a first pad column, and the data output pad is located in a second pad column;

[0081] In each pad unit column, the data output pad of the first pad area of ​​the i-th level is electrically connected to the first portion of the first subsegment, and the data output pad of the first pad area of ​​the i-th level is electrically connected to the data input pad of the first pad area of ​​the (i+1)-th level through the first subsegment; wherein i is a positive integer;

[0082] In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data output pad of the last first pad area in a pad unit column, and the other end of the second data signal line is electrically connected to the data input pad of the first first pad area in a pad unit column.

[0083] In some embodiments, the at least one data pad includes: a data input pad and a data output pad; the data output pad is located in a first pad column, and the data input pad is located in a second pad column;

[0084] In each pad unit column, the data input pad of the first pad area of ​​the i-th level is electrically connected to the first portion of the first sub-segment, and the data input pad of the first pad area of ​​the i-th level is electrically connected to the data output pad of the first pad area of ​​the (i+1)-th level through the first sub-segment; wherein i is a positive integer;

[0085] In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data input pad of the last first pad area in a pad unit column, and the other end of the second data signal line is electrically connected to the data output pad of the first first pad area in a pad unit column.

[0086] In some embodiments, the at least one power pad includes: a first power pad and a second power pad; the first power pad is located in a first pad column, and the second power pad is located in a second pad column;

[0087] The second power supply pad of the i-th level first pad region is electrically connected to the first power supply pad of the (i+1)-th level first pad region through the third sub-segment.

[0088] In some embodiments, the first pad area includes two ground pads, the two ground pads are respectively located in a first pad column and a second pad column; in the first direction, the two ground pads are located in the same row;

[0089] In the first pad column, the ground pad is located on a side of the data pad facing away from the address pad;

[0090] In the second direction, the data input pads and the data output pads are located in the same row, the address pads and the relay pads are located in the same row, and the first power pads and the second power pads are located in the same row.

[0091] In some embodiments, the first pad region includes a plurality of output pads;

[0092] Some output pads are located in the second pad column;

[0093] In the second pad column, in the second direction, the output pad is located on a side of the second power pad away from the relay pad.

[0094] In some embodiments, the first pad area further includes: a first connecting lead; and the data input pad and the data output pad are electrically connected via the first connecting lead.

[0095] In some embodiments, the first power pad and the second power pad in the first pad region are not electrically connected via a trace.

[0096] In some embodiments, the first pad area further includes: a second connecting lead; and the first power pad and the second power pad are electrically connected via the second connecting lead.

[0097] In some embodiments, the second voltage line includes a third sub-segment; and the power pads of two adjacent pad unit columns and cascaded in the first pad region are electrically connected via the third sub-segment.

[0098] In some embodiments, the binding region includes a plurality of binding electrodes;

[0099] In adjacent pad unit columns electrically connected through the third sub-segment, the power pads in the first-level first pad area of ​​one pad unit column and the power pads in the last-level first pad area of ​​another pad unit column are electrically connected to the binding electrodes through wiring.

[0100] In some embodiments, the binding region includes a plurality of binding electrodes;

[0101] In adjacent pad unit columns electrically connected by the third sub-segment, the power pad of the first-level first pad area of ​​one pad unit column is electrically connected to the binding electrode through a routing, and the power pad of the last-level first pad area of ​​another pad unit column is not connected to the binding electrode.

[0102] In some embodiments, the first pad area further includes: a third connecting lead; two ends of the third connecting lead are electrically connected to different ground pads respectively.

[0103] In some embodiments, the first pad column and the second pad column include the same number of first pads.

[0104] An embodiment of the present disclosure provides a light-emitting substrate, which includes: a wiring substrate provided by an embodiment of the present disclosure, a driving chip bound one-to-one with the first pad area, and a light-emitting element bound one-to-one with the pad groups in multiple second pad areas.

[0105] In some embodiments, the light emitting element is a micro-sized inorganic light emitting diode.

[0106] A display device provided by an embodiment of the present disclosure includes the light-emitting substrate provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0108] FIG1 is a schematic structural diagram of a light-emitting substrate provided by the related art;

[0109] FIG2 is a schematic structural diagram of a wiring substrate provided in an embodiment of the present disclosure;

[0110] FIG3 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0111] FIG4 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0112] FIG5 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0113] FIG6 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0114] FIG7 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0115] FIG8 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0116] FIG9 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0117] FIG10 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0118] FIG11 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0119] FIG12 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0120] FIG13 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0121] FIG14 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0122] FIG15 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0123] FIG16 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0124] FIG17 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0125] FIG18 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0126] FIG19 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0127] FIG20 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0128] FIG21 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0129] FIG22 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0130] FIG23 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0131] FIG24 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0132] FIG25 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0133] FIG26 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0134] FIG27 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0135] FIG28 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0136] FIG29 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0137] FIG30 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0138] FIG31 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0139] FIG32 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0140] FIG33 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0141] FIG34 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0142] FIG35 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0143] FIG36 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0144] FIG37 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0145] FIG38 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0146] FIG39 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0147] FIG40 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0148] FIG41 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0149] FIG42 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0150] FIG43 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0151] FIG44 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0152] FIG45 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0153] FIG46 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0154] FIG47 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0155] FIG48 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0156] FIG49 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0157] FIG50 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0158] FIG51 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0159] FIG52 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0160] FIG53 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0161] FIG54 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0162] FIG55 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0163] FIG56 is a schematic structural diagram of another wiring substrate provided by an embodiment of the present disclosure;

[0164] FIG57 is a schematic structural diagram of another light-emitting substrate provided in an embodiment of the present disclosure;

[0165] Figure 58 is a structural schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0166] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0167] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0168] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0169] The present disclosure provides a wiring substrate, as shown in FIG3 and FIG4 , which includes:

[0170] A substrate 1 includes a functional area 101 and a binding area 102 located on one side of the functional area 101 in a first direction Y;

[0171] A plurality of pad unit columns 2 are located on one side of the substrate 1 in the functional area 101; at least one of the plurality of pad unit columns 2 includes a plurality of pad units 3 cascaded along a first direction Y; at least one of the plurality of pad units 3 includes: a first pad area 301; the first pad area 301 includes: a plurality of first pads 4, the plurality of first pads 4 including at least one data pad C and at least one ground pad GND;

[0172] Multiple routing lines 5; multiple routing lines 5 are electrically connected to multiple pad units 3; multiple routing lines 5 include: multiple data signal lines DA and multiple ground signal lines gnd; multiple data signal lines DA include: multiple first data signal lines DA1; the first data signal line DA1 is electrically connected to the data pads C of multiple first pad areas 301 in a column of pad unit columns 2, and the ground signal line gnd is electrically connected to the ground pads GND of two first pad areas 301 located in adjacent pad unit columns 2 and cascaded.

[0173] In the wiring substrate provided by the embodiment of the present disclosure, the data pads of two first pad areas located in adjacent pad unit columns and cascaded are electrically connected through the same ground signal line, which can reduce the number of ground signal lines, thereby saving wiring space and reducing the wiring difficulty.

[0174] In some embodiments, as shown in FIG4 , a plurality of pad unit columns 2 are arranged along a second direction X and extend along a first direction Y, and the second direction X intersects the first direction Y. FIG4 takes the second direction X and the first direction Y as perpendicular to each other as an example for illustration; each of the plurality of pad unit columns 2 includes a plurality of pad units 3 cascaded along the first direction Y; each of the plurality of pad units 3 includes a first pad area 301.

[0175] In some embodiments, multiple traces are arranged on the same layer of a functional area.

[0176] In some embodiments, as shown in FIG3 and FIG4 , the pad unit 3 further includes: at least one second pad area 302 ; the second pad area 302 is electrically connected to the first pad area 301 ; as shown in FIG3 , the second pad area 302 includes at least one pad group 3021 .

[0177] In specific implementation, the wiring substrate provided by the embodiment of the present disclosure can be applied to a light-emitting substrate, each pad group is bound to a light-emitting device, and the multiple first pads included in the first pad area are bound to the pins of a driver chip (for example, an integrated circuit core with a size of hundreds of microns), so that the light-emitting device can be driven to emit light under the control of the driver chip. For example, a driver chip can control the light-emitting devices bound and connected in a corresponding second pad area to emit light. The area occupied by multiple pads bound to a driver chip is the first pad area, and the area occupied by multiple pad groups and the enclosed area is the second pad area.

[0178] It is understood that an insulating layer is formed on the side of the trace 5 away from the substrate 1, and the insulating layer is used to isolate the trace 5 from water and oxygen. The insulating layer may include multiple vias, and the surface of a portion of the trace 5 is exposed by the vias, and the corresponding area constitutes a pad (including any one of the first pad 4, the positive pad 30211, and the negative pad 30212).

[0179] In some embodiments, as shown in Figures 3 to 6, the ground signal line gnd includes at least a portion located between two adjacent and cascaded pad unit columns 2. This makes it easier to electrically connect the ground pads GND of two adjacent and cascaded first pad regions 301 located in two adjacent pad unit columns 2 via the ground signal line gnd.

[0180] In some embodiments, as shown in Figures 3 to 6 , in two adjacent and cascaded pad unit columns 2 in the second direction X, no pad unit 3 is interposed between at least a portion of the ground pads GND in one pad unit column 2 and at least a portion of the ground pads GND in the other pad unit column 2. The second direction X intersects the first direction Y, and Figures 3 to 6 illustrate this by taking the second direction X and the first direction Y as being perpendicular to each other as an example.

[0181] In some embodiments, as shown in FIG. 3 to FIG. 5 , the ground pads of the plurality of first pad regions in one pad unit column are mirrored with the ground pads of the plurality of first pad regions in an adjacent pad unit column.

[0182] In some embodiments, as shown in FIG3 to FIG5 , the ground pads GND of the plurality of first pad areas 301 in one pad unit column 2 are adjacent to the ground pads GND of the plurality of first pad areas 301 in an adjacent pad unit column 2. Thus, the ground pads GND of the two adjacent columns can be directly electrically connected via the ground signal line gnd, making it easier to electrically connect the ground pads GND of two cascaded first pad areas 301 in two adjacent pad unit columns 2 via the ground signal line gnd, thereby reducing wiring difficulty.

[0183] In some embodiments, as shown in FIG3 to FIG6 , the multiple first pads 4 further include: an address pad Di, a relay pad Do, and at least one power pad VDD;

[0184] The routing line 5 further includes: a plurality of address signal lines D, and a plurality of second voltage lines vdd;

[0185] The address signal line D is electrically connected to the address pad Di and the relay pad Do, and the second voltage line vdd is electrically connected to the power pad VDD.

[0186] In a specific implementation, when the wiring substrate is applied to a light-emitting substrate, that is, the driver chip is bound to the first pad included in the first pad area, the address pad Di can be used to receive an address signal, configure the address information of the driver chip according to the address signal, and generate a relay signal; the relay signal can serve as the address signal for the next-level micro driver chip; the data pad C is used to receive drive data, which includes drive information and address verification information. When the address verification information matches the address information, a drive current corresponding to the light-emitting device electrically connected to the driver chip is generated according to the drive information, and the output pad of the driver chip is controlled to form an electrical path with the corresponding light-emitting device, and the drive current flows in the electrical path; the address pad Di can receive an address signal and configure the address information according to the address signal. The driver chip generates a relay signal based on the received address information, which is output by the relay pad Do to the address pad Di of the next-level first pad area as the address signal of the next-level first pad area. The power pad VDD input voltage allows the driver chip to operate normally. The data signal line can also be used to transmit test signals for testing whether the light-emitting devices in the second pad areas electrically connected to the first pad areas are abnormal; that is, the data signal line is configured to transmit test signals and drive data signals in a time-sharing manner.

[0187] In the wiring substrate provided by the embodiments of the present disclosure, the data signal line and the second voltage line respectively use different routings, which can simplify the circuit structure in the area where the first pad area is located. There is no need to set a power regulation circuit (the power regulation circuit is used to generate a driving voltage based on the DC component of the power supply signal and generate driving data based on the modulation component of the power supply signal) in the area where the first pad area is located, thereby helping to reduce the area of ​​the area where the first pad area is located. In addition, this setting method can also simplify the external circuit structure, avoiding the need to set a modulation circuit that modulates the driving voltage and driving data into power line carrier communication, and can also reduce the quality requirements for the driving voltage.

[0188] In some embodiments, as shown in Figures 3 to 5, in two first pad areas 301 adjacent to and respectively located in cascaded two pad unit columns 2, one address pad Di is disposed adjacent to a relay pad Do of the other first pad area 301. Thus, in two adjacent and cascaded pad unit columns 2, the two cascaded first pad areas 301 can be directly electrically connected via an address signal line D, which can reduce wiring difficulty.

[0189] In some embodiments, as shown in Figures 3 to 6, the address pads Di and relay pads Do of multiple first pad areas 301 in a column of pad unit columns 2 are rotated 180° and mirrored with the address pads Di and relay pads Do of multiple first pad areas 301 in an adjacent pad unit column 2.

[0190] In the wiring substrate provided by the embodiments of the present disclosure, the arrangement of the address pads and relay pads in two adjacent and cascaded pad unit columns is different, and accordingly, the positions of the wiring electrically connected to the two pad unit columns are also different. The embodiments of the present disclosure are equivalent to changing the arrangement of the address pads and relay pads in the first pad area of ​​one of the two adjacent and cascaded pad unit columns, which can change the wiring arrangement position of the wiring substrate, making it easier to achieve electrical connection of the two cascaded first pad areas through address signal lines, and can reduce the difficulty of wiring.

[0191] In some embodiments, the wiring substrate includes 2N pad unit columns, where N is a positive integer, and the wiring substrate includes N cascade loops, each of which includes two cascaded pad unit columns.

[0192] In some embodiments, as shown in FIG. 4 , in two adjacent pad unit columns 2 , the cascading directions of the plurality of pad units 3 are opposite.

[0193] In the wiring substrate provided by the embodiment of the present disclosure, the cascade directions of the multiple pad units in two adjacent pad unit columns are opposite, so that the cascade between the two pad units farthest from the binding area in the two pad unit columns in a cascade loop can be achieved, which facilitates the electrical connection of the ground pads in the two first pad areas located in adjacent pad unit columns and cascaded through the address signal line, thereby reducing the difficulty of wiring.

[0194] It should be noted that the cascade of multiple pad units specifically refers to the cascade of the first pad areas of multiple pad units. As shown in Figure 4, taking each pad unit column 2 including two pad units 3 as an example, the 2nth pad unit column 2 and the 2n-1th pad unit column 2 form a cascade loop, where n is a positive integer not greater than N; the four cascaded first pad areas 301 are cascaded in the order of A1, A2, A3, and A4. That is, in the 2nth pad unit column 2, A1 is the first-level first pad area 301 of the multiple first pad areas 301 cascaded in the column, A2 is the last-level first pad area 301 of the multiple first pad areas 301 cascaded in the column, and in the 2n-1th pad unit column 2, A3 is the first-level first pad area 301 of the multiple first pad areas 301 cascaded in the column, and A4 is the last-level first pad area 301 of the multiple first pad areas 301 cascaded in the column.

[0195] It should be noted that Figure 4 only shows one cascade loop, that is, only shows two adjacent pad unit columns 2. In specific implementation, the number of pad unit columns included in the wiring substrate can be set according to actual needs.

[0196] In some embodiments, as shown in Figures 3 to 6, the arrangement of the multiple first pads 4 after the first pad area 301 in the 2nth pad unit column 2 is rotated 180° is the same as the arrangement of the multiple first pads 4 in the first pad area 301 in the (2n-1)th pad unit column 2.

[0197] That is, in the wiring substrate provided by the embodiment of the present disclosure, the arrangement of the pads in the first pad area of ​​the odd-numbered pad unit column is different from the arrangement of the pads in the first pad area of ​​the even-numbered pad unit column. Accordingly, the positions of the traces corresponding to the even-numbered columns are different from the positions of the traces corresponding to the odd-numbered columns. The embodiment of the present disclosure is equivalent to changing the arrangement of the pads in the first pad area of ​​the even-numbered pad unit column, which can change the trace arrangement position of the wiring substrate, making it easier to achieve trace cascading of two adjacent pad unit columns.

[0198] In some embodiments, as shown in FIG. 3 to FIG. 6 , the ground signal line gnd is electrically connected to the ground pads GND of the plurality of first pad regions 301 in the pad unit column 2 .

[0199] The ground signal line gnd includes a trunk portion gnd- 1 extending along the first direction Y. The trunk portion gnd- 1 is located between two pad unit columns 2 electrically connected to the ground signal line gnd.

[0200] In some embodiments, as shown in FIG. 2 to FIG. 6 , at least one data pad C and at least one ground pad GND are located in the same column in the first direction Y; and at least one data pad C and at least one ground pad GND include a portion located at an edge of the first pad region 301 close to the trunk gnd-1;

[0201] The ground signal line gnd also includes a branch gnd-2 extending along the second direction X. The orthographic projection of the branch gnd-2 on the substrate 1 is located between the orthographic projection of the main body gnd-1 on the substrate 1 and the orthographic projection of the pad unit column 2 on the substrate 1. The main body gnd-1 is connected to the ground pad GND included in the second pad column through the branch gnd-2.

[0202] In the wiring substrate provided by the embodiment of the present disclosure, at least one data pad and at least one ground pad are located in the same column in the first direction, and at least one data pad and at least one ground pad include a portion located in the edge of the first pad area close to the main body. This facilitates the connection of the data pads of the two pad unit columns of a cascade loop through the second data signal line. Moreover, since the arrangement of the various first pads after the first pad area in the 2nth pad unit column is rotated 180° is the same as the arrangement of the various first pads in the first pad area in the (2n-1)th pad unit column, when the main body is located between the two pad unit columns electrically connected to the second data signal line, the two cascaded pad unit columns both include a ground pad that is closer to the main body, which facilitates the electrical connection of the ground pad to the main body through the branch, and can simplify the wiring difficulty while reasonably utilizing the wiring space.

[0203] In some embodiments, as shown in FIG3 to FIG6 , the first data signal line DA1 includes a plurality of first sub-segments DA1 - 1 ; the first sub-segments DA1 - 1 are electrically connected to the data pads C of the two cascaded first pad areas 301 in the pad unit column 2 ;

[0204] The orthographic projection of the first sub-segment DA1 - 1 on the substrate 1 is located on a side of the orthographic projection of the main portion gnd- 1 on the substrate 1 facing the orthographic projection of the pad unit column 2 on the substrate 1 .

[0205] In the wiring substrate provided by the embodiment of the present disclosure, the cascaded pad units in the pad unit column are electrically connected through the first sub-segment. Since the cascade directions of two adjacent pad unit columns are opposite, in a cascade loop, the two pad units farthest from the binding area in the two pad unit columns are cascaded, and the orthographic projection of the first sub-segment on the substrate is located on the side where the orthographic projection of the main body on the substrate faces the orthographic projection of the pad unit column on the substrate, which can avoid interference between the data signal line and the ground signal line.

[0206] As shown in FIG1 , a light-emitting substrate in the related art uses a signal line to transmit a specific function from a binding area 102 to the driver IC closest to the flexible printed circuit board (FPC) in the first column. The signal is then transmitted sequentially along the column direction to the driver IC farthest from the FPC in the first column. The signal is then transmitted back to the FPC in the binding area 102 via a feedback signal line FB1. After being relayed by the FPC, the signal is transmitted to the driver IC closest to the FPC in the second column. The signal is then transmitted sequentially along the column direction to the driver IC farthest from the FPC in the first column. Finally, the signal is transmitted back to the FPC in the binding area 102 via a feedback signal line FB2. These two columns of driver ICs form a loop. Because the feedback signal line FB must be routed from the farthest end of a column of driver ICs to the binding area, the signal is subject to time constraints during transmission due to its width (i.e., its resistance). This results in a delay in the time it takes each driver IC in the loop to receive the signal, which in turn reduces the frequency of signal transmission.

[0207] In some embodiments, as shown in FIG. 2 to FIG. 6 , the plurality of data signal lines DA further include: a plurality of second data signal lines DA2 , which are electrically connected to the data pads C of two cascaded first pad areas 301 located in adjacent pad unit columns 2 .

[0208] In the wiring substrate provided by the embodiments of the present disclosure, data pads in two cascaded first pad areas located in adjacent pad unit columns are electrically connected via a second data signal line. This prevents the data signals output by the data pads in the first pad area farthest from the binding area from being transmitted back to the binding area via a long routing line. This can reduce data signal transmission time, increase data signal transmission frequency, and avoid data signal transmission delays. Furthermore, this can save wiring space, facilitate increasing the line width of other routing lines, and reduce routing resistance and voltage drop.

[0209] Furthermore, in the wiring substrate provided by the embodiment of the present disclosure, the cascade directions of the multiple pad units in two adjacent pad unit columns are opposite, so that the cascade between the two pad units in the two pad unit columns farthest from the binding area in a cascade loop can be achieved, which facilitates the electrical connection of the data pads of the two first pad areas located in adjacent pad unit columns and cascaded through the second data signal line, and can avoid the data signals output by the data pads in the first pad area farthest from the binding area from being transmitted back to the binding area through a routing line with a longer length while reducing the wiring difficulty.

[0210] In some embodiments, as shown in Figure 2, when the multiple data signal lines DA include multiple second data signal lines DA2, the ground pads GND of two cascaded first pad areas 301 located in adjacent pad unit columns 2 may be electrically connected to different ground signal lines gnd respectively.

[0211] In some embodiments, as shown in FIG. 2 to FIG. 6 , the trunk portion gnd- 1 is located between two pad unit columns 2 electrically connected to the second data signal line DA2 ;

[0212] The orthographic projection of the second data signal line DA2 on the substrate 1 is located on a side of the orthographic projection of the trunk portion gnd- 1 on the substrate 1 away from the binding region 102 .

[0213] In the wiring substrate provided by the embodiment of the present disclosure, the cascaded pad units in the pad unit column are electrically connected through the first sub-segment. Since the cascade directions of two adjacent pad unit columns are opposite, in a cascade loop, the two pad units in the two pad unit columns that are farthest from the binding area are cascaded, and the data pads of the two first pad areas of adjacent pad unit columns and cascaded are electrically connected through the second data signal line. The orthographic projection of the first sub-segment on the substrate is located on the side where the orthographic projection of the main body on the substrate faces the orthographic projection of the pad unit column on the substrate, and the orthographic projection of the second data signal line on the substrate is located on the side where the orthographic projection of the main body on the substrate is far from the binding area, which can avoid interference between the data signal line and the ground signal line.

[0214] In some embodiments, the binding area includes a plurality of binding electrodes; and at least some of the traces are electrically connected to the binding electrodes.

[0215] In some embodiments, as shown in Figure 2, the first data signal line DA1 also includes a fourth sub-segment DA1-2; one end of the fourth sub-segment DA1-2 is electrically connected to the binding electrode (not shown) of the binding area 102, and the other end of the fourth sub-segment DA1-2 is electrically connected to the data pad C of the first pad area 301 closest to the binding area 102 in the pad unit column 2.

[0216] In some embodiments, as shown in Figures 3 to 6, two adjacent and cascaded pad unit columns 2 are electrically connected to the same trunk gnd-1. That is, the two pad unit columns 2 electrically connected to the second data signal line DA2 are electrically connected to the same trunk gnd-1. This further saves wiring space, increases the width of the trace between the two pad unit columns, and thus reduces trace resistance and voltage drop.

[0217] Alternatively, in some embodiments, as shown in FIG11 , two adjacent and cascaded pad unit columns 2 are electrically connected to different main body gnd-1, and the branch gnd-2 is electrically connected to the ground pads GND of two cascaded first pad areas 301 located in adjacent pad unit columns 2, respectively.

[0218] In some embodiments, as shown in FIG. 2 to FIG. 11 , the first pad 4 further includes: at least one output pad S;

[0219] The plurality of traces 5 further include: a plurality of first voltage lines Vled extending along the first direction Y;

[0220] The first voltage line Vled is electrically connected to the input ends of the plurality of second pad regions 302 in the pad unit column 2, and the output ends of the second pad regions 302 are electrically connected to the output pad S;

[0221] The first voltage line Vled and the trunk portion gnd- 1 electrically connected to the same pad unit column 2 are respectively located on both sides of the pad unit column 2 .

[0222] In some embodiments, as shown in FIG5 , at least some adjacent pad unit columns 2 are electrically connected to the same first voltage line Vled, thereby further saving wiring space, increasing the width of the trace between two pad unit columns, and thus reducing trace resistance and voltage drop.

[0223] In a specific implementation, two pad unit columns electrically connected to the same first voltage line are respectively located in two adjacent cascade loops, that is, the two pad unit columns are not electrically connected through the second data signal line.

[0224] In some embodiments, as shown in Figures 2, 4-6, and 8-11, the number of second pad regions 302 is the same as the number of output pads S, i.e., one output pad S is electrically connected to one second pad region 302. Figure 2 illustrates an example in which a first pad 4 includes four output pads S, and a pad unit 3 includes four second pad regions 302. The four output pads S are S1, S2, S3, and S4, respectively. S1, S2, S3, and S4 are electrically connected to the output ends of the four second pad regions 302, respectively.

[0225] In some embodiments, as shown in FIG3 , the second pad region 302 includes at least one pad group 3021, and each pad group 3021 includes a positive pad 30211 and a negative pad 30212. In a specific implementation, the positive pad is electrically connected to the anode of the light-emitting device, and the negative pad is electrically connected to the cathode of the light-emitting device;

[0226] In some embodiments, as shown in FIG3 , the second pad region 302 includes multiple pad groups 3021; ​​the multiple pad groups 3021 are connected in series; the multiple traces 5 further include a fourth connecting lead 504; and each pad group 3021 includes a positive pad 30211 and a negative pad 30212. Of the two connected pad groups 3021, the positive pad 30211 of one pad group 3021 is connected to the negative pad 30212 of the other pad group 3021 via the fourth connecting lead 504. FIG3 illustrates an example in which the second pad region 302 includes four pad groups 3021 connected in series, where the four pad groups 3021 are B1, B2, B3, and B4. The negative electrode pad 30212 of the B1 pad group 3021 is connected to the positive electrode pad 30211 of the B2 pad group 3021, the negative electrode pad 30212 of the B2 pad group 3021 is connected to the positive electrode pad 30211 of the B3 pad group 3021, and the negative electrode pad 30212 of the B3 pad group 3021 is connected to the positive electrode pad 30211 of the B4 pad group 3021. It should be noted that the input end of the second pad area refers to the positive electrode pad of one of the pad groups included in the second pad area. As shown in FIG3 , when the plurality of pad groups 3021 included in the second pad area 302 are connected in series, the positive pad 30211 of the first second pad group 3021 in the plurality of series-connected second pad groups 3021, i.e., the B1 pad group 3021 in FIG4 , is connected to the first voltage line Vled, and the negative pad 30212 of the last second pad group 3021 in the plurality of series-connected second pad groups 3021, i.e., the B4 pad group 3021 in FIG3 , is connected to the output pad S of the first pad area 301. The negative pad 30212 of the last second pad group 3021 in the plurality of series-connected second pad groups 3021 is connected to the output pad S via the fifth connection lead 505.

[0227] Of course, in specific implementation, multiple pad groups can also be connected in parallel.

[0228] In some embodiments, the pad group, the first pad, and the plurality of traces are disposed on the same layer. That is, the traces, the positive pad, the negative pad, and the plurality of first pads are disposed on the same layer. The traces, the positive pad, the negative pad, and the first pads are made of the same material (for example, their main material all includes copper) or have the same structure. In a specific implementation, a conductive layer can be formed on one side of the substrate, and then the conductive layer is patterned to form patterns for the traces and the pads.

[0229] In some embodiments, the wiring substrate further includes a first insulating layer located on a side of the traces, positive electrode pads, negative electrode pads, and the plurality of first pads facing away from the substrate. The first insulating layer has multiple openings. It is understood that, in the patterned conductive layer, the portions exposed by the insulating layer openings are the pads, and the areas covered by the insulating layer are the traces. In other words, the traces are integrally connected to the pads.

[0230] In some embodiments, as shown in FIG. 2 , FIG. 4 to FIG. 6 , and FIG. 8 to FIG. 11 , the address signal line D includes a plurality of second sub-segments D- 1 ;

[0231] One end of the second sub-segment D- 1 is electrically connected to the relay pad Do of a first pad area 301 , and the other end of the second sub-segment D- 1 is electrically connected to the address pad Di of the next first pad area 301 of the first pad area 301 .

[0232] In some embodiments, as shown in FIG. 2 , FIG. 4 to FIG. 6 , and FIG. 8 to FIG. 11 , the second voltage line vdd includes a plurality of third sub-segments vdd-1;

[0233] The third sub-segment vdd-1 is electrically connected to the power pads VDD of the two first pad regions 301 in cascade.

[0234] In some embodiments, as shown in FIG. 2 , FIG. 4 to FIG. 5 , and FIG. 11 , in a pad unit column 2 , the power pads VDD of the two cascaded first pad areas 301 are electrically connected via the third sub-segment vdd-1;

[0235] The power pads VDD of two cascaded first pad areas 301 that are respectively located in adjacent pad unit columns 2 are not electrically connected via the third sub-segment vdd-1.

[0236] Alternatively, as shown in FIG. 6 and FIG. 12 to FIG. 16 , the power pads VDD of two cascaded first pad areas 301 , which are respectively located in adjacent pad unit columns 2 , are electrically connected via the third sub-segment vdd- 1 .

[0237] In some embodiments, as shown in Figures 2, 4 to 6, and 8 to 16, the relay pad Do and the at least one power pad VDD are located in different columns in the first direction Y. This reduces the wiring difficulty of the second and third sub-segments and helps avoid interference between the two.

[0238] In some embodiments, as shown in Figures 2, 4 to 6, and 8 to 16, the address signal line D further includes a fifth sub-segment D-2; one end of the fifth sub-segment D-2 is electrically connected to the binding electrode (not shown) of the binding area 102, and the other end of the fifth sub-segment D-2 is electrically connected to the address pad Di or relay pad Do of the first pad area 301 closest to the binding area 102 in the pad unit column 2.

[0239] In specific implementation, as shown in Figures 2, 4, 6, 8 to 16, in two pad unit columns 2 of a cascade loop, the address pad Di of the first pad area 301 (A1) in the first-level pad unit 3 is electrically connected to the binding electrode (not shown) of the binding area 102 through the fifth sub-segment D-2, and the relay pad Do of the first pad area 301 (A4) in the last-level pad unit 3 is electrically connected to the binding electrode (not shown) of the binding area 102 through the fifth sub-segment D-2.

[0240] In some embodiments, as shown in Figures 2, 4 to 6, and 8 to 16, the second voltage line vdd also includes a sixth sub-segment vdd-2; one end of the sixth sub-segment vdd-2 is electrically connected to the binding electrode (not shown) of the binding area 102, and the other end of the sixth sub-segment vdd-2 is electrically connected to the power pad VDD of the first pad area 301 closest to the binding area 102 in the pad unit column 2.

[0241] In some embodiments, as shown in FIG. 2 , FIG. 4 - FIG. 5 , and FIG. 11 , in each pad unit column 2 , the power pad VDD of the first pad area 301 closest to the bonding area 102 is electrically connected to the bonding electrode (not shown) through the sixth subsegment vdd- 2 .

[0242] In some embodiments, as shown in Figures 6 and 12 to 13, in adjacent pad unit columns 2 electrically connected through the third sub-segment vdd-1, the power pad VDD of the first-level first pad area 301 of one pad unit column 2 and the power pad VDD of the last-level first pad area 301 of another pad unit column are both electrically connected to the binding electrode (not shown) through the routing, i.e., the sixth sub-segment vdd-2.

[0243] Alternatively, in some embodiments, as shown in Figures 14 to 16, in adjacent pad unit columns 2 electrically connected through the third sub-segment vdd-1, the power pad VDD of the first-level first pad area 301 of one pad unit column 2 and the power pad VDD of the last-level first pad area 301 of another pad unit column are not connected to the binding electrode (not shown) through the routing, i.e., the sixth sub-segment vdd-2.

[0244] In some embodiments, as shown in FIG. 2 , FIG. 4 to FIG. 6 , and FIG. 8 to FIG. 16 , the first pad area 301 includes a plurality of first pads 4 arranged in an M×2 manner as a first pad column 3011 and a second pad column 3012 ; M is a positive integer;

[0245] In the second direction X, the orthographic projection of the second pad column 3012 on the substrate 1 is located between the orthographic projection of the first pad column 3011 on the substrate 1 and the orthographic projection of the trunk portion gnd- 1 on the substrate 1 .

[0246] In a specific implementation, since the arrangement of the various first pads in the first pad area in the 2nth pad unit column after rotating 180° is the same as the arrangement of the various first pads in the first pad area in the (2n-1)th pad unit column, the first pad column in the first pad area in the 2nth pad unit column after rotating 180° is the same as the first pad column in the first pad area in the (2n-1)th pad unit column, and the second pad column in the first pad area in the 2nth pad unit column after rotating 180° is the same as the second pad column in the first pad area in the (2n-1)th pad unit column. For two pad unit columns in a cascade loop, the main body is located between the two pad unit columns, and the first voltage line and the main body are located on either side of the pad unit column, i.e., the second pad column is closer to the main body and the first pad column is closer to the first voltage line.

[0247] It should be noted that the multiple first pads included in the first pad area are arranged into a first pad column and a second pad column in an M*2 manner, which means that the first pad column and the second pad column include the same number of first pads, both M.

[0248] In the wiring substrate provided by the embodiment of the present disclosure, the first pad column and the second pad column include the same number of first pads, and the multiple first pads in the first pad area are arranged regularly and evenly, which can improve the thickness uniformity of the first pad area, thereby improving the supporting effect of the first pad area on the driver chip, which is conducive to achieving the center of gravity balance after the driver chip is bound to the first pad.

[0249] In a specific implementation, each first pad 4 may be located in the first pad column 3011 or the second pad column 3012, as shown in Figures 2, 4-6, and 8-16. Alternatively, a specific type of first pad 4 may be located partially in the first pad column 3011 and partially in the second pad column 3012, as shown in Figure 7. In Figure 7, taking the example of a first pad region 301 including a data pad C, a ground pad GND, and a power pad VDD, the data pad C is located partially in the first pad column 3011 and partially in the second pad column 3012, the ground pad GND is located partially in the first pad column 3011 and partially in the second pad column 3012, and the power pad VDD is located partially in the first pad column 3011 and partially in the second pad column 3012. It will be appreciated that in this case, the ground pad GND, the power pad VDD, and the data pad C are larger than those of other types of first pads.

[0250] In some embodiments, as shown in Figures 2, 4 to 6, and 8 to 16, at least a portion of at least one data pad C, the relay pad Do, and at least a portion of at least one ground pad GND are located in the second pad column 3012. Because the second pad column 3012 is closer to the main portion gnd-1, the location of at least a portion of the at least one ground pad GND in the second pad column 3012 facilitates connection of the ground pad GND to the main portion gnd-1 through the branch gnd-.

[0251] It should be noted that, in FIG. 2 , FIG. 4 to FIG. 6 , and FIG. 8 to FIG. 16 , the example in which the entire area of ​​at least one data pad C and at least one ground pad GND is located in the second pad column 3012 is used for illustration.

[0252] In some embodiments, as shown in Figures 2, 4 to 6, and 8 to 16, at least a portion of at least one output pad S and at least one power pad VDD are located in first pad column 3011. Because first pad column 3011 is close to first voltage line Vled, second pad region 302 is electrically connected to both output pad S and first voltage line Vled. At least one output pad S is located in first pad column 3011, which is closer to first voltage line Vled. This reduces the difficulty of electrical connection between second pad region 302, output pad S, and first voltage line Vled.

[0253] It should be noted that, in FIG. 2 , FIG. 4 to FIG. 6 , and FIG. 8 to FIG. 16 , an example is given in which the entire area of ​​at least one power pad VDD is located in the first pad column 3011 .

[0254] In some embodiments, as shown in FIG. 2 , FIG. 4 , FIG. 8 , FIG. 9 , and FIG. 11 to FIG. 15 , the address pad Di is located in the second pad column 3012 ; that is, the address pad Di and the relay pad Do are both located in the second pad column 3012 ;

[0255] In the second pad column 3012, the arrangement direction of the address pads Di and the relay pads Do is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2; for example, in the 2n-1th pad unit column 2, the cascade direction of the multiple pad units 3 (i.e., the arrangement direction in the order of A3, A4) is the direction from the functional area 101 to the binding area 102, and in each first pad area 3, the arrangement direction of the address pads Di and the relay pads Do is also the direction from the functional area 101 to the binding area 102; in the 2nth pad unit column 2, the cascade direction of the multiple pad units 3 (i.e., the arrangement direction in the order of A1, A2) is the direction from the binding area 102 to the functional area 101, and in each first pad area 3, the arrangement direction of the address pads Di and the relay pads Do is also the direction from the binding area 102 to the functional area 101;

[0256] In the second pad column 3012 , in the first direction Y, the orthographic projection of the ground pad GND on the substrate 1 is located between the orthographic projection of the address pad Di on the substrate 1 and the orthographic projection of the relay pad Do on the substrate 1 .

[0257] In the wiring substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 4, 8, 9, 11 to 15, the orthographic projection of the ground pad GND on the substrate 1 is located between the orthographic projection of the address pad Di on the substrate 1 and the orthographic projection of the relay pad Do on the substrate 1, that is, the arrangement direction of the address pad Di, the ground pad GND, and the relay pad Do is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2; in the pad unit column 2, in the first direction Y, the relay pad Do of the i-th first pad area 301 and the address pad Di of the (i+1)-th first pad area 301 are located between the ground pad GND of the i-th first pad area 301 and the (i+1)-th Between the ground pad GND of the (i+1)-th level first pad area 301, since one end of the second sub-segment D-1 is electrically connected to the relay pad Do of the i-th level first pad area 301, and the other end of the second sub-segment D-1 is electrically connected to the address pad Di of the (i+1)-th level first pad area 301, in this way, in the first direction Y, in a pad unit column 2, the orthographic projection of the second sub-segment D-1 on the substrate 1 is located between the orthographic projections of the two branches gnd-2 corresponding to the two cascaded first pad areas 301 on the substrate 1, which can simplify the wiring difficulty of the trace, is conducive to the rational use of the wiring space to ensure the line width of the trace, and avoids interference between different types of traces.

[0258] In some embodiments, as shown in FIG. 2 , FIG. 4 , FIG. 8 , FIG. 9 , FIG. 11 to FIG. 15 , and FIG. 17 to FIG. 22 , at least one data pad C includes: a data input pad Ci and a data output pad Co; in each pad unit column 2 , of the two cascaded first pad areas 301 , the data output pad Co of one first pad area 301 is electrically connected to the data input pad Ci of the other first pad area 301 through a first sub-segment DA1-1;

[0259] The data input pad Ci and the data output pad Co are located in the second pad column 3012 .

[0260] In some embodiments, as shown in FIG2 , FIG4 , FIG8 , FIG9 , and FIG11 to FIG15 , in each pad unit column 2 , the data output pad Co of the i-th level first pad region 301 is electrically connected to the data input pad Ci of the (i+1)-th level first pad region 301 through the first sub-segment DA1-1; wherein i is a positive integer;

[0261] In the adjacent pad unit column 2, one end of the second data signal line DA2 is electrically connected to the data output pad Co of the last-level first pad area 301 in the pad unit column 2, and the other end of the second data signal line DA2 is electrically connected to the data input pad Ci of the first-level first pad area 301 in the pad unit column 2;

[0262] The arrangement direction of the data input pad Ci and the data output pad Co is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2;

[0263] The orthographic projection of the address pad Di on substrate 1 is located between the orthographic projection of the data input pad Ci on substrate 1 and the orthographic projection of the ground pad GND on substrate 1, and the orthographic projection of the relay pad Do on substrate 1 is located between the orthographic projection of the data output pad Co on substrate 1 and the orthographic projection of the ground pad GND on substrate 1.

[0264] Alternatively, in some embodiments, as shown in FIG17 to FIG22 , in each pad unit column 2 , the data input pad Ci of the i-th level first pad region 301 is electrically connected to the data output pad Co of the (i+1)-th level first pad region 301 through the first sub-segment DA1-1; wherein i is a positive integer;

[0265] In the adjacent pad unit column 2, one end of the second data signal line DA2 is electrically connected to the data input pad Ci of the last-level first pad area 301 in the pad unit column 2, and the other end of the second data signal line DA2 is electrically connected to the data output pad Co of the first-level first pad area 301 in the pad unit column 2;

[0266] The arrangement direction of the data output pad Co and the data input pad Ci is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2;

[0267] The orthographic projection of the address pad Di on substrate 1 is located between the orthographic projection of the data output pad Co on substrate 1 and the orthographic projection of the ground pad GND on substrate 1, and the orthographic projection of the relay pad Do on substrate 1 is located between the orthographic projection of the data input pad Ci on substrate 1 and the orthographic projection of the ground pad GND on substrate 1.

[0268] That is, in a specific implementation, the positions of the data input pad Ci and the data output pad Co can be interchanged.

[0269] In some embodiments, as shown in Figures 2, 4, 8, 9, 11 to 15, and 17 to 22, the orthographic projection of the second sub-segment D-1 of the two cascaded first pad areas 301 in the electrically connected pad unit column 2 on the substrate 1 is located between the orthographic projection of the first sub-segment DA1-1 on the substrate 1 and the orthographic projection of the main body gnd-1 on the substrate 1.

[0270] In the wiring substrate provided by the embodiment of the present disclosure, the data pads include a data input pad Ci and a data output pad Co located in the second pad column, and the remaining first pads of the second pad column are located between the data input pad Ci and the data output pad Co, which is conducive to realizing the connection of the data pads of the cascaded first pad area through the first sub-segment, which can reduce the difficulty of wiring.

[0271] The wiring substrate provided by the embodiment of the present disclosure, as shown in Figures 2, 4, 8, 9, and 11 to 15, has data input pads Ci, address pads Di, ground pads GND, relay pads Do, and data output pads Co arranged in the same direction as the cascade direction of the plurality of pad units 3 in pad unit column 2. In pad unit column 2, in the first direction Y, the data output pads Co of the i-th level first pad area 301 and the data input pads Ci of the (i+1)-th level first pad area 301 are located at the i-th level first pad area 301. Between the relay pad Do and the address pad Di of the (i+1)th level first pad area 301, since the data output pad Co of the i-th level first pad area 301 is electrically connected to the data input pad Ci of the (i+1)-th level first pad area 301 through the first sub-segment DA1-1, in this way, in the first direction Y, in a pad unit column 2, the orthographic projections of the first sub-segment DA1-1 and the second sub-segment D-1 on the substrate 1 are located between the orthographic projections of the two branches gnd-2 corresponding to the two cascaded first pad areas 301 on the substrate 1. Alternatively, as shown in Figures 17 to 22, the arrangement direction of the data output pad Co, the address pad Di, the ground pad GND, the relay pad Do, and the data input pad Ci is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2. In the pad unit column 2, in the first direction Y, the data input pad Ci of the i-th level first pad area 301 and the data output pad Co of the (i+1)-th level first pad area 301, the relay pad Do located in the i-th level first pad area 301 and the (i+1)-th level first pad area 301 are arranged in the same direction. Since the data input pad Ci of the i-th first pad area 301 is electrically connected to the data output pad Co of the (i+1)-th first pad area 301 via the first subsegment DA1-1, in a pad unit column 2, in the first direction Y, the orthographic projections of the first subsegment DA1-1 and the second subsegment D-1 on substrate 1 are located between the orthographic projections of the two branches gnd-2 corresponding to the two cascaded first pad areas 301 on substrate 1. Therefore, the orthographic projections of the second subsegment D-1 on substrate 1 of the two cascaded first pad areas 301 in the electrically connected pad unit column 2 are located between the orthographic projections of the first subsegment DA1-1 on substrate 1 and the orthographic projections of the main body gnd-1 on substrate 1. This simplifies the routing of traces, saves routing space, and avoids interference between different types of traces.

[0272] In some embodiments, as shown in FIG. 2 , FIG. 4 , FIG. 8 , FIG. 9 , FIG. 11 to FIG. 15 , and FIG. 17 to FIG. 22 , the orthographic projection of the second data signal line DA2 on the substrate 1 is located on a side of the orthographic projection of the branch gnd- 2 on the substrate 1 away from the binding region 102 ;

[0273] The orthographic projection of the second subsegment D- 1 electrically connecting two adjacent pad unit columns 2 on the substrate 1 is located between the orthographic projection of the second data signal line DA2 on the substrate 1 and the orthographic projection of the branch gnd- 2 on the substrate 1 .

[0274] The wiring substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 4, 8, 9, 11 to 15, and 17 to 22, in the two first pad areas 3 of the two pad unit columns 2 of a cascade loop that are farthest from the binding area 102, the address pad Di and the relay pad Do electrically connected through the second sub-segment D-1 are located on the side of the ground pad GND away from the binding area 102, because the arrangement of the various first pads 4 after the first pad area 301 in the 2nth pad unit column 2 is rotated 180° is the same as the arrangement of the various first pads 4 in the first pad area 301 in the (2n-1)th pad unit column 2, in the two first pad areas 3 of the two pad unit columns 2 of a cascade loop that are farthest from the binding area 102, the data input pad Ci and the data output pad Co electrically connected through the second data signal line DA2 are both located at the position farthest from the binding area 102 in the second pad column 3012. Thus, it can be set that the second data signal line DA2 is connected between the area between the two pad unit columns 2 and the data input pad Ci and the data output pad Co, and the second sub-segment D-1 is connected between the area between the two pad unit columns 2 and the address pad Di and the relay pad Do. It can also be set that the positive projection of the second data signal line DA2 on the substrate 1 and the positive projection of the second sub-segment D-1 electrically connecting the two adjacent pad unit columns 2 on the substrate 1 are located on the side of the main body gnd-1 and the branch gnd-2 away from the binding area 102, and the positive projection of the second sub-segment D-1 electrically connecting the two adjacent pad unit columns 2 on the substrate 1 are located between the positive projection of the second data signal line DA2 on the substrate 1 and the positive projection of the branch gnd-2 on the substrate 1. The second sub-segment D-1, branch gnd-2 and main body gnd-1 of the second data signal line DA2 will not interfere with each other, which can reduce the wiring difficulty and save wiring space.

[0275] In some embodiments, as shown in Figures 2, 4, 8, 9, and 11 to 15, in two pad unit columns 2 of a cascade loop, the data input pads Ci of the first pad area 301 (A1) in the first-stage pad unit 3 are electrically connected to the binding electrode (not shown) of the binding area 102 via the fourth sub-segment DA1-2, and the data output pads Co of the first pad area 301 (A4) in the last-stage pad unit 3 are electrically connected to the binding electrode (not shown) of the binding area 102 via the fourth sub-segment DA1-2. Alternatively, in some embodiments, as shown in Figures 17 to 22, in two pad unit columns 2 of a cascade loop, the data output pads Co of the first pad area 301 (A1) in the first-stage pad unit 3 are electrically connected to the binding electrode (not shown) of the binding area 102 via the fourth sub-segment DA1-2, and the data input pads Ci of the first pad area 301 (A4) in the last-stage pad unit 3 are electrically connected to the binding electrode (not shown) of the binding area 102 via the fourth sub-segment DA1-2.

[0276] In some embodiments, as shown in FIG. 2 to FIG. 5 , FIG. 8 , FIG. 9 , FIG. 11 to FIG. 15 , and FIG. 17 to FIG. 22 , in the second direction X, the data output pads Co of the first pad area 301 and the data input pads Ci after the first pad area 301 is rotated 180° are located in the same row;

[0277] The address pads Di of the first pad area 301 and the relay pads Do after the first pad area 301 is rotated 180° are located in the same row;

[0278] The second data signal line DA2 extends along the second direction X;

[0279] The second sub-segment D- 1 electrically connecting two adjacent pad unit columns 2 extends along the second direction X.

[0280] In some embodiments, as shown in FIG. 2 , FIG. 4 , FIG. 8 , FIG. 9 , FIG. 11 to FIG. 15 , and FIG. 17 to FIG. 22 , at least one power pad VDD includes: a first power pad VDD1 and a second power pad VDD2 ; the first power pad VDD1 and the second power pad VDD2 are both located in the first pad column 3011 ;

[0281] In the first pad column 3011, the arrangement direction of the first power pad VDD1 and the second power pad VDD2 is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2; for example, in the 2n-1th pad unit column 2, the cascade direction of the multiple pad units 3 (i.e., the arrangement direction in the order of A3, A4) is the direction from the functional area 101 to the binding area 102, and in each first pad area 3, the arrangement direction of the first power pad VDD1 and the second power pad VDD2 is also the direction from the functional area 101 to the binding area 102; in the 2nth pad unit column 2, the cascade direction of the multiple pad units 3 (i.e., the arrangement direction in the order of A1, A2) is the direction from the binding area 102 to the functional area 101, and in each first pad area 3, the arrangement direction of the first power pad VDD1 and the second power pad VDD2 is also the direction from the binding area 102 to the functional area 101;

[0282] In the first direction Y, the orthographic projection of the output pad S on the substrate 1 is located between the orthographic projection of the first power pad VDD1 on the substrate 1 and the orthographic projection of the second power pad VDD2 on the substrate 1;

[0283] One end of the third sub-segment vdd-1 is electrically connected to the second power pad VDD2 of a first pad area 301 , and the other end of the third sub-segment vdd-1 is electrically connected to the first power pad VDD1 of the next first pad area 301 .

[0284] The wiring substrate provided by the embodiment of the present disclosure includes a plurality of power pads in the first pad area, so that the number of first pads in the first pad column and the second pad column can be balanced, so that the number of pads included in the first pad column and the second pad column is equal, which can improve the thickness uniformity of the first pad area for supporting the driver chip to which it is bound, and improve the balance of the center of gravity of the driver chip. It can also improve the reliability of the electrical connection between the driver chip and the first pad. In addition, the remaining pads in the first pad column are located between the first power pad and the second power pad, and are respectively located adjacent to the first power pad and the second power pad in the two cascaded first pad areas in the pad unit column, which facilitates the electrical connection between the cascaded power pads through the third sub-segment, and is more conducive to reducing the difficulty of wiring.

[0285] In the wiring substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 4, 8, 9, 11 to 15, and 17 to 22, the first power pad VDD1 and the second power pad VDD2 are located in the first pad column 3011, which can fully utilize the wiring space and prevent interference between the third sub-segment VDD-1 and the first sub-segment DA1-1 and the second sub-segment D-1. Furthermore, the arrangement direction of the first power pad VDD1, the output pad S, and the second power pad VDD2 is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2. Thus, in a pad unit column 2, the first power pad VDD1 and the second power pad VDD2 located in the two cascaded first pad areas 301 are adjacent in the first direction Y, which can reduce the wiring difficulty of the electrical connection between the first power pad VDD1 and the second power pad VDD2 via the third sub-segment VDD-1.

[0286] In some embodiments, as shown in Figures 2, 4, 8, 9, 11 to 15, and 17 to 22, for two pad unit columns 2 of a cascade loop, the first power pad VDD1 of the first pad area 301 (A1) in the first-level pad unit 3 is electrically connected to the binding electrode (not shown) of the binding area 102 through the sixth sub-segment vdd-2, and the second power pad VDD2 of the first pad area 301 (A4) in the last-level pad unit 3 is electrically connected to the binding electrode (not shown) of the binding area 102 through the sixth sub-segment vdd-2.

[0287] In some embodiments, as shown in FIG. 2 , FIG. 4 , FIG. 8 , FIG. 9 , FIG. 11 to FIG. 15 , and FIG. 17 to FIG. 22 , in the second direction X, the power pad VDD and the data pad C are located in the same row.

[0288] In some embodiments, as shown in Figures 2, 4, 8, 9, and 11 to 15, in the second direction X, the first power pad VDD1 and the data input pad Ci are located in the same row, and the second power pad VDD2 and the data output pad Co are located in the same row.

[0289] Alternatively, in some embodiments, as shown in FIG. 17 to FIG. 22 , in the second direction X, the first power pad VDD1 and the data output pad Co are located in the same row, and the second power pad VDD2 and the data input pad Ci are located in the same row.

[0290] In some embodiments, as shown in Figures 2, 4, 8, 9, 11-15, and 17-22, first pad region 301 includes multiple output pads S, and the multiple output pads S included in first pad region 301 are all located in first pad column 3011. In the first direction Y, the orthographic projections of the multiple output pads S on substrate 1 are located between the orthographic projections of the first power pad VDD1 and the orthographic projections of the second power pad VDD2 on substrate 1. This prevents interference between the traces electrically connecting the output pads S to second pad region 302 and the third subsegment vdd-1, thereby reducing routing difficulty.

[0291] In some embodiments, as shown in FIG. 2 , FIG. 4 , FIG. 8 , FIG. 9 , FIG. 11 to FIG. 15 , and FIG. 17 to FIG. 22 , the first pad region 301 includes a plurality of ground pads GND, and the plurality of ground pads GND are all located in the second pad column 3012 .

[0292] In the wiring substrate provided by the embodiments of the present disclosure, when the first pad area includes multiple output pads, the first pad area also includes multiple ground pads. This balances the number of first pads in the first and second pad columns, ensuring that the first and second pad columns include equal numbers of pads. This improves the thickness uniformity of the first pad area supporting the driver chip to which it is attached, improving the center of gravity balance of the driver chip. It also improves the reliability of the electrical connection between the driver chip and the first pads.

[0293] It should be noted that Figures 2, 4, 8, 9, 11 to 15, and 17 to 22 are illustrated by taking the first pad area including four output pads S and two ground pads GND as an example. In specific implementation, the number of output pads S and ground pads GND can be set according to actual needs.

[0294] 2, 4, 8, 9, 11 to 15, and 17 to 22 illustrate the case where data pad C is located only in second pad column 3012. In practice, both first pad column 3011 and second pad column 3012 may include data pad C.

[0295] In some embodiments, as shown in FIG6 , FIG10 , and FIG16 , at least a portion of at least one data pad C and an address pad Di are located in a first pad column 3011 ;

[0296] In the first pad column 3011, the arrangement direction of the data pad C, the address pad Di, the power pad VDD and the output pad S is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2;

[0297] In the second pad column 3012, the arrangement direction of the ground pad GND, the data pad C, and the relay pad Do is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2;

[0298] One end of the first sub-segment DA1-1 is electrically connected to the data pad C located in the second pad column 3012, and the other end of the first sub-segment DA1-1 is electrically connected to the data pad C located in the first pad column 3011;

[0299] The orthographic projection of the first subsegment DA1 - 1 on the substrate 1 is located between the orthographic projection of the second subsegment D- 1 on the substrate 1 and the orthographic projection of the main portion gnd- 1 on the substrate 1 .

[0300] In a specific implementation, as shown in Figures 6, 10, and 16, both the first pad column 3011 and the second pad column 3012 include data pads C, and the address pads Di and relay pads Do are located in the first pad column 3011 and the second pad column 3012, respectively. The two ends of the first subsegment DA1-1 are electrically connected to the first pad unit column 3011 and the second pad unit column 3012, respectively. The two ends of the second subsegment D-1 are electrically connected to the first pad unit column 3011 and the second pad unit column 3012, respectively. As a result, the orthographic projection of the first subsegment DA1-1 on substrate 1 passes through the area between adjacent first pad areas 301. The orthographic projection of the second subsegment D-1 on substrate 1, which is electrically connected to the two cascaded first pad areas 301 in pad unit column 2, also passes through the area between adjacent first pad areas 301. This allows the routing of the cascaded pad unit lines to utilize the area between adjacent first pad areas, reducing routing complexity.

[0301] In a specific implementation, for example, the first sub-segment and the second sub-segment are both led out from the second pad column toward one side of the trunk portion, pass through the area between adjacent first pad regions, and extend to the area between the first pad region and the first voltage line.

[0302] In a specific implementation, as shown in Figures 6, 10, and 16, in the second pad column 3012, the arrangement direction of the ground pad GND, the data pad C, and the relay pad Do is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2; thus, the arrangement direction of the branch gnd-2, the first sub-segment DA1-1, and the second sub-segment D-1 electrically connected to the two first pad areas 301 cascaded in the pad unit column 2 is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2. While realizing the cascade of the first pad area through the first sub-segment DA1-1 and the second sub-segment D-1, mutual interference between the branch gnd-2, the first sub-segment DA1-1, and the second sub-segment D-1 is avoided. Correspondingly, in the first pad column 3011, the arrangement direction of the data pad C and the address pad Di is the same as the cascade direction of the multiple pad units 3 in the pad unit column 2, so that the orthographic projection of the first sub-segment DA1-1 on the substrate 1 is located between the orthographic projection of the second sub-segment D-1 on the substrate 1 and the orthographic projection of the main body gnd-1 on the substrate 1, thereby avoiding mutual interference between the first sub-segment DA1-1 and the second sub-segment D-1.

[0303] In some embodiments, as shown in FIG6 , FIG10 , and FIG16 , at least a portion of at least one power pad VDD is located in the second pad column 3012 ;

[0304] In the second pad column 3012, the arrangement direction of the ground pad GND, the data pad C, the relay pad Do, and the power pad VDD is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2;

[0305] One end of the third sub-segment vdd-1 is electrically connected to the power pad VDD located in the second pad column 3012, and the other end of the third sub-segment vdd-1 is electrically connected to the power pad VDD located in the first pad column 3011;

[0306] The orthographic projection of the second sub-segment D-1 of the two first pad areas 301 cascaded in the electrically connected pad unit column 2 on the substrate 1 is located between the orthographic projection of the first sub-segment DA1-1 on the substrate 1 and the orthographic projection of the third sub-segment vdd-1 of the two first pad areas 301 cascaded in the electrically connected pad unit column 2 on the substrate 1.

[0307] In a specific implementation, the third sub-segment is also led out from the second pad column toward one side of the trunk portion, passes through the area between adjacent first pad areas in the first direction Y, and extends to the area between the first pad area and the first voltage line.

[0308] In a specific implementation, as shown in Figures 6, 10, and 16, the first subsegment DA1-1, the second subsegment D-1 connecting the two first pad areas cascaded in the pad unit column, and the third subsegment vdd-1 are all broken line segments (e.g., having a "bow" shape). The broken line segment includes a plurality of first line segments 10 and second line segments 11 extending in different directions, alternately connected end to end. In Figures 6, 10, and 16, the extending directions of the first line segments 10 and the second line segments 11 are perpendicular.

[0309] In some embodiments, as shown in FIG6 , FIG10 , and FIG16 , in the plurality of traces 5 electrically connected to the two first pad areas 301 cascaded in the pad unit column 2, the arrangement direction of the first sub-segment DA1-1, the second sub-segment D-1, and the third sub-segment vdd-1 in the first direction Y is the same as the cascade direction of the plurality of pad units 3 in the pad unit column 2;

[0310] Among the multiple traces 5 electrically connected to the two first pad areas 301 cascaded in the two pad unit columns 2, the second data signal line DA2, the second sub-segment D-1 and the third sub-segment vdd-1 are arranged in sequence from the binding area 102 to the functional area 101.

[0311] In the wiring substrate provided by the embodiment of the present disclosure, the arrangement direction of the ground pads, data pads, relay pads and power pads in the second pad column is the same as the arrangement direction of the branches, the first sub-segment, the second sub-segment and the third sub-segment; the arrangement direction of the data pads, address pads and power pads in the first pad column is the same as the arrangement direction of the first sub-segment, the second sub-segment and the third sub-segment, that is, for the various routing lines that cascade the pad units in the pad unit column, the arrangement order of the different routing lines matches the arrangement order of the corresponding first pads, which can avoid mutual interference between the different routing lines. In addition, the second data signal line, the second sub-segment connecting two adjacent pad columns, and the third sub-segment connecting two adjacent pad columns are all located on the side of the branch and the main body away from the binding area, and for the first pad column and the second pad column respectively located in two pad unit columns and cascaded, the arrangement direction of the data pads, relay pads and power pads in the second pad column, the arrangement direction of the data pads, address pads and power pads in the first pad column, the second data signal line, the second sub-segment connecting two adjacent pad columns, and the arrangement direction of the third sub-segment connecting two adjacent pad columns are matched, which can simplify the wiring difficulty, is conducive to the rational use of wiring space to ensure the line width of the routing, and can avoid mutual interference between the routings connecting two adjacent pad columns.

[0312] In a specific implementation, the second data signal line, the second subsegment connecting two adjacent pad columns, and the third subsegment connecting two adjacent pad columns are also alternately connected by first line segments 10 and second line segments 11 extending in different directions.

[0313] In some embodiments, as shown in FIG6 , FIG10 , FIG16 , FIG23 , and FIG24 , at least one data pad C includes: a data input pad Ci and a data output pad Co; one of the data input pad Ci and the data output pad Co is located in a first pad column 3011 , and the other of the data input pad Ci and the data output pad Co is located in a second pad column 3012 ;

[0314] In some embodiments, as shown in FIG6 , FIG10 , and FIG16 , the data input pad Ci is located in the first pad column 3011 , and the data output pad Co is located in the second pad column 3012 ;

[0315] In each pad unit column 2, the data output pad Co of the i-th level first pad area 301 is electrically connected to the first portion of the first sub-segment DA1-1, and the data output pad Co of the i-th level first pad area 301 is electrically connected to the data input pad Ci of the (i+1)-th level first pad area 301 through the first sub-segment DA1-1; where i is a positive integer;

[0316] In the adjacent pad unit column 2, one end of the second data signal line DA2 is electrically connected to the data output pad Co of the last level first pad area 301 in a column of pad unit column 2, and the other end of the second data signal line DA2 is electrically connected to the data input pad Ci of the first level first pad area 301 in a column of pad unit column 2.

[0317] Alternatively, in some embodiments, as shown in FIG. 23 and FIG. 24 , the data output pad Co is located in the first pad column 3011 , and the data input pad Ci is located in the second pad column 3012 ;

[0318] In each pad unit column 2, the data input pad Ci of the i-th level first pad area 301 is electrically connected to the first portion of the first sub-segment DA1-1, and the data input pad Ci of the i-th level first pad area 301 is electrically connected to the data output pad Co of the (i+1)-th level first pad area 301 through the first sub-segment DA1-1; where i is a positive integer;

[0319] In the adjacent pad unit column 2, one end of the second data signal line DA2 is electrically connected to the data input pad Ci of the last level first pad area 301 in a column of pad unit column 2, and the other end of the second data signal line DA2 is electrically connected to the data output pad Co of the first level first pad area 301 in a column of pad unit column 2.

[0320] The wiring substrate provided in the embodiments of the present disclosure includes two data pads located in different pad columns in the first pad area. This balances the number of first pads in the first and second pad columns, improves the thickness uniformity of the first pad area supporting the driver chip to which it is attached, and improves the center of gravity balance of the driver chip. Furthermore, the reliability of the electrical connection between the driver chip and the first pads is improved.

[0321] In some embodiments, as shown in FIG6 , FIG10 , FIG16 , FIG23 , and FIG24 , at least one power pad VDD includes: a first power pad VDD1 and a second power pad VDD2 ; the first power pad VDD1 is located in a first pad column 3011 , and the second power pad VDD2 is located in a second pad column 3012 ;

[0322] The second power pad VDD2 of the i-th level first pad region 301 is electrically connected to the first power pad VDD1 of the (i+1)-th level first pad region 301 through the third subsegment vdd-1.

[0323] The wiring substrate provided by the embodiment of the present disclosure includes multiple power pads in the first pad area, thereby balancing the number of first pads in the first pad column and the second pad column, so that the number of pads included in the first pad column and the second pad column is equal. This can improve the thickness uniformity of the first pad area for supporting the driver chip it is bound to, and improve the center of gravity balance of the driver chip. It can also improve the reliability of the electrical connection between the driver chip and the first pad. It is more conducive to reducing the wiring difficulty and realizing the electrical connection of cascaded power pads through the third sub-segment.

[0324] In some embodiments, as shown in FIG6 , FIG10 , FIG16 , FIG23 , and FIG24 , the first pad area 301 includes a plurality of output pads S;

[0325] Some output pads S are located in the second pad column 3012;

[0326] In the second pad column 3012 , in the second direction X, the output pad S is located on a side of the second power pad VDD2 away from the relay pad Do.

[0327] In a specific implementation, as shown in Figures 6, 10, 16, 23, and 24, when the first pad area 301 includes multiple output pads S, and some of the output pads S are located in the second pad column 3012, the fifth connecting lead 505 electrically connected to the output pads S located in the second pad column 3012 passes through the area between the cascaded first pad areas 301. In the second direction X, the output pads S are located on the side of the second power pad VDD2 away from the relay pad Do. The arrangement order of the fifth connecting lead 505 and the third sub-segment vdd1 matches the arrangement order of the output pads S and the second power pad VDD2. This prevents interference between the fifth connecting lead 505 and the third sub-segment vdd1, simplifies routing complexity, and saves wiring space.

[0328] In some embodiments, as shown in FIG6 , FIG10 , FIG16 , FIG23 , and FIG24 , the first pad area 301 includes two ground pads GND, which are respectively located in a first pad column 3011 and a second pad column 3012 ; in the first direction Y, the two ground pads GND are located in the same row;

[0329] In the first pad column 3011, the ground pad GND is located on the side of the data pad C away from the address pad Di; as shown in FIG6, FIG10, and FIG16, in the first pad column 3011, the ground pad GND is located on the side of the data input pad Ci away from the address pad Di; or, as shown in FIG23 and FIG24, in the first pad column 3011, the ground pad GND is located on the side of the data output pad Co away from the address pad Di;

[0330] In the second pad column 3012, the ground pad GND is located on the side of the data pad C away from the relay pad Do; as shown in Figures 6, 10, and 16, in the second pad column 3012, the ground pad GND is located on the side of the data output pad Co away from the relay pad Do; or, as shown in Figures 23 and 24, in the first pad column 3011, the ground pad GND is located on the side of the data input pad Ci away from the relay pad Do;

[0331] In the second direction X, the data input pad Ci and the data output pad Co are located in the same row, the address pad Di and the relay pad Do are located in the same row, and the first power pad VDD1 and the second power pad VDD2 are located in the same row.

[0332] In the wiring substrate provided by the embodiments of the present disclosure, when the first pad area includes multiple output pads, the first pad area also includes multiple ground pads. This balances the number of first pads in the first and second pad columns, ensuring that the first and second pad columns include equal numbers of pads. This improves the thickness uniformity of the first pad area supporting the driver chip to which it is attached, improving the center of gravity balance of the driver chip. It also improves the reliability of the electrical connection between the driver chip and the first pads.

[0333] In some embodiments, as shown in Figures 6, 10, 16, 23, and 24, the trace 5 further includes: a seventh sub-segment gnd-3; one end of the seventh sub-segment gnd-3 is electrically connected to the binding electrode (not shown) of the binding area 102, and the other end of the seventh sub-segment gnd-3 is electrically connected to the ground pad GND in the first-level pad unit 3 in a cascade loop; the ground pad GND is located in the first pad column 3011.

[0334] In some embodiments, when the first pad area 301 includes a plurality of data pads C, namely a data input pad Ci and a data output pad Co, it is necessary to configure the data input pad Ci and the data output pad Co to be electrically connected.

[0335] In some embodiments, when the wiring substrate is applied to a light-emitting substrate, that is, the first pad area is bound to the driver chip, the data input pads Ci and the data output pads Co belonging to the same first pad area can be electrically connected through the driver chip, that is, the driver chip includes internal wiring connected to the data input pads Ci and the data output pads Co. In other words, as shown in Figures 2, 4, 6, and 11 to 24, the data input pads Ci and the data output pads Co in the first pad area 301 are not directly connected through traces provided on the substrate.

[0336] Alternatively, in some embodiments, as shown in FIG. 8 , FIG. 9 , FIG. 10 , and FIG. 25 to FIG. 32 , the first pad area 301 further includes: a first connecting lead 6 ; the data input pad Ci and the data output pad Co are electrically connected via the first connecting lead 6 .

[0337] In the wiring substrate provided by the embodiment of the present disclosure, the first pad area includes a first connecting lead connected to the data pad, so that there is no need to set a circuit inside the driver chip bound to the first pad area to electrically connect multiple data pads, which can simplify the design difficulty of the driver chip.

[0338] In some embodiments, when the first pad area 301 includes a plurality of power pads VDD, namely a first power pad VDD1 and a second power pad VDD2, it is necessary to configure the first power pad VDD1 and the second power pad VDD2 to be electrically connected.

[0339] In some embodiments, when the wiring substrate is used in a light-emitting substrate, that is, the first pad area is bound to a driver chip, the first power pad VDD1 and the second power pad VDD2 belonging to the same first pad area can be electrically connected through the driver chip, that is, the driver chip includes internal wiring for the first power pad VDD1 and the second power pad VDD2. As shown in Figures 2, 4, 6, and 11 to 32, the first power pad VDD1 and the second power pad VDD2 of the first pad area 301 are not electrically connected by wiring.

[0340] Alternatively, in some embodiments, as shown in FIG. 8 , FIG. 9 , FIG. 10 , and FIG. 33 to FIG. 40 , the first pad area 301 further includes: a second connecting lead 7 ; the first power pad VDD1 and the second power pad VDD2 are electrically connected via the second connecting lead 7 .

[0341] In the wiring substrate provided by the embodiment of the present disclosure, the first pad area includes a second connecting lead connected to the power pad, so that there is no need to set up a circuit inside the driver chip bound to the first pad area to electrically connect multiple power pads, which can simplify the design difficulty of the driver chip.

[0342] In some embodiments, as shown in FIG. 2 , FIG. 4 , and FIG. 6 , when the first pad area 301 includes a plurality of ground pads GND, it is necessary to configure electrical connections between the plurality of ground pads GND.

[0343] In some embodiments, when the wiring substrate is used in a light-emitting substrate, that is, the first pad area is bound to a driver chip, multiple ground pads GND belonging to the same first pad area can be electrically connected through the driver chip, that is, the driver chip includes internal wiring electrically connected to the multiple ground pads GND. As shown in Figures 2, 4, 6, and 11 to 40, the multiple ground pads GND in the first pad area 301 are not directly electrically connected via wiring.

[0344] Alternatively, in some embodiments, as shown in FIG8 , FIG9 , FIG10 , and FIG41 to FIG48 , the first pad area 301 further includes: a third connecting lead 8 ; both ends of the third connecting lead 8 are electrically connected to different ground pads GND, respectively.

[0345] In the wiring substrate provided by the embodiment of the present disclosure, the first pad area includes a third connecting lead connected to the ground pad, so that there is no need to set a circuit inside the driver chip bound to the first pad area to electrically connect multiple ground pads, which can simplify the design difficulty of the driver chip.

[0346] It should be noted that the first connecting lead, the second connecting lead, and the third connecting lead can be present in any combination simultaneously in a first pad area; for example, the first pad area can include: the first connecting lead and the second connecting lead, or the first connecting lead and the third connecting lead, or the second connecting lead and the third connecting lead, or the first connecting lead, the second connecting lead, and the third connecting lead. Figures 8, 9, 10, and 49 to 56 illustrate the example where the first pad area 301 includes the first connecting lead 6, the second connecting lead 7, and the third connecting lead 8.

[0347] An embodiment of the present disclosure provides a light-emitting substrate, as shown in FIG57 , which includes: a wiring substrate 9 provided in an embodiment of the present disclosure, and a plurality of driving circuit ICs and a plurality of light-emitting elements bound to the wiring substrate 9 .

[0348] In some embodiments, the driver chip is bound to the first pad area in a one-to-one correspondence, and the light-emitting element is bound to the pad groups in the plurality of second pad areas in a one-to-one correspondence.

[0349] In some embodiments, the driver chip includes a first circuit, and the plurality of data pads included in the first pad region are electrically connected via the first circuit. This eliminates the need for wiring in the first pad region to connect the plurality of data pads, thereby saving wiring space. In a specific implementation, the first circuit is electrically connected to the data input pad and the data output pad.

[0350] In some embodiments, the driver chip includes a second circuit, and the plurality of power pads included in the first pad area are electrically connected via the second circuit. This eliminates the need for wiring in the first pad area to connect the plurality of power pads, thereby saving wiring space. In a specific implementation, the second circuit is electrically connected to the first power pad and the second power pad.

[0351] In some embodiments, the driver chip includes a third circuit, and the plurality of ground pads included in the first pad region are electrically connected via the third circuit. This eliminates the need to provide wiring in the first pad region to connect the plurality of ground pads, thereby saving wiring space.

[0352] In some embodiments, as shown in FIG57 , the light emitting substrate further includes:

[0353] The circuit board is bound to the wiring substrate 9 in the binding area 102 .

[0354] During specific implementation, the circuit board is bound to the binding electrodes located in the binding area.

[0355] In a specific implementation, the circuit board can be either a rigid printed circuit board or a flexible printed circuit board.

[0356] In some embodiments, the light emitting element is a micro-sized inorganic light emitting diode.

[0357] In a specific implementation, the micro-sized inorganic light-emitting diode is, for example, a mini light-emitting diode (Mini Light Emitting Diode, Mini-LED) or a micro light-emitting diode (Micro Light Emitting Diode, Micro-LED). Mini-LED and Micro-LED are small in size and high in brightness, and can be widely used in display devices or their backlight modules. For example, the typical size (e.g., length) of Micro-LED is less than 100 microns, such as 10 microns to 80 microns; the typical size (e.g., length) of Mini-LED is 80 microns to 350 microns, such as 80 microns to 120 microns. The electronic component can be at least one of Micro-LED or Mini-LED.

[0358] A display device provided by an embodiment of the present disclosure includes the light-emitting substrate provided by an embodiment of the present disclosure.

[0359] In some embodiments, as shown in FIG58 , the display device further includes:

[0360] The display panel 13 is located on the light emitting side of the light emitting substrate 12 .

[0361] That is, the light-emitting substrate serves as the backlight source of the display panel.

[0362] In a specific implementation, as shown in FIG58 , the display panel 13 is, for example, a liquid crystal display panel, including: an array substrate 1301 and an opposing substrate 1302 that are arranged opposite to each other, and a liquid crystal layer 1303 located between the array substrate 1301 and the opposing substrate 1302 .

[0363] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the wiring substrate and light-emitting substrate, and any repetitive details will be omitted.

[0364] To sum up, in the wiring substrate, light-emitting substrate and display device provided by the embodiments of the present disclosure, the data pads of the two first pad areas located in adjacent pad unit columns and cascaded are electrically connected through the second data signal line, thereby avoiding the data signal output by the data pad of the first pad area farthest from the binding area from being transmitted back to the binding area through a routing line with a longer length, which can reduce the data signal transmission time, increase the data signal transmission frequency, and avoid data signal transmission delay.

[0365] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0366] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A wiring substrate, wherein, The wiring substrate includes: A substrate including a functional area and a bonding area located on one side of the functional area in a first direction; A plurality of pad unit columns located on one side of the substrate in the functional area; at least one of the plurality of pad unit columns includes a plurality of pad units; at least one of the plurality of pad units includes: a first pad area; the first pad area includes: a plurality of first pads, the plurality of first pads including at least one data pad and at least one ground pad; A plurality of traces; the plurality of traces are electrically connected to the plurality of pad units; the plurality of traces includes: a plurality of data signal lines and a plurality of ground signal lines; the plurality of data signal lines includes: a plurality of first data signal lines, the first data signal lines are electrically connected to the data pads of the plurality of first pad areas in one column of the pad unit columns, and the ground signal lines are respectively electrically connected to the ground pads of two adjacent and cascaded first pad areas in adjacent pad unit columns.

2. The wiring substrate according to claim 1, wherein, The ground pads of the plurality of first pad areas in one column of the pad unit columns are adjacent to the ground pads of the plurality of first pad areas in adjacent pad unit columns.

3. The wiring substrate according to claim 1 or 2, wherein, The ground pads of the plurality of first pad areas in one column of the pad unit columns are mirror - image arranged with the ground pads of the plurality of first pad areas in adjacent pad unit columns.

4. The wiring substrate according to claim 3, wherein, The traces further include: a plurality of address signal lines and a plurality of second voltage lines; The first pad area further includes: an address pad, a relay pad, and at least one power pad; The address signal lines are electrically connected to the address pads and the relay pads, and the second voltage lines are electrically connected to the power pads; In two adjacent and cascaded first pad areas of two pad unit columns respectively, one of the address pads is adjacent to the relay pad of the other first pad area.

5. The wiring substrate according to claim 4, wherein, After the address pads and relay pads of the plurality of first pad areas in one column of the pad unit columns are rotated 180°, they are mirror - image arranged with the address pads and relay pads of the plurality of first pad areas in adjacent pad unit columns.

6. The wiring substrate according to any one of claims 1 to 5, wherein, In two adjacent pad unit columns, the cascading directions of the plurality of pad units are opposite; The wiring substrate includes 2N pad unit columns; the arrangement of the plurality of first pads after the first pad area in the 2n - th pad unit column is rotated 180° is the same as the arrangement of the plurality of first pads in the (2n - 1)-th pad unit column; where N is a positive integer and n is a positive integer not greater than N.

7. The wiring substrate according to any one of claims 1 to 6, wherein, At least one of the data pads and at least one of the ground pads are in the same column in the first direction; And at least one of the data pads and at least one of the ground pads include portions located at the edge of the first pad area close to the ground signal line.

8. The wiring substrate according to claim 7, wherein, The ground signal line includes: a main trunk extending in the first direction; the main trunk is located between two pad unit columns electrically connected to the ground signal line.

9. The wiring substrate according to claim 8, wherein, The grounding signal line further includes a branch extending in a second direction, and a positive projection of the branch on the substrate is located between a positive projection of the main trunk on the substrate and a positive projection of the pad unit column on the substrate. The main trunk and the grounding pads included in the second pad column are connected through the branch; The second direction intersects the first direction.

10. The wiring substrate according to claim 8 or 9, wherein, The first data signal line includes a plurality of first sub-segments; the first sub-segments are electrically connected to the data pads of two cascaded first pad regions in the pad unit column; A positive projection of the first sub-segment on the substrate is located on a side of the positive projection of the main trunk on the substrate facing the positive projection of the pad unit column on the substrate.

11. The wiring substrate according to any one of claims 1 to 10, wherein, The plurality of data signal lines further includes: a plurality of second data signal lines; The second data signal lines are respectively electrically connected to the data pads of two cascaded first pad regions located in adjacent pad unit columns.

12. The wiring substrate according to claim 11, wherein, The grounding signal line includes the main trunk; a positive projection of the second data signal line on the substrate is located on a side of the positive projection of the main trunk on the substrate away from the bonding area.

13. The wiring substrate according to any one of claims 8 to 12, wherein, Two adjacent and cascaded pad unit columns are electrically connected to the same main trunk.

14. The wiring substrate according to any one of claims 9 to 12, wherein, Two adjacent and cascaded pad unit columns are electrically connected to different main trunks, and the branch is respectively electrically connected to the grounding pads of two cascaded first pad regions located in adjacent pad unit columns.

15. The wiring substrate according to any one of claims 11 to 14, wherein, The grounding signal line includes the main trunk; the pad unit further includes: at least one second pad region; the second pad region is electrically connected to the first pad region; The first pad further includes: at least one output pad; The plurality of traces further includes: a plurality of first voltage lines extending along the first direction; The first voltage lines are electrically connected to the input ends of a plurality of second pad regions in the pad unit column, and the output ends of the second pad regions are electrically connected to the output pads; The first voltage line and the main trunk electrically connected to the same pad unit column are respectively located on two sides of the pad unit column.

16. The wiring substrate according to claim 15, wherein, At least some adjacent pad unit columns are electrically connected to the same first voltage line.

17. The wiring substrate according to claim 16, wherein, The first pad region further includes: address pads, relay pads, and at least one power supply pad; The traces further includes: a plurality of address signal lines, and a plurality of second voltage lines; the address signal lines include a plurality of second sub-segments; One end of the second sub-segment is electrically connected to a relay pad of a first pad region, and the other end of the second sub-segment is electrically connected to an address pad of the next-level first pad region of the first pad region; The second voltage line includes a plurality of third sub-segments; the third sub-segments are electrically connected to the power supply pads of two cascaded first pad regions; In the first direction, the relay pad and at least one of the power supply pads are located in different columns.

18. The wiring substrate according to claim 17, wherein, The plurality of first pads included in the first pad region are arranged in a first pad column and a second pad column in a manner of M×2; M is a positive integer; In the second direction, the orthographic projection of the second pad column on the substrate is located between the orthographic projection of the first pad column on the substrate and the orthographic projection of the main trunk on the substrate; At least a partial area of at least one of the data pads, the relay pad, and at least a partial area of at least one of the ground pads are located in the second pad column, and at least a partial area of at least one of the output pads and at least a partial area of at least one of the power pads are located in the first pad column.

19. The wiring substrate according to claim 18, wherein, The trace is provided on the same layer as the first pad; the address pad is located in the second pad column; In the second pad column, the arrangement direction of the address pad and the relay pad is the same as the cascading direction of the plurality of pad units in the pad unit column; In the second pad column, in the first direction, the orthographic projection of the ground pad on the substrate is located between the orthographic projection of the address pad on the substrate and the orthographic projection of the relay pad on the substrate; The orthographic projection of the second sub-segment that electrically connects two cascaded first pad regions in the pad unit column on the substrate is located between the orthographic projection of the first sub-segment on the substrate and the orthographic projection of the main trunk on the substrate.

20. The wiring substrate according to claim 19, wherein, At least one of the data pads includes: a data input pad and a data output pad; in each pad unit column, the data output pad of the i-th stage first pad region is electrically connected to the data input pad of the (i + 1)-th stage first pad region through the first sub-segment; where i is a positive integer; In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data output pad of the last stage first pad region in one column of the pad unit column, and the other end of the second data signal line is electrically connected to the data input pad of the first stage first pad region in one column of the pad unit column; The data input pad and the data output pad are located in the second pad column; the arrangement direction of the data input pad and the data output pad is the same as the cascading direction of the plurality of pad units in the pad unit column; The orthographic projection of the address pad on the substrate is located between the orthographic projection of the data input pad on the substrate and the orthographic projection of the ground pad on the substrate, and the orthographic projection of the relay pad on the substrate is located between the orthographic projection of the data output pad on the substrate and the orthographic projection of the ground pad on the substrate.

21. The wiring substrate according to claim 19, wherein, At least one of the data pads includes: a data input pad and a data output pad; in each pad unit column, the data input pad of the i-th stage first pad region is electrically connected to the data output pad of the (i + 1)-th stage first pad region through the first sub-segment; where i is a positive integer; In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data input pad of the last stage first pad region in one column of the pad unit column, and the other end of the second data signal line is electrically connected to the data output pad of the first stage first pad region in one column of the pad unit column; The data input pad and the data output pad are located in the second pad column; the arrangement direction of the data output pad and the data input pad is the same as the cascading direction of multiple pad units in the pad unit column; The orthographic projection of the address pad on the substrate is located between the orthographic projection of the data input pad on the substrate and the orthographic projection of the ground pad on the substrate, and the orthographic projection of the relay pad on the substrate is located between the orthographic projection of the data output pad on the substrate and the orthographic projection of the ground pad on the substrate.

22. The wiring substrate according to claim 20 or 21, wherein, In the second direction, the data output pad of the first pad region and the data input pad after the first pad region is rotated 180° are located in the same row; The address pad of the first pad region and the relay pad after the first pad region is rotated 180° are located in the same row; The second data signal line extends along the second direction, and the orthographic projection of the second data signal line on the substrate is located on the side of the orthographic projection of the branch on the substrate away from the bonding region; The second sub-segment connecting adjacent two pad unit columns extends along the second direction, and the orthographic projection of the second sub-segment connecting adjacent two pad unit columns on the substrate is located between the orthographic projection of the second data signal line on the substrate and the orthographic projection of the branch on the substrate.

23. The wiring substrate according to claim 22, wherein, At least one power pad includes: a first power pad and a second power pad; both the first power pad and the second power pad are located in the first pad column; In the first pad column, the arrangement direction of the first power pad and the second power pad is the same as the cascading direction of multiple pad units in the pad unit column; In the first direction, the orthographic projection of the output pad on the substrate is located between the orthographic projection of the first power pad on the substrate and the orthographic projection of the second power pad on the substrate; One end of the third sub-segment is electrically connected to the second power pad of one first pad region, and the other end of the third sub-segment is electrically connected to the first power pad of the next-level first pad region of this first pad region.

24. The wiring substrate according to claim 23, wherein, In the second direction, the power pad and the data pad are located in the same row.

25. The wiring substrate according to any one of claims 18 to 24, wherein, The first pad region includes multiple ground pads, and all the multiple ground pads are located in the second pad column.

26. The wiring substrate according to any one of claims 18 to 25, wherein, The output pads included in the first pad region are all located in the first pad column.

27. The wiring substrate according to claim 18, wherein, At least part of at least one data pad and the address pad are located in the first pad column; In the first pad column, the data pad, the address pad, the power pad and the arrangement direction of the output pad are the same as the cascading direction of multiple pad units in the pad unit column; In the second pad column, the arrangement direction of the ground pad, the data pad, and the relay pad is the same as the cascading direction of multiple pad units in the pad unit column; One end of the first sub-segment is electrically connected to the data pad located in the second pad column, and the other end of the first sub-segment is electrically connected to the data pad located in the first pad column; The orthographic projection of the first sub-segment on the substrate is located between the orthographic projection of the second sub-segment on the substrate and the orthographic projection of the main trunk on the substrate.

28. The wiring substrate according to claim 27, wherein, The trace is provided on the same layer as the first pad; At least a partial area of at least one of the power pads is located in the second pad column; In the second pad column, the arrangement direction of the ground pad, the data pad, the relay pad, and the power pad is the same as the cascading direction of the multiple pad units in the pad unit column; One end of the third sub-segment is electrically connected to the power pad located in the second pad column, and the other end of the third sub-segment is electrically connected to the power pad located in the first pad column; The orthographic projection of the second sub-segment on the substrate that electrically connects two cascaded first pad regions in the pad unit column is located between the orthographic projection of the first sub-segment on the substrate and the orthographic projection of the third sub-segment on the substrate that electrically connects two cascaded first pad regions in the pad unit column.

29. The wiring substrate according to claim 28, wherein, Among the multiple traces electrically connected to two cascaded first pad regions in the pad unit column, the arrangement direction of the first sub-segment, the second sub-segment, and the third sub-segment in the first direction is the same as the cascading direction of the multiple pad units in the pad unit column; Among the multiple traces electrically connected to two cascaded first pad regions respectively located in two pad unit columns, the second data signal line, the second sub-segment, and the third sub-segment are arranged in sequence in the direction from the bonding region to the functional region.

30. The wiring substrate according to claim 29, wherein, At least one of the data pads includes a data input pad and a data output pad; the data input pad is located in the first pad column, and the data output pad is located in the second pad column; In each pad unit column, the data output pad of the i-th stage first pad region is electrically connected to the first part of the first sub-segment, and the data output pad of the i-th stage first pad region is electrically connected to the data input pad of the (i + 1)-th stage first pad region through the first sub-segment; where i is a positive integer; In adjacent pad unit columns, one end of the second data signal line is electrically connected to the data output pad of the last stage first pad region in one column of the pad unit column, and the other end of the second data signal line is electrically connected to the data input pad of the first stage first pad region in one column of the pad unit column.

31. The wiring substrate according to claim 29, wherein, At least one of the data pads includes a data input pad and a data output pad; the data output pad is located in the first pad column, and the data input pad is located in the second pad column; In each column of the pad units, the data input pad of the first pad area at the i-th level is electrically connected to the first part of the first sub-segment, and the data input pad of the first pad area at the i-th level is electrically connected to the data output pad of the first pad area at the (i + 1)-th level through the first sub-segment; where i is a positive integer; In adjacent columns of the pad units, one end of the second data signal line is electrically connected to the data input pad of the first pad area at the last level in one column of the pad units, and the other end of the second data signal line is electrically connected to the data output pad of the first pad area at the first level in one column of the pad units.

32. The wiring substrate according to claim 30 or 31, wherein, At least one of the power pads includes: a first power pad and a second power pad; the first power pad is located in the first pad column, and the second power pad is located in the second pad column; The second power pad of the first pad area at the i-th level is electrically connected to the first power pad of the first pad area at the (i + 1)-th level through the third sub-segment.

33. The wiring substrate according to claim 32, wherein, The first pad area includes two ground pads, and the two ground pads are respectively located in the first pad column and the second pad column; in the first direction, the two ground pads are in the same row; In the first pad column, the ground pad is located on the side of the data pad away from the address pad; In the second direction, the data input pad and the data output pad are in the same row, the address pad and the relay pad are in the same row, and the first power pad and the second power pad are in the same row.

34. The wiring substrate according to claim 33, wherein, The first pad area includes a plurality of output pads; Some of the output pads are located in the second pad column; In the second pad column, in the second direction, the output pad is located on the side of the second power pad away from the relay pad.

35. The wiring substrate according to any one of claims 20 to 26 and 30 to 34, wherein, The first pad area further includes: a first connection lead; the data input pad and the data output pad are electrically connected through the first connection lead.

36. The wiring substrate according to any one of claims 23 to 26 and 32 to 35, wherein, The first power pad and the second power pad in the first pad area are not electrically connected through the trace.

37. The wiring substrate according to any one of claims 23 to 26 and 32 to 35, wherein, The first pad area further includes: a second connection lead; the first power pad and the second power pad are electrically connected through the second connection lead.

38. The wiring substrate according to claim 36 or 37, wherein, The second voltage line includes a third sub-segment; the power pads of the first pad areas that are respectively located in adjacent columns of the pad units and are cascaded are electrically connected through the third sub-segment.

39. The wiring substrate according to claim 38, wherein, The bonding area includes a plurality of bonding electrodes; In adjacent columns of the pad units that are electrically connected through the third sub-segment, the power pads of the first pad area at the first level in one column of the pad units and the power pads of the first pad area at the last level in the other column of the pad units are both electrically connected to the bonding electrodes through the traces.

40. The wiring substrate according to claim 38, wherein, The bonding area includes a plurality of bonding electrodes; Among the adjacent pad unit columns electrically connected through the third sub-segment, the power pad of the first-stage first pad region of one column of the pad unit columns is electrically connected to the bonding electrode through the trace, and the power pad of the last-stage first pad region of the other column of the pad unit columns is not connected to the bonding electrode.

41. The wiring substrate according to any one of claims 25 and 32 to 34, wherein, The first pad region further includes: a third connection lead; both ends of the third connection lead are electrically connected to different ground pads respectively.

42. The wiring substrate according to any one of claims 18 to 41, wherein, The number of the first pads included in the first pad column is the same as that of the second pad column.

43. A light-emitting substrate, wherein, The light-emitting substrate includes: the wiring substrate according to any one of claims 1 to 42, a driving chip bonded in one-to-one correspondence with the first pad region, and a light-emitting element bonded in one-to-one correspondence with the pad groups in a plurality of the second pad regions.

44. The light-emitting substrate according to claim 43, wherein, The light-emitting element is a micro-sized inorganic light-emitting diode.

45. A display device, wherein, Including the light-emitting substrate according to any one of claims 43 to 44.

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