Preparation method for solar cell, solar cell, and photovoltaic module

Abstract

The present invention relates to the technical field of solar cells, and in particular relates to a preparation method for a solar cell, a solar cell, and a photovoltaic module. The preparation method comprises the following steps: annealing and crystallizing a first doped silicon layer and a second doped silicon layer in an annealing environment, a second mask layer being used for separating the second doped silicon layer from the annealing environment; removing the second mask layer on a light-receiving surface of a silicon wafer; irradiating the light-receiving surface of the silicon wafer by using a laser in an aerobic environment; and removing the second doped silicon layer and a second dielectric layer outside of a coverage range of an oxide layer.

Description

A method for preparing a solar cell, a solar cell and a photovoltaic module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311868605.8 and invention name “A method for preparing solar cells, solar cells and photovoltaic modules”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0003] The passivation contact structure, composed of an ultrathin layer of silicon oxide and a layer of doped polysilicon, is primarily used for passivation on the backlight side of the solar cell, achieving excellent surface passivation and selective carrier collection. A passivation contact structure with a localized pattern on the light-receiving side of the solar cell prevents the poorly transparent polysilicon from affecting the solar cell's light absorption, thereby improving the solar cell's efficiency. However, the current manufacturing process for solar cells with localized passivation contact structures suffers from difficult challenges such as low precision, multiple steps, and a long production process. In particular, it is difficult to produce a localized passivation contact structure with high pattern accuracy. Summary of the Invention

[0004] In order to solve the above technical problems, the present application discloses a method for preparing a solar cell, a solar cell and a photovoltaic module. By filling nitrogen or an inert gas into the annealing environment and using a second mask layer to separate the second doped silicon layer from the annealing environment, the accuracy of the oxide layer produced by subsequent laser oxidation is facilitated.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0006] Depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, on a backlit surface of a silicon wafer of a first conductivity type; wherein the first conductivity type and the second conductivity type are opposite;

[0007] Depositing on the light-receiving surface of the silicon wafer a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer, which are arranged in sequence away from the silicon wafer;

[0008] Filling nitrogen or an inert gas into an annealing environment, annealing and crystallizing the first doped silicon layer and the second doped silicon layer in the annealing environment; wherein the second mask layer is used to isolate the second doped silicon layer from the annealing environment;

[0009] removing the second mask layer on the light-receiving surface of the silicon wafer to expose a side of the second doped silicon layer facing away from the second dielectric layer;

[0010] irradiating the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on a side of the second doped silicon layer facing away from the second dielectric layer;

[0011] removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer;

[0012] The oxide layer and the first mask layer are removed.

[0013] Optionally, before the step of removing the second mask layer on the light-receiving surface of the silicon wafer to expose a side of the second doped silicon layer facing away from the second dielectric layer, the method for preparing a solar cell further comprises:

[0014] Removing the second mask layer on the backlight surface and the edge of the silicon wafer, and retaining the second mask layer on the light-receiving surface of the silicon wafer and a portion of the thickness of the first mask layer on the backlight surface;

[0015] By covering the light-receiving surface of the silicon wafer with the second mask layer, the coating layers of the second dielectric layer and the second doped silicon layer on the backlight surface and edge of the silicon wafer are removed.

[0016] Optionally, the step of removing the second mask layer on the backlight surface and the edge of the silicon wafer, and retaining the second mask layer on the light-receiving surface of the silicon wafer and a partial thickness of the first mask layer on the backlight surface, includes:

[0017] Use hydrofluoric acid with a mass percentage concentration of x% to clean the backlight surface and the edge of the silicon wafer, and control the cleaning time t1 to satisfy: t2≤t1<t3; wherein t2 is the time required for the wrap-around coating of the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%.

[0018] Optionally, the thickness of the first mask layer is greater than the thickness of the coating layer of the second mask layer;

[0019] And / or, in a hydrofluoric acid solution of the same concentration, the etching rate of the first mask layer is lower than the etching rate of the wrap-around coating of the second mask layer.

[0020] Optionally, the step of filling nitrogen or an inert gas into the annealing environment and annealing and crystallizing the first doped silicon layer and the second doped silicon layer in the annealing environment includes:

[0021] Filling the annealing environment with nitrogen or an inert gas to normal pressure to reduce the concentration of oxygen in the annealing environment;

[0022] placing the silicon wafer into the annealing environment;

[0023] The temperature in the annealing environment is raised to 780° C. to 820° C., and the pressure is reduced to 28KPa to 32KPa;

[0024] The annealing environment is filled with the nitrogen or the inert gas to 78KPa to 82KPa to reduce the concentration of oxygen in the annealing environment;

[0025] The annealing environment continues to heat up to 900° C. to 920° C.;

[0026] The first doped silicon layer and the second doped silicon layer are annealed at 900° C. to 920° C.;

[0027] The annealing environment is cooled to 700° C. to 740° C.;

[0028] The annealing environment is filled with the nitrogen or the inert gas to normal pressure to reduce the concentration of oxygen in the annealing environment;

[0029] The silicon wafer is taken out.

[0030] Optionally, in the step of irradiating the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on a side of the second doped silicon layer facing away from the second dielectric layer, the temperature of the heated area formed by the laser on the second doped silicon layer is lower than the melting point of the second doped silicon layer;

[0031] The frequency of the laser is 1800KHz to 2200KHz, the line width of the laser is 70μm to 100μm, and the power of the laser is 10W to 20W.

[0032] Optionally, before the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence away from the silicon wafer on the backlight side of the silicon wafer of the first conductivity type, the method for preparing a solar cell further comprises:

[0033] Polishing the light-receiving surface and the backlight surface of the silicon wafer; wherein the reflectivity of the light-receiving surface and the backlight surface of the silicon wafer is controlled to be 40% to 50%;

[0034] And / or, the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, on the backlight side of the silicon wafer of the first conductivity type, comprises:

[0035] growing the first dielectric layer;

[0036] sequentially growing an intrinsic silicon layer and one or more in-situ doped layers;

[0037] growing the first mask layer;

[0038] And / or, after the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence on the backlight side of the silicon wafer of the first conductivity type, facing away from the silicon wafer, the method for preparing a solar cell further comprises:

[0039] removing the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer, and retaining the first mask layer on the backlight surface;

[0040] By covering the first mask layer on the backlight surface, removing the coating layers of the first dielectric layer and the first doped silicon layer on the light-receiving surface and the edge of the silicon wafer;

[0041] The silicon wafer is etched to form a polished surface on the light-receiving surface.

[0042] Optionally, the step of depositing a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer on the light-receiving surface of the silicon wafer, which are arranged in sequence away from the silicon wafer, includes:

[0043] sequentially growing the second dielectric layer, the second in-situ doped silicon layer, and the second mask layer;

[0044] And / or, the step of removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer includes:

[0045] The second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer are removed by alkaline etching, and the light-receiving surface of the silicon wafer is corroded to form a velvet surface, wherein the emissivity of the velvet surface is 6% to 8%.

[0046] Optionally, after the step of removing the oxide layer and the first mask layer, the method for preparing a solar cell further includes:

[0047] Depositing a first functional layer on the light-receiving surface of the silicon wafer, and depositing a second functional layer on the backlight surface of the silicon wafer;

[0048] A light-receiving surface electrode is fabricated on the light-receiving surface of the silicon wafer, and a backlight surface electrode is fabricated on the backlight surface of the silicon wafer; wherein the light-receiving surface electrode penetrates the first functional layer and is in ohmic contact with the second doped silicon layer, and the backlight surface electrode penetrates the second functional layer and is in ohmic contact with the first doped silicon layer.

[0049] Optionally, the first dielectric layer is a silicon oxide layer;

[0050] And / or, the thickness of the first dielectric layer is 0.1 nm to 5 nm;

[0051] and / or, the thickness of the first doped silicon layer is 230 nm to 270 nm;

[0052] And / or, the thickness of the first mask layer is 15 nm to 25 nm;

[0053] And / or, the second dielectric layer is a silicon oxide layer;

[0054] And / or, the thickness of the second dielectric layer is 0.1 nm to 5 nm;

[0055] and / or, the thickness of the second doped silicon layer is 100 nm to 140 nm;

[0056] And / or, the thickness of the second mask layer is 5 nm to 15 nm.

[0057] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared by the solar cell preparation method as described in the first aspect.

[0058] In a third aspect, an embodiment of the present application provides a photovoltaic module comprising the solar cell as described in the second aspect.

[0059] Compared with the prior art, the present invention has the following beneficial effects:

[0060] The present invention provides a method for preparing a solar cell. The method uses laser oxidation to form a local oxide layer as a mask for forming a local passivation contact structure. The local mask formation requires only one step, while the acid-resistant slurry method requires at least three steps: printing the slurry, etching the mask, and cleaning the slurry. In other words, the method has fewer steps than the acid-resistant slurry method and does not produce wastewater from cleaning the slurry, making it more environmentally friendly.

[0061] Furthermore, the solar cell fabrication method reduces the oxygen concentration in the annealing environment by introducing nitrogen or an inert gas into the annealing environment, thereby reducing the probability of oxygen diffusion into the second doped silicon layer. However, the presence of oxygen in the annealing environment is difficult to avoid, for example, when the furnace door is opened and closed. The present application utilizes a second mask layer to isolate the second doped silicon layer from the annealing environment, thereby preventing any oxygen present in the annealing environment from contacting the second doped silicon layer. This facilitates the accuracy of the oxide layer produced by subsequent laser oxidation, thereby further increasing the precision of the resulting locally passivated contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0063] FIG1 is a flow chart of a method for preparing a solar cell according to Example 1;

[0064] FIG2 is a schematic diagram of step S1 of Example 1;

[0065] FIG3 is a schematic diagram of step S2 of Example 1;

[0066] FIG4 is a schematic diagram of step S3 of Example 1;

[0067] FIG5 is a schematic diagram of step S4 of Example 1;

[0068] FIG6 is a schematic diagram of step S6 of Example 1;

[0069] FIG7 is a schematic diagram of step S8 of Example 1;

[0070] FIG8 is a schematic diagram of step S9 of Example 1;

[0071] FIG9 is a schematic diagram of step S10 of Example 1;

[0072] FIG10 is a schematic diagram of step S11 of Example 1;

[0073] FIG11 is a schematic diagram of step S12 of Example 1;

[0074] FIG12 is a schematic diagram of step S13 of Example 1;

[0075] FIG13 is a schematic diagram of step S14 of Example 1;

[0076] FIG14 is a schematic diagram of step S15 of Example 1.

[0077] Explanation of the accompanying drawings: 100, solar cell; 101, silicon wafer; 1011, light-receiving surface; 1012, backlight surface; 1013, edge; 102, first dielectric layer; 103, P-type doped silicon layer; 104, first mask layer; 105, second dielectric layer; 106, N-type doped silicon layer; 107, second mask layer; 108, oxide layer; 109, first functional layer; 110, second functional layer; 111, light-receiving surface electrode; 112, backlight surface electrode. DETAILED DESCRIPTION

[0078] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0079] In the present invention, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may or may not be the same in type and configuration), and are not intended to indicate or imply the relative importance or quantity of the devices, elements, or components indicated. Unless otherwise specified, "plurality" means two or more.

[0080] Passivated contact solar cells utilize a passivation contact structure composed of an ultra-thin dielectric layer and a doped polysilicon layer on the back of a silicon wafer to achieve excellent surface passivation and selective carrier collection. However, the light-receiving side of this type of cell is still in direct contact between the metal and the semiconductor. Recombination losses at the contact between the metal and the semiconductor limit further improvements in cell efficiency. This problem can be avoided by using a double-sided passivation contact structure, that is, passivation contact structures are provided on both the light-receiving and backlight sides of the cell. Although the passivation contact structure can significantly reduce metallization recombination, the light absorption characteristics of the polysilicon layer of the light-receiving passivation contact structure will affect the cell's absorption of light, so the light-receiving passivation contact structure needs to be made into a local passivation contact structure.

[0081] The method of making a local passivation contact structure on the light-receiving surface can adopt the paste printing method. Taking N-type batteries as an example, the light-receiving surface is formed into a PN junction by boron doping, and then a tunneling oxide layer and a P-type doping layer are deposited on it. Then, the acid-resistant paste method is used to print and dry the paste in the metallized contact area, etch part of the P-type doping layer, and then clean the paste to form a local P-type doping layer in the downstream process. The overall process steps are relatively complex. The preparation steps of the local passivation contact structure and PN junction of the entire light-receiving surface require 5-6 steps. In addition, the wet etching cleaning machine and printing machine occupy a large area, the equipment investment cost is high, and it takes a long time. The wastewater generated by cleaning the acid-resistant paste is difficult to treat and is prone to environmental problems.

[0082] More importantly, the inventors of the present application have discovered that although laser oxidation can be used to produce a local passivation contact structure, the uniformity and pattern accuracy of the oxide layer formed on the doped polysilicon layer during the laser oxidation process are difficult to control, resulting in the problem of low pattern accuracy in the local passivation contact structure. Since the doped polysilicon layer in the passivation contact structure is formed by annealing and crystallizing a doped amorphous silicon layer, and the presence of oxygen in the annealing environment is unavoidable, the oxygen element during the annealing process will diffuse into the doped polysilicon layer, resulting in an uneven distribution of oxygen concentration in the doped polysilicon layer, and even causing the oxide layer to form prematurely. The above situation results in an inaccurate pattern of the oxide layer formed on the doped polysilicon layer after laser oxidation, which in turn affects the subsequent pattern etching, and the local passivation contact structure cannot be accurately produced.

[0083] Based on the analysis of the above problems, the embodiment of the present application proposes a method for preparing solar cells, which can produce a high-precision local passivation contact structure, and has fewer production steps compared to the acid-resistant slurry method. The production process does not use acid-resistant slurry, and no wastewater is generated for cleaning the acid-resistant slurry.

[0084] The technical solution of the present invention will be described below with reference to embodiments and drawings.

[0085] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0086] Depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence on a backlit surface of a silicon wafer of a first conductivity type facing away from the silicon wafer; wherein the first conductivity type and the second conductivity type are opposite;

[0087] Depositing a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer on the light-receiving surface of the silicon wafer, which are arranged in sequence away from the silicon wafer;

[0088] Filling nitrogen or an inert gas into the annealing environment, annealing and crystallizing the first doped silicon layer and the second doped silicon layer in the annealing environment; wherein the second mask layer is used to isolate the second doped silicon layer from the annealing environment;

[0089] removing the second mask layer on the light-receiving surface of the silicon wafer to expose a side of the second doped silicon layer facing away from the second dielectric layer;

[0090] irradiating the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on the side of the second doped silicon layer facing away from the second dielectric layer;

[0091] removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer;

[0092] The oxide layer and the first mask layer are removed.

[0093] Because the annealing process uses high temperatures, there is a possibility that oxygen in the annealing environment will diffuse into the doped silicon layer. This solar cell preparation method reduces the concentration of oxygen in the annealing environment by filling it with nitrogen or an inert gas, thereby reducing the probability of oxygen diffusion into the second doped silicon layer. However, the presence of oxygen in the annealing environment is difficult to avoid. For example, opening and closing the furnace door introduces air and oxygen. This application also utilizes a second mask layer to separate the second doped silicon layer from the annealing environment to prevent any oxygen in the annealing environment from contacting the second doped silicon layer. This facilitates the accuracy of the oxide layer produced by subsequent laser oxidation, thereby increasing the accuracy of the resulting locally passivated contact structure.

[0094] Finally, laser oxidation is performed in an oxygen environment to form a local oxide layer as an etching mask layer to replace the acid-resistant slurry. The term "oxygen environment" refers to an environment containing oxygen, such as air.

[0095] It should be noted that it is difficult to ensure the accuracy of the oxide layer produced by laser oxidation by only filling nitrogen or inert gas without setting a second mask layer to block oxygen diffusion, or only setting a second mask layer without introducing nitrogen or inert gas to reduce the oxygen concentration in the annealing environment. Inaccurate oxide layer patterns may still occur, thereby affecting the performance of solar cells.

[0096] In other words, the present application combines the introduction of nitrogen or an inert gas with the provision of a second mask layer to achieve a precise pattern of the local oxide layer produced by laser oxidation.

[0097] In addition, a local mask layer can also be formed by the acid-resistant slurry method. Taking the N-type battery as an example, the light-receiving surface is doped with boron to form a PN junction, and then a dielectric layer and a P-type doped layer are deposited on it. The acid-resistant slurry method is then used to print and dry the slurry in the metallized contact area, etch part of the P-type doped layer, and then the slurry is cleaned to form a local P-type doped layer, which is then passed on to the subsequent process. The overall process steps are relatively complicated. The preparation steps of the local passivation contact structure and the PN junction of the entire light-receiving surface require 5-6 steps, and the wet etching cleaning machine and printing machine occupy a large area, the equipment investment cost is high, and it takes a long time. The wastewater generated by cleaning the acid-resistant slurry is difficult to treat and is prone to environmental problems.

[0098] In other words, the acid-resistant slurry method requires at least three steps to form a local mask layer: printing the acid-resistant slurry, etching the mask layer, and cleaning the acid-resistant slurry, while the laser oxidation method only requires one step to form a local oxide layer. This application uses laser oxidation to produce a localized passivated contact structure. Compared to the acid-resistant slurry method, this application's preparation steps are simpler, the preparation process is shorter, and the laser oxidation method does not produce wastewater.

[0099] On the other hand, the above-mentioned acid-resistant slurry method requires two high-temperature processes, namely, boron doping to form a PN junction and annealing of the P-type doped layer after deposition. However, the present application activates the doped elements in the first doped silicon layer and the second doped silicon layer through a single annealing, which makes the process simpler and more energy-efficient. In addition, even if there is a coating around the backlight side of the second doped silicon layer, the first mask layer prevents the doped elements of the second doped silicon layer from diffusing into the first doped silicon layer during the annealing process, that is, the first mask layer protects the first dielectric layer and the first doped silicon layer during the etching process, and can also prevent element doping.

[0100] It should be noted that one of the first conductivity type and the second conductivity type is N-type and the other is P-type. More specifically, the silicon wafer in this application is an N-type silicon wafer or a P-type silicon wafer. When the silicon wafer is an N-type silicon wafer, the first doped silicon layer is a P-type doped silicon layer, and the second doped silicon layer is an N-type doped silicon layer. When the silicon wafer is a P-type silicon wafer, the first doped silicon layer is an N-type doped silicon layer, and the second doped silicon layer is a P-type doped silicon layer.

[0101] When the present application adopts PECVD or LPCVD to deposit the second dielectric layer, the second doped silicon layer and the second mask layer, it is inevitable that a wrap-around coating will be formed on the backlight surface and edge of the silicon wafer. In order to avoid the wrap-around coating affecting the performance of the solar cell, such as the edge leakage problem caused by the connection of two wrap-around coatings with opposite conductivity types, it is necessary to remove the wrap-around coating.

[0102] When removing the wrap-around coating of the second mask layer on the backlight side, the first mask layer on the backlight side is also exposed to etching. If the first mask layer is removed at the same time, then when the wrap-around coating of the second dielectric layer and the second doped silicon layer is subsequently removed, the first dielectric layer and the first doped silicon layer on the backlight side will be exposed to etching, thereby causing the structure of the solar cell to be destroyed.

[0103] In order to avoid the above situation, before the step of removing the second mask layer on the light-receiving surface of the silicon wafer to expose the side of the second doped silicon layer facing away from the second dielectric layer, the method for preparing a solar cell further includes:

[0104] The second mask layer on the backlight surface and the edge of the silicon wafer is removed, and the second mask layer on the light-receiving surface of the silicon wafer is retained.

[0105] By covering the light-receiving surface of the silicon wafer with the second mask layer, the second dielectric layer and the second doped silicon layer on the backlight surface and edge of the silicon wafer are removed, and a partial thickness of the first mask layer on the backlight surface of the silicon wafer is retained.

[0106] The retained partial thickness of the first mask layer protects the first dielectric layer and the first doped silicon layer on the backlight surface when the surrounding coating of the second dielectric layer and the second doped silicon layer is subsequently removed. In addition, in the step of removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer, the retained partial thickness of the first mask layer can also protect the first dielectric layer and the first doped silicon layer on the backlight surface.

[0107] Optionally, the step of removing the second mask layer on the backlight side and the edge of the silicon wafer, and retaining the second mask layer on the light-receiving side of the silicon wafer and a partial thickness of the first mask layer on the backlight side, includes:

[0108] Use hydrofluoric acid with a mass percentage concentration of x% to clean the backlight surface and edge of the silicon wafer, and control the cleaning time t1 to satisfy: t2≤t1<t3; where t2 is the time required for the wrap-around coating of the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%.

[0109] It can be understood that the present application sets the difference in time required to completely remove the wrap-around coating of the first mask layer and the second mask layer, and controls the etching time. When the wrap-around coating of the second mask layer is completely etched, the etching is stopped to retain a partial thickness of the first mask layer.

[0110] Optionally, the thickness of the first mask layer is greater than the thickness of the wrap-around plating layer of the second mask layer;

[0111] And / or, in a hydrofluoric acid solution of the same concentration, the etching rate of the first mask layer is lower than the etching rate of the wrap-around coating of the second mask layer.

[0112] It is understood that if the thickness of the first mask layer is greater than that of the second mask layer, even if the two mask layers are made of the same material, in a hydrofluoric acid solution of the same concentration, the time required to completely remove the first mask layer will still be greater than the time required to completely remove the second mask layer. If the first mask layer is more acid-resistant than the second mask layer, that is, the etching rate of the first mask layer is lower than the etching rate of the second mask layer, even if the two mask layers are of the same thickness, the time required to completely remove the first mask layer will still be greater than the time required to completely remove the second mask layer.

[0113] Furthermore, the step of filling nitrogen or an inert gas into the annealing environment and annealing and crystallizing the first doped silicon layer and the second doped silicon layer in the annealing environment includes:

[0114] Filling the annealing environment with nitrogen or inert gas to normal pressure to reduce the oxygen concentration in the annealing environment;

[0115] Place the silicon wafer into the annealing environment;

[0116] The temperature in the annealing environment is raised to 780℃~820℃ and the pressure is reduced to 28KPa~32KPa;

[0117] The annealing environment is filled with nitrogen or inert gas to 78KPa~82KPa to reduce the concentration of oxygen in the annealing environment;

[0118] The annealing environment continues to heat up to 900℃~920℃;

[0119] The first doped silicon layer and the second doped silicon layer are annealed at 900° C. to 920° C.;

[0120] The annealing environment is cooled to 700℃~740℃;

[0121] The annealing environment is filled with nitrogen or inert gas to normal pressure to reduce the concentration of oxygen in the annealing environment;

[0122] Remove the silicon wafer.

[0123] Optionally, the inert gas in this application refers to the gaseous substances corresponding to all Group 0 elements on the periodic table, such as helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc.

[0124] Before placing the silicon wafers, the furnace is filled with nitrogen or an inert gas to atmospheric pressure to facilitate opening the furnace door and prevent a large amount of air from entering the annealing environment when the door is opened, which could lead to excessive oxygen concentrations in the annealing environment. The term "annealing environment" refers to the environment in which the silicon wafers are annealed, such as the space within the furnace tube. The annealing environment is then heated to 780°C to 820°C and pressure is reduced to 28 kPa to 32 kPa. A leak check is then performed to prevent air from entering the annealing environment. After annealing is complete, the temperature is lowered and nitrogen or an inert gas is then filled back to atmospheric pressure to prevent air from entering the annealing environment when the furnace door is opened, potentially affecting the next annealing process.

[0125] Furthermore, in order to avoid the laser melting the second doped silicon layer, thereby damaging the second doped silicon layer and causing an inaccurate oxide layer, in the step of irradiating the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on a side of the second doped silicon layer facing away from the second dielectric layer, the temperature of the heated area formed by the laser on the second doped silicon layer is lower than the melting point of the second doped silicon layer;

[0126] In which, the frequency of the laser is 1800KHz~2200KHz, including any value within the frequency range, for example, 1800KHz, 2000KHz or 2200KHz; the line width of the laser is 70μm~100μm, including any value within the line width range, for example, 70μm, 90μm or 100μm, and the power of the laser is 10W~20W, including any value within the power range, for example, 10W, 15W or 20W.

[0127] Furthermore, before the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence on the backlight side of the silicon wafer of the first conductivity type, facing away from the silicon wafer, the method for preparing a solar cell further includes:

[0128] Polishing the light-receiving surface and the backlight surface of the silicon wafer; wherein the reflectivity of the light-receiving surface and the backlight surface of the silicon wafer is controlled at 40% to 50%;

[0129] The polished morphology is beneficial to the subsequent deposition of film layers.

[0130] Furthermore, the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence and facing away from the silicon wafer on the backlight side of the silicon wafer of the first conductivity type includes:

[0131] growing a first dielectric layer;

[0132] sequentially growing an intrinsic silicon layer and one or more in-situ doped layers;

[0133] A first mask layer is grown.

[0134] As described above, when the present application adopts PECVD or LPCVD to deposit the first dielectric layer, the first doped silicon layer and the first mask layer, it is inevitable that a wrap-around layer will be formed on the light-receiving surface and edge of the silicon wafer. In order to avoid the wrap-around layer affecting the performance of the solar cell, such as the connection of two wrap-around layers with opposite conductivity types, which may cause edge leakage problems, it is necessary to remove the wrap-around layer.

[0135] Furthermore, after depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence on the backlight side of the silicon wafer of the first conductivity type, facing away from the silicon wafer, the method for preparing a solar cell further includes:

[0136] The wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer is removed, and the first mask layer on the backlight surface is retained.

[0137] By covering the first mask layer on the backlight surface, removing the wrap-around layers of the first dielectric layer and the first doped silicon layer on the light-receiving surface and edge of the silicon wafer;

[0138] Etching the silicon wafer to form a polished surface on the light-receiving side;

[0139] The influence of the wrap-around coating is eliminated by removing the wrap-around coating, and the polishing morphology is formed again, which is beneficial to the production of the film layer on the backlight surface.

[0140] Furthermore, the step of depositing a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer on the light-receiving surface of the silicon wafer, which are arranged in sequence away from the silicon wafer, includes:

[0141] A second dielectric layer, an in-situ doped second doped silicon layer and a second mask layer are grown in sequence.

[0142] It can be seen from this that the present application is a double-sided passivation contact structure with better passivation effect.

[0143] Furthermore, the step of removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer includes:

[0144] The second doped silicon layer outside the oxide layer coverage is removed by alkali etching, the laser oxide layer and the second dielectric layer are removed by hydrofluoric acid, and the light-receiving surface of the silicon wafer is corroded to form a velvet surface with an emissivity of 6% to 8%.

[0145] A local passivation contact structure is made and further etched into the silicon wafer to remove the doping element diffusion area outside the local passivation contact structure. Only the diffusion area is formed in the area where the local passivation contact structure is located. At the same time, a velvet surface is made without the need for additional velvet making to further simplify the process flow. The formed velvet surface can improve the light trapping effect of the silicon wafer.

[0146] Furthermore, after the step of removing the oxide layer and the first mask layer, the method for preparing a solar cell further includes:

[0147] Depositing a first functional layer on the light-receiving side of the silicon wafer and depositing a second functional layer on the backlight side of the silicon wafer;

[0148] A light-receiving surface electrode is fabricated on the light-receiving surface of the silicon wafer, and a backlight surface electrode is fabricated on the backlight surface of the silicon wafer; wherein the light-receiving surface electrode penetrates the first functional layer and is in ohmic contact with the second doped silicon layer, and the backlight surface electrode penetrates the second functional layer and is in ohmic contact with the first doped silicon layer.

[0149] Optionally, the first dielectric layer and the second dielectric layer may include one or more dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a film with excellent durability for subsequent high-temperature processes.

[0150] The first and second dielectric layers act as a barrier between electrons and holes, combining with the polysilicon layer to prevent minority carriers from passing through. They can also function as pinhole channels, allowing carriers within the solar cell to move freely. The heavily doped polysilicon selectively allows majority carriers to pass through, thus reducing minority carrier recombination losses. Furthermore, the first and second dielectric layers can act as diffusion barriers to prevent dopants from the doped polysilicon layer from diffusing into the semiconductor substrate.

[0151] Preferably, the first dielectric layer is a silicon oxide layer;

[0152] And / or, the thickness of the first dielectric layer is 0.1 nm to 5 nm, including any value within the thickness range, for example, 0.1 nm, 3 nm, 4 nm or 5 nm;

[0153] And / or, the thickness of the first doped silicon layer is 230 nm to 270 nm, including any value within the thickness range, for example, 230 nm, 250 nm or 270 nm;

[0154] and / or, the thickness of the first mask layer is 15 nm to 25 nm, including any value within the thickness range, for example, 15 nm, 20 nm or 25 nm;

[0155] And / or, the second dielectric layer is a silicon oxide layer;

[0156] And / or, the thickness of the second dielectric layer is 0.1 nm to 5 nm, including any value within the thickness range, for example, 0.1 nm, 1 nm, 2 nm, 3 nm or 5 nm;

[0157] And / or, the thickness of the second doped silicon layer is 100 nm to 140 nm, including any value within the thickness range, for example, 100 nm, 120 nm or 140 nm;

[0158] and / or, the second mask layer has a thickness of 5 nm to 15 nm, including any value within the thickness range, for example, 5 nm, 10 nm or 15 nm;

[0159] And / or, the second mask layer is a silicon dioxide layer or a silicon oxynitride layer.

[0160] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared by the solar cell preparation method as described in the first aspect.

[0161] The solar cell manufactured in the present application includes a silicon wafer, wherein a second dielectric layer and a second doped silicon layer are sequentially stacked and disposed away from the wafer on the light-receiving surface of the silicon wafer, wherein the local second doped silicon layer and the local second dielectric layer constitute a local passivation contact structure. The backlight surface of the silicon wafer also includes a second dielectric layer, a second doped silicon layer of a first conductivity type, and a second mask layer, which are sequentially disposed away from the wafer.

[0162] First, the solar cell manufactured in this application has double-sided passivation contact, that is, both the light-receiving side and the backlight side of the solar cell use polysilicon layers and dielectric layers to passivate the metal areas, thereby improving the opening voltage of the solar cell.

[0163] The passivation contact structure of the light-receiving surface of the present application is made into a local passivation contact structure, which reduces the area of ​​the second doped silicon layer with poor light transmittance to avoid the second doped silicon layer with poor light transmittance covering the entire light-receiving surface and affecting the solar cell's absorption of light, which is beneficial to improving the efficiency of the solar cell.

[0164] The solar cell prepared in the present application is a back junction cell, which forms a PN junction with the silicon wafer through the first doped silicon layer on the backlight surface. In the related art, since the lateral resistance of the emitter seriously affects the resistance of the solar cell, and the lateral resistance of the emitter is inversely proportional to the square of the spacing between the fine grid lines of the emitter, in order to reduce the lateral resistance of the emitter, the number of grid lines is increased to reduce the spacing between the grid lines. When the emitter is set on the light-receiving surface, increasing the number of grid lines will affect the absorption of light by the light-receiving surface, which is not conducive to the conversion efficiency of the battery. The emitter of the solar cell prepared in the present application is located on its backlight surface. In order to reduce the lateral resistance of the emitter, the number of grid lines on the backlight surface can be increased. Therefore, there is no high requirement for the number of grid lines on the light-receiving surface, which is more conducive to the distribution design of the grid lines on the light-receiving surface and the backlight surface. By reducing the number of grid lines on the light-receiving surface, the amount of silver paste used can be reduced, thereby reducing costs, which is conducive to improving the efficiency of the solar cell and reducing the metallization cost. In addition, reducing the number of grid lines on the light-receiving surface can also simplify the pattern of the light-receiving surface electrode. Since the pattern of the poly film layer structure on the light-receiving surface is the same as the pattern of the light-receiving surface electrode, the difficulty of manufacturing the patterned second doped polysilicon layer and the patterned second dielectric layer can be reduced, thereby improving the manufacturing yield.

[0165] In a third aspect, an embodiment of the present application provides a photovoltaic module comprising the solar cell as described in the second aspect.

[0166] The technical solution of the present invention will be described below with reference to embodiments and drawings.

[0167] Example 1

[0168] Referring to FIG1 , the method for preparing a solar cell provided in this embodiment comprises the following steps:

[0169] S1. Polishing the light-receiving surface and the backlight surface of the silicon wafer: As shown in FIG2 , alkaline solution is used to polish the light-receiving surface 1011 and the backlight surface 1012 of the N-type silicon wafer 101. First, NaOH and H2O2 are used to remove some organic dirt on the surface of the silicon wafer and etch the damaged layer. The silicon wafer is cleaned with pure water to remove reaction byproducts, and then NaOH and additives are used to etch the silicon wafer to form a polished surface. NaOH and H2O2 are used again to remove organic dirt on the surface of the silicon wafer 101. After cleaning with pure water, the wafer is placed in an HCl tank to remove metal ions. After cleaning with pure water and drying, the wafer is transferred to the next process. The reflectivity is controlled at 45%±5%.

[0170] S2. Depositing a first dielectric layer, a first doped silicon layer of the second conductive type, and a first mask layer on the backlight surface of the silicon wafer of the first conductive type, which are stacked in sequence away from the silicon wafer: As shown in Figure 3, a PECVD device is used to sequentially grow a first dielectric layer 102, a P-type doped silicon layer 103, and a first mask layer 104 on the backlight surface 1012; wherein, the first dielectric layer 102 is made of silicon oxide, and the thickness of the first dielectric layer 102 is controlled to be 4nm; the P-type doped silicon layer 103 is the first doped silicon layer of the second conductive type, and the thickness of the P-type doped silicon layer is controlled to be 250nm, the depth is 230nm, and the square resistance is controlled to be 90Ω / sq. The P-type doped silicon layer 103 is completed by sequentially depositing an intrinsic silicon layer, a first in-situ doped layer, a second in-situ doped layer, and a third in-situ doped layer on the first dielectric layer; the thickness of the first mask layer 104 is controlled to be 20±5nm.

[0171] S3. Remove the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer, and retain the first mask layer on the backlight surface: As shown in Figure 4, use HF to remove the wrap-around coating of the first mask layer 104 on the light-receiving surface 1011 and edge 1013 of the silicon wafer 101, and retain the first mask layer 104 on the backlight surface 1012.

[0172] S4. By covering with the first mask layer on the backlight surface, the coating layers of the first dielectric layer and the first doped silicon layer on the light-receiving surface and edge of the silicon wafer are removed: As shown in Figures 4 and 5, the coating layers of the first dielectric layer 102 and the P-type doped silicon layer 103 on the light-receiving surface 1011 and edge 1013 of the silicon wafer 101 are removed using alkaline solution.

[0173] S5. Etching the silicon wafer to form a polished surface on the light-receiving surface: Use NaOH and additives to etch the light-receiving surface 1011 of the silicon wafer 101 to form a polished surface; again use NaOH and H2O2 to remove some organic dirt on the surface of the silicon wafer, clean and dry with pure water, and transfer to the next process. The reflectivity is controlled at 45% ± 5%.

[0174] S6. Depositing a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer on the light-receiving surface of the silicon wafer in sequence, which are arranged away from the silicon wafer: As shown in FIG6 , a PECVD device is used to deposit a second dielectric layer 105, an N-type doped silicon layer 106, and a second mask layer 107 on the light-receiving surface 1011 in sequence; wherein, the second dielectric layer 105 is made of silicon oxide, and the thickness of the second dielectric layer 105 is controlled to be 2 nm; the N-type doped silicon layer 106 is the second doped silicon layer, and the thickness of the N-type doped silicon layer 106 is controlled to be 120±20 nm, the depth is 100 nm, and the square resistance is 25 Ω / sq; the thickness of the second mask layer 107 is 10 nm.

[0175] S7. Fill nitrogen into the annealing environment, and anneal and crystallize the first doped silicon layer and the second doped silicon layer in the annealing environment; wherein the second mask layer is used to separate the second doped silicon layer from the annealing environment: first, ensure that the furnace tube is at normal pressure and the furnace door is easy to open; open the furnace door, place the boat with the silicon wafer 101 into the furnace tube, that is, into the annealing environment, and close the furnace door; raise the temperature in the furnace tube to 800°C, pump down the pressure to 30KPa, and check whether the furnace tube is leaking; Nitrogen is filled into the furnace tube to 80 kPa, and the temperature is continuously raised to 840° C., then to 860° C., and finally to 910° C. to stabilize the temperature; the N-type doped silicon layer 106 and the P-type doped silicon layer 103 are annealed at 910° C. After the annealing is completed, the temperature is first lowered to 850° C., then to 720° C., nitrogen is filled into the furnace tube to normal pressure, and the temperature is simultaneously lowered to 680° C., and the temperature is further lowered to 620° C., the furnace door is opened, the boat is dragged out of the furnace tube, and the furnace door is closed.

[0176] S8. Remove the wrap-around coating of the second mask layer on the backlight side and the edge of the silicon wafer, retaining the second mask layer on the light-receiving side of the silicon wafer and a portion of the first mask layer on the backlight side: As shown in FIG7 , HF is used to remove the wrap-around coating of the second mask layer 107 on the backlight side 1012 and the edge 1013 of the silicon wafer 101. The thickness of the first mask layer 104 is greater than the thickness of the wrap-around coating of the second mask layer 107. After the wrap-around coating of the second mask layer 107 is completely removed, etching is stopped, retaining a portion of the thickness of the first mask layer 104.

[0177] S9. By covering the light-receiving surface of the silicon wafer with the second mask layer, the second dielectric layer and the second doped silicon layer on the backlight surface and edge of the silicon wafer are removed: As shown in FIG8 , an alkaline solution is used to remove the wrap-around layer of the N-type doped silicon layer 106 on the backlight surface 1012 and edge 1013 of the silicon wafer 101, and the wrap-around layer of the second dielectric layer 105 on the edge 1013 of the silicon wafer 101 is removed. Since the second dielectric layer 105 is formed by oxidizing the silicon wafer using an oxygen source, and the oxygen source does not react with the first mask layer 104, the second dielectric layer 105 has no wrap-around layer on the backlight surface 1012, and the second dielectric layer 105 may have a wrap-around layer on the edge of the P-type doped silicon layer 103.

[0178] S10. Remove the second mask layer on the light-receiving surface of the silicon wafer to expose the side of the second doped silicon layer facing away from the second dielectric layer. As shown in FIG8 and FIG9 , use HF to remove the second mask layer 107 on the light-receiving surface 1011. Rinse and dry with pure water, and transfer to the next process. The reflectivity of the light-receiving surface 1011 is controlled at 45%±5%.

[0179] S11. In an oxygen environment, a laser is used to irradiate the light-receiving surface of the silicon wafer to form a local oxide layer on the side of the second doped silicon layer facing away from the second dielectric layer: as shown in FIG10 , low-energy laser oxidation is performed on a local area of ​​the light-receiving surface 1011 using a femtosecond laser. The temperature of the heated area formed by the laser on the N-type doped silicon layer 106 is lower than the melting point of the N-type doped silicon layer 106. Specifically, the frequency of the laser is 2000 kHz, the line width of the laser is 80 μm, the spot is square, and the power of the laser is 15 W, thereby inducing the formation of a local oxide layer 108 on the side of the N-type doped silicon layer 106 facing away from the second dielectric layer 105.

[0180] S12. Remove the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer: As shown in FIG11 , an alkaline solution etching method is used to etch the N-type doped silicon layer 106 and the second dielectric layer 105 outside the coverage of the oxide layer 108. NaOH and additives corrode the silicon wafer 101 and form a velvet surface on the light-receiving surface 1011. The reflectivity of the velvet surface is controlled at 6% to 8%.

[0181] S13, removing the oxide layer and the first mask layer: as shown in FIG11 and FIG12, using HF to remove the oxide layer 108 on the light-receiving surface 1011 and the first mask layer 104 on the backlight surface 1012, and using HCl to perform RCA cleaning.

[0182] S14. Depositing a first functional layer on the light-receiving surface of the silicon wafer and depositing a second functional layer on the backlight surface of the silicon wafer: As shown in FIG13 , silicon nitride is deposited on the light-receiving surface 1011 to form a first functional layer 109 , and silicon nitride is deposited on the backlight surface 1012 to form a second functional layer 110 .

[0183] S15. A light-receiving surface electrode is fabricated on the light-receiving surface of the silicon wafer, and a backlight surface electrode is fabricated on the backlight surface of the silicon wafer: as shown in FIG14 , the light-receiving surface 1011 is screen-printed with slurry and then metallized to form a light-receiving surface electrode 111, and the backlight surface 1012 is screen-printed with slurry and then metallized to form a backlight surface electrode 112; wherein, the light-receiving surface electrode 111 penetrates the first functional layer 109 and makes ohmic contact with the N-type doped silicon layer 106, and the backlight surface electrode 112 penetrates the second functional layer 110 and makes ohmic contact with the P-type doped silicon layer 103.

[0184] Example 2

[0185] The steps of preparing the solar cell provided in this embodiment are as follows:

[0186] S1. Polishing the light-receiving and back-lighting surfaces of the silicon wafer: Use alkaline solution to polish the light-receiving and back-lighting surfaces of the P-type silicon wafer 101. First, use NaOH and H2O2 to remove some organic dirt on the surface of the silicon wafer and etch the damaged layer; use pure water to clean the silicon wafer to remove reaction by-products, and then use NaOH and additives to corrode the silicon wafer to form a polished surface; use NaOH and H2O2 again to remove organic dirt on the surface of the silicon wafer, rinse with pure water, and then enter the HCl tank to complete the removal of metal ions. After pure water cleaning and drying, it flows to the next process, and the reflectivity is controlled at 45%±5%.

[0187] S2. Depositing a first dielectric layer, a first doped silicon layer of the second conductive type, and a first mask layer on the backlight surface of a silicon wafer of the first conductive type, which are stacked in sequence away from the silicon wafer: using PECVD equipment to sequentially grow the first dielectric layer, the N-type doped silicon layer, and the first mask layer on the backlight surface; wherein the first dielectric layer is made of silicon oxide, and the thickness of the first dielectric layer is controlled to be 1.5nm; the N-type doped silicon layer is the first doped silicon layer of the second conductive type, and the thickness of the N-type doped silicon layer is controlled to be 130nm, the depth is 130nm, and the square resistance is controlled to be 100Ω / sq. The N-type doped silicon layer is completed by sequentially depositing an intrinsic silicon layer, a first in-situ doped layer, a second in-situ doped layer, and a third in-situ doped layer on the first dielectric layer; the thickness of the first mask layer is controlled to be 10nm.

[0188] S3. Remove the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer, and retain the first mask layer on the backlight surface: Use HF to remove the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer, and retain the first mask layer on the backlight surface.

[0189] S4. Remove the wrap-around layers of the first dielectric layer and the first doped silicon layer on the light-receiving surface and edge of the silicon wafer by covering with the first mask layer on the backlight surface: Use alkaline solution to remove the wrap-around layers of the first dielectric layer and the N-type doped silicon layer on the light-receiving surface and edge of the silicon wafer.

[0190] S5. Etch the silicon wafer to form a polished surface on the light-receiving surface: Use NaOH and additives to etch the light-receiving surface of the silicon wafer to form a polished surface; use NaOH and H2O2 again to remove some organic dirt on the surface of the silicon wafer, clean and dry with pure water, and transfer to the next process. The reflectivity is controlled at 45%±5%.

[0191] S6. Deposit a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer on the light-receiving surface of the silicon wafer in sequence, which are arranged away from the silicon wafer: use PECVD equipment to deposit the second dielectric layer, the P-type doped silicon layer, and the second mask layer on the light-receiving surface in sequence; wherein, the second dielectric layer is made of silicon oxide, and the thickness of the second dielectric layer is controlled to be 4nm; the P-type doped silicon layer is the second doped silicon layer, and the thickness of the P-type doped silicon layer is controlled to be 300±20nm, the depth is 280nm, and the square resistance is 15Ω / sq; the thickness of the second mask layer is 25nm.

[0192] S7. Fill nitrogen into the annealing environment, and anneal and crystallize the first doped silicon layer and the second doped silicon layer in the annealing environment; wherein the second mask layer is used to separate the second doped silicon layer from the annealing environment: first, ensure that the furnace tube is at normal pressure and the furnace door is easy to open; open the furnace door, place the boat with the silicon wafer into the furnace tube, that is, into the annealing environment, and close the furnace door; raise the temperature in the furnace tube to 800°C, pump down the pressure to 30KPa, and check whether the furnace tube is leaking; Nitrogen is filled into the furnace tube to 80 kPa, and the temperature is continuously raised to 840° C., then to 860° C., and finally to 910° C. to stabilize the temperature; the P-type doped silicon layer 106 and the N-type doped silicon layer are annealed at 910° C. After the annealing is completed, the temperature is first lowered to 850° C., then to 720° C., nitrogen is filled into the furnace tube to normal pressure, and the temperature is simultaneously lowered to 680° C., and the temperature is further lowered to 620° C., the furnace door is opened, the boat is dragged out of the furnace tube, and the furnace door is closed.

[0193] S8. Remove the wrap-around coating of the second mask layer on the backlight side and edge of the silicon wafer, retaining the second mask layer on the light-receiving side of the silicon wafer and a portion of the first mask layer on the backlight side: Use HF to remove the wrap-around coating of the second mask layer on the backlight side and edge of the silicon wafer. The thickness of the first mask layer is greater than the thickness of the wrap-around coating of the second mask layer. After the wrap-around coating of the second mask layer is completely removed, etching is stopped, retaining a portion of the first mask layer.

[0194] S9. Remove the second dielectric layer and the second doped silicon layer on the backlight side and edge of the silicon wafer by covering the light-receiving surface of the silicon wafer with the second mask layer: use alkaline solution to remove the P-type doped silicon layer on the backlight side and edge of the silicon wafer, and remove the second dielectric layer on the edge of the silicon wafer. Since the second dielectric layer is formed by oxidizing the silicon wafer using an oxygen source, and the oxygen source does not react with the first mask layer, the second dielectric layer has no coating on the backlight side.

[0195] S10. Remove the second mask layer on the light-receiving surface of the silicon wafer to expose the side of the second doped silicon layer facing away from the second dielectric layer: use HF to remove the second mask layer on the light-receiving surface, clean and dry with pure water, and transfer to the next process. The reflectivity of the light-receiving surface is controlled at 45%±5%.

[0196] S11. Irradiate the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on the side of the second doped silicon layer facing away from the second dielectric layer: perform low-energy laser oxidation on the local area of ​​the light-receiving surface, using a femtosecond laser, and the temperature of the heated area formed by the laser on the P-type doped silicon layer is lower than the melting point of the P-type doped silicon layer; specifically, the frequency of the laser is 2000KHz, the line width of the laser is 80μm, the spot is square, and the power of the laser is 15W, inducing the formation of a local oxide layer on the side of the P-type doped silicon layer facing away from the second dielectric layer.

[0197] S12. Remove the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer: use alkaline solution etching to etch the P-type doped silicon layer and the second dielectric layer outside the coverage of the oxide layer, NaOH and additives corrode the silicon wafer and form a velvet surface on the light-receiving surface, and the reflectivity of the velvet surface is controlled at 6% to 8%.

[0198] S13, removing the oxide layer and the first mask layer: using HF to remove the oxide layer on the light-receiving surface and the first mask layer on the backlight surface, and using HCL to perform RCA cleaning.

[0199] S14. Depositing a first functional layer on the light-receiving surface of the silicon wafer and depositing a second functional layer on the backlight surface of the silicon wafer: depositing silicon nitride on the light-receiving surface to form the first functional layer and depositing silicon nitride on the backlight surface to form the second functional layer.

[0200] S15. A light-receiving surface electrode is fabricated on the light-receiving surface of the silicon wafer, and a backlight surface electrode is fabricated on the backlight surface of the silicon wafer: the light-receiving surface electrode is formed by screen-printing the slurry and then metallizing the slurry; the backlight surface electrode is formed by screen-printing the slurry and then metallizing the slurry; wherein, the light-receiving surface electrode penetrates the first functional layer to make ohmic contact with the P-type doped silicon layer, and the backlight surface electrode penetrates the second functional layer to make ohmic contact with the P-type doped silicon layer.

[0201] Example 3

[0202] The only difference between this embodiment and embodiment 1 is that in step S11 , the frequency of the laser is 1000 KHz, the line width of the laser is 150 μm, and the power of the laser is 5 W.

[0203] Example 4

[0204] The only difference between this embodiment and embodiment 1 is that in step S11 , the frequency of the laser is 3000 KHz, the line width of the laser is 50 μm, and the power of the laser is 30 W.

[0205] Comparative Example 1

[0206] The preparation method of the solar cell provided in this comparative example comprises the following steps:

[0207] Texturing: Use alkali and texturing additives at 80°C to etch N-type silicon wafers to a depth of 3μm and a reflectivity of 9.5%;

[0208] Boron diffusion on the light-receiving surface: Use high-temperature tubular equipment at 1060°C, introduce N2, O2, and BCl3 for boron diffusion, with a square resistance of 110Ω / sq and a junction depth of 1.0 micron to form BSG;

[0209] Backlight surface alkali polishing: First, use a chain HF device to remove the BSG on the backlight surface and edge, and then use a tank wet process device to polish the silicon wafer with 70°C alkali and polishing additives. The etching depth is 0.4 microns, and the reflectivity of the backlight surface is increased to 45%;

[0210] Backlight n-poly layer; use PECVD equipment to prepare a 1.5nm dielectric layer and a 120nm intrinsically doped n-poly layer and mask layer;

[0211] Annealing: Annealing at 910°C to crystallize the backlight side n-poly layer and activate the phosphorus in it;

[0212] Removal of light-receiving surface plating and cleaning: First, use chain HF equipment to remove the mask layer of the light-receiving surface plating, then use tank-type wet equipment to perform alkaline etching to remove the light-receiving surface plating of the n-poly layer, and then perform acid washing to remove the BSG on the light-receiving surface, the mask layer and dirt on the backlight side, etc.

[0213] Preparation of passivation film and anti-reflection film: 5nm aluminum oxide film + 80nm silicon nitride film is used as passivation and anti-reflection layer on the light-receiving side, and 90nm silicon nitride film is used as anti-reflection layer on the backlight side;

[0214] A light-receiving surface electrode is made on the light-receiving surface of the silicon wafer, and a backlight surface electrode is made on the backlight surface of the silicon wafer: the light-receiving surface is metallized with silver-aluminum paste to obtain the light-receiving surface electrode, and the backlight surface is metallized with back paste to obtain the backlight surface electrode.

[0215] Comparative Example 2

[0216] The only difference between this comparative example and Example 1 is that step S11 and step S12 are not performed, and in step S13 only the first mask layer needs to be removed.

[0217] Comparative Example 3

[0218] This comparative example differs only from Example 1 in that, in step S6, a second dielectric layer and an N-type doped silicon layer are sequentially deposited on the light-receiving surface using a PVD device, without depositing a second mask layer. Because PVD deposition is performed using a PVD device, the PVD method avoids the problem of wraparound plating, and thus, no wraparound plating layer is formed on the backlight side or edge of the silicon wafer. Therefore, steps S9 and S10 of Example 1 are omitted. That is, during the annealing process, no second mask layer isolates the second doped silicon layer from the annealing environment.

[0219] The solar cells prepared in Examples 1-4 and Comparative Examples 1-3 before the steps of fabricating the light-receiving surface electrode on the light-receiving surface of the silicon wafer and the backlight surface electrode on the backlight surface of the silicon wafer were passed through a sintering furnace with a sintering peak temperature of 860°C. The passivation performance of the solar cells, i.e., the passivation performance before metallization, was tested. The test results are shown in Table 1.

[0220] In Examples 1-4 and Comparative Examples 1-3, solar cells produced before the aforementioned steps of forming the light-receiving electrode on the light-receiving side of the silicon wafer and the backlight-receiving electrode on the backlight side of the silicon wafer were passed through a sintering furnace with a peak sintering temperature of 860°C and then subjected to light injection. The peak heating temperature of the solar cell during light injection was 670°C, and the light source used for light injection had a power of 50W. The passivation performance of the solar cells after light injection was tested. The test results are shown in Table 2.

[0221] The solar cells produced in Examples 1-4 and Comparative Examples 1-3, following the steps of forming the light-receiving electrode on the light-receiving surface of the silicon wafer and the backlight electrode on the backlight surface of the silicon wafer, were tested for IV performance after light injection. The test results are shown in Table 3. The peak heating temperature of the solar cells during light injection was 670°C, and the light source used for light injection had a power of 50 W.

[0222] Table 1: Passivation performance test results of solar cells before metallization of Examples 1-4 and Comparative Examples 1-3

[0223] Table 2: Test results of passivation performance after light injection before metallization of solar cells of Examples 1-4 and Comparative Examples 1-3

[0224] Table 3: IV electrical performance test results of solar cells of Examples 1-4 and Comparative Examples 1-3 after light injection

[0225] Referring to Tables 1 to 3, compared with the single-sided passivated contact of Comparative Example 1, Examples 1-4 are double-sided passivated contacts, and therefore have better passivation performance. Compared with Comparative Example 1, Examples 1-4 have a longer minority carrier lifetime (Lifetime), a smaller reverse saturation current density (J0), a higher theoretical opening voltage (iVoc), and a higher theoretical fill factor (iFF).

[0226] The improved passivation performance, the localized passivation contact structure on the light-receiving surface, and the back-side PN junction design resulted in higher conversion efficiency, short-circuit current, open-circuit voltage, and fill factor in Examples 1-4 than in Comparative Example 1, and lower series resistance. After the de-wrapping operations in Steps S4 and S9, the edge leakage in Examples 1-4 was reduced, resulting in lower leakage current and higher parallel resistance in Examples 1-4 relative to Comparative Example 1.

[0227] Compared to Comparative Example 2, in which the entire light-receiving surface is passivated using an N-type doped silicon layer, Examples 1, 3, and 4 utilize a localized passivation contact structure on the light-receiving surface, all of which are N-type solar cells. After etching in step S12, the N-type doped silicon layer 106 and the second dielectric layer 105 on the light-receiving surface of Examples 1, 3, and 4 form a localized N-type doped silicon layer 106 and a second dielectric layer 105. A localized passivation contact structure is used for passivation in the region where the light-receiving surface electrode of the solar cell is formed. This reduces the area of ​​the N-type doped silicon layer 106 with poor light transmittance, thereby preventing the N-type doped silicon layer 106 with poor light transmittance from covering the entire light-receiving surface and affecting the solar cell's light absorption, thereby improving the efficiency of the solar cell. The passivation effect of Examples 1, 3, and 4 is superior to that of Comparative Example 2, with longer minority carrier lifetimes, lower reverse saturation current densities, higher theoretical opening voltages, and higher theoretical fill factors. Furthermore, the conversion efficiency, short-circuit current, open-circuit voltage, and fill factor of Examples 1, 3, and 4 are all higher than those of Comparative Example 2. After the de-plating operation in step S4 and step S9, the edge leakage of Examples 1, 3, and 4 is reduced, so that the leakage current of Examples 1, 3, and 4 is smaller than that of Comparative Example 2, and the parallel resistance is larger than that of Comparative Example 2.

[0228] Compared to Comparative Example 2, although Example 2 is a P-type solar cell, the light-receiving surface of Example 2 also features a localized passivated contact structure. The passivation performance test data for Example 2 is still superior to that of Comparative Example 2. Example 2 exhibits a longer minority carrier lifetime, lower reverse saturation current density, higher theoretical opening voltage, and higher theoretical fill factor. Example 2 also exhibits higher conversion efficiency and open-circuit voltage, greater parallel resistance, and lower leakage current.

[0229] Compared to Comparative Example 3, the second mask layer produced in Examples 1, 3, and 4 not only protects the second doped silicon layer and the second mask layer on the light-receiving surface in step S9, but also isolates the second doped silicon layer from the annealing environment in step S7 to prevent the second doped silicon layer from reacting with the oxygen inevitably present in the annealing environment and affecting the accuracy of the subsequent oxide layer production. This makes the local passivation contact structure pattern on the subsequent light-receiving surface more precise, and the passivation effect on the metallized area is better. This results in longer minority carrier lifetimes, lower reverse saturation current densities, higher theoretical opening voltages, and higher theoretical fill factors in Examples 1, 3, and 4. In addition, the electrical performance test results of Examples 1, 3, and 4 show higher conversion efficiency, open-circuit voltage, and fill factor, and greater short-circuit current.

[0230] Compared with Comparative Example 3, although Example 2 is a P-type solar cell, Example 2 also separates the second doped silicon layer from the annealing environment in step S7 to prevent the second doped silicon layer from reacting with the oxygen inevitably present in the annealing environment and affecting the production accuracy of the subsequent oxide layer. As a result, the passivation performance test results and electrical performance test results of Example 2 are better than those of Comparative Example 3. Example 2 has a longer minority carrier lifetime before metallization, a smaller reverse saturation current density, a higher theoretical opening voltage, and a higher theoretical fill factor; Example 2 has higher conversion efficiency, open-circuit voltage, and short-circuit current.

[0231] Compared with Examples 3 and 4, in step S11 of Example 1, the frequency of the laser is 2000KHz, the line width of the laser is 80μm, the spot is square, and the power of the laser is 15W. The selection of a laser with this frequency, line width, and power makes the pattern of the laser-induced oxide layer more precise. A more precise oxide layer is conducive to making a more precise local passivation contact structure on the light-receiving surface, which in turn is conducive to improving the passivation performance and electrical performance. The resistivity, theoretical opening voltage, and theoretical fill factor of Example 1 before metallization are higher, and the minority carrier lifetime is longer than those of Examples 3 and 4. After light injection, Example 1 has higher resistivity, theoretical opening voltage, and theoretical fill factor, and longer minority carrier lifetime. The conversion efficiency, open circuit voltage, short-circuit current, and fill factor of Example 1 are all higher.

[0232] The above is a detailed introduction to a method for preparing a solar cell, a solar cell and a photovoltaic module disclosed in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method for preparing a solar cell, a solar cell and a photovoltaic module of the present invention and their core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A method for preparing a solar cell, comprising the following steps: Depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence away from the silicon wafer on a backlight surface of a silicon wafer of a first conductivity type, wherein the first conductivity type is opposite to the second conductivity type; Depositing on the light-receiving surface of the silicon wafer a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer, which are sequentially arranged away from the silicon wafer; Filling nitrogen or an inert gas into an annealing environment, the first doped silicon layer and the second doped silicon layer are annealed and crystallized in the annealing environment; wherein the second mask layer is used to separate the second doped silicon layer from the annealing environment; removing the second mask layer on the light-receiving surface of the silicon wafer to expose a side of the second doped silicon layer away from the second dielectric layer; irradiating the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on a side of the second doped silicon layer away from the second dielectric layer; Removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer; The oxide layer and the first mask layer are removed.

2. The manufacturing method of the solar cell according to claim 1, wherein, Before the step of removing the second mask layer on the light-receiving surface of the silicon wafer to expose the side of the second doped silicon layer away from the second dielectric layer, the method for preparing a solar cell further includes: Removing the second mask layer on the backlight surface and the edge of the silicon wafer, and retaining the second mask layer on the light-receiving surface of the silicon wafer and a portion of the thickness of the first mask layer on the backlight surface; By covering the light-receiving surface of the silicon wafer with the second mask layer, the coating layers of the second dielectric layer and the second doped silicon layer on the backlight surface and the edge of the silicon wafer are removed.

3. The method for manufacturing a solar cell according to claim 2, wherein, The step of removing the second mask layer on the backlight surface and the coating layer at the edge of the silicon wafer, and retaining the second mask layer on the light-receiving surface of the silicon wafer and a partial thickness of the first mask layer on the backlight surface, comprises: Use hydrofluoric acid with a mass percentage concentration of x% to clean the backlight surface and the edge of the silicon wafer, and control the cleaning time t1 to satisfy: t2≤t1<t3; wherein t2 is the time required for the wrap-around coating of the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%.

4. The method for preparing a solar cell according to claim 3, wherein, The thickness of the first mask layer is greater than the thickness of the coating layer of the second mask layer.

5. The method for manufacturing a solar cell according to any one of claims 3 to 4, wherein, In a hydrofluoric acid solution of the same concentration, the etching rate of the first mask layer is lower than the etching rate of the coating layer around the second mask layer.

6. The method for preparing a solar cell according to any one of claims 1 to 5, wherein, The step of filling nitrogen or an inert gas into the annealing environment and annealing and crystallizing the first doped silicon layer and the second doped silicon layer in the annealing environment comprises: Filling nitrogen or an inert gas into the annealing environment to normal pressure to reduce the concentration of oxygen in the annealing environment; placing the silicon wafer into the annealing environment; The temperature in the annealing environment is raised to 780° C. to 820° C., and the pressure is reduced to 28 KPa to 32 KPa; The annealing environment is filled with the nitrogen or the inert gas to 78KPa-82KPa to reduce the concentration of oxygen in the annealing environment; The annealing environment continues to heat up to 900° C. to 920° C.; The first doped silicon layer and the second doped silicon layer are annealed at 900° C. to 920° C.; The annealing environment is cooled to 700° C. to 740° C.; The annealing environment is filled with the nitrogen or the inert gas to normal pressure to reduce the concentration of oxygen in the annealing environment; The silicon wafer is taken out.

7. The manufacturing method of the solar cell according to any one of claims 1 to 6, wherein, In the step of irradiating the light-receiving surface of the silicon wafer with a laser in an oxygen environment to form a local oxide layer on a side of the second doped silicon layer away from the second dielectric layer, the temperature of the heated area formed by the laser on the second doped silicon layer is lower than the melting point of the second doped silicon layer; The frequency of the laser is 1800KHz to 2200KHz, the line width of the laser is 70μm to 100μm, and the power of the laser is 10W to 20W.

8. The manufacturing method of the solar cell according to any one of claims 1 to 7, wherein, Before the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence away from the silicon wafer on the backlight surface of the silicon wafer of the first conductivity type, the method for preparing a solar cell further includes: The light-receiving surface and the backlight surface of the silicon wafer are polished; wherein the reflectivity of the light-receiving surface and the backlight surface of the silicon wafer is controlled at 40% to 50%.

9. The method for preparing a solar cell according to any one of claims 1 to 8, wherein, The step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence away from the silicon wafer on the backlight surface of the silicon wafer of the first conductivity type comprises: growing the first dielectric layer; sequentially growing an intrinsic silicon layer and one or more in-situ doping layers; The first mask layer is grown.

10. The method for manufacturing a solar cell according to any one of claims 1 to 9, wherein, After the step of depositing a first dielectric layer, a first doped silicon layer of a second conductivity type, and a first mask layer stacked in sequence away from the silicon wafer on the backlight surface of the silicon wafer of the first conductivity type, the method for preparing a solar cell further includes: Removing the coating layer of the first mask layer on the light-receiving surface and edge of the silicon wafer, and retaining the first mask layer on the backlight surface; By covering with the first mask layer on the backlight surface, removing the coating layers of the first dielectric layer and the first doped silicon layer on the light-receiving surface and the edge of the silicon wafer; The silicon wafer is etched to form a polished surface on the light receiving surface.

11. The manufacturing method of the solar cell according to any one of claims 1 to 10, wherein, The step of depositing a second dielectric layer, a second doped silicon layer of the first conductivity type, and a second mask layer, which are sequentially arranged away from the silicon wafer, on the light-receiving surface of the silicon wafer, comprises: The second dielectric layer, the second in-situ doped silicon layer, and the second mask layer are grown in sequence.

12. The method for manufacturing a solar cell according to any one of claims 1 to 11, wherein, The step of removing the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer to form a local second doped silicon layer and a local second dielectric layer includes: Remove the second doped silicon layer and the second dielectric layer outside the coverage of the oxide layer by alkali etching, and etch the light-receiving surface of the silicon wafer to form a textured surface, and the emissivity of the textured surface is 6% to 8%.

13. The manufacturing method of the solar cell according to any one of claims 1 to 12, wherein, After the step of removing the oxide layer and the first mask layer, the method for manufacturing the solar cell further includes: Deposit a first functional layer on the light-receiving surface of the silicon wafer, and deposit a second functional layer on the backlight surface of the silicon wafer; Fabricate a light-receiving surface electrode on the light-receiving surface of the silicon wafer, and fabricate a backlight surface electrode on the backlight surface of the silicon wafer; wherein, the light-receiving surface electrode penetrates through the first functional layer and makes an ohmic contact with the second doped silicon layer, and the backlight surface electrode penetrates through the second functional layer and makes an ohmic contact with the first doped silicon layer.

14. The method for preparing a solar cell according to any one of claims 1 to 13, wherein, The first dielectric layer is a silicon oxide layer.

15. The manufacturing method of a solar cell according to any one of claims 1 to 14, wherein, The thickness of the first dielectric layer is 0.1 nm to 5 nm.

16. The manufacturing method of the solar cell according to any one of claims 1 to 15, wherein, The thickness of the first doped silicon layer is 230 nm to 270 nm.

17. The manufacturing method of a solar cell according to any one of claims 1 to 16, wherein, The thickness of the first mask layer is 15 nm to 25 nm.

18. The method for preparing a solar cell according to any one of claims 1 to 17, wherein, The second dielectric layer is a silicon oxide layer.

19. The method for preparing a solar cell according to any one of claims 1 to 18, wherein, The thickness of the second dielectric layer is 0.1 nm to 5 nm.

20. The manufacturing method of the solar cell according to any one of claims 1 to 19, wherein, The thickness of the second doped silicon layer is 100 nm to 140 nm.

21. The manufacturing method of the solar cell according to any one of claims 1 to 20, wherein, The thickness of the second mask layer is 5 nm to 15 nm.

22. A solar cell is manufactured by the method for manufacturing a solar cell according to any one of claims 1 to 21.

23. A photovoltaic module includes the solar cell according to claim 22.

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