Encoding method and communication apparatus

Abstract

The present application provides an encoding method and a communication apparatus. A plurality of modes of generating a pre-transformed codeword on the basis of a shift register are provided for a pre-transformed polar (PC-polar) code, thereby achieving better error correction performance for the PC-polar code. In addition, modes for processing a message bit, a check bit, and a frozen bit in the polar code are more uniform, thereby achieving low description complexity. The output of the shift register not only supports the pre-transformed codeword as a non-system code, but also supports the pre-transformed codeword as a system code. The diverse combinations of the shift register, the number of taps, the directions of the taps, and feedback modes enable further performance enhancement of the PC-polar code.

Description

Coding method and communication device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 28, 2023, with application number 202311847181.7 and invention name “Encoding method and communication device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of channel coding, and more specifically, to a coding method and a communication device. Background Art

[0003] Performing upper triangular pre-transformed encoding before polar coding can improve the code spectrum of polar codes and enhance their error correction performance. Cyclic redundancy check (CRC) coding, parity check (PC) coding, and convolutional coding are all examples of upper triangular pre-transformations that can improve the code spectrum of polar codes. The pre-transformed polar codes used in fifth-generation (5G) systems are PC-polar codes. PC-polar codes generate pre-transformed codewords based on a shift register with single-tap feedback. However, the PC check relations generated by this single-tap feedback shift register are simple, resulting in limited improvement in the code spectrum. Furthermore, long-term evolution (LTE) turbo codes are also convolutional codewords generated based on shift registers. This technology uses a single-tap feedback method followed by tap reading, resulting in limited error correction performance.

[0004] Therefore, how to further improve the error correction performance of polar codes is an urgent problem to be solved. Summary of the Invention

[0005] The present application provides a coding method and a communication device, which can enhance the error correction performance of polar codes and improve the code spectrum.

[0006] In a first aspect, a coding method is provided. The method can be performed by a first communication device, a component in the first communication device (e.g., a processor, a chip, a chip system, a hardware circuit, etc.), or a logic module or software capable of implementing all or part of the functions of the first communication device. The method includes: obtaining an input sequence; performing pre-transform coding on the input sequence according to a shift register to obtain an output sequence; and performing polarization coding on the output sequence to obtain a codeword sequence. The shift register corresponds to at least two taps, the directions of the at least two taps are write-in, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest-order terms and the highest-order terms of the pre-transform coding polynomial are both 1. If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the Lth register in the shift direction of the shift register, the Lth register being the register corresponding to the highest-order term of the pre-transform coding polynomial, and L being an integer greater than or equal to 1.

[0007] In this technical solution, the input sequence is pre-transformed and encoded using a shift register having at least two taps, each of which is oriented for writing. Because the taps are oriented for writing, the shift register can be immediately updated based on the values ​​on the taps. Therefore, the values ​​in the shift register are updated without delay, which can improve the error correction performance of the PC-polar code.

[0008] In combination with the first aspect, in certain implementations of the first aspect, the value in the Lth register is related to the values ​​in the previous L-1 registers.

[0009] In this implementation, the taps are fed forward, and the shift register output is dependent on the value in the Lth register, which is obtained by shifting the values ​​in the previous L-1 registers. This provides a stronger code check capability. Furthermore, in the feedforward approach, the value in the Lth register is dependent on the portion of the message bits preceding the current position in the input sequence.

[0010] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence is a message bit, the value in the first register in the shift register is updated to the XOR of the value in the first register and the value of the first tap corresponding to the first register, the value of the first tap is the input of the shift register, and the first register is any one of the shift registers.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the value in the Lth register is related to all message bits before the current position in the input sequence.

[0012] In this implementation, the tap is in feedback mode, and the shift register has a longer memory length. Pre-transform coding is performed based on the shift register and cascaded with the polar code to obtain better code spectrum performance.

[0013] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence is a message bit, the value of the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the corresponding first tap, the value of the first tap is the XOR value of the value of the feedback input and the message bit at the current position, and the first register is any one of the registers in the shift register.

[0014] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value in the Lth register in the shift direction of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0015] In this implementation, the pre-transform code is a non-systematic code. Regardless of whether the current position in the input sequence is a message bit or a dynamically frozen bit, it is output from a fixed position in the shift register, such as the last register in the shift direction (i.e., the Lth register). This allows for a more unified description of message bits and dynamically frozen bits, reducing description complexity.

[0016] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0017] In this implementation, the pre-transform code is a systematic code, which not only achieves the beneficial technical effect of writing the tap direction, but also reduces the decoding complexity.

[0018] In combination with the first aspect, in some implementations of the first aspect, the length L of the shift register is a prime number.

[0019] In combination with the first aspect, in certain implementations of the first aspect, L is 5 or 7; if L is 7, the number of taps corresponding to the shift register does not exceed 5; or, if L is 5, the number of taps corresponding to the shift register does not exceed 3.

[0020] In this implementation, the design of the length L of the shift register and the design of the number of taps corresponding to the shift register can take into account both the coding complexity and the error correction performance of the code.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the shift register corresponds to at least two taps, the direction of the at least two taps is writing, the positions of the at least two taps are determined by a pre-transformation coding polynomial, and the coefficient of the lowest-order term and the coefficient of the highest-order term of the pre-transformation coding polynomial are both 1, including: the shift register corresponds to two tap groups, the direction of the taps in at least one of the two tap groups is writing; the positions of the taps in the first tap group of the two tap groups are determined by a first pre-transformation coding polynomial, and the positions of the taps in the second tap group of the two tap groups are determined by a second pre-transformation coding polynomial; the coefficient of the lowest-order term and the coefficient of the highest-order term of each of the first pre-transformation coding polynomial and the second pre-transformation coding polynomial are both 1.

[0022] In this implementation, the shift register has both feedforward and feedback taps. Combining feedforward and feedback, with at least one set of the feedforward and feedback taps oriented in a write direction, can improve code spectrum performance or enhance code verification capabilities.

[0023] In combination with the first aspect, in certain implementations of the first aspect, the direction of the taps in the first tap group is writing, and the direction of the taps in the second tap group is reading; if the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register, the value of the first tap is the XOR value of the feedback input and the message bit at the current position, the feedback input is the XOR value of the values ​​of the taps corresponding to the power terms with coefficients greater than 0 in the second pre-transformation coding polynomial, and the first register is any one of the registers in the shift register.

[0024] In this implementation, the shift register is of a type with feedforward and feedback, and the feedforward mode is multi-tap writing, and the feedback mode is multi-tap reading, which has a larger memory length. Based on this, pre-transform coding is performed and cascaded with polar code to further improve the code spectrum performance.

[0025] In combination with the first aspect, in certain implementations of the first aspect, the direction of the taps in the first tap group is write, and the direction of the taps in the second tap group is write; if the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register and the value of the second tap, the value of the first tap or the value of the second tap is the XOR value of the input of the shift register and the feedback input, and the feedback input is the output of the shift register, wherein the first tap belongs to the first tap group, and the second tap belongs to the second tap group.

[0026] In this implementation, the shift register is of a type with feedforward and feedback, and the feedforward method is multi-tap writing, and the feedback method is also multi-tap writing. The feedback bit is used as the output bit, and has a lower correlation with the current input bit, and the codeword of the pre-transformation code is more random.

[0027] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the Lth register in the shift direction of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0028] In this implementation, the pre-transform code is a non-systematic code. Regardless of whether the current position in the input sequence is a message bit or a dynamically frozen bit, the bits are output from a fixed position in the shift register. This allows for a more unified description of message bits and dynamically frozen bits, reducing description complexity.

[0029] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0030] In this implementation, the pre-transform code is a systematic code, which not only achieves the beneficial technical effect of writing the tap direction, but also reduces the decoding complexity.

[0031] In combination with the first aspect, in certain implementations of the first aspect, the direction of the taps in the first tap group is read, and the direction of the taps in the second tap group is write; if the current position in the input sequence corresponds to a message bit, the value of the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register, the first tap belongs to the second tap group, and the first register is any one of the registers in the shift register.

[0032] In this implementation, the shift register is a type with both feedforward and feedback, with the feedforward mode being multi-tap readout and the feedback mode being multi-tap write. The shift register's output is dependent on the values ​​in multiple registers, providing enhanced verification capabilities.

[0033] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the tap in the first tap group; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0034] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the tap in the first tap group, and the output of the shift register is related to the value of the tap in the first tap group, including: if the current position of the input sequence corresponds to a message bit, the output of the shift register is the exclusive OR value of the values ​​of the taps corresponding to the power terms with coefficients greater than 0 in the first pre-transformation coding polynomial.

[0035] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0036] In combination with the first aspect, in certain implementations of the first aspect, the value of the tap in the second tap group is the exclusive OR value of the input and feedback input of the shift register, and the feedback input is the value in the Lth register in the shift direction of the shift register.

[0037] In a second aspect, a coding method is provided. The method can be performed by a first communication device, a component in the first communication device (e.g., a processor, a chip, a chip system, a hardware circuit, etc.), or a logic module or software capable of implementing all or part of the functions of the first communication device. The method includes: obtaining an input sequence; performing pre-transform coding on the input sequence according to a shift register to obtain an output sequence; and performing polarization coding on the output sequence to obtain a codeword sequence. The shift register corresponds to at least two taps, the directions of the at least two taps are read, and the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest-order terms and the highest-order terms of the pre-transform coding polynomial are both 1. If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the Lth register in the shift direction of the shift register, where the Lth register is the register corresponding to the highest-order term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

[0038] In this technical solution, the shift register corresponds to at least two taps, and the direction of the at least two taps is read. When the tap direction is read, as opposed to the tap direction being write, the read tap performs an exclusive-or operation on the values ​​in the register corresponding to the pre-transformed coding polynomial coefficients, and then uses the result as the output or feedback input of the shift register. The resulting shift register output or feedback input value is the XOR value of the values ​​in all related shift registers, which can improve the code spectrum and enhance error correction performance.

[0039] In combination with the second aspect, in certain implementations of the second aspect, the output of the shift register is the XOR value of the input of the shift register and the value of the first tap of the at least two taps, and the first tap is the tap corresponding to the power term with a coefficient greater than 0 in the pre-transformation coding polynomial.

[0040] In this implementation, the tap corresponding to the shift register is a feedforward tap, the direction is readout, and the output of the shift register is related to the value in the shift register corresponding to the pre-transform coding polynomial.

[0041] In combination with the second aspect, in some implementations of the second aspect, the output of the shift register is an exclusive OR value of an input of the shift register and a feedback input, and the feedback input is an exclusive OR value of the at least two taps.

[0042] In this implementation, the tap corresponding to the shift register is a feedback tap, and the direction is read. The feedback input of the shift register is related to the value in the shift register corresponding to the pre-transform coding polynomial. The feedback input provides more comprehensive information than the write direction, which can improve the code spectrum.

[0043] With reference to the second aspect, in certain implementations of the second aspect, the shift register corresponds to at least two taps, the direction of the at least two taps is readout, the at least two taps are determined by a pre-transformation coding polynomial, and the coefficient of the lowest-order term and the coefficient of the highest-order term of the pre-transformation coding polynomial are both 1, including:

[0044] The shift register corresponds to two tap groups, and the directions of the taps in the two tap groups are both read; the positions of the taps in a first tap group of the two tap groups are determined by a first pre-transform coding polynomial, and the positions of the taps in a second tap group of the two tap groups are determined by a second pre-transform coding polynomial; the coefficient of the lowest power term and the coefficient of the highest power term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1;

[0045] Furthermore, the output of the shift register is the XOR value of the first input and the value of the tap in the first tap group; the first input is the XOR value of the input of the shift register and the feedback input, and the feedback input is the XOR value of the tap in the second tap group.

[0046] In this implementation, the shift register taps include feedforward and feedback taps, and the tap direction is read. The feedback input and output values ​​of the shift register are the result of combining the values ​​in the shift register corresponding to the current tap, which can improve the code spectrum.

[0047] In a third aspect, a communication device is provided, wherein the communication device has the function of implementing the method of the first aspect or the second aspect, or the method in any possible implementation of the first aspect or the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software implementation. The hardware or software includes one or more units corresponding to the above-mentioned functions.

[0048] In a fourth aspect, the present application provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, the at least one memory being used to store computer programs or instructions, and the at least one processor being used to call and run the computer program or instructions from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation thereof, or executes the method in the second aspect or any possible implementation thereof.

[0049] In a fifth aspect, the present application provides a communication device comprising a communication interface and a circuit. The communication interface is configured to receive an input sequence and input the input sequence into the circuit. The circuit is configured to perform pre-transform encoding on the input sequence to obtain an output sequence. The communication interface is further configured to output the output sequence. Optionally, the circuit may be configured to perform polarization encoding on the output sequence to obtain a codeword sequence. In this case, the communication interface is configured to output the codeword sequence.

[0050] As an example, the communication device of the third to fifth aspects is an encoding device, such as an encoder.

[0051] In a sixth aspect, the present application provides a computer-readable storage medium, which stores computer program code or instructions. When the computer instructions are executed on a computer, the method as in the first aspect or any possible implementation thereof is implemented, or the method as in the second aspect or any possible implementation thereof is implemented.

[0052] In a seventh aspect, the present application provides a computer program product, comprising computer program code or instructions, which, when the computer program code or instructions are run on a computer, enables the method in the first aspect or any possible implementation thereof to be implemented, or the method in the second aspect or any possible implementation thereof to be implemented.

[0053] In an eighth aspect, the present application provides a wireless communication system, comprising a communication device as described in any one of the third to fifth aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a schematic diagram of the single-tap feedback shift register used in 5G polar.

[0055] Figure 2 is a flow chart of the communication system.

[0056] FIG3 is a schematic flow chart of the encoding method provided in this application.

[0057] FIG4 is a schematic diagram of a feed-forward poly RSB RHS, right shift, and pre-transformed coding output from a tap write as a non-systematic code.

[0058] FIG5 is another equivalent diagram of the poly RSB RHS feed-forward, right-shifted, pre-transformed code output from the tap write as a non-systematic code.

[0059] FIG6 is a schematic diagram of feeding forward poly MSB RHS, right shifting, and outputting the pre-transformed code written from the taps as a systematic code.

[0060] FIG7 is a schematic diagram of a shift register with poly MSB RHS feedback, right shift, and write from a tap.

[0061] FIG8 is a schematic diagram of a shift register in which the feedforward tap is for writing and the feedback tap is for reading.

[0062] FIG9 is a schematic diagram of a shift register in which the feedforward tap is for reading and the feedback tap is for writing.

[0063] FIG10 shows a shift register in which both the feedforward tap and the feedback tap are written.

[0064] FIG11 is a schematic diagram of a shift register with a feedforward tap for readout.

[0065] FIG12 is a schematic diagram of a shift register with a feedback tap for readout.

[0066] FIG13 is a schematic diagram of a shift register in which both the feedforward tap and the feedback tap are in the read direction.

[0067] 14 to 22 are performance simulation diagrams of various shift registers provided in this application.

[0068] FIG23 is a schematic structural diagram of a communication device provided in this application.

[0069] FIG24 is a schematic structural diagram of another communication device provided in this application.

[0070] FIG25 is a schematic structural diagram of another communication device provided in this application. DETAILED DESCRIPTION

[0071] The technical solution in this application will be described below with reference to the accompanying drawings.

[0072] In order to facilitate understanding of the technical solutions of the present application, a brief introduction to the relevant concepts or technologies involved in the embodiments is first given.

[0073] Performing upper triangular pre-transformation before polar coding can improve the code spectrum of polar codes and enhance their error correction performance. CRC coding, PC coding, and convolutional coding are examples of upper triangular pre-transformation that can improve the code spectrum of polar codes.

[0074] In 5G, control channel coding uses a combination of PC and CRC coding as a pre-transform coding strategy when 12 ≤ k ≤ 19, where k is the message length. When k ≥ 20, CRC coding is used as a pre-transform coding strategy to further improve the performance of Polar codes.

[0075] Figure 1 shows a schematic diagram of the shift register used in NR PC-polar. NR PC-polar code implements pre-transform coding using a shift register of length 5, as shown in Figure 1. If the current bit is a message bit, the current bit is XORed with the value of the leftmost shift register and then stored in the leftmost shift register. The currently input message bit is used as the bit at the current position, and the register is then circularly shifted. If the current bit is a parity bit, the value of the leftmost shift register is used as the parity bit, and the register is then circularly shifted left. If the current bit is a frozen bit, a zero is directly output as the bit at the current position, and the register is then circularly shifted left.

[0076] The pseudo code and comments for pre-transformation polar coding based on shift registers in the NR standard are as follows:

[0077] After the pre-transformed codeword u, polar coding is performed to obtain the output d = [d0d1d2...d N-1 ],d=uG N .

[0078] As described above, the PC-polar code in the NR standard generates pre-transformed coded codewords based on a single-tap feedback shift register. The shift register is a feedback shift register; the tap direction is write; the number of taps is single; the shift register shifts left; the feedback tap and the output tap are both located at the end (leftmost) of the shift direction; and the shift register can only be used to input bits when the bits are in the message position; when the current position is the check position, the shift register is used to output bits. The shift register's shift timing logic is: read at time t and write at time t+1. The PC check relation generated by this single-tap feedback shift register is simple, resulting in limited improvement in the code spectrum. Furthermore, the processing of message bits, check bits, and frozen bits is not uniform, resulting in a high degree of description complexity.

[0079] LTE-turbo codes also use shift registers to generate convolutional codewords. However, this coding method is used as a standalone channel coding strategy, without concatenation with polar codes. Therefore, the error correction performance of direct pre-transform coding with polar codes is uncertain.

[0080] To this end, the present application provides a coding method, which is mainly aimed at pre-transformation polar codes, and proposes a variety of methods for generating pre-transformation codewords based on shift registers, which can obtain better error correction performance than NR PC-polar codes. In addition, the processing methods for message bits, check bits, and frozen bits in polar codes are more unified, and the description complexity is low. The output of the shift register supports both the pre-transformed codeword as a non-systematic code and the transformed codeword as a systematic code. The combination of various forms of shift registers and the number of taps, tap directions, and feedback methods further improves the performance of pre-transformation polar codes.

[0081] Figure 2 is a schematic diagram of the communication system flow. As shown in Figure 2, the technical solution of this application primarily involves channel coding. Channel coding, located between source coding and modulation, is responsible for channel coding the bits generated by the source. After modulation, the transmitter sends the modulated symbols across a noisy channel to the receiver. After demodulation, the receiver performs channel decoding. Channel decoding, located between demodulation and source decoding, is responsible for recovering the source bit stream.

[0082] Figure 3 is a schematic flow chart of a coding method 300 provided herein. Method 300 can be performed by a first communications device, a component (e.g., a chip, a chip system, or a circuit) within the first communications device, or a logic module or software capable of implementing all or part of the functionality of the first communications device. As an example, the first communications device can be a coding device. The following description uses a coding device as an example.

[0083] 310. The encoding device obtains an input sequence.

[0084] 320. The encoding device performs pre-transform encoding on the input sequence according to the shift register to obtain an output sequence.

[0085] The input sequence here refers to the input sequence of the pre-transform coding, and the output sequence refers to the output sequence of the pre-transform coding.

[0086] 330. The encoding device performs polarization encoding on the output sequence to obtain a codeword sequence.

[0087] The coding device further performs polar coding on the output sequence of the pre-transform coding. Through steps 310 to 330, the coding device performs concatenated coding of the pre-transform coding and polar coding to obtain a codeword sequence.

[0088] The pre-transform coding is performed based on a shift register. The shift register corresponds to at least two taps, the direction of the at least two taps is write, and the positions of the at least two taps are determined by the pre-transform coding polynomial, and the coefficients of the lowest-order term and the highest-order term of the pre-transform coding polynomial are both 1. If the current position of the input sequence corresponds to a dynamic freeze bit, the output of the shift register is related to the value in the Lth register in the shift direction of the shift register. The Lth register is the register corresponding to the highest-order term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

[0089] The length of the shift register is L, which is generally equal to the highest power of the pre-transform coding polynomial. For example, if the highest power of the pre-transform coding polynomial is 1, then L = 1, and there is only one register. For another example, if the pre-transform coding polynomial is 1 + D + D 3 , the highest power of the pre-transform coding polynomial is 3. At this time, L=3, so there are three registers, among which D corresponds to the first register, D 3 Corresponding to the third register. It should be understood that D 2 Corresponding to the second register, but due to D 2 The coefficient in the pre-coding polynomial is 0, so the tap corresponding to the second register does not exist. The taps corresponding to the shift register (such as the read tap and / or write tap) will be described in the following embodiments with respect to the structure of the specific shift register. In the pseudocode provided in the following embodiments, it is assumed that the highest power of the pre-transform coding polynomial is L, so there are L shift registers. Among them, y0 represents the value in the first register, y1 represents the value in the second register. And so on, y L-1 Indicates the value in the Lth register.

[0090] In addition, the shift register corresponds to at least two taps. When the at least two taps are two taps, they should be taps corresponding to the lowest power term and the highest power term, respectively.

[0091] In each embodiment of the present application, L is a prime number. As an example, L is equal to 5 or 7. If L is equal to 7, the number of taps corresponding to the shift register (feedforward taps or feedback taps) does not exceed 5. If L is equal to 5, the number of taps corresponding to the shift register (feedforward taps or feedback taps) does not exceed 3. It should be understood that if the shift register is a type with both feedforward and feedback, when L is equal to 7, the number of feedforward taps and feedback taps does not exceed 5 respectively; if L is equal to 5, the number of feedforward taps and feedback taps does not exceed 3 respectively. The value of L and the design of the number of taps are to take into account both the pre-transform coding complexity and the decoding performance. The description of the number of taps is also applicable to the following embodiments and will not be repeated below.

[0092] In addition, the dynamic frozen bits may refer to parity bits.

[0093] In method 300, the at least two taps corresponding to the shift register may correspond to one pre-transform coding polynomial, such as a feedforward polynomial or a feedback polynomial; or the at least two taps may correspond to two pre-transform coding polynomials, such as a feedforward polynomial and a feedback polynomial. This will be described below with reference to specific examples.

[0094] In addition, in the embodiment of the present application, the shift direction of the shift register can be left shift or right shift, without limitation. The following embodiments are all described using right shift as an example.

[0095] In the embodiments of the present application, the pre-transform coding polynomial is exemplified by a poly polynomial, with the most significant bit (MSB) of the poly polynomial located on the right hand side (RHS) of the polynomial, i.e., poly MSB RHS. Alternatively, the poly polynomial may be exemplified by the most significant bit (MSB) located on the left hand side (RHS), i.e., poly MSB LHS. The following embodiments use poly MSB RHS as an example for illustration.

[0096] Example 1

[0097] Feed forward + poly MSB RHS + right shift + write from tap

[0098] FIG4 is a schematic diagram of a feed-forward poly MSB RHS, right shift, and pre-transformed coding output from a tap write as a non-systematic code.

[0099] The sequence of pre-transformed input (simplified as input sequence in the embodiment) is the message sequence to be encoded v0, v1, v2, ..., v K-1 , the output sequence is u0,u1,u2,…,u N-1 , N is the length of the polar code mother code, and the relationship between the input sequence and the output sequence is determined according to the shift register and the pre-transformation coding polynomial.

[0100] As shown in FIG4 , in this example, the structure of the pre-transform coding is a feedforward shift register, the number of registers is L, and the tap position is based on the polynomial g(D)=1+g1D+g2D 2 +…+g m D m The number of shift registers L is generally equal to the highest power of the polynomial g(D), for example, the polynomial g(D) = 1 + D + D 3, the polynomial coefficients are g0=1, g1=1, g2=0, g3=1, the highest power m=3, and the corresponding number of registers L is also equal to 3.

[0101] From the timing point of view, g0 corresponds to the tap at the current moment, g1 corresponds to the tap at one moment before the current moment, that is, the moment after one register; g2 corresponds to the tap at two moments before the current moment, that is, the moment after two registers; similarly, g m The corresponding tap is after m registers have passed. represents the exclusive-or operation on a binary field, Represents a binary switch, the coefficient g of the polynomial g(D) i When 0 is taken, is closed, indicating that there is no tap at the i-th moment; otherwise is open, indicating that there is a tap at the i-th moment.

[0102] Figure 4 shows the structure of a non-systematic pre-transformation code. It can be seen that if the pre-transformation code is a non-systematic code, the shift register output is independent of the set to which the current position in the input sequence belongs. Specifically, regardless of whether the current position belongs to the message bit set or the dynamic frozen bit set, the shift register output is read from the last register in the shift direction.

[0103] As mentioned above, the length of the shift register is L, so the last register in the shift direction is the Lth register. Therefore, if the current position in the input sequence corresponds to a message bit or a set of dynamically frozen bits, the shift register output is based on the value in the Lth register in the shift direction. The value in the Lth register is obtained by right-shifting the values ​​in registers 1 through L-1. Furthermore, if the current position in the input sequence corresponds to a frozen bit, the shift register output is 0.

[0104] If the pre-transform coding uses a non-systematic code, although the decoding complexity of the shift register is slightly higher, the output of the shift register is more uniform and the description complexity is lower.

[0105] Another structure equivalent to the pre-transform coding structure in Figure 4 is shown in Figure 5. Figure 5 illustrates another example of a pre-transform coding process with poly MSB RHS feedforward, right shift, and non-systematic code output from tap writes. It should be understood that the pre-transform coding process shown in Figure 5 is essentially equivalent to that shown in Figure 4 and is not further described.

[0106] FIG6 is a schematic diagram of feeding forward poly MSB RHS, right shifting, and outputting the pre-transformed code written from the taps as a systematic code.

[0107] If the pre-transform code is a systematic code, the shift register output is related to the set to which the current position in the input sequence belongs. Specifically, if the current position belongs to the message bit set, the shift register output is the input at that position; if the current position belongs to the dynamic frozen bit set, the shift register output is read from the last register in the shift direction.

[0108] Before starting encoding, the values ​​in the L shift registers need to be initialized, for example, the value of each register is initialized to 0.

[0109] In the case where the pre-transform coding is a non-systematic code or a systematic code, if the current position of the input sequence is a frozen bit (eg, a punctured and shortened position), the output of the shift register is 0.

[0110] In Example 1, for the case of non-systematic code, the pseudo code is expressed as follows:

[0111] In Example 1, for the case of systematic code, the pseudo code is expressed as follows:

[0112] As can be seen from the pseudocode above, in Example 1, if the current position of the input sequence corresponds to a message bit, the value of the first register in the shift register is updated to the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register. The value of the first tap is the input to the shift register. In the feedforward mode of Example 1, the input to the shift register is also the message bit at the current position. Here, the first register can refer to any register in the first register.

[0113] In the above pseudocode, the process of obtaining the message bit set I, the dynamic frozen (DF) bit set, and the position of the frozen bit (such as puncturing or shortening) is as follows:

[0114] (1) Obtaining the reliability sequence of the mother code length And perform rate matching, from Remove the puncturing and / or shortening positions to obtain the reliability sequence after rate matching The length of N is N minus the number of punctured bits and / or shortened bits.

[0115] For example, the mother code length N=32, Rate matching requires puncturing 2 bits. The length of the reliability sequence after puncturing is 30 bits.

[0116] (2) In the sequence Choose the most reliable The positions are recorded as a set Where K represents the information bit length. It is a construction parameter required for selecting message bits, which indicates the number of bits that sacrifice reliability when selecting message bits, or the number of bits that are pre-frozen.

[0117] For example, K = 11, In the reliability series Choose the most reliable positions, get a collection

[0118] (3) Sequence The remaining positions in constitute the frozen bit set F.

[0119] For example, the frozen bit set F = {3, 4, 5, 6, 7, 8, 9, 17, 10, 18, 11, 19, 13, 21, 25}, with a length of 15.

[0120] (4) Calculation set The minimum row weight in is denoted as w min , then in the collection Freeze up to 100% of the data in the order of reliability from high to low. The weight of each row is equal to w min If the set The row weight in is equal to w min Less than Then continue in the row weight equal to 2w min Pre-freeze at the position until the collection There are positions are pre-frozen as PC positions.

[0121] For example, The minimum row weight is 8, The positions with the highest reliability and weight of 8 are {27,26,23,29}, that is, the PC position set is {23,26,27,29}, with a length of 4.

[0122] (5) Obtain the dynamic frozen bit set DF, which is the set consisting of the set F plus the PC position.

[0123] The set DF = {3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 17, 18, 19, 21, 23, 25, 26, 27, 29}, with a length of 19.

[0124] (6) Get the message bit set I, the message bit set is a set The size of the set after removing the set DF is K.

[0125] I={12,20,14,15,22,16,24,28,30,31,32}.

[0126] The message bit set I, dynamic frozen bit set DF, and the acquisition process of the frozen bit set DF provided here are applicable in other embodiments below and will not be repeated below.

[0127] In Example 1, the shift register is of feedforward type, and the feedforward mode is multi-tap writing, the number of taps (or feedforward taps) is greater than or equal to 1, and the shift register outputs at the end of its shift direction.

[0128] In addition, as described in Example 1, this example does not restrict the rules for how to use the shift register to output bits. For example, the bits may be read from the shift register both when the current position is the message position and when the dynamic freeze position is the dynamic freeze position (when the pre-transformation encoding is a non-systematic code), or may be read from the register only when the current position is the dynamic freeze position (when the pre-transformation encoding is a systematic code). Therefore, the codeword after pre-transformation encoding can be a systematic code or a non-systematic code. The following examples are explained using non-systematic codes as examples.

[0129] Example 2

[0130] Feedback + poly MSB RHS + right shift + write from tap

[0131] FIG7 is a schematic diagram of a multi-tap shift register with feedback.

[0132] In this example, the input sequence of the pre-transform coding is the message sequence to be encoded v0,v1,v2,…,v K-1 , the output sequence is u0,u1,u2,…,u N-1 , N is the length of the polar code mother code, and the relationship between the input sequence and the output sequence is determined by the shift register and the polynomial. The structure of the pre-transform coding is a shift register with feedback. The number of registers is L, and the tap position is determined by the polynomial q(D) = 1 + q1D + q2D 2 +…+q m D m The number of shift registers L is generally equal to the highest power of the polynomial q(D), for example, the polynomial q(D) = 1 + D 2 +D 3 , the polynomial coefficients are q0=1, q1=0, q2=1, q3=1, the highest power m=3, and the corresponding number of registers L is also equal to 3.

[0133] From the perspective of timing, q0 corresponds to the tap at the current moment; q1 corresponds to the tap at one moment before the current moment; q2 corresponds to the tap at two moments before the current moment; similarly, q m The corresponding value is the tap after m registers have passed. represents the exclusive-or operation on a binary field, Represents a binary switch, the coefficient q of the polynomial q(D) i When 0 is taken, is closed, indicating that there is no tap at the i-th moment; otherwise is open, indicating that there is a tap at the i-th moment.

[0134] In Example 2, the parameters are used in the acquisition process of the message bit set I, the dynamic frozen bit set DF, and the position of the frozen bits (such as shortened or punctured). This parameter The values ​​in Example 2 may specifically refer to one or more groups of values ​​shown in Table 1 below.

[0135] The following also provides a pre-transformation coding polynomial in Example 2. The pre-transformation coding polynomial can be given in the form of Table 2.

[0136] In Tables 1 and 2, the parameter E represents the transmit code length, which is the code length after rate matching. Specifically, it refers to the length of the sequence to be decoded by the decoding device after the encoding device performs polarization coding, rate matching, modulation, or frequency conversion on the message bits and passes through the wireless transmission environment. In Tables 1 and 2, "-1" indicates that the corresponding value of E is meaningless for the current K. A pre-transform coding polynomial of 0 indicates that no pre-transform coding is performed.

[0137] The following Tables 1 and 2 describe or store multiple sets of data under different K and E in a tabular form. Correspondence of pre-transform coding polynomials. It is understood that other descriptions or storage formats may be used in specific implementations, and not all groups of correspondences are required. In one implementation, one or more groups of correspondences in Table 1 or 2 below may be included. For example, the correspondences in the first 16 rows of Table 1 may be included.

[0138] Table 1

[0139] Table 2

[0140] Table 1 shows the values ​​of K ranging from 1 to 16. Since the code rate R = K / E is usually less than 1, the value of E is usually greater than K. In addition, if the mother code length is 32, the value of E is less than or equal to 32. In practice, considering the case of repeated rate matching, the value of E can also be greater than 32. However, the mother code length corresponding to E of the ultra-short code is less than or equal to 32. Therefore, in this application, the value of E is K+1 to 32 (so the value of E is 2 to 32) as an example. Table 1 shows the PC polynomials corresponding to K values ​​of 1 to 16 and E values ​​of 2 to 32.

[0141] The taps q0 to q1 in FIG. 7 of Example 2 are determined according to the PC polynomial. m The specific steps are as follows: convert PC poly from decimal to binary sequence, q m On the far right, q0 is on the far left, take q0~q m The value of determines the switch of the tap. For example, PC poly = 97, and its corresponding binary sequence is [1000011], where the highest bit to the lowest bit are q6 = 1, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, and q0 = 1.

[0142] Among them, q4~q1 are all zero, indicating that there is no write tap at the time corresponding to q4~q1. And q0 corresponds to the current time, and q 6～ There is a write tap at the moment corresponding to q5. Therefore, at the moments corresponding to these coefficients equal to 1, the value written to the tap will be XORed with the value in the corresponding register and then written back to the register.

[0143] PC poly=97 is one of the most frequently appearing PC polynomials among many PC polynomials selected based on the technical solution of the present application. Considering that a limited number of PC polynomials are compatible with various situations, PC poly=97 can be used as the PC polynomial.

[0144] In one implementation, the pre-transformation code in Example 2 is a non-systematic code, as shown in Figure 7. If the pre-transformation code is a non-systematic code, the output of the shift register is independent of the set to which the current position in the input sequence belongs. Specifically, regardless of whether the current position belongs to the message bit set or the dynamic frozen bit set, the output of the shift register is read from the last register in the shift direction of the shift register. This last register is also the Lth register in the shift direction. In addition, in Example 2, due to the introduction of feedback, the value in the Lth register is related to the message bit preceding the current position in the input sequence.

[0145] In another implementation, the pre-transformation code in Example 2 may be a systematic code. If the pre-transformation code is a systematic code, the output of the shift register is related to the set to which the current position of the input sequence belongs. Specifically, if the current position corresponds to a message bit, the output of the shift register is the input of the shift register, that is, the output of the shift register is the message bit at the current position; if the current position corresponds to a frozen bit, the output of the shift register is 0.

[0146] The pseudo code for Example 2 is as follows:

[0147] It can be seen from the above pseudo code that in Example 2, if the current position of the input sequence corresponds to the message bit, the value of the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register. Among them, the value of the first tap is the XOR value of the feedback input of the shift register and the message bit at the current position. The first register can refer to any register in the shift register. Among them, the first tap corresponds to any one of the write taps in Figure 7 (the structure of the shift register is shown as q0=1 in Figure 7). For example, q0~q m Each of them corresponds to a write tap (because q0=1, the tap corresponding to q0 is not shown in the form of a binary switch in Figure 7, which means that the write tap corresponding to q0 at the current moment exists). According to the examples in Table 1 and Table 2 above, the coefficients of some terms of the pre-transform coding polynomial may be zero, and the zero coefficient indicates that there is no write tap at the corresponding moment. For example, in the above example of PC poly=97, taking poly RHS as an example, q m On the far right, q0 is on the far left, and the binary sequence corresponding to 97 is [1000011]. Therefore, q6 = 1, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, and q0 = 1. As can be seen, q4 to q1 are all zero, so there is no write tap at the time corresponding to q4 to q1.

[0148] It can be seen that the type of shift register in Example 2 is feedback, and the feedback mode is multi-tap writing. The number of feedback taps is greater than or equal to 1. The output of the shift register is on the far right of the shift register, as shown in Figure 7, which is the XOR value of the end register value and the feedback input. Compared with Example 1, the register in Example 2 has a larger memory length (memory length), and the code spectrum improvement performance after the cascade of pre-transform coding and polar code is better.

[0149] In the above-mentioned Examples 1 and 2, at least two taps corresponding to the shift register come from a tap group, which corresponds to a pre-transformation coding polynomial, such as the feedforward polynomial g(D) in Example 1 or the feedback polynomial q(D) in Example 2.

[0150] The present application also provides an example in which at least two taps corresponding to the shift register come from two tap groups, which can also improve the code spectrum performance.

[0151] In an example involving two tap groups, the taps in at least one of the two tap groups are oriented in a write direction. For example, the taps in one of the two tap groups are oriented in a write direction, or the taps in both groups are oriented in a write direction. The two tap groups include a first tap group and a second tap group, the positions of the taps in the first tap group are determined by a first pre-transform coding polynomial, and the positions of the taps in the second tap group are determined by a second pre-transform coding polynomial. In addition, the coefficient of the lowest-order term and the coefficient of the highest-order term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1.

[0152] The implementation of the two tap groups is described below with reference to some specific examples.

[0153] Example 3

[0154] Feedforward write from tap + feedback write from tap + poly MSB RHS + right shift

[0155] Figure 8 is a schematic diagram of a shift register in which the feedforward taps are for writing and the feedback taps are for reading. As shown in Figure 8, the taps in the first tap group are for writing and the taps in the second tap group are for reading. The taps in the first tap group are the feedforward taps, and the positions of the feedforward taps are determined by the first pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +…+g m D m In this example, the first pre-transform coding polynomial can also be called a feedforward polynomial. The taps in the second tap group are feedback taps, and the position of the feedback tap is determined by the second pre-transform coding polynomial q(D)=1+q1D+q2D 2 +…+q m D m Sure.

[0156] It can be seen that the structure of the pre-transform coding is a shift register with feedback taps and feedforward taps. In this example, the length L of the shift register can be equal to the maximum of the powers of the feedforward polynomial g(D) and the feedback polynomial q(D). For example, the feedback polynomial q(D) = 1 + D 2 +D 3 , the polynomial coefficients are q0=1, q1=0, q2=1, q3=1, and the highest power is 3; the feedforward polynomial g(D)=1+D+D 5, the polynomial coefficients are g0=1, g1=1, g2=0, g3=0, g4=0, g5=1, and the highest power is 5, then the length of the shift register L=5.

[0157] From the timing point of view, q0 (or g0) corresponds to the tap at the current moment, q1 (or g1) corresponds to the tap at one moment before the current moment; q2 (or g2) corresponds to the tap at two moments before the current moment; similarly, q m (or g m ) corresponds to the tap after passing through m registers. represents the exclusive-or operation on a binary field, For binary switches, the polynomial q(D) = 1 + q1D + q2D 2 +…+q m D m The coefficient q i When 0 is taken, is off (when there is no tap at moment i), otherwise is open (there is a tap at the i-th moment), the coefficients of the polynomial g(D) have similar meanings and are not repeated here.

[0158] Similarly, the input sequence of the pre-transform coding is the message sequence to be encoded v0,v1,v2,…,v K-1 , the output sequence is u0,u1,u2,…,u N-1 , N is the mother code length of the polar code. The relationship between the input sequence and the output sequence is determined by the shift register and the feedback polynomial q(D) and the feedforward polynomial g(D).

[0159] Before starting encoding, the values ​​in the L shift registers need to be initialized, for example, the value of each register is initialized to 0.

[0160] In one implementation, the pre-transformation code is a non-systematic code. In this case, the output of the shift register is independent of the set to which the current position of the input sequence belongs. Specifically, regardless of whether the current position belongs to the message bit, it is output from a fixed position in the shift register, for example, from the end register in the shift direction of the shift register, as shown in u in FIG8 . i =z i .

[0161] In another implementation, the pre-transform code is a systematic code. In this case, the output of the shift register is related to the set to which the current position of the input sequence belongs. For example, if the current position of the input sequence belongs to the message bit set, the output of the pre-transform code is the input of the pre-transform code, u i =v iIf the current position of the input sequence belongs to the dynamic frozen bit set, the value is read from the end register of the shift register in the shift direction as the output of the pre-transform coding, u i =z i .

[0162] For non-systematic or systematic codes, if the current position of the input sequence corresponds to a frozen bit, the output of the pre-transform coding is 0.

[0163] The pseudo code for Example 3 is as follows:

[0164] As can be seen from the pseudocode, if the direction of the taps in the first tap group is write, the direction of the taps in the second tap group is read, and the current position of the input sequence corresponds to the message bit, the value in the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register. Among them, the value of the first tap is the XOR value of the feedback input of the shift register and the message bit at the current position. The feedback input of the shift register is the XOR value of the values ​​of the taps corresponding to the power terms with coefficients greater than 0 in the second pre-transform coding polynomial. The first register is any register in the shift register.

[0165] Compared with Example 2, Example 3 adds feedforward on the basis of feedback and changes the direction of the feedback tap in Example 2. It has a longer memory length and has a better code spectrum improvement effect as a cascade of pre-transform coding and polar code.

[0166] Example 4

[0167] Feedforward is read from the tap, feedback is written from the tap, poly MSB RHS+right shift

[0168] Figure 9 is a schematic diagram of a shift register with feedforward taps for reading and feedback taps for writing. As shown in Figure 9, the tap direction in the first tap group is for reading, and the tap direction in the second tap group is for writing. The taps in the first tap group are feedforward taps, and the positions of the feedforward taps are determined by the first pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +…+g m D m In this example, the first pre-transform coding polynomial can also be called a feedforward polynomial. The taps in the second tap group are feedback taps, and the position of the feedback tap is determined by the second pre-transform coding polynomial q(D)=1+q1D+q2D 2 +…+q m D m The second pre-transform coding polynomial may also be referred to as a feedback polynomial.

[0169] In this example, the pre-transform coding structure is a shift register having a feedforward tap and a feedback tap. The length of the shift register is L, which is equal to the maximum power of the polynomial g(D) and the polynomial q(D).

[0170] From the timing point of view, q0 (or g0) corresponds to the tap at the current moment, q1 (or g1) corresponds to the tap at one moment before the current moment; q2 (or g2) corresponds to the tap at two moments before the current moment; similarly, q m (or g m ) corresponds to the tap after passing through m registers. represents the exclusive-or operation on a binary field, For binary switches, the polynomial q(D) = 1 + q1D + q2D 2 +…+q m D m The coefficient q i When 0 is taken, is off (when there is no tap at moment i), otherwise is open (there is a tap at the i-th moment), the coefficients of the polynomial g(D) have similar meanings and are not repeated here.

[0171] In one implementation, the pre-transform code is a non-systematic code. If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of a tap in the first tap group (i.e., the feedforward tap group). Specifically, the output of the shift register is the exclusive-OR value of the tap values ​​corresponding to the power terms with coefficients greater than 0 in the first pre-transform code polynomial.

[0172] In another implementation, the pre-transform code is a systematic code. If the current position of the input sequence corresponds to the message bit, the output of the shift register is related to the set to which the current position belongs. For example, if the current position of the input sequence belongs to the message bit set, the output of the shift register is the input of the shift register, u i =v i .

[0173] In addition, for non-systematic codes or systematic codes, if the current position of the input sequence belongs to the frozen bit set, the output of the shift register is 0.

[0174] In Example 4, the tap values ​​in the second tap group (ie, feedback tap group) are the exclusive OR values ​​of the shift register input and the shift register feedback input, and the feedback input is the value in the Lth register in the shift direction of the shift register.

[0175] The pseudo code for Example 4 could be as follows:

[0176] It can be seen from the above pseudo code that for the structure in Example 4 where the tap direction in the first tap group is read and the tap direction in the second tap group is write, if the current position in the input sequence corresponds to the message bit, the value of the first register in the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register, the first tap belongs to the second tap group, and the first register is any register in the shift register.

[0177] The register type in Example 4 is feedforward + feedback. Compared with the feedforward method in Example 3, Example 4 uses multi-tap reading and multi-tap writing as the feedback method. The number of feedforward taps or feedback taps is greater than or equal to 1.

[0178] Unlike Example 3 in which the output of the pre-transformation coding is only related to the value stored in one register of the shift register, the output of the pre-transformation coding in Example 4 is related to the values ​​stored in multiple registers of the shift register, and therefore has a stronger verification capability.

[0179] Example 5

[0180] Feedforward write from tap + feedback write from tap + poly MSB RHS + right shift

[0181] Figure 10 shows a shift register in which both the feedforward tap and the feedback tap are written. As shown in Figure 10, the tap directions in the first tap group and the second tap group are both written. The taps in the first tap group are feedforward taps, and the positions of the feedforward taps are determined by the first pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +…+g m D m In this example, the first pre-transform coding polynomial can also be called a feedforward polynomial. The taps in the second tap group are feedback taps, and the position of the feedback tap is determined by the second pre-transform coding polynomial q(D)=1+q1D+q2D 2 +…+q m D m The second pre-transform coding polynomial may also be referred to as a feedback polynomial.

[0182] In this example, pre-transform coding is based on a shift register with both feedforward and feedback taps written into it. After the feedforward and feedback polynomials are combined, the input bits are XORed with the feedback bits, and then written into the taps. The bits are then read out of the shift register at the end of the shift register.

[0183] For the description of the feedforward polynomial, feedback polynomial and polynomial coefficients, please refer to the description in other examples above and will not be repeated here.

[0184] The pseudo code for Example 5 could be as follows:

[0185] As can be seen from the above pseudocode, for the structure in Example 5 where both taps in the two tap groups are used for writing, if the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the XOR value of the value in the first register, the value of the first tap corresponding to the first register, and the value of the second tap, where the value of the first tap or the value of the second tap is the XOR value of the input and feedback input of the shift register. The feedback input of the shift register is the output of the shift register. Here, the first tap belongs to the first tap group and is a feedforward tap. The second tap belongs to the second tap group and is a feedback tap.

[0186] Compared with Example 4, the feedforward method in Example 5 is changed to multi-tap writing, and the feedback method is also multi-tap writing, with the number of taps being greater than or equal to 1.

[0187] It should be noted that after the feedforward polynomial and the feedback polynomial are combined in Example 5, the feedback effect is similar to that of Example 2. The input of the shift register is XORed with the feedback input of the upper shift register and then written from the tap and output from the end register in the shift direction of the shift register.

[0188] In the above examples 3 to 5, the taps of at least one of the two tap groups are used for writing. The following also provides an embodiment in which the taps of the shift register are all used for reading.

[0189] Specifically, the shift register corresponds to at least two taps, and the direction of the at least two taps is readout. The positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest-order terms and the highest-order terms of the pre-transform coding polynomial are both 1. In addition, if the current position of the pre-transform coded input sequence corresponds to a dynamic freeze bit, the output of the shift register is related to the value in the Lth register based on the shift direction of the shift register. The Lth register is the register corresponding to the highest-order term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1. Examples 6 to 8 are used below for illustration.

[0190] Example 6

[0191] Feed forward + poly MSB RHS + right shift + read from tap

[0192] FIG11 is a schematic diagram of a shift register with a feedforward tap as a readout. In FIG11 , the pre-transform coding is based on a shift register with a feedforward tap, wherein the position of the feedforward tap is based on a pre-transform coding polynomial (also referred to as a feedforward polynomial) g(D)=1+g1D+g2D 2 +…+g m D mDetermine. For the pre-transform coding polynomial g(D), refer to the description in Example 1 and will not be repeated here. Different from Example 1, in Example 6, the tap direction is readout.

[0193] In FIG6 , the output of the shift register is the XOR value of the input of the shift register and the value of the first tap, where the first tap is the tap corresponding to the power term with a coefficient greater than 0 in the pre-transform coding polynomial.

[0194] Example 7

[0195] Feedback + poly MSB RHS + right shift + read from tap

[0196] Figure 12 is a schematic diagram of a shift register with feedback taps for readout. In Figure 12, the pre-transform coding is based on a shift register with feedback taps. The position of the feedback taps is based on a pre-transform coding polynomial q(D) = 1 + q1D + q2D 2 +…+q m D m Determine. For the pre-transform coding polynomial q(D), please refer to the description in Example 2, which will not be repeated here. Different from Example 2, in Example 7, the tap direction is readout.

[0197] In Example 7, the output of the shift register is an exclusive OR value of the input of the shift register and a feedback input of the shift register, wherein the feedback input is an exclusive OR value of at least two taps corresponding to the shift register.

[0198] Example 8

[0199] Feedback + poly MSB RHS + right shift + read from tap

[0200] FIG13 is a schematic diagram of a shift register in which both the feedforward tap and the feedback tap are in the read direction. The pre-transform coding in FIG13 is based on a shift register with feedforward taps and feedback taps. The position of the feedforward tap is based on the pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +…+g m D m Determine, corresponding to the first tap group; the position of the feedback tap is based on the pre-transform coding polynomial q(D) = 1 + q1D + q2D 2 +…+q m D m Determine, corresponding to the second tap group. For the pre-transform coding polynomials g(D) and q(D), refer to the description in Example 3 and are not repeated here. Unlike Example 3, in Example 8, the direction of the feedforward tap and the feedback tap are both readout.

[0201] In Example 8, the output of the shift register is the XOR value of the first input and the value of the tap in the first tap group, the first input is the XOR value of the input of the shift register and the feedback input of the shift register, and the feedback input is the XOR value of the value of the tap in the second tap group.

[0202] Figures 14 to 22 are the performance simulation results of the encoding method provided by the present application. Among them, the "nested LTE-RM FHT" in the legend is the performance of the existing LTE-RM code, the "nested PC-polar SCL8 searched RateMatching and PC" is the performance of the existing nested PC-Polar code, the asterisk line of "NR seq&RM ADminMetric PC-Polar fulChk SCL8 Non-Nested" is the case by case performance, and the triangle line of "NR seq&RM ADminMetric PC-Polar fulChk SCL8 Non-Nested" is the case by case performance of feedback, poly MSBRHS, right shift, and write from tap. It can be seen from the performance simulation graph that the scheme provided by the present application has better performance at high code rates (corresponding to when E is relatively small). In addition, in the entire value range of E, compared with the fast Hadamard transform (FHT), the decoding complexity of the scheme of the present application is lower, and the performance is basically unchanged or even better.

[0203] The above describes the encoding method provided by the present application in detail. The following describes the communication device provided by the present application.

[0204] As shown in FIG23 , the present application provides a communication device 1000 .

[0205] The communication device 1000 can be a coding device, or a device applied to the coding device and capable of realizing the corresponding functions of the coding device in the embodiment of the method of this application, such as a chip, a chip system or a circuit.

[0206] Optionally, communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device. Processing module 1001 is configured to perform pre-transform coding on an input sequence to obtain an output sequence. Optionally, processing module 1001 is further configured to perform polar coding on the pre-transform coded output sequence to obtain a codeword sequence. The specific process may be referred to the detailed description of the method embodiment and will not be further described here.

[0207] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver, or transceiver device, etc., configured to perform receiving (or inputting) and / or transmitting (or outputting) operations. For example, the communication module 1002 may be configured to obtain a pre-transformed coded input sequence, output a pre-transformed coded output sequence, or output a codeword sequence after concatenated coding.

[0208] In some embodiments, the aforementioned communication module and / or processing module may be implemented by a virtual module, for example, the processing module may be implemented by a software functional unit or a virtual device, and the communication module may be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module may also be implemented by a physical device, for example, if the device is implemented using a chip / circuit (such as an integrated circuit, a dedicated circuit, a logic circuit, etc.). The communication module may be an input / output circuit and / or a communication interface that performs input operations (corresponding to the aforementioned receiving operations) and output operations (corresponding to the aforementioned sending operations); the processing module is an integrated processor or microprocessor or circuit (such as an integrated circuit, a logic circuit, etc.).

[0209] The division of modules in this application is illustrative and represents only a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the examples of this application may be integrated into a single processor, exist physically as separate modules, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in either hardware or software functional modules.

[0210] As shown in Figure 24, the present application also provides a communication device 1100. The communication device 1100 includes at least one processor 1110, which implements the functions of the encoding device described in the above method embodiment.

[0211] Optionally, the processor 1110 is coupled to a memory, which may be located within the communication device, integrated with the processor, or external to the communication device. The communication device 1100 may further include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary to implement any of the above-described method embodiments. The processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to perform the encoding method of any of the above-described embodiments.

[0212] Optionally, the communication device 1100 may further include a communication interface 1130, and the communication device 1100 may exchange information with other devices via the communication interface 1130. Exemplarily, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of interface.

[0213] Coupling in this application refers to an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, and is used for information exchange between devices, units, or modules. Processor 1110 may operate in conjunction with memory 1120 and communication interface 1130. This application does not limit the specific connection medium between the processor 1110, memory 1120, and communication interface 1130.

[0214] As shown in Figure 25, the present application also provides a chip (or chip system). The chip (or chip system) 30 may include a circuit 31 and an input / input interface 32. The circuit 31 may be a logic circuit, an integrated circuit, etc., and the input / output interface 32 may also be an input / output circuit, or an interface circuit, which can input information (or receive information) and output information (or send information). Optionally, the chip system can be composed of chips, or it can include chips and other discrete devices. The chip 30 can be used to execute the method performed by the encoding device in each embodiment of the present application.

[0215] In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are run on a computer, the operations and / or processing performed by the encoding device in each method embodiment of the present application are executed.

[0216] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processing performed by the encoding device in the various method embodiments of the present application are executed.

[0217] In addition, the present application also provides a chip, which includes a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory so that the operations and / or processing performed by the encoding device in any one of the method embodiments are executed. Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may also include a memory that stores the code and / or instructions required for the chip to execute the encoding method of the present application.

[0218] The present application provides a communication system, including an encoding device according to an embodiment of the present application, which is used to implement steps 310 to 330 of the above method embodiment. In some embodiments, the encoding device is a communication device with corresponding encoding functions as shown in Figure 23 or Figure 24, or a chip for implementing the encoding method according to an embodiment of the present application as shown in Figure 25.

[0219] In each embodiment of the present application, "plurality" includes two or more.

[0220] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0221] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0222] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0223] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0224] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0225] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Claims

1. A coding method, characterized in that, Comprising: Obtaining an input sequence; Performing pre - transform coding on the input sequence according to a shift register to obtain an output sequence; Performing polarization coding on the output sequence to obtain a codeword sequence; Wherein, The shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre - transform coding polynomial, and the coefficients of the lowest - power term and the highest - power term of the pre - transform coding polynomial are both 1; If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the L - th register in the shift direction of the shift register, and the L - th register is the register corresponding to the highest - power term of the pre - transform coding polynomial, where L is an integer greater than or equal to 1.

2. The method according to claim 1, wherein The value in the L - th register is related to the values in the previous L - 1 registers.

3. The method according to claim 2, wherein If the current position of the input sequence is a message bit, the value in the first register in the shift register is updated to the exclusive - OR of the value in the first register and the value of the first tap corresponding to the first register, and the value of the first tap is the input of the shift register, and the first register is any one of the registers in the shift register.

4. The method according to claim 1, wherein The value in the L - th register is related to all the message bits before the current position in the input sequence.

5. The method according to claim 4, characterized in that If the current position of the input sequence is a message bit, the value of the first register in the shift register is updated to: the exclusive - OR value of the value in the first register and the value of the corresponding first tap, where the value of the first tap is the exclusive - OR value of the feedback input value and the message bit at the current position, and the first register is any one of the registers in the shift register.

6. The method according to any one of claims 1-5, characterized in that, If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value in the L - th register in the shift direction of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

7. The method according to any one of claims 1-5, characterized in that, If the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

8. The method according to any one of claims 1 to 7, characterized in that The length L of the shift register is a prime number.

9. The method according to claim 8, wherein The L is 5 or 7; If L is 7, the number of taps corresponding to the shift register does not exceed 5; or, If L is 5, the number of taps corresponding to the shift register does not exceed 3.

10. The method according to claim 1, characterized in that, The shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre - transform coding polynomial, and the coefficients of the lowest - power term and the highest - power term of the pre - transform coding polynomial are both 1, including: The shift register corresponds to two tap groups, and the taps in at least one of the two tap groups are in the writing direction; The positions of the taps in the first tap group among the two tap groups are determined by a first pre-transform coding polynomial, and the positions of the taps in the second tap group among the two tap groups are determined by a second pre-transform coding polynomial; The coefficients of the lowest-degree term and the highest-degree term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1.

11. The method according to claim 10, wherein The direction of the taps in the first tap group is writing, and the direction of the taps in the second tap group is reading; If the current position of the input sequence corresponds to a message bit, the value in the first register of the shift register is updated as: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register, where the value of the first tap is the exclusive OR value of the feedback input and the message bit at the current position, and the feedback input is the exclusive OR value of the values of the taps corresponding to the power terms with coefficients greater than 0 in the second pre-transform coding polynomial, and the first register is any one of the registers in the shift register.

12. The method according to claim 10, wherein The direction of the taps in the first tap group is writing, and the direction of the taps in the second tap group is writing; If the current position of the input sequence corresponds to a message bit, the value in the first register of the shift register is updated as: the exclusive OR value of the value in the first register, the value of the first tap, and the value of the second tap corresponding to the first register, where the value of the first tap or the value of the second tap is the exclusive OR value of the input of the shift register and the feedback input, and the feedback input is the output of the shift register, where the first tap belongs to the first tap group and the second tap belongs to the second tap group.

13. The method according to claim 11 or 12, characterized in that, If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the L-th register in the shift direction of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

14. The method according to claim 11 or 12, characterized in that, If the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

15. The method according to claim 10, characterized in that, The direction of the taps in the first tap group is reading, and the direction of the taps in the second tap group is writing; If the current position in the input sequence corresponds to a message bit, the value in the first register of the shift register is updated as: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register, where the first tap belongs to the second tap group, and the first register is any one of the registers in the shift register.

16. The method according to claim 15, characterized in that If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the taps in the first tap group; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

17. The method according to claim 16, wherein If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the taps in the first tap group, and the output of the shift register is related to the value of the taps in the first tap group, including: If the current position of the input sequence corresponds to a message bit, the output of the shift register is the exclusive OR value of the tap values corresponding to the power terms with coefficients greater than 0 in the first pre-transform coding polynomial.

18. The method according to claim 15, characterized in that If the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

19. The method according to any one of claims 15 - 18, characterized in that The value of the tap in the second tap group is the exclusive OR value of the input of the shift register and the feedback input, and the feedback input is the value in the L-th register in the shift direction of the shift register.

20. A communication device, characterized in that, Comprising: A communication module for obtaining an input sequence; A processing module for: Performing pre-transform coding on the input sequence according to a shift register to obtain an output sequence; and, Performing polarization coding on the output sequence to obtain a codeword sequence; Wherein, the shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1; If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register, and the L-th register is the register corresponding to the highest power term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

21. A communication device, characterized in that, Comprising a communication interface and a circuit, The communication interface is used for receiving an input sequence and inputting the input sequence into the circuit; the communication interface is also used for outputting a codeword sequence output by the circuit; The circuit is used for implementing the method according to any one of claims 1-19.

22. A communication device, characterized in that, Comprising: A processor, the processor is coupled to a memory, and the processor is used for executing a computer program or instruction stored in the memory to implement the method according to any one of claims 1-19.

23. A computer-readable storage medium, characterized in that, A computer-readable storage medium stores computer instructions, and when the computer instructions run on a computer, the method according to any one of claims 1-19 is implemented.

24. A computer program product, characterized in that, The computer program product includes computer program code or instructions, and when the computer program code or instructions run on a computer, the method according to any one of claims 1-19 is implemented.

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